./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:48:09,574 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:48:09,707 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:48:09,713 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:48:09,714 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:48:09,740 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:48:09,741 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:48:09,741 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:48:09,743 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:48:09,744 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:48:09,744 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:48:09,745 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:48:09,746 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:48:09,747 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:48:09,748 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:48:09,748 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:48:09,749 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:48:09,750 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:48:09,751 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:48:09,751 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:48:09,752 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:48:09,753 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:48:09,753 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:48:09,754 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:48:09,755 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:48:09,755 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:48:09,756 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:48:09,756 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:48:09,757 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:48:09,757 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:48:09,758 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:48:09,758 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:48:09,759 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:48:09,759 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:48:09,760 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:48:09,760 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:48:09,761 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2023-11-19 07:48:10,123 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:48:10,159 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:48:10,162 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:48:10,164 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:48:10,164 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:48:10,166 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/transmitter.16.cil.c [2023-11-19 07:48:13,668 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:48:13,950 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:48:13,951 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/sv-benchmarks/c/systemc/transmitter.16.cil.c [2023-11-19 07:48:13,971 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/data/4cf4271e7/01c11dfcce744dd8b2638737325ee734/FLAGeb1fbd0ea [2023-11-19 07:48:13,986 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/data/4cf4271e7/01c11dfcce744dd8b2638737325ee734 [2023-11-19 07:48:13,988 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:48:13,990 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:48:13,991 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:48:13,991 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:48:13,997 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:48:13,998 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:48:13" (1/1) ... [2023-11-19 07:48:13,999 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1ee420e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:13, skipping insertion in model container [2023-11-19 07:48:13,999 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:48:13" (1/1) ... [2023-11-19 07:48:14,084 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:48:14,410 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:48:14,439 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:48:14,554 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:48:14,584 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:48:14,584 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14 WrapperNode [2023-11-19 07:48:14,585 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:48:14,586 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:48:14,586 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:48:14,586 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:48:14,594 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:14,609 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:14,835 INFO L138 Inliner]: procedures = 56, calls = 72, calls flagged for inlining = 67, calls inlined = 304, statements flattened = 4745 [2023-11-19 07:48:14,836 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:48:14,836 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:48:14,837 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:48:14,837 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:48:14,848 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:14,848 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:14,866 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:14,867 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:14,936 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:14,986 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:14,996 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:15,011 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:15,035 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:48:15,036 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:48:15,037 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:48:15,037 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:48:15,038 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (1/1) ... [2023-11-19 07:48:15,044 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:48:15,057 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:48:15,072 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:48:15,090 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5edcabb0-bfb5-45ef-a678-1e4f70aebb00/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:48:15,120 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:48:15,121 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:48:15,121 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:48:15,121 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:48:15,282 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:48:15,284 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:48:18,303 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:48:18,338 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:48:18,338 INFO L302 CfgBuilder]: Removed 18 assume(true) statements. [2023-11-19 07:48:18,351 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:48:18 BoogieIcfgContainer [2023-11-19 07:48:18,351 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:48:18,379 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:48:18,380 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:48:18,384 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:48:18,385 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:48:18,385 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:48:13" (1/3) ... [2023-11-19 07:48:18,389 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5482281a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:48:18, skipping insertion in model container [2023-11-19 07:48:18,389 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:48:18,389 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:14" (2/3) ... [2023-11-19 07:48:18,390 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5482281a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:48:18, skipping insertion in model container [2023-11-19 07:48:18,390 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:48:18,390 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:48:18" (3/3) ... [2023-11-19 07:48:18,392 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.16.cil.c [2023-11-19 07:48:18,515 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:48:18,516 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:48:18,516 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:48:18,516 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:48:18,516 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:48:18,517 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:48:18,517 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:48:18,517 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:48:18,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2069 states, 2068 states have (on average 1.4956479690522244) internal successors, (3093), 2068 states have internal predecessors, (3093), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:18,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1880 [2023-11-19 07:48:18,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:18,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:18,652 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:18,652 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:18,652 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:48:18,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2069 states, 2068 states have (on average 1.4956479690522244) internal successors, (3093), 2068 states have internal predecessors, (3093), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:18,707 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1880 [2023-11-19 07:48:18,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:18,707 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:18,723 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:18,723 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:18,747 INFO L748 eck$LassoCheckResult]: Stem: 166#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1978#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 754#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1975#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1939#L939true assume !(1 == ~m_i~0);~m_st~0 := 2; 468#L939-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1678#L944-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 303#L949-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1342#L954-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1984#L959-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 677#L964-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1184#L969-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1792#L974-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 610#L979-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 959#L984-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 249#L989-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 448#L994-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1215#L999-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 574#L1004-1true assume !(1 == ~t14_i~0);~t14_st~0 := 2; 44#L1009-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124#L1342true assume !(0 == ~M_E~0); 428#L1342-2true assume !(0 == ~T1_E~0); 1624#L1347-1true assume !(0 == ~T2_E~0); 1316#L1352-1true assume !(0 == ~T3_E~0); 1083#L1357-1true assume !(0 == ~T4_E~0); 443#L1362-1true assume !(0 == ~T5_E~0); 1395#L1367-1true assume !(0 == ~T6_E~0); 204#L1372-1true assume 0 == ~T7_E~0;~T7_E~0 := 1; 559#L1377-1true assume !(0 == ~T8_E~0); 392#L1382-1true assume !(0 == ~T9_E~0); 952#L1387-1true assume !(0 == ~T10_E~0); 1536#L1392-1true assume !(0 == ~T11_E~0); 415#L1397-1true assume !(0 == ~T12_E~0); 1693#L1402-1true assume !(0 == ~T13_E~0); 216#L1407-1true assume !(0 == ~T14_E~0); 1873#L1412-1true assume 0 == ~E_1~0;~E_1~0 := 1; 1210#L1417-1true assume !(0 == ~E_2~0); 2068#L1422-1true assume !(0 == ~E_3~0); 1692#L1427-1true assume !(0 == ~E_4~0); 320#L1432-1true assume !(0 == ~E_5~0); 1544#L1437-1true assume !(0 == ~E_6~0); 1129#L1442-1true assume !(0 == ~E_7~0); 1467#L1447-1true assume !(0 == ~E_8~0); 945#L1452-1true assume 0 == ~E_9~0;~E_9~0 := 1; 109#L1457-1true assume !(0 == ~E_10~0); 1161#L1462-1true assume !(0 == ~E_11~0); 1870#L1467-1true assume !(0 == ~E_12~0); 1178#L1472-1true assume !(0 == ~E_13~0); 1370#L1477-1true assume !(0 == ~E_14~0); 897#L1482-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199#L646true assume 1 == ~m_pc~0; 618#L647true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 626#L657true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 644#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 250#L1666true assume !(0 != activate_threads_~tmp~1#1); 2003#L1666-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1757#L665true assume !(1 == ~t1_pc~0); 534#L665-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1208#L676true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1050#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1715#L1674true assume !(0 != activate_threads_~tmp___0~0#1); 788#L1674-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 894#L684true assume 1 == ~t2_pc~0; 1882#L685true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 885#L695true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1323#L1682true assume !(0 != activate_threads_~tmp___1~0#1); 1827#L1682-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1803#L703true assume !(1 == ~t3_pc~0); 332#L703-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1413#L714true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1033#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32#L1690true assume !(0 != activate_threads_~tmp___2~0#1); 265#L1690-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1339#L722true assume 1 == ~t4_pc~0; 758#L723true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 597#L733true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1630#L1698true assume !(0 != activate_threads_~tmp___3~0#1); 645#L1698-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125#L741true assume 1 == ~t5_pc~0; 279#L742true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 816#L752true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1670#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 867#L1706true assume !(0 != activate_threads_~tmp___4~0#1); 1394#L1706-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 429#L760true assume !(1 == ~t6_pc~0); 743#L760-2true is_transmit6_triggered_~__retres1~6#1 := 0; 992#L771true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 238#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1671#L1714true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 723#L1714-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1412#L779true assume 1 == ~t7_pc~0; 141#L780true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69#L790true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1995#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1387#L1722true assume !(0 != activate_threads_~tmp___6~0#1); 287#L1722-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1702#L798true assume !(1 == ~t8_pc~0); 1955#L798-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1265#L809true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1615#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1759#L1730true assume !(0 != activate_threads_~tmp___7~0#1); 1926#L1730-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60#L817true assume 1 == ~t9_pc~0; 835#L818true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 490#L828true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 268#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1875#L1738true assume !(0 != activate_threads_~tmp___8~0#1); 255#L1738-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 780#L836true assume !(1 == ~t10_pc~0); 269#L836-2true is_transmit10_triggered_~__retres1~10#1 := 0; 229#L847true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1376#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 371#L1746true assume !(0 != activate_threads_~tmp___9~0#1); 1279#L1746-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1285#L855true assume 1 == ~t11_pc~0; 624#L856true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1154#L866true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1497#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 943#L1754true assume !(0 != activate_threads_~tmp___10~0#1); 793#L1754-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 198#L874true assume !(1 == ~t12_pc~0); 1652#L874-2true is_transmit12_triggered_~__retres1~12#1 := 0; 292#L885true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2005#L1762true assume !(0 != activate_threads_~tmp___11~0#1); 48#L1762-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1874#L893true assume 1 == ~t13_pc~0; 1552#L894true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 391#L904true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1426#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1569#L1770true assume !(0 != activate_threads_~tmp___12~0#1); 1406#L1770-2true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1777#L912true assume 1 == ~t14_pc~0; 1134#L913true assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 2041#L923true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1206#is_transmit14_triggered_returnLabel#1true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 165#L1778true assume !(0 != activate_threads_~tmp___13~0#1); 638#L1778-2true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1356#L1495true assume 1 == ~M_E~0;~M_E~0 := 2; 1006#L1495-2true assume !(1 == ~T1_E~0); 1683#L1500-1true assume !(1 == ~T2_E~0); 719#L1505-1true assume !(1 == ~T3_E~0); 1933#L1510-1true assume !(1 == ~T4_E~0); 765#L1515-1true assume !(1 == ~T5_E~0); 1736#L1520-1true assume !(1 == ~T6_E~0); 1402#L1525-1true assume !(1 == ~T7_E~0); 1034#L1530-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 252#L1535-1true assume !(1 == ~T9_E~0); 1851#L1540-1true assume !(1 == ~T10_E~0); 15#L1545-1true assume !(1 == ~T11_E~0); 1990#L1550-1true assume !(1 == ~T12_E~0); 129#L1555-1true assume !(1 == ~T13_E~0); 281#L1560-1true assume !(1 == ~T14_E~0); 1713#L1565-1true assume !(1 == ~E_1~0); 1946#L1570-1true assume 1 == ~E_2~0;~E_2~0 := 2; 915#L1575-1true assume !(1 == ~E_3~0); 446#L1580-1true assume !(1 == ~E_4~0); 782#L1585-1true assume !(1 == ~E_5~0); 1052#L1590-1true assume !(1 == ~E_6~0); 464#L1595-1true assume !(1 == ~E_7~0); 1911#L1600-1true assume !(1 == ~E_8~0); 727#L1605-1true assume !(1 == ~E_9~0); 1659#L1610-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1247#L1615-1true assume !(1 == ~E_11~0); 358#L1620-1true assume !(1 == ~E_12~0); 1116#L1625-1true assume !(1 == ~E_13~0); 946#L1630-1true assume !(1 == ~E_14~0); 463#L1635-1true assume { :end_inline_reset_delta_events } true; 430#L2017-2true [2023-11-19 07:48:18,762 INFO L750 eck$LassoCheckResult]: Loop: 430#L2017-2true assume !false; 47#L2018true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 236#L1316-1true assume !true; 585#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 354#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 623#L1342-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1089#L1342-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1173#L1347-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 756#L1352-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1365#L1357-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 2052#L1362-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1896#L1367-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1860#L1372-3true assume !(0 == ~T7_E~0); 38#L1377-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 486#L1382-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 379#L1387-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1135#L1392-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1967#L1397-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1676#L1402-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 711#L1407-3true assume 0 == ~T14_E~0;~T14_E~0 := 1; 178#L1412-3true assume !(0 == ~E_1~0); 1407#L1417-3true assume 0 == ~E_2~0;~E_2~0 := 1; 648#L1422-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1358#L1427-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1546#L1432-3true assume 0 == ~E_5~0;~E_5~0 := 1; 983#L1437-3true assume 0 == ~E_6~0;~E_6~0 := 1; 724#L1442-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1005#L1447-3true assume 0 == ~E_8~0;~E_8~0 := 1; 67#L1452-3true assume !(0 == ~E_9~0); 2019#L1457-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1262#L1462-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1700#L1467-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1054#L1472-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1720#L1477-3true assume 0 == ~E_14~0;~E_14~0 := 1; 177#L1482-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 517#L646-42true assume !(1 == ~m_pc~0); 1690#L646-44true is_master_triggered_~__retres1~0#1 := 0; 1319#L657-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 435#is_master_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1628#L1666-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1718#L1666-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1226#L665-42true assume 1 == ~t1_pc~0; 1190#L666-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1549#L676-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1887#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 270#L1674-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1898#L1674-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1895#L684-42true assume 1 == ~t2_pc~0; 865#L685-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1908#L695-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 668#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 674#L1682-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 774#L1682-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1750#L703-42true assume 1 == ~t3_pc~0; 957#L704-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1864#L714-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1021#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1639#L1690-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1058#L1690-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 697#L722-42true assume !(1 == ~t4_pc~0); 1499#L722-44true is_transmit4_triggered_~__retres1~4#1 := 0; 1727#L733-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1100#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 349#L1698-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1940#L1698-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1739#L741-42true assume !(1 == ~t5_pc~0); 1074#L741-44true is_transmit5_triggered_~__retres1~5#1 := 0; 601#L752-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 720#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1916#L1706-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 529#L1706-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 631#L760-42true assume !(1 == ~t6_pc~0); 869#L760-44true is_transmit6_triggered_~__retres1~6#1 := 0; 735#L771-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1649#L1714-42true assume !(0 != activate_threads_~tmp___5~0#1); 501#L1714-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1332#L779-42true assume 1 == ~t7_pc~0; 1249#L780-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1885#L790-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 741#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1710#L1722-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 228#L1722-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 496#L798-42true assume 1 == ~t8_pc~0; 1943#L799-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1443#L809-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 880#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 751#L1730-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 143#L1730-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1381#L817-42true assume !(1 == ~t9_pc~0); 1156#L817-44true is_transmit9_triggered_~__retres1~9#1 := 0; 295#L828-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1913#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1194#L1738-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 981#L1738-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1525#L836-42true assume !(1 == ~t10_pc~0); 1830#L836-44true is_transmit10_triggered_~__retres1~10#1 := 0; 317#L847-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 864#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1562#L1746-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1706#L1746-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2061#L855-42true assume 1 == ~t11_pc~0; 1730#L856-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85#L866-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1568#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1175#L1754-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2063#L1754-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 413#L874-42true assume !(1 == ~t12_pc~0); 577#L874-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1496#L885-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 701#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 896#L1762-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 163#L1762-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 2001#L893-42true assume !(1 == ~t13_pc~0); 806#L893-44true is_transmit13_triggered_~__retres1~13#1 := 0; 1850#L904-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 393#is_transmit13_triggered_returnLabel#15true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 734#L1770-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 369#L1770-44true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1862#L912-42true assume !(1 == ~t14_pc~0); 988#L912-44true is_transmit14_triggered_~__retres1~14#1 := 0; 25#L923-14true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 439#is_transmit14_triggered_returnLabel#15true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1229#L1778-42true assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 226#L1778-44true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 608#L1495-3true assume !(1 == ~M_E~0); 974#L1495-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1583#L1500-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1078#L1505-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 352#L1510-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 333#L1515-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 792#L1520-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1003#L1525-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1589#L1530-3true assume !(1 == ~T8_E~0); 246#L1535-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 267#L1540-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1300#L1545-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1545#L1550-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1523#L1555-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 510#L1560-3true assume 1 == ~T14_E~0;~T14_E~0 := 2; 1027#L1565-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1890#L1570-3true assume !(1 == ~E_2~0); 977#L1575-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1427#L1580-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1533#L1585-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1769#L1590-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1674#L1595-3true assume 1 == ~E_7~0;~E_7~0 := 2; 813#L1600-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1325#L1605-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1408#L1610-3true assume !(1 == ~E_10~0); 360#L1615-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1932#L1620-3true assume 1 == ~E_12~0;~E_12~0 := 2; 783#L1625-3true assume 1 == ~E_13~0;~E_13~0 := 2; 2055#L1630-3true assume 1 == ~E_14~0;~E_14~0 := 2; 700#L1635-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 326#L1022-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 532#L1100-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 215#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1004#L2036true assume !(0 == start_simulation_~tmp~3#1); 1183#L2036-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1641#L1022-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1428#L1100-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 736#L1991true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1744#L1998true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1404#stop_simulation_returnLabel#1true start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1821#L2049true assume !(0 != start_simulation_~tmp___0~1#1); 430#L2017-2true [2023-11-19 07:48:18,777 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:18,777 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 1 times [2023-11-19 07:48:18,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:18,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352438012] [2023-11-19 07:48:18,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:18,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:19,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:19,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:19,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:19,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [352438012] [2023-11-19 07:48:19,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [352438012] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:19,348 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:19,348 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:19,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2073281822] [2023-11-19 07:48:19,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:19,357 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:19,359 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:19,359 INFO L85 PathProgramCache]: Analyzing trace with hash -114923038, now seen corresponding path program 1 times [2023-11-19 07:48:19,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:19,360 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199959909] [2023-11-19 07:48:19,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:19,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:19,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:19,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:19,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:19,505 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199959909] [2023-11-19 07:48:19,505 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199959909] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:19,505 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:19,506 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:19,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696910573] [2023-11-19 07:48:19,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:19,508 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:19,509 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:19,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-19 07:48:19,552 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-19 07:48:19,560 INFO L87 Difference]: Start difference. First operand has 2069 states, 2068 states have (on average 1.4956479690522244) internal successors, (3093), 2068 states have internal predecessors, (3093), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 83.5) internal successors, (167), 2 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:19,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:19,673 INFO L93 Difference]: Finished difference Result 2067 states and 3054 transitions. [2023-11-19 07:48:19,675 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2067 states and 3054 transitions. [2023-11-19 07:48:19,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:19,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2067 states to 2062 states and 3049 transitions. [2023-11-19 07:48:19,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:19,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:19,733 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3049 transitions. [2023-11-19 07:48:19,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:19,746 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3049 transitions. [2023-11-19 07:48:19,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3049 transitions. [2023-11-19 07:48:19,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:19,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4786614936954414) internal successors, (3049), 2061 states have internal predecessors, (3049), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:19,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3049 transitions. [2023-11-19 07:48:19,885 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3049 transitions. [2023-11-19 07:48:19,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-19 07:48:19,890 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3049 transitions. [2023-11-19 07:48:19,890 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:48:19,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3049 transitions. [2023-11-19 07:48:19,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:19,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:19,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:19,911 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:19,911 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:19,912 INFO L748 eck$LassoCheckResult]: Stem: 4502#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 4503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 5434#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5435#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6196#L939 assume !(1 == ~m_i~0);~m_st~0 := 2; 5039#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5040#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4752#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4753#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6005#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5331#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5332#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5870#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5237#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5238#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4662#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4663#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5009#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5191#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 4243#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4244#L1342 assume !(0 == ~M_E~0); 4412#L1342-2 assume !(0 == ~T1_E~0); 4976#L1347-1 assume !(0 == ~T2_E~0); 5986#L1352-1 assume !(0 == ~T3_E~0); 5777#L1357-1 assume !(0 == ~T4_E~0); 4998#L1362-1 assume !(0 == ~T5_E~0); 4999#L1367-1 assume !(0 == ~T6_E~0); 4577#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4578#L1377-1 assume !(0 == ~T8_E~0); 4916#L1382-1 assume !(0 == ~T9_E~0); 4917#L1387-1 assume !(0 == ~T10_E~0); 5658#L1392-1 assume !(0 == ~T11_E~0); 4957#L1397-1 assume !(0 == ~T12_E~0); 4958#L1402-1 assume !(0 == ~T13_E~0); 4601#L1407-1 assume !(0 == ~T14_E~0); 4602#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5902#L1417-1 assume !(0 == ~E_2~0); 5903#L1422-1 assume !(0 == ~E_3~0); 6140#L1427-1 assume !(0 == ~E_4~0); 4781#L1432-1 assume !(0 == ~E_5~0); 4782#L1437-1 assume !(0 == ~E_6~0); 5822#L1442-1 assume !(0 == ~E_7~0); 5823#L1447-1 assume !(0 == ~E_8~0); 5652#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 4381#L1457-1 assume !(0 == ~E_10~0); 4382#L1462-1 assume !(0 == ~E_11~0); 5852#L1467-1 assume !(0 == ~E_12~0); 5865#L1472-1 assume !(0 == ~E_13~0); 5866#L1477-1 assume !(0 == ~E_14~0); 5601#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4566#L646 assume 1 == ~m_pc~0; 4567#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5247#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5262#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4664#L1666 assume !(0 != activate_threads_~tmp~1#1); 4665#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6161#L665 assume !(1 == ~t1_pc~0); 5142#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5143#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5751#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5752#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 5483#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5484#L684 assume 1 == ~t2_pc~0; 5598#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5522#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4651#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 5991#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6174#L703 assume !(1 == ~t3_pc~0); 4806#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4807#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5738#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4215#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 4216#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4694#L722 assume 1 == ~t4_pc~0; 5441#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4881#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4326#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4327#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 5283#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4413#L741 assume 1 == ~t5_pc~0; 4414#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4716#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5516#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5568#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 5569#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4977#L760 assume !(1 == ~t6_pc~0); 4805#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4804#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4642#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4643#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5398#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5399#L779 assume 1 == ~t7_pc~0; 4450#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4297#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4298#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6023#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 4728#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4729#L798 assume !(1 == ~t8_pc~0); 6033#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5950#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5951#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6115#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 6163#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4276#L817 assume 1 == ~t9_pc~0; 4277#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5075#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4698#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4699#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 4676#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4677#L836 assume !(1 == ~t10_pc~0); 4700#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4626#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4627#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4882#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 4883#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5963#L855 assume 1 == ~t11_pc~0; 5258#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5259#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5846#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5649#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 5489#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4563#L874 assume !(1 == ~t12_pc~0); 4564#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4737#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4265#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4266#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 4251#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4252#L893 assume 1 == ~t13_pc~0; 6098#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4604#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4915#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 6046#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 6038#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 6039#L912 assume 1 == ~t14_pc~0; 5829#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 5830#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 5899#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4500#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 4501#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5276#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 5707#L1495-2 assume !(1 == ~T1_E~0); 5708#L1500-1 assume !(1 == ~T2_E~0); 5392#L1505-1 assume !(1 == ~T3_E~0); 5393#L1510-1 assume !(1 == ~T4_E~0); 5451#L1515-1 assume !(1 == ~T5_E~0); 5452#L1520-1 assume !(1 == ~T6_E~0); 6034#L1525-1 assume !(1 == ~T7_E~0); 5739#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4669#L1535-1 assume !(1 == ~T9_E~0); 4670#L1540-1 assume !(1 == ~T10_E~0); 4176#L1545-1 assume !(1 == ~T11_E~0); 4177#L1550-1 assume !(1 == ~T12_E~0); 4423#L1555-1 assume !(1 == ~T13_E~0); 4424#L1560-1 assume !(1 == ~T14_E~0); 4719#L1565-1 assume !(1 == ~E_1~0); 6149#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5622#L1575-1 assume !(1 == ~E_3~0); 5004#L1580-1 assume !(1 == ~E_4~0); 5005#L1585-1 assume !(1 == ~E_5~0); 5475#L1590-1 assume !(1 == ~E_6~0); 5033#L1595-1 assume !(1 == ~E_7~0); 5034#L1600-1 assume !(1 == ~E_8~0); 5406#L1605-1 assume !(1 == ~E_9~0); 5407#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5937#L1615-1 assume !(1 == ~E_11~0); 4855#L1620-1 assume !(1 == ~E_12~0); 4856#L1625-1 assume !(1 == ~E_13~0); 5653#L1630-1 assume !(1 == ~E_14~0); 5032#L1635-1 assume { :end_inline_reset_delta_events } true; 4978#L2017-2 [2023-11-19 07:48:19,914 INFO L750 eck$LassoCheckResult]: Loop: 4978#L2017-2 assume !false; 4249#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4250#L1316-1 assume !false; 4638#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5648#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4189#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4526#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5672#L1115 assume !(0 != eval_~tmp~0#1); 5203#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4850#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4851#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5257#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5784#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5437#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5438#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6017#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6189#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6181#L1372-3 assume !(0 == ~T7_E~0); 4229#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4230#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4895#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4896#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5832#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 6135#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5384#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 4524#L1412-3 assume !(0 == ~E_1~0); 4525#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5286#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5287#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6015#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5692#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5400#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5401#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4293#L1452-3 assume !(0 == ~E_9~0); 4294#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5948#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5949#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5756#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5757#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 4522#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4523#L646-42 assume 1 == ~m_pc~0; 5118#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5987#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4986#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4987#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6119#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5919#L665-42 assume 1 == ~t1_pc~0; 5877#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5879#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6094#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4701#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4702#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6188#L684-42 assume 1 == ~t2_pc~0; 5564#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5565#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5317#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5318#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5327#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5463#L703-42 assume !(1 == ~t3_pc~0); 5665#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 5664#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5728#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5729#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5761#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5367#L722-42 assume 1 == ~t4_pc~0; 5368#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5797#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5793#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4843#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4844#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6155#L741-42 assume 1 == ~t5_pc~0; 6099#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5222#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5223#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5394#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5136#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5137#L760-42 assume !(1 == ~t6_pc~0); 5264#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 5413#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4615#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4616#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 5091#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5092#L779-42 assume 1 == ~t7_pc~0; 5938#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5885#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5421#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5422#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4624#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4625#L798-42 assume !(1 == ~t8_pc~0); 4241#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 4242#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5583#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5431#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4456#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4457#L817-42 assume 1 == ~t9_pc~0; 5229#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4739#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4740#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5883#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5687#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5688#L836-42 assume 1 == ~t10_pc~0; 5788#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4776#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4777#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5563#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6101#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6143#L855-42 assume 1 == ~t11_pc~0; 6153#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4332#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4333#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5863#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5864#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4954#L874-42 assume !(1 == ~t12_pc~0); 4955#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 5182#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5372#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5373#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4496#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4497#L893-42 assume 1 == ~t13_pc~0; 5714#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5503#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4918#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4919#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4878#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 4879#L912-42 assume 1 == ~t14_pc~0; 6136#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 4199#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4200#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4992#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 4621#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4622#L1495-3 assume !(1 == ~M_E~0); 5234#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5678#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5774#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4849#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4808#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4809#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5488#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5704#L1530-3 assume !(1 == ~T8_E~0); 4658#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4659#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4697#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5978#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 6085#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5106#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 5107#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5735#L1570-3 assume !(1 == ~E_2~0); 5682#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5683#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6047#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6089#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6134#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5510#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5511#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5992#L1610-3 assume !(1 == ~E_10~0); 4859#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4860#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5476#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5477#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 5371#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4792#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4408#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4599#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4600#L2036 assume !(0 == start_simulation_~tmp~3#1); 5705#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5869#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 5023#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4245#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 4246#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5414#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6036#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 6037#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 4978#L2017-2 [2023-11-19 07:48:19,915 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:19,915 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 2 times [2023-11-19 07:48:19,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:19,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867495948] [2023-11-19 07:48:19,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:19,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:19,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:20,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:20,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:20,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867495948] [2023-11-19 07:48:20,088 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867495948] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:20,088 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:20,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:20,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679614411] [2023-11-19 07:48:20,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:20,089 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:20,090 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:20,090 INFO L85 PathProgramCache]: Analyzing trace with hash -903547823, now seen corresponding path program 1 times [2023-11-19 07:48:20,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:20,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925178486] [2023-11-19 07:48:20,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:20,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:20,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:20,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:20,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:20,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1925178486] [2023-11-19 07:48:20,231 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1925178486] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:20,231 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:20,231 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:20,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170175032] [2023-11-19 07:48:20,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:20,233 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:20,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:20,233 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:20,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:20,234 INFO L87 Difference]: Start difference. First operand 2062 states and 3049 transitions. cyclomatic complexity: 988 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:20,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:20,288 INFO L93 Difference]: Finished difference Result 2062 states and 3048 transitions. [2023-11-19 07:48:20,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3048 transitions. [2023-11-19 07:48:20,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:20,322 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3048 transitions. [2023-11-19 07:48:20,322 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:20,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:20,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3048 transitions. [2023-11-19 07:48:20,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:20,329 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3048 transitions. [2023-11-19 07:48:20,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3048 transitions. [2023-11-19 07:48:20,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:20,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.478176527643065) internal successors, (3048), 2061 states have internal predecessors, (3048), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:20,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3048 transitions. [2023-11-19 07:48:20,383 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3048 transitions. [2023-11-19 07:48:20,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:20,385 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3048 transitions. [2023-11-19 07:48:20,385 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:48:20,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3048 transitions. [2023-11-19 07:48:20,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:20,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:20,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:20,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:20,409 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:20,412 INFO L748 eck$LassoCheckResult]: Stem: 8633#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 8634#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 9565#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9566#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10327#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 9170#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9171#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8883#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8884#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10136#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9462#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9463#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10001#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9368#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9369#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8793#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8794#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9140#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9322#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 8374#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8375#L1342 assume !(0 == ~M_E~0); 8543#L1342-2 assume !(0 == ~T1_E~0); 9107#L1347-1 assume !(0 == ~T2_E~0); 10117#L1352-1 assume !(0 == ~T3_E~0); 9908#L1357-1 assume !(0 == ~T4_E~0); 9129#L1362-1 assume !(0 == ~T5_E~0); 9130#L1367-1 assume !(0 == ~T6_E~0); 8708#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8709#L1377-1 assume !(0 == ~T8_E~0); 9047#L1382-1 assume !(0 == ~T9_E~0); 9048#L1387-1 assume !(0 == ~T10_E~0); 9789#L1392-1 assume !(0 == ~T11_E~0); 9088#L1397-1 assume !(0 == ~T12_E~0); 9089#L1402-1 assume !(0 == ~T13_E~0); 8732#L1407-1 assume !(0 == ~T14_E~0); 8733#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 10033#L1417-1 assume !(0 == ~E_2~0); 10034#L1422-1 assume !(0 == ~E_3~0); 10271#L1427-1 assume !(0 == ~E_4~0); 8912#L1432-1 assume !(0 == ~E_5~0); 8913#L1437-1 assume !(0 == ~E_6~0); 9953#L1442-1 assume !(0 == ~E_7~0); 9954#L1447-1 assume !(0 == ~E_8~0); 9783#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8512#L1457-1 assume !(0 == ~E_10~0); 8513#L1462-1 assume !(0 == ~E_11~0); 9983#L1467-1 assume !(0 == ~E_12~0); 9996#L1472-1 assume !(0 == ~E_13~0); 9997#L1477-1 assume !(0 == ~E_14~0); 9732#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8697#L646 assume 1 == ~m_pc~0; 8698#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9378#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9393#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8795#L1666 assume !(0 != activate_threads_~tmp~1#1); 8796#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10292#L665 assume !(1 == ~t1_pc~0); 9273#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9274#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9882#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9883#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 9614#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9615#L684 assume 1 == ~t2_pc~0; 9729#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9653#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8781#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8782#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 10122#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10305#L703 assume !(1 == ~t3_pc~0); 8937#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8938#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9869#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8346#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 8347#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8825#L722 assume 1 == ~t4_pc~0; 9572#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9012#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8457#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8458#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 9414#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8544#L741 assume 1 == ~t5_pc~0; 8545#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8847#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9647#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9699#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 9700#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9108#L760 assume !(1 == ~t6_pc~0); 8936#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8935#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8773#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8774#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9529#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9530#L779 assume 1 == ~t7_pc~0; 8581#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8428#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8429#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10154#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 8859#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8860#L798 assume !(1 == ~t8_pc~0); 10164#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10081#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10082#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10246#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 10294#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8407#L817 assume 1 == ~t9_pc~0; 8408#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9206#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8829#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8830#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 8807#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8808#L836 assume !(1 == ~t10_pc~0); 8831#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8757#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8758#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9013#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 9014#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10094#L855 assume 1 == ~t11_pc~0; 9389#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9390#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9977#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9780#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 9620#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8694#L874 assume !(1 == ~t12_pc~0); 8695#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8868#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8396#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8397#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 8382#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8383#L893 assume 1 == ~t13_pc~0; 10229#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8735#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9046#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 10177#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 10169#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 10170#L912 assume 1 == ~t14_pc~0; 9960#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 9961#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 10030#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8631#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 8632#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9407#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 9838#L1495-2 assume !(1 == ~T1_E~0); 9839#L1500-1 assume !(1 == ~T2_E~0); 9523#L1505-1 assume !(1 == ~T3_E~0); 9524#L1510-1 assume !(1 == ~T4_E~0); 9582#L1515-1 assume !(1 == ~T5_E~0); 9583#L1520-1 assume !(1 == ~T6_E~0); 10165#L1525-1 assume !(1 == ~T7_E~0); 9870#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8800#L1535-1 assume !(1 == ~T9_E~0); 8801#L1540-1 assume !(1 == ~T10_E~0); 8307#L1545-1 assume !(1 == ~T11_E~0); 8308#L1550-1 assume !(1 == ~T12_E~0); 8554#L1555-1 assume !(1 == ~T13_E~0); 8555#L1560-1 assume !(1 == ~T14_E~0); 8850#L1565-1 assume !(1 == ~E_1~0); 10280#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9753#L1575-1 assume !(1 == ~E_3~0); 9135#L1580-1 assume !(1 == ~E_4~0); 9136#L1585-1 assume !(1 == ~E_5~0); 9606#L1590-1 assume !(1 == ~E_6~0); 9164#L1595-1 assume !(1 == ~E_7~0); 9165#L1600-1 assume !(1 == ~E_8~0); 9537#L1605-1 assume !(1 == ~E_9~0); 9538#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10068#L1615-1 assume !(1 == ~E_11~0); 8986#L1620-1 assume !(1 == ~E_12~0); 8987#L1625-1 assume !(1 == ~E_13~0); 9784#L1630-1 assume !(1 == ~E_14~0); 9163#L1635-1 assume { :end_inline_reset_delta_events } true; 9109#L2017-2 [2023-11-19 07:48:20,412 INFO L750 eck$LassoCheckResult]: Loop: 9109#L2017-2 assume !false; 8380#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8381#L1316-1 assume !false; 8769#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9779#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8320#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8657#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9803#L1115 assume !(0 != eval_~tmp~0#1); 9334#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8981#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8982#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9388#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9915#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9568#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9569#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10148#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10320#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10312#L1372-3 assume !(0 == ~T7_E~0); 8360#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8361#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9026#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9027#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9963#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10266#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9515#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 8655#L1412-3 assume !(0 == ~E_1~0); 8656#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9417#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9418#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10146#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9823#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9531#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9532#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8424#L1452-3 assume !(0 == ~E_9~0); 8425#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10079#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10080#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 9887#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9888#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 8653#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8654#L646-42 assume 1 == ~m_pc~0; 9249#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10118#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9117#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9118#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10250#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10050#L665-42 assume 1 == ~t1_pc~0; 10008#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10010#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10225#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8832#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8833#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10319#L684-42 assume !(1 == ~t2_pc~0); 9697#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 9696#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9448#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9449#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9458#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9594#L703-42 assume 1 == ~t3_pc~0; 9794#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9795#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9859#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9860#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9892#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9498#L722-42 assume 1 == ~t4_pc~0; 9499#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9928#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9924#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8974#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8975#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10286#L741-42 assume !(1 == ~t5_pc~0); 9904#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 9353#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9354#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9525#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9267#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9268#L760-42 assume !(1 == ~t6_pc~0); 9395#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 9544#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8746#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8747#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 9222#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9223#L779-42 assume 1 == ~t7_pc~0; 10069#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10016#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9552#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9553#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8755#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8756#L798-42 assume !(1 == ~t8_pc~0); 8372#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 8373#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9714#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9562#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8587#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8588#L817-42 assume 1 == ~t9_pc~0; 9362#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8870#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8871#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10014#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9818#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9819#L836-42 assume !(1 == ~t10_pc~0); 9920#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 8907#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8908#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9694#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10232#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10274#L855-42 assume 1 == ~t11_pc~0; 10284#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8463#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8464#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9994#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9995#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9085#L874-42 assume !(1 == ~t12_pc~0); 9086#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 9316#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9503#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9504#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8627#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8628#L893-42 assume !(1 == ~t13_pc~0); 9633#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 9634#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9049#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9050#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 9009#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 9010#L912-42 assume !(1 == ~t14_pc~0); 9826#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 8330#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 8331#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9123#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 8752#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8753#L1495-3 assume !(1 == ~M_E~0); 9365#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9809#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9905#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8980#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8939#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8940#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9619#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9835#L1530-3 assume !(1 == ~T8_E~0); 8789#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8790#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8828#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10109#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 10216#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9237#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 9238#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9866#L1570-3 assume !(1 == ~E_2~0); 9813#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9814#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10178#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10221#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10265#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9641#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9642#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10123#L1610-3 assume !(1 == ~E_10~0); 8990#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8991#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9607#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9608#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 9502#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 8923#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8539#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8730#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8731#L2036 assume !(0 == start_simulation_~tmp~3#1); 9836#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 10000#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 9154#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8376#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 8377#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9545#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10167#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10168#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 9109#L2017-2 [2023-11-19 07:48:20,413 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:20,414 INFO L85 PathProgramCache]: Analyzing trace with hash -1949208090, now seen corresponding path program 1 times [2023-11-19 07:48:20,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:20,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846764257] [2023-11-19 07:48:20,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:20,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:20,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:20,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:20,533 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:20,533 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846764257] [2023-11-19 07:48:20,533 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1846764257] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:20,534 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:20,534 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:20,534 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871879621] [2023-11-19 07:48:20,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:20,535 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:20,535 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:20,535 INFO L85 PathProgramCache]: Analyzing trace with hash -102240755, now seen corresponding path program 1 times [2023-11-19 07:48:20,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:20,537 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1777109682] [2023-11-19 07:48:20,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:20,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:20,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:20,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:20,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:20,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1777109682] [2023-11-19 07:48:20,662 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1777109682] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:20,662 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:20,663 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:20,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1843842295] [2023-11-19 07:48:20,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:20,664 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:20,664 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:20,664 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:20,664 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:20,665 INFO L87 Difference]: Start difference. First operand 2062 states and 3048 transitions. cyclomatic complexity: 987 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:20,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:20,726 INFO L93 Difference]: Finished difference Result 2062 states and 3047 transitions. [2023-11-19 07:48:20,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3047 transitions. [2023-11-19 07:48:20,743 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:20,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3047 transitions. [2023-11-19 07:48:20,761 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:20,763 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:20,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3047 transitions. [2023-11-19 07:48:20,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:20,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3047 transitions. [2023-11-19 07:48:20,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3047 transitions. [2023-11-19 07:48:20,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:20,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4776915615906887) internal successors, (3047), 2061 states have internal predecessors, (3047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:20,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3047 transitions. [2023-11-19 07:48:20,818 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3047 transitions. [2023-11-19 07:48:20,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:20,821 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3047 transitions. [2023-11-19 07:48:20,822 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:48:20,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3047 transitions. [2023-11-19 07:48:20,834 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:20,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:20,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:20,838 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:20,838 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:20,838 INFO L748 eck$LassoCheckResult]: Stem: 12764#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 12765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 13696#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13697#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14458#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 13301#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13302#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13014#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13015#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14267#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13593#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13594#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14132#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13499#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13500#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12924#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12925#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13271#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13453#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 12505#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12506#L1342 assume !(0 == ~M_E~0); 12674#L1342-2 assume !(0 == ~T1_E~0); 13238#L1347-1 assume !(0 == ~T2_E~0); 14248#L1352-1 assume !(0 == ~T3_E~0); 14039#L1357-1 assume !(0 == ~T4_E~0); 13260#L1362-1 assume !(0 == ~T5_E~0); 13261#L1367-1 assume !(0 == ~T6_E~0); 12839#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12840#L1377-1 assume !(0 == ~T8_E~0); 13178#L1382-1 assume !(0 == ~T9_E~0); 13179#L1387-1 assume !(0 == ~T10_E~0); 13920#L1392-1 assume !(0 == ~T11_E~0); 13221#L1397-1 assume !(0 == ~T12_E~0); 13222#L1402-1 assume !(0 == ~T13_E~0); 12863#L1407-1 assume !(0 == ~T14_E~0); 12864#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14164#L1417-1 assume !(0 == ~E_2~0); 14165#L1422-1 assume !(0 == ~E_3~0); 14402#L1427-1 assume !(0 == ~E_4~0); 13043#L1432-1 assume !(0 == ~E_5~0); 13044#L1437-1 assume !(0 == ~E_6~0); 14084#L1442-1 assume !(0 == ~E_7~0); 14085#L1447-1 assume !(0 == ~E_8~0); 13914#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 12643#L1457-1 assume !(0 == ~E_10~0); 12644#L1462-1 assume !(0 == ~E_11~0); 14114#L1467-1 assume !(0 == ~E_12~0); 14127#L1472-1 assume !(0 == ~E_13~0); 14128#L1477-1 assume !(0 == ~E_14~0); 13863#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12828#L646 assume 1 == ~m_pc~0; 12829#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13509#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13524#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12926#L1666 assume !(0 != activate_threads_~tmp~1#1); 12927#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14423#L665 assume !(1 == ~t1_pc~0); 13404#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13405#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14013#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14014#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 13745#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13746#L684 assume 1 == ~t2_pc~0; 13860#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13784#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12912#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12913#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 14253#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14436#L703 assume !(1 == ~t3_pc~0); 13068#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13069#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14000#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12477#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 12478#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12956#L722 assume 1 == ~t4_pc~0; 13703#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13143#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12588#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12589#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 13545#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12675#L741 assume 1 == ~t5_pc~0; 12676#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12978#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13778#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13830#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 13831#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13239#L760 assume !(1 == ~t6_pc~0); 13067#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13066#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12904#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12905#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13660#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13661#L779 assume 1 == ~t7_pc~0; 12712#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12559#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12560#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14285#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 12990#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12991#L798 assume !(1 == ~t8_pc~0); 14295#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14212#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14213#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14377#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 14425#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12538#L817 assume 1 == ~t9_pc~0; 12539#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13337#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12960#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12961#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 12938#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12939#L836 assume !(1 == ~t10_pc~0); 12962#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12888#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12889#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13144#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 13145#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14225#L855 assume 1 == ~t11_pc~0; 13520#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13521#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14108#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13911#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 13751#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12825#L874 assume !(1 == ~t12_pc~0); 12826#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12999#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12527#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12528#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 12513#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12514#L893 assume 1 == ~t13_pc~0; 14360#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12866#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13177#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14308#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 14300#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 14301#L912 assume 1 == ~t14_pc~0; 14091#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 14092#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 14161#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12762#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 12763#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13538#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 13969#L1495-2 assume !(1 == ~T1_E~0); 13970#L1500-1 assume !(1 == ~T2_E~0); 13654#L1505-1 assume !(1 == ~T3_E~0); 13655#L1510-1 assume !(1 == ~T4_E~0); 13713#L1515-1 assume !(1 == ~T5_E~0); 13714#L1520-1 assume !(1 == ~T6_E~0); 14296#L1525-1 assume !(1 == ~T7_E~0); 14001#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12931#L1535-1 assume !(1 == ~T9_E~0); 12932#L1540-1 assume !(1 == ~T10_E~0); 12438#L1545-1 assume !(1 == ~T11_E~0); 12439#L1550-1 assume !(1 == ~T12_E~0); 12685#L1555-1 assume !(1 == ~T13_E~0); 12686#L1560-1 assume !(1 == ~T14_E~0); 12981#L1565-1 assume !(1 == ~E_1~0); 14411#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13884#L1575-1 assume !(1 == ~E_3~0); 13266#L1580-1 assume !(1 == ~E_4~0); 13267#L1585-1 assume !(1 == ~E_5~0); 13737#L1590-1 assume !(1 == ~E_6~0); 13295#L1595-1 assume !(1 == ~E_7~0); 13296#L1600-1 assume !(1 == ~E_8~0); 13668#L1605-1 assume !(1 == ~E_9~0); 13669#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14199#L1615-1 assume !(1 == ~E_11~0); 13117#L1620-1 assume !(1 == ~E_12~0); 13118#L1625-1 assume !(1 == ~E_13~0); 13915#L1630-1 assume !(1 == ~E_14~0); 13294#L1635-1 assume { :end_inline_reset_delta_events } true; 13240#L2017-2 [2023-11-19 07:48:20,839 INFO L750 eck$LassoCheckResult]: Loop: 13240#L2017-2 assume !false; 12511#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12512#L1316-1 assume !false; 12900#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13910#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12451#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12788#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13934#L1115 assume !(0 != eval_~tmp~0#1); 13465#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13112#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13113#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13519#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14046#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13699#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13700#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14279#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14451#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14443#L1372-3 assume !(0 == ~T7_E~0); 12491#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12492#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13157#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13158#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14094#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14397#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13646#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 12786#L1412-3 assume !(0 == ~E_1~0); 12787#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13548#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13549#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14277#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13954#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13662#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13663#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12555#L1452-3 assume !(0 == ~E_9~0); 12556#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14210#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14211#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14018#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 14019#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 12784#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12785#L646-42 assume 1 == ~m_pc~0; 13380#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14249#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13248#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13249#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14381#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14181#L665-42 assume 1 == ~t1_pc~0; 14139#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14141#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14356#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12963#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12964#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14450#L684-42 assume 1 == ~t2_pc~0; 13826#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13827#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13579#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13580#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13589#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13725#L703-42 assume 1 == ~t3_pc~0; 13926#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13927#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13990#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13991#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14023#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13629#L722-42 assume 1 == ~t4_pc~0; 13630#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14059#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14055#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13105#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13106#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14417#L741-42 assume !(1 == ~t5_pc~0); 14035#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 13484#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13485#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13656#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13398#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13399#L760-42 assume !(1 == ~t6_pc~0); 13526#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 13675#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12877#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12878#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 13353#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13354#L779-42 assume !(1 == ~t7_pc~0); 14146#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 14147#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13683#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13684#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12886#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12887#L798-42 assume 1 == ~t8_pc~0; 13346#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12504#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13845#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13693#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12718#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12719#L817-42 assume 1 == ~t9_pc~0; 13493#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13001#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13002#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14145#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13949#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13950#L836-42 assume 1 == ~t10_pc~0; 14050#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13038#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13039#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13825#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14363#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14405#L855-42 assume !(1 == ~t11_pc~0); 14416#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 12594#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12595#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14125#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14126#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13216#L874-42 assume !(1 == ~t12_pc~0); 13217#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 13447#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13634#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13635#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12758#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12759#L893-42 assume !(1 == ~t13_pc~0); 13764#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 13765#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13180#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13181#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 13140#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 13141#L912-42 assume !(1 == ~t14_pc~0); 13957#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 12461#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12462#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13254#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 12883#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12884#L1495-3 assume !(1 == ~M_E~0); 13496#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13940#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14036#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13111#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13070#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13071#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13750#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13966#L1530-3 assume !(1 == ~T8_E~0); 12920#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12921#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12959#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14240#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14347#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13368#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 13369#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13997#L1570-3 assume !(1 == ~E_2~0); 13944#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13945#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14309#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14352#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14396#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13775#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13776#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14254#L1610-3 assume !(1 == ~E_10~0); 13121#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13122#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13738#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13739#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 13633#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13054#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12670#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12861#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12862#L2036 assume !(0 == start_simulation_~tmp~3#1); 13967#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 14131#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 13279#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12507#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 12508#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13676#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14298#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14299#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 13240#L2017-2 [2023-11-19 07:48:20,842 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:20,842 INFO L85 PathProgramCache]: Analyzing trace with hash -224599768, now seen corresponding path program 1 times [2023-11-19 07:48:20,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:20,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855772679] [2023-11-19 07:48:20,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:20,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:20,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:20,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:20,928 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:20,929 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855772679] [2023-11-19 07:48:20,929 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855772679] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:20,930 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:20,930 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:20,930 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [959322803] [2023-11-19 07:48:20,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:20,931 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:20,931 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:20,931 INFO L85 PathProgramCache]: Analyzing trace with hash 850948718, now seen corresponding path program 1 times [2023-11-19 07:48:20,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:20,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472362298] [2023-11-19 07:48:20,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:20,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:20,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:21,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:21,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:21,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [472362298] [2023-11-19 07:48:21,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [472362298] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:21,035 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:21,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:21,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1946513704] [2023-11-19 07:48:21,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:21,036 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:21,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:21,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:21,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:21,037 INFO L87 Difference]: Start difference. First operand 2062 states and 3047 transitions. cyclomatic complexity: 986 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:21,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:21,125 INFO L93 Difference]: Finished difference Result 2062 states and 3046 transitions. [2023-11-19 07:48:21,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3046 transitions. [2023-11-19 07:48:21,143 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:21,159 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3046 transitions. [2023-11-19 07:48:21,160 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:21,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:21,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3046 transitions. [2023-11-19 07:48:21,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:21,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3046 transitions. [2023-11-19 07:48:21,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3046 transitions. [2023-11-19 07:48:21,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:21,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4772065955383122) internal successors, (3046), 2061 states have internal predecessors, (3046), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:21,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3046 transitions. [2023-11-19 07:48:21,211 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3046 transitions. [2023-11-19 07:48:21,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:21,215 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3046 transitions. [2023-11-19 07:48:21,218 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:48:21,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3046 transitions. [2023-11-19 07:48:21,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:21,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:21,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:21,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:21,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:21,232 INFO L748 eck$LassoCheckResult]: Stem: 16895#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 16896#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 17827#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17828#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18589#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 17432#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17433#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17145#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17146#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18398#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17724#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17725#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18263#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17630#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17631#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17055#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17056#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17402#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17584#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 16636#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16637#L1342 assume !(0 == ~M_E~0); 16805#L1342-2 assume !(0 == ~T1_E~0); 17369#L1347-1 assume !(0 == ~T2_E~0); 18379#L1352-1 assume !(0 == ~T3_E~0); 18170#L1357-1 assume !(0 == ~T4_E~0); 17391#L1362-1 assume !(0 == ~T5_E~0); 17392#L1367-1 assume !(0 == ~T6_E~0); 16970#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16971#L1377-1 assume !(0 == ~T8_E~0); 17309#L1382-1 assume !(0 == ~T9_E~0); 17310#L1387-1 assume !(0 == ~T10_E~0); 18051#L1392-1 assume !(0 == ~T11_E~0); 17352#L1397-1 assume !(0 == ~T12_E~0); 17353#L1402-1 assume !(0 == ~T13_E~0); 16994#L1407-1 assume !(0 == ~T14_E~0); 16995#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 18295#L1417-1 assume !(0 == ~E_2~0); 18296#L1422-1 assume !(0 == ~E_3~0); 18533#L1427-1 assume !(0 == ~E_4~0); 17174#L1432-1 assume !(0 == ~E_5~0); 17175#L1437-1 assume !(0 == ~E_6~0); 18215#L1442-1 assume !(0 == ~E_7~0); 18216#L1447-1 assume !(0 == ~E_8~0); 18045#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16774#L1457-1 assume !(0 == ~E_10~0); 16775#L1462-1 assume !(0 == ~E_11~0); 18245#L1467-1 assume !(0 == ~E_12~0); 18258#L1472-1 assume !(0 == ~E_13~0); 18259#L1477-1 assume !(0 == ~E_14~0); 17994#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16959#L646 assume 1 == ~m_pc~0; 16960#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17640#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17655#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17057#L1666 assume !(0 != activate_threads_~tmp~1#1); 17058#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18554#L665 assume !(1 == ~t1_pc~0); 17535#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17536#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18144#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18145#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 17876#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17877#L684 assume 1 == ~t2_pc~0; 17991#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17915#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17043#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17044#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 18384#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18567#L703 assume !(1 == ~t3_pc~0); 17199#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17200#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18131#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16608#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 16609#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17087#L722 assume 1 == ~t4_pc~0; 17834#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17274#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16719#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16720#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 17676#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16806#L741 assume 1 == ~t5_pc~0; 16807#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17109#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17909#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17961#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 17962#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17370#L760 assume !(1 == ~t6_pc~0); 17198#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17197#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17035#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17036#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17791#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17792#L779 assume 1 == ~t7_pc~0; 16843#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16690#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16691#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18416#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 17121#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17122#L798 assume !(1 == ~t8_pc~0); 18426#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18343#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18344#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18508#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 18556#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16669#L817 assume 1 == ~t9_pc~0; 16670#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17468#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17091#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17092#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 17069#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17070#L836 assume !(1 == ~t10_pc~0); 17093#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17019#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17020#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17275#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 17276#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18356#L855 assume 1 == ~t11_pc~0; 17651#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17652#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18239#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18042#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 17882#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16956#L874 assume !(1 == ~t12_pc~0); 16957#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17130#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16658#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16659#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 16644#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16645#L893 assume 1 == ~t13_pc~0; 18491#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16997#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17308#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18439#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 18431#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 18432#L912 assume 1 == ~t14_pc~0; 18222#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 18223#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 18292#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16893#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 16894#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17669#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 18100#L1495-2 assume !(1 == ~T1_E~0); 18101#L1500-1 assume !(1 == ~T2_E~0); 17785#L1505-1 assume !(1 == ~T3_E~0); 17786#L1510-1 assume !(1 == ~T4_E~0); 17844#L1515-1 assume !(1 == ~T5_E~0); 17845#L1520-1 assume !(1 == ~T6_E~0); 18427#L1525-1 assume !(1 == ~T7_E~0); 18132#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17062#L1535-1 assume !(1 == ~T9_E~0); 17063#L1540-1 assume !(1 == ~T10_E~0); 16569#L1545-1 assume !(1 == ~T11_E~0); 16570#L1550-1 assume !(1 == ~T12_E~0); 16816#L1555-1 assume !(1 == ~T13_E~0); 16817#L1560-1 assume !(1 == ~T14_E~0); 17112#L1565-1 assume !(1 == ~E_1~0); 18542#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 18015#L1575-1 assume !(1 == ~E_3~0); 17397#L1580-1 assume !(1 == ~E_4~0); 17398#L1585-1 assume !(1 == ~E_5~0); 17868#L1590-1 assume !(1 == ~E_6~0); 17426#L1595-1 assume !(1 == ~E_7~0); 17427#L1600-1 assume !(1 == ~E_8~0); 17799#L1605-1 assume !(1 == ~E_9~0); 17800#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 18330#L1615-1 assume !(1 == ~E_11~0); 17248#L1620-1 assume !(1 == ~E_12~0); 17249#L1625-1 assume !(1 == ~E_13~0); 18046#L1630-1 assume !(1 == ~E_14~0); 17425#L1635-1 assume { :end_inline_reset_delta_events } true; 17371#L2017-2 [2023-11-19 07:48:21,233 INFO L750 eck$LassoCheckResult]: Loop: 17371#L2017-2 assume !false; 16642#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16643#L1316-1 assume !false; 17031#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 18041#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16582#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16919#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18065#L1115 assume !(0 != eval_~tmp~0#1); 17596#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17243#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17244#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17650#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18177#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17830#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17831#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18410#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18582#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18574#L1372-3 assume !(0 == ~T7_E~0); 16622#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16623#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17288#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17289#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18225#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18528#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17777#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 16917#L1412-3 assume !(0 == ~E_1~0); 16918#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17679#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17680#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18408#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18085#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17793#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17794#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16686#L1452-3 assume !(0 == ~E_9~0); 16687#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18341#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18342#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18149#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18150#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 16915#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16916#L646-42 assume 1 == ~m_pc~0; 17511#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18380#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17379#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17380#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18512#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18312#L665-42 assume !(1 == ~t1_pc~0); 18272#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 18273#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18487#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17094#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17095#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18581#L684-42 assume 1 == ~t2_pc~0; 17958#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17959#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17710#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17711#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17720#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17856#L703-42 assume 1 == ~t3_pc~0; 18057#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18058#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18121#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18122#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18154#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17760#L722-42 assume 1 == ~t4_pc~0; 17761#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18190#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18186#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17236#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17237#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18548#L741-42 assume !(1 == ~t5_pc~0); 18166#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 17615#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17616#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17787#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17529#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17530#L760-42 assume !(1 == ~t6_pc~0); 17657#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 17806#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17008#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17009#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 17484#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17485#L779-42 assume !(1 == ~t7_pc~0); 18277#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18278#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17814#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17815#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17017#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17018#L798-42 assume 1 == ~t8_pc~0; 17477#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16635#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17976#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17824#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16849#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16850#L817-42 assume 1 == ~t9_pc~0; 17624#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17132#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17133#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18276#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18080#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18081#L836-42 assume 1 == ~t10_pc~0; 18181#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17169#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17170#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17956#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18494#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18536#L855-42 assume 1 == ~t11_pc~0; 18546#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16725#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16726#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18256#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18257#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17347#L874-42 assume !(1 == ~t12_pc~0); 17348#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 17578#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17765#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17766#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16889#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16890#L893-42 assume !(1 == ~t13_pc~0); 17895#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 17896#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17311#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17312#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 17271#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 17272#L912-42 assume 1 == ~t14_pc~0; 18529#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 16592#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 16593#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17385#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 17014#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17015#L1495-3 assume !(1 == ~M_E~0); 17627#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18071#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18167#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17242#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17201#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17202#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17881#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18097#L1530-3 assume !(1 == ~T8_E~0); 17051#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17052#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17090#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18371#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18478#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17499#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 17500#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18128#L1570-3 assume !(1 == ~E_2~0); 18075#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18076#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18440#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18483#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18527#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17906#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17907#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18385#L1610-3 assume !(1 == ~E_10~0); 17252#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17253#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17869#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17870#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 17764#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17185#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16801#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16992#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 16993#L2036 assume !(0 == start_simulation_~tmp~3#1); 18098#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 18262#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 17410#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16638#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 16639#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17807#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18429#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18430#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 17371#L2017-2 [2023-11-19 07:48:21,235 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:21,236 INFO L85 PathProgramCache]: Analyzing trace with hash -723156570, now seen corresponding path program 1 times [2023-11-19 07:48:21,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:21,236 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262552316] [2023-11-19 07:48:21,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:21,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:21,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:21,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:21,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:21,310 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262552316] [2023-11-19 07:48:21,310 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [262552316] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:21,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:21,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:21,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1287763303] [2023-11-19 07:48:21,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:21,312 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:21,312 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:21,312 INFO L85 PathProgramCache]: Analyzing trace with hash 1267461967, now seen corresponding path program 1 times [2023-11-19 07:48:21,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:21,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697002145] [2023-11-19 07:48:21,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:21,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:21,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:21,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:21,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:21,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697002145] [2023-11-19 07:48:21,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697002145] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:21,425 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:21,425 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:21,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [45755722] [2023-11-19 07:48:21,426 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:21,426 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:21,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:21,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:21,427 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:21,427 INFO L87 Difference]: Start difference. First operand 2062 states and 3046 transitions. cyclomatic complexity: 985 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:21,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:21,475 INFO L93 Difference]: Finished difference Result 2062 states and 3045 transitions. [2023-11-19 07:48:21,475 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3045 transitions. [2023-11-19 07:48:21,488 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:21,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3045 transitions. [2023-11-19 07:48:21,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:21,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:21,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3045 transitions. [2023-11-19 07:48:21,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:21,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3045 transitions. [2023-11-19 07:48:21,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3045 transitions. [2023-11-19 07:48:21,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:21,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.476721629485936) internal successors, (3045), 2061 states have internal predecessors, (3045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:21,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3045 transitions. [2023-11-19 07:48:21,559 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3045 transitions. [2023-11-19 07:48:21,559 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:21,562 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3045 transitions. [2023-11-19 07:48:21,562 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:48:21,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3045 transitions. [2023-11-19 07:48:21,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:21,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:21,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:21,575 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:21,575 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:21,576 INFO L748 eck$LassoCheckResult]: Stem: 21026#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 21027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 21958#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21959#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22720#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 21563#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21564#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21276#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21277#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22529#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21855#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21856#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22394#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21761#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21762#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21186#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21187#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21533#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21715#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 20769#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20770#L1342 assume !(0 == ~M_E~0); 20936#L1342-2 assume !(0 == ~T1_E~0); 21500#L1347-1 assume !(0 == ~T2_E~0); 22510#L1352-1 assume !(0 == ~T3_E~0); 22301#L1357-1 assume !(0 == ~T4_E~0); 21522#L1362-1 assume !(0 == ~T5_E~0); 21523#L1367-1 assume !(0 == ~T6_E~0); 21101#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21102#L1377-1 assume !(0 == ~T8_E~0); 21440#L1382-1 assume !(0 == ~T9_E~0); 21441#L1387-1 assume !(0 == ~T10_E~0); 22182#L1392-1 assume !(0 == ~T11_E~0); 21483#L1397-1 assume !(0 == ~T12_E~0); 21484#L1402-1 assume !(0 == ~T13_E~0); 21125#L1407-1 assume !(0 == ~T14_E~0); 21126#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 22426#L1417-1 assume !(0 == ~E_2~0); 22427#L1422-1 assume !(0 == ~E_3~0); 22664#L1427-1 assume !(0 == ~E_4~0); 21305#L1432-1 assume !(0 == ~E_5~0); 21306#L1437-1 assume !(0 == ~E_6~0); 22346#L1442-1 assume !(0 == ~E_7~0); 22347#L1447-1 assume !(0 == ~E_8~0); 22176#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 20905#L1457-1 assume !(0 == ~E_10~0); 20906#L1462-1 assume !(0 == ~E_11~0); 22376#L1467-1 assume !(0 == ~E_12~0); 22389#L1472-1 assume !(0 == ~E_13~0); 22390#L1477-1 assume !(0 == ~E_14~0); 22125#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21090#L646 assume 1 == ~m_pc~0; 21091#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21771#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21786#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21188#L1666 assume !(0 != activate_threads_~tmp~1#1); 21189#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22685#L665 assume !(1 == ~t1_pc~0); 21666#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21667#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22275#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22276#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 22007#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22008#L684 assume 1 == ~t2_pc~0; 22122#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22046#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21174#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21175#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 22515#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22698#L703 assume !(1 == ~t3_pc~0); 21330#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21331#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22262#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20739#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 20740#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21218#L722 assume 1 == ~t4_pc~0; 21965#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21405#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20850#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20851#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 21807#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20937#L741 assume 1 == ~t5_pc~0; 20938#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21240#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22040#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22092#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 22093#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21501#L760 assume !(1 == ~t6_pc~0); 21329#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21328#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21166#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21167#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21922#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21923#L779 assume 1 == ~t7_pc~0; 20974#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20821#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20822#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22547#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 21252#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21253#L798 assume !(1 == ~t8_pc~0); 22557#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22474#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22475#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22639#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 22687#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20800#L817 assume 1 == ~t9_pc~0; 20801#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21599#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21222#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21223#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 21200#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21201#L836 assume !(1 == ~t10_pc~0); 21224#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21150#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21151#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21406#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 21407#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22487#L855 assume 1 == ~t11_pc~0; 21782#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21783#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22370#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22173#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 22013#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21087#L874 assume !(1 == ~t12_pc~0); 21088#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21261#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20789#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20790#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 20775#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20776#L893 assume 1 == ~t13_pc~0; 22622#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21128#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21439#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22570#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 22562#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 22563#L912 assume 1 == ~t14_pc~0; 22353#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 22354#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 22423#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21024#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 21025#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21800#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 22231#L1495-2 assume !(1 == ~T1_E~0); 22232#L1500-1 assume !(1 == ~T2_E~0); 21916#L1505-1 assume !(1 == ~T3_E~0); 21917#L1510-1 assume !(1 == ~T4_E~0); 21975#L1515-1 assume !(1 == ~T5_E~0); 21976#L1520-1 assume !(1 == ~T6_E~0); 22558#L1525-1 assume !(1 == ~T7_E~0); 22263#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21193#L1535-1 assume !(1 == ~T9_E~0); 21194#L1540-1 assume !(1 == ~T10_E~0); 20700#L1545-1 assume !(1 == ~T11_E~0); 20701#L1550-1 assume !(1 == ~T12_E~0); 20947#L1555-1 assume !(1 == ~T13_E~0); 20948#L1560-1 assume !(1 == ~T14_E~0); 21243#L1565-1 assume !(1 == ~E_1~0); 22673#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22146#L1575-1 assume !(1 == ~E_3~0); 21528#L1580-1 assume !(1 == ~E_4~0); 21529#L1585-1 assume !(1 == ~E_5~0); 21999#L1590-1 assume !(1 == ~E_6~0); 21557#L1595-1 assume !(1 == ~E_7~0); 21558#L1600-1 assume !(1 == ~E_8~0); 21930#L1605-1 assume !(1 == ~E_9~0); 21931#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22461#L1615-1 assume !(1 == ~E_11~0); 21379#L1620-1 assume !(1 == ~E_12~0); 21380#L1625-1 assume !(1 == ~E_13~0); 22177#L1630-1 assume !(1 == ~E_14~0); 21556#L1635-1 assume { :end_inline_reset_delta_events } true; 21502#L2017-2 [2023-11-19 07:48:21,576 INFO L750 eck$LassoCheckResult]: Loop: 21502#L2017-2 assume !false; 20773#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20774#L1316-1 assume !false; 21162#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22172#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20713#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 21050#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22196#L1115 assume !(0 != eval_~tmp~0#1); 21727#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21374#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21375#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21781#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22308#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21961#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21962#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22541#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22713#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22705#L1372-3 assume !(0 == ~T7_E~0); 20753#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20754#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21419#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21420#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22356#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22659#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21908#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 21048#L1412-3 assume !(0 == ~E_1~0); 21049#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21810#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21811#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22539#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22216#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21924#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21925#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20817#L1452-3 assume !(0 == ~E_9~0); 20818#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22472#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22473#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22280#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22281#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 21046#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21047#L646-42 assume 1 == ~m_pc~0; 21642#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22511#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21510#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21511#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22643#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22443#L665-42 assume 1 == ~t1_pc~0; 22402#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22404#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22618#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21225#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21226#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22712#L684-42 assume 1 == ~t2_pc~0; 22089#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22090#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21841#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21842#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21851#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21987#L703-42 assume 1 == ~t3_pc~0; 22188#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22189#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22252#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22253#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22285#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21891#L722-42 assume 1 == ~t4_pc~0; 21892#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22321#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22317#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21367#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21368#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22679#L741-42 assume !(1 == ~t5_pc~0); 22297#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 21746#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21747#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21918#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21660#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21661#L760-42 assume !(1 == ~t6_pc~0); 21788#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 21937#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21139#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21140#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 21615#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21616#L779-42 assume !(1 == ~t7_pc~0); 22408#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 22409#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21945#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21946#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21148#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21149#L798-42 assume 1 == ~t8_pc~0; 21608#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20766#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22107#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21955#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20980#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20981#L817-42 assume 1 == ~t9_pc~0; 21755#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21263#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21264#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22407#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22211#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22212#L836-42 assume 1 == ~t10_pc~0; 22312#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21300#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21301#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22087#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22625#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22667#L855-42 assume 1 == ~t11_pc~0; 22677#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20856#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20857#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22387#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22388#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21478#L874-42 assume !(1 == ~t12_pc~0); 21479#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 21710#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21896#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21897#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21020#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21021#L893-42 assume !(1 == ~t13_pc~0); 22026#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 22027#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21442#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21443#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 21402#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 21403#L912-42 assume 1 == ~t14_pc~0; 22660#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 20723#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20724#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21516#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 21145#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21146#L1495-3 assume !(1 == ~M_E~0); 21758#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22202#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22298#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21373#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21332#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21333#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22012#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22228#L1530-3 assume !(1 == ~T8_E~0); 21182#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21183#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21221#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22502#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22609#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21630#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 21631#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22259#L1570-3 assume !(1 == ~E_2~0); 22206#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22207#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22571#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22613#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22658#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22034#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22035#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22516#L1610-3 assume !(1 == ~E_10~0); 21383#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21384#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 22000#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 22001#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 21894#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 21316#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20932#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 21121#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 21122#L2036 assume !(0 == start_simulation_~tmp~3#1); 22229#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22393#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 21541#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 20767#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 20768#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21938#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22560#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22561#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 21502#L2017-2 [2023-11-19 07:48:21,577 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:21,578 INFO L85 PathProgramCache]: Analyzing trace with hash -1293428376, now seen corresponding path program 1 times [2023-11-19 07:48:21,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:21,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897226221] [2023-11-19 07:48:21,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:21,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:21,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:21,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:21,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:21,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897226221] [2023-11-19 07:48:21,701 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [897226221] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:21,701 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:21,701 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:21,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186911051] [2023-11-19 07:48:21,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:21,702 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:21,703 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:21,703 INFO L85 PathProgramCache]: Analyzing trace with hash 596088560, now seen corresponding path program 1 times [2023-11-19 07:48:21,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:21,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054411469] [2023-11-19 07:48:21,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:21,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:21,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:21,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:21,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:21,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054411469] [2023-11-19 07:48:21,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2054411469] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:21,794 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:21,795 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:21,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609245923] [2023-11-19 07:48:21,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:21,796 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:21,796 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:21,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:21,797 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:21,797 INFO L87 Difference]: Start difference. First operand 2062 states and 3045 transitions. cyclomatic complexity: 984 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:21,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:21,843 INFO L93 Difference]: Finished difference Result 2062 states and 3044 transitions. [2023-11-19 07:48:21,843 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3044 transitions. [2023-11-19 07:48:21,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:21,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3044 transitions. [2023-11-19 07:48:21,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:21,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:21,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3044 transitions. [2023-11-19 07:48:21,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:21,880 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3044 transitions. [2023-11-19 07:48:21,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3044 transitions. [2023-11-19 07:48:21,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:21,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4762366634335597) internal successors, (3044), 2061 states have internal predecessors, (3044), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:21,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3044 transitions. [2023-11-19 07:48:21,929 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3044 transitions. [2023-11-19 07:48:21,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:21,931 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3044 transitions. [2023-11-19 07:48:21,932 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:48:21,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3044 transitions. [2023-11-19 07:48:21,942 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:21,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:21,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:21,945 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:21,946 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:21,946 INFO L748 eck$LassoCheckResult]: Stem: 25157#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 25158#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 26089#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26090#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26851#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 25694#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25695#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25407#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25408#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26660#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25986#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25987#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26525#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25892#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25893#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25317#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25318#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25664#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25846#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 24900#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24901#L1342 assume !(0 == ~M_E~0); 25067#L1342-2 assume !(0 == ~T1_E~0); 25631#L1347-1 assume !(0 == ~T2_E~0); 26641#L1352-1 assume !(0 == ~T3_E~0); 26432#L1357-1 assume !(0 == ~T4_E~0); 25653#L1362-1 assume !(0 == ~T5_E~0); 25654#L1367-1 assume !(0 == ~T6_E~0); 25232#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25233#L1377-1 assume !(0 == ~T8_E~0); 25571#L1382-1 assume !(0 == ~T9_E~0); 25572#L1387-1 assume !(0 == ~T10_E~0); 26313#L1392-1 assume !(0 == ~T11_E~0); 25614#L1397-1 assume !(0 == ~T12_E~0); 25615#L1402-1 assume !(0 == ~T13_E~0); 25256#L1407-1 assume !(0 == ~T14_E~0); 25257#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 26557#L1417-1 assume !(0 == ~E_2~0); 26558#L1422-1 assume !(0 == ~E_3~0); 26795#L1427-1 assume !(0 == ~E_4~0); 25436#L1432-1 assume !(0 == ~E_5~0); 25437#L1437-1 assume !(0 == ~E_6~0); 26477#L1442-1 assume !(0 == ~E_7~0); 26478#L1447-1 assume !(0 == ~E_8~0); 26307#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 25036#L1457-1 assume !(0 == ~E_10~0); 25037#L1462-1 assume !(0 == ~E_11~0); 26507#L1467-1 assume !(0 == ~E_12~0); 26520#L1472-1 assume !(0 == ~E_13~0); 26521#L1477-1 assume !(0 == ~E_14~0); 26256#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25221#L646 assume 1 == ~m_pc~0; 25222#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 25902#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25917#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25319#L1666 assume !(0 != activate_threads_~tmp~1#1); 25320#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26816#L665 assume !(1 == ~t1_pc~0); 25797#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25798#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26406#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26407#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 26138#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26139#L684 assume 1 == ~t2_pc~0; 26253#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26177#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25305#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25306#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 26646#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26829#L703 assume !(1 == ~t3_pc~0); 25461#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25462#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26393#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24870#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 24871#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25349#L722 assume 1 == ~t4_pc~0; 26096#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25536#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24981#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24982#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 25938#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25068#L741 assume 1 == ~t5_pc~0; 25069#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25371#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26171#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26223#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 26224#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25632#L760 assume !(1 == ~t6_pc~0); 25460#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25459#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25297#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25298#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26053#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26054#L779 assume 1 == ~t7_pc~0; 25105#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24952#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24953#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26678#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 25383#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25384#L798 assume !(1 == ~t8_pc~0); 26688#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26605#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26606#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26770#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 26818#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24931#L817 assume 1 == ~t9_pc~0; 24932#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25730#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25353#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25354#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 25331#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25332#L836 assume !(1 == ~t10_pc~0); 25355#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25281#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25282#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25537#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 25538#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26618#L855 assume 1 == ~t11_pc~0; 25913#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25914#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26501#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26304#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 26144#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25218#L874 assume !(1 == ~t12_pc~0); 25219#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25392#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24920#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24921#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 24906#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24907#L893 assume 1 == ~t13_pc~0; 26753#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25259#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25570#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26701#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 26693#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 26694#L912 assume 1 == ~t14_pc~0; 26484#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 26485#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 26554#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25155#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 25156#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25931#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 26362#L1495-2 assume !(1 == ~T1_E~0); 26363#L1500-1 assume !(1 == ~T2_E~0); 26047#L1505-1 assume !(1 == ~T3_E~0); 26048#L1510-1 assume !(1 == ~T4_E~0); 26106#L1515-1 assume !(1 == ~T5_E~0); 26107#L1520-1 assume !(1 == ~T6_E~0); 26689#L1525-1 assume !(1 == ~T7_E~0); 26394#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25324#L1535-1 assume !(1 == ~T9_E~0); 25325#L1540-1 assume !(1 == ~T10_E~0); 24831#L1545-1 assume !(1 == ~T11_E~0); 24832#L1550-1 assume !(1 == ~T12_E~0); 25078#L1555-1 assume !(1 == ~T13_E~0); 25079#L1560-1 assume !(1 == ~T14_E~0); 25374#L1565-1 assume !(1 == ~E_1~0); 26804#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 26277#L1575-1 assume !(1 == ~E_3~0); 25659#L1580-1 assume !(1 == ~E_4~0); 25660#L1585-1 assume !(1 == ~E_5~0); 26130#L1590-1 assume !(1 == ~E_6~0); 25688#L1595-1 assume !(1 == ~E_7~0); 25689#L1600-1 assume !(1 == ~E_8~0); 26061#L1605-1 assume !(1 == ~E_9~0); 26062#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26592#L1615-1 assume !(1 == ~E_11~0); 25510#L1620-1 assume !(1 == ~E_12~0); 25511#L1625-1 assume !(1 == ~E_13~0); 26308#L1630-1 assume !(1 == ~E_14~0); 25687#L1635-1 assume { :end_inline_reset_delta_events } true; 25633#L2017-2 [2023-11-19 07:48:21,947 INFO L750 eck$LassoCheckResult]: Loop: 25633#L2017-2 assume !false; 24904#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24905#L1316-1 assume !false; 25293#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26303#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 24844#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 25181#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26327#L1115 assume !(0 != eval_~tmp~0#1); 25858#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25505#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25506#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25912#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26439#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26092#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26093#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26672#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26844#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26836#L1372-3 assume !(0 == ~T7_E~0); 24884#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24885#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25550#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25551#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26487#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26790#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 26039#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 25179#L1412-3 assume !(0 == ~E_1~0); 25180#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25941#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25942#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26670#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26348#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26055#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26056#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24948#L1452-3 assume !(0 == ~E_9~0); 24949#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26603#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26604#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26411#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26412#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 25177#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25178#L646-42 assume 1 == ~m_pc~0; 25773#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 26642#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25641#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25642#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26774#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26574#L665-42 assume 1 == ~t1_pc~0; 26533#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26535#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26749#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25356#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25357#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26843#L684-42 assume 1 == ~t2_pc~0; 26220#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26221#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25972#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25973#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25982#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26118#L703-42 assume !(1 == ~t3_pc~0); 26321#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 26320#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26383#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26384#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26416#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26022#L722-42 assume 1 == ~t4_pc~0; 26023#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26452#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26448#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25498#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25499#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26810#L741-42 assume 1 == ~t5_pc~0; 26754#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25877#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25878#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26049#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25791#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25792#L760-42 assume 1 == ~t6_pc~0; 25920#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26068#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25270#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25271#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 25746#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25747#L779-42 assume 1 == ~t7_pc~0; 26593#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26540#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26076#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26077#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25279#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25280#L798-42 assume !(1 == ~t8_pc~0); 24896#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 24897#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26238#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26086#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25111#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25112#L817-42 assume 1 == ~t9_pc~0; 25886#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25394#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25395#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26538#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26342#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26343#L836-42 assume 1 == ~t10_pc~0; 26443#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25431#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25432#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26218#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26756#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26798#L855-42 assume 1 == ~t11_pc~0; 26808#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24987#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24988#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26518#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26519#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25609#L874-42 assume !(1 == ~t12_pc~0); 25610#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25841#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26027#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26028#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25151#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25152#L893-42 assume 1 == ~t13_pc~0; 26368#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 26156#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25573#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25574#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 25533#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 25534#L912-42 assume 1 == ~t14_pc~0; 26791#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 24852#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 24853#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25647#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 25276#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25277#L1495-3 assume !(1 == ~M_E~0); 25889#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26333#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26429#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25503#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25463#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25464#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26143#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26359#L1530-3 assume !(1 == ~T8_E~0); 25313#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25314#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25352#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26633#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26740#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25761#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 25762#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26387#L1570-3 assume !(1 == ~E_2~0); 26337#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26338#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26702#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26744#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26789#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26165#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26166#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26647#L1610-3 assume !(1 == ~E_10~0); 25514#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25515#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26131#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 26132#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 26025#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 25447#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 25063#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 25252#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 25253#L2036 assume !(0 == start_simulation_~tmp~3#1); 26360#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26524#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 25672#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 24898#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 24899#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26069#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26691#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26692#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 25633#L2017-2 [2023-11-19 07:48:21,948 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:21,948 INFO L85 PathProgramCache]: Analyzing trace with hash 1597669734, now seen corresponding path program 1 times [2023-11-19 07:48:21,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:21,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570015726] [2023-11-19 07:48:21,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:21,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:21,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:22,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:22,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:22,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1570015726] [2023-11-19 07:48:22,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1570015726] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:22,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:22,017 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:22,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282696676] [2023-11-19 07:48:22,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:22,018 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:22,018 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:22,019 INFO L85 PathProgramCache]: Analyzing trace with hash -1259144270, now seen corresponding path program 1 times [2023-11-19 07:48:22,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:22,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104396310] [2023-11-19 07:48:22,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:22,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:22,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:22,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:22,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:22,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104396310] [2023-11-19 07:48:22,110 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2104396310] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:22,110 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:22,110 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:22,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1616297142] [2023-11-19 07:48:22,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:22,111 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:22,111 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:22,112 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:22,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:22,112 INFO L87 Difference]: Start difference. First operand 2062 states and 3044 transitions. cyclomatic complexity: 983 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:22,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:22,163 INFO L93 Difference]: Finished difference Result 2062 states and 3043 transitions. [2023-11-19 07:48:22,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3043 transitions. [2023-11-19 07:48:22,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:22,194 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3043 transitions. [2023-11-19 07:48:22,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:22,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:22,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3043 transitions. [2023-11-19 07:48:22,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:22,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3043 transitions. [2023-11-19 07:48:22,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3043 transitions. [2023-11-19 07:48:22,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:22,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4757516973811833) internal successors, (3043), 2061 states have internal predecessors, (3043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:22,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3043 transitions. [2023-11-19 07:48:22,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3043 transitions. [2023-11-19 07:48:22,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:22,295 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3043 transitions. [2023-11-19 07:48:22,295 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:48:22,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3043 transitions. [2023-11-19 07:48:22,308 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:22,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:22,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:22,312 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:22,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:22,313 INFO L748 eck$LassoCheckResult]: Stem: 29288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 29289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 30220#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30221#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30982#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 29825#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29826#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29538#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29539#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30791#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30117#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30118#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30656#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30023#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30024#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29448#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29449#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29795#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29977#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 29031#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29032#L1342 assume !(0 == ~M_E~0); 29198#L1342-2 assume !(0 == ~T1_E~0); 29762#L1347-1 assume !(0 == ~T2_E~0); 30772#L1352-1 assume !(0 == ~T3_E~0); 30563#L1357-1 assume !(0 == ~T4_E~0); 29784#L1362-1 assume !(0 == ~T5_E~0); 29785#L1367-1 assume !(0 == ~T6_E~0); 29363#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29364#L1377-1 assume !(0 == ~T8_E~0); 29702#L1382-1 assume !(0 == ~T9_E~0); 29703#L1387-1 assume !(0 == ~T10_E~0); 30444#L1392-1 assume !(0 == ~T11_E~0); 29745#L1397-1 assume !(0 == ~T12_E~0); 29746#L1402-1 assume !(0 == ~T13_E~0); 29387#L1407-1 assume !(0 == ~T14_E~0); 29388#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 30688#L1417-1 assume !(0 == ~E_2~0); 30689#L1422-1 assume !(0 == ~E_3~0); 30926#L1427-1 assume !(0 == ~E_4~0); 29567#L1432-1 assume !(0 == ~E_5~0); 29568#L1437-1 assume !(0 == ~E_6~0); 30608#L1442-1 assume !(0 == ~E_7~0); 30609#L1447-1 assume !(0 == ~E_8~0); 30438#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 29167#L1457-1 assume !(0 == ~E_10~0); 29168#L1462-1 assume !(0 == ~E_11~0); 30638#L1467-1 assume !(0 == ~E_12~0); 30651#L1472-1 assume !(0 == ~E_13~0); 30652#L1477-1 assume !(0 == ~E_14~0); 30387#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29352#L646 assume 1 == ~m_pc~0; 29353#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30033#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30048#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29450#L1666 assume !(0 != activate_threads_~tmp~1#1); 29451#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30947#L665 assume !(1 == ~t1_pc~0); 29928#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29929#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30537#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30538#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 30269#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30270#L684 assume 1 == ~t2_pc~0; 30384#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30308#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29436#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29437#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 30777#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30960#L703 assume !(1 == ~t3_pc~0); 29592#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29593#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30524#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29001#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 29002#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29480#L722 assume 1 == ~t4_pc~0; 30227#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29667#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29112#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29113#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 30069#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29199#L741 assume 1 == ~t5_pc~0; 29200#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29502#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30302#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30354#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 30355#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29763#L760 assume !(1 == ~t6_pc~0); 29591#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29590#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29428#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29429#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30184#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30185#L779 assume 1 == ~t7_pc~0; 29236#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29083#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29084#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30809#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 29514#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29515#L798 assume !(1 == ~t8_pc~0); 30819#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30736#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30737#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30901#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 30949#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29062#L817 assume 1 == ~t9_pc~0; 29063#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29861#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29484#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29485#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 29462#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29463#L836 assume !(1 == ~t10_pc~0); 29486#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29412#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29413#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29668#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 29669#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30749#L855 assume 1 == ~t11_pc~0; 30044#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30045#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30632#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30435#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 30275#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29349#L874 assume !(1 == ~t12_pc~0); 29350#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29523#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29051#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29052#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 29037#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29038#L893 assume 1 == ~t13_pc~0; 30884#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29390#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29701#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30832#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 30824#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 30825#L912 assume 1 == ~t14_pc~0; 30615#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 30616#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 30685#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29286#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 29287#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30062#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 30493#L1495-2 assume !(1 == ~T1_E~0); 30494#L1500-1 assume !(1 == ~T2_E~0); 30178#L1505-1 assume !(1 == ~T3_E~0); 30179#L1510-1 assume !(1 == ~T4_E~0); 30237#L1515-1 assume !(1 == ~T5_E~0); 30238#L1520-1 assume !(1 == ~T6_E~0); 30820#L1525-1 assume !(1 == ~T7_E~0); 30525#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29455#L1535-1 assume !(1 == ~T9_E~0); 29456#L1540-1 assume !(1 == ~T10_E~0); 28962#L1545-1 assume !(1 == ~T11_E~0); 28963#L1550-1 assume !(1 == ~T12_E~0); 29209#L1555-1 assume !(1 == ~T13_E~0); 29210#L1560-1 assume !(1 == ~T14_E~0); 29505#L1565-1 assume !(1 == ~E_1~0); 30935#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30408#L1575-1 assume !(1 == ~E_3~0); 29790#L1580-1 assume !(1 == ~E_4~0); 29791#L1585-1 assume !(1 == ~E_5~0); 30261#L1590-1 assume !(1 == ~E_6~0); 29819#L1595-1 assume !(1 == ~E_7~0); 29820#L1600-1 assume !(1 == ~E_8~0); 30192#L1605-1 assume !(1 == ~E_9~0); 30193#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30723#L1615-1 assume !(1 == ~E_11~0); 29641#L1620-1 assume !(1 == ~E_12~0); 29642#L1625-1 assume !(1 == ~E_13~0); 30439#L1630-1 assume !(1 == ~E_14~0); 29818#L1635-1 assume { :end_inline_reset_delta_events } true; 29764#L2017-2 [2023-11-19 07:48:22,314 INFO L750 eck$LassoCheckResult]: Loop: 29764#L2017-2 assume !false; 29035#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29036#L1316-1 assume !false; 29424#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30434#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28975#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29312#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30458#L1115 assume !(0 != eval_~tmp~0#1); 29991#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29636#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29637#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30043#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30570#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30223#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30224#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30803#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30975#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30967#L1372-3 assume !(0 == ~T7_E~0); 29015#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29016#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29681#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29682#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30618#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 30921#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30170#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 29310#L1412-3 assume !(0 == ~E_1~0); 29311#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30072#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30073#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30801#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30481#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30186#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30187#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29079#L1452-3 assume !(0 == ~E_9~0); 29080#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30734#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30735#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 30542#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30543#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 29308#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29309#L646-42 assume 1 == ~m_pc~0; 29904#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30773#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29772#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29773#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30905#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30705#L665-42 assume 1 == ~t1_pc~0; 30664#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30666#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30880#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29487#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29488#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30974#L684-42 assume !(1 == ~t2_pc~0); 30353#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 30352#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30103#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30104#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30113#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30249#L703-42 assume 1 == ~t3_pc~0; 30450#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30451#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30514#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30515#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30547#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30153#L722-42 assume 1 == ~t4_pc~0; 30154#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30583#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30579#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29629#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29630#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30941#L741-42 assume 1 == ~t5_pc~0; 30885#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30008#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30009#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30180#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29922#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29923#L760-42 assume !(1 == ~t6_pc~0); 30050#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 30199#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29401#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29402#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 29877#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29878#L779-42 assume 1 == ~t7_pc~0; 30724#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30671#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30207#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30208#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29410#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29411#L798-42 assume !(1 == ~t8_pc~0); 29027#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 29028#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30369#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30217#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29242#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29243#L817-42 assume 1 == ~t9_pc~0; 30017#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29525#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29526#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30669#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30473#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30474#L836-42 assume 1 == ~t10_pc~0; 30574#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 29562#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29563#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30349#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30887#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30929#L855-42 assume 1 == ~t11_pc~0; 30939#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29118#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29119#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30648#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30649#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29737#L874-42 assume !(1 == ~t12_pc~0); 29738#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 29967#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30158#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30159#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29282#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29283#L893-42 assume 1 == ~t13_pc~0; 30499#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30287#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29704#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29705#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 29664#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 29665#L912-42 assume 1 == ~t14_pc~0; 30922#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 28983#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 28984#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29778#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 29407#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29408#L1495-3 assume !(1 == ~M_E~0); 30020#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30464#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30560#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29634#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29594#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29595#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30274#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30490#L1530-3 assume !(1 == ~T8_E~0); 29444#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29445#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29483#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30764#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30871#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29892#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 29893#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30519#L1570-3 assume !(1 == ~E_2~0); 30468#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30469#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30833#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30875#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30920#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30296#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30297#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30778#L1610-3 assume !(1 == ~E_10~0); 29645#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29646#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30262#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 30263#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 30156#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 29578#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29194#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29383#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29384#L2036 assume !(0 == start_simulation_~tmp~3#1); 30491#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30655#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29803#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29029#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 29030#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30200#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30822#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30823#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 29764#L2017-2 [2023-11-19 07:48:22,315 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:22,316 INFO L85 PathProgramCache]: Analyzing trace with hash -1911299672, now seen corresponding path program 1 times [2023-11-19 07:48:22,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:22,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158012863] [2023-11-19 07:48:22,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:22,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:22,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:22,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:22,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:22,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158012863] [2023-11-19 07:48:22,407 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [158012863] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:22,407 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:22,407 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:22,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842465014] [2023-11-19 07:48:22,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:22,411 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:22,416 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:22,416 INFO L85 PathProgramCache]: Analyzing trace with hash 712511761, now seen corresponding path program 1 times [2023-11-19 07:48:22,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:22,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363128182] [2023-11-19 07:48:22,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:22,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:22,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:22,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:22,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:22,535 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [363128182] [2023-11-19 07:48:22,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [363128182] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:22,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:22,538 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:22,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590544178] [2023-11-19 07:48:22,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:22,539 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:22,539 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:22,539 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:22,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:22,540 INFO L87 Difference]: Start difference. First operand 2062 states and 3043 transitions. cyclomatic complexity: 982 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:22,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:22,591 INFO L93 Difference]: Finished difference Result 2062 states and 3042 transitions. [2023-11-19 07:48:22,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3042 transitions. [2023-11-19 07:48:22,603 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:22,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3042 transitions. [2023-11-19 07:48:22,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:22,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:22,622 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3042 transitions. [2023-11-19 07:48:22,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:22,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3042 transitions. [2023-11-19 07:48:22,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3042 transitions. [2023-11-19 07:48:22,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:22,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.475266731328807) internal successors, (3042), 2061 states have internal predecessors, (3042), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:22,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3042 transitions. [2023-11-19 07:48:22,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3042 transitions. [2023-11-19 07:48:22,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:22,678 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3042 transitions. [2023-11-19 07:48:22,678 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:48:22,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3042 transitions. [2023-11-19 07:48:22,688 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:22,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:22,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:22,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:22,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:22,692 INFO L748 eck$LassoCheckResult]: Stem: 33419#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 33420#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 34351#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34352#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35113#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 33956#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33957#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33669#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33670#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34922#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34248#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34249#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34787#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 34154#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34155#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33579#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33580#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33926#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 34108#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 33162#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33163#L1342 assume !(0 == ~M_E~0); 33329#L1342-2 assume !(0 == ~T1_E~0); 33893#L1347-1 assume !(0 == ~T2_E~0); 34903#L1352-1 assume !(0 == ~T3_E~0); 34694#L1357-1 assume !(0 == ~T4_E~0); 33915#L1362-1 assume !(0 == ~T5_E~0); 33916#L1367-1 assume !(0 == ~T6_E~0); 33494#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33495#L1377-1 assume !(0 == ~T8_E~0); 33833#L1382-1 assume !(0 == ~T9_E~0); 33834#L1387-1 assume !(0 == ~T10_E~0); 34575#L1392-1 assume !(0 == ~T11_E~0); 33876#L1397-1 assume !(0 == ~T12_E~0); 33877#L1402-1 assume !(0 == ~T13_E~0); 33518#L1407-1 assume !(0 == ~T14_E~0); 33519#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 34819#L1417-1 assume !(0 == ~E_2~0); 34820#L1422-1 assume !(0 == ~E_3~0); 35057#L1427-1 assume !(0 == ~E_4~0); 33698#L1432-1 assume !(0 == ~E_5~0); 33699#L1437-1 assume !(0 == ~E_6~0); 34739#L1442-1 assume !(0 == ~E_7~0); 34740#L1447-1 assume !(0 == ~E_8~0); 34569#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 33298#L1457-1 assume !(0 == ~E_10~0); 33299#L1462-1 assume !(0 == ~E_11~0); 34769#L1467-1 assume !(0 == ~E_12~0); 34782#L1472-1 assume !(0 == ~E_13~0); 34783#L1477-1 assume !(0 == ~E_14~0); 34518#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33483#L646 assume 1 == ~m_pc~0; 33484#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34164#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34179#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33581#L1666 assume !(0 != activate_threads_~tmp~1#1); 33582#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35078#L665 assume !(1 == ~t1_pc~0); 34059#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34060#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34668#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34669#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 34400#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34401#L684 assume 1 == ~t2_pc~0; 34515#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34441#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33567#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33568#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 34908#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35091#L703 assume !(1 == ~t3_pc~0); 33723#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33724#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34655#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33132#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 33133#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33611#L722 assume 1 == ~t4_pc~0; 34358#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33798#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33243#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33244#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 34200#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33330#L741 assume 1 == ~t5_pc~0; 33331#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33633#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34433#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34485#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 34486#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33894#L760 assume !(1 == ~t6_pc~0); 33722#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33721#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33559#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33560#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34315#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34316#L779 assume 1 == ~t7_pc~0; 33367#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33214#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33215#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34940#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 33645#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33646#L798 assume !(1 == ~t8_pc~0); 34950#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34867#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34868#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35032#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 35080#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33193#L817 assume 1 == ~t9_pc~0; 33194#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33992#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33615#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33616#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 33593#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33594#L836 assume !(1 == ~t10_pc~0); 33617#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33543#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33544#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33799#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 33800#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34880#L855 assume 1 == ~t11_pc~0; 34175#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34176#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34763#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34566#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 34406#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33480#L874 assume !(1 == ~t12_pc~0); 33481#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33654#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33182#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33183#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 33168#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33169#L893 assume 1 == ~t13_pc~0; 35015#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33521#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33832#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34963#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 34955#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 34956#L912 assume 1 == ~t14_pc~0; 34746#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 34747#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 34816#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33417#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 33418#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34193#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 34624#L1495-2 assume !(1 == ~T1_E~0); 34625#L1500-1 assume !(1 == ~T2_E~0); 34309#L1505-1 assume !(1 == ~T3_E~0); 34310#L1510-1 assume !(1 == ~T4_E~0); 34368#L1515-1 assume !(1 == ~T5_E~0); 34369#L1520-1 assume !(1 == ~T6_E~0); 34951#L1525-1 assume !(1 == ~T7_E~0); 34656#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33586#L1535-1 assume !(1 == ~T9_E~0); 33587#L1540-1 assume !(1 == ~T10_E~0); 33093#L1545-1 assume !(1 == ~T11_E~0); 33094#L1550-1 assume !(1 == ~T12_E~0); 33340#L1555-1 assume !(1 == ~T13_E~0); 33341#L1560-1 assume !(1 == ~T14_E~0); 33636#L1565-1 assume !(1 == ~E_1~0); 35066#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34539#L1575-1 assume !(1 == ~E_3~0); 33921#L1580-1 assume !(1 == ~E_4~0); 33922#L1585-1 assume !(1 == ~E_5~0); 34392#L1590-1 assume !(1 == ~E_6~0); 33950#L1595-1 assume !(1 == ~E_7~0); 33951#L1600-1 assume !(1 == ~E_8~0); 34323#L1605-1 assume !(1 == ~E_9~0); 34324#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 34854#L1615-1 assume !(1 == ~E_11~0); 33772#L1620-1 assume !(1 == ~E_12~0); 33773#L1625-1 assume !(1 == ~E_13~0); 34570#L1630-1 assume !(1 == ~E_14~0); 33949#L1635-1 assume { :end_inline_reset_delta_events } true; 33895#L2017-2 [2023-11-19 07:48:22,693 INFO L750 eck$LassoCheckResult]: Loop: 33895#L2017-2 assume !false; 33166#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33167#L1316-1 assume !false; 33555#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34565#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33106#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33443#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34589#L1115 assume !(0 != eval_~tmp~0#1); 34122#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33767#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33768#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34174#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34701#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34354#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34355#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34934#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35106#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35098#L1372-3 assume !(0 == ~T7_E~0); 33146#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33147#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33812#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33813#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34749#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35052#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34301#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 33441#L1412-3 assume !(0 == ~E_1~0); 33442#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34203#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34204#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34932#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34612#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34317#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34318#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33210#L1452-3 assume !(0 == ~E_9~0); 33211#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34865#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34866#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 34673#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34674#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 33439#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33440#L646-42 assume 1 == ~m_pc~0; 34035#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34904#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33903#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33904#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35036#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34836#L665-42 assume 1 == ~t1_pc~0; 34795#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34797#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35011#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33618#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33619#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35105#L684-42 assume 1 == ~t2_pc~0; 34482#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34483#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34234#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34235#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34244#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34380#L703-42 assume 1 == ~t3_pc~0; 34581#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34582#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34645#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34646#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34678#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34284#L722-42 assume 1 == ~t4_pc~0; 34285#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34714#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34710#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33760#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33761#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35072#L741-42 assume !(1 == ~t5_pc~0); 34690#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 34139#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34140#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34311#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34053#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34054#L760-42 assume !(1 == ~t6_pc~0); 34181#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34330#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33532#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33533#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 34008#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34009#L779-42 assume !(1 == ~t7_pc~0); 34801#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 34802#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34338#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34339#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33541#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33542#L798-42 assume 1 == ~t8_pc~0; 34001#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33159#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34500#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34348#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33373#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33374#L817-42 assume 1 == ~t9_pc~0; 34148#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33656#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33657#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34800#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34604#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34605#L836-42 assume 1 == ~t10_pc~0; 34705#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33693#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33694#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34480#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35018#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35060#L855-42 assume 1 == ~t11_pc~0; 35070#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33247#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33248#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34779#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34780#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33868#L874-42 assume !(1 == ~t12_pc~0); 33869#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 34098#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34289#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34290#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33413#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33414#L893-42 assume !(1 == ~t13_pc~0); 34417#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 34418#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33835#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33836#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 33795#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 33796#L912-42 assume !(1 == ~t14_pc~0); 34608#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 33114#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 33115#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33909#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 33538#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33539#L1495-3 assume !(1 == ~M_E~0); 34151#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34595#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34691#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33765#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33725#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33726#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34405#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34621#L1530-3 assume !(1 == ~T8_E~0); 33575#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33576#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33614#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34895#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35002#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34023#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 34024#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34650#L1570-3 assume !(1 == ~E_2~0); 34599#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34600#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34964#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35006#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35051#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34427#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34428#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34909#L1610-3 assume !(1 == ~E_10~0); 33776#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33777#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34393#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 34394#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 34287#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 33709#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33325#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33514#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 33515#L2036 assume !(0 == start_simulation_~tmp~3#1); 34622#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34786#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33934#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33160#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 33161#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34331#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34953#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34954#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 33895#L2017-2 [2023-11-19 07:48:22,694 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:22,694 INFO L85 PathProgramCache]: Analyzing trace with hash 1716285734, now seen corresponding path program 1 times [2023-11-19 07:48:22,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:22,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8835842] [2023-11-19 07:48:22,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:22,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:22,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:22,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:22,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:22,756 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [8835842] [2023-11-19 07:48:22,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [8835842] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:22,756 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:22,757 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:22,757 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439983294] [2023-11-19 07:48:22,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:22,758 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:22,758 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:22,758 INFO L85 PathProgramCache]: Analyzing trace with hash 2028923279, now seen corresponding path program 1 times [2023-11-19 07:48:22,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:22,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617578334] [2023-11-19 07:48:22,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:22,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:22,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:22,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:22,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:22,841 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617578334] [2023-11-19 07:48:22,841 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617578334] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:22,841 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:22,841 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:22,842 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319032448] [2023-11-19 07:48:22,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:22,842 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:22,842 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:22,843 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:22,843 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:22,843 INFO L87 Difference]: Start difference. First operand 2062 states and 3042 transitions. cyclomatic complexity: 981 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:22,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:22,889 INFO L93 Difference]: Finished difference Result 2062 states and 3041 transitions. [2023-11-19 07:48:22,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3041 transitions. [2023-11-19 07:48:22,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:22,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3041 transitions. [2023-11-19 07:48:22,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:22,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:22,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3041 transitions. [2023-11-19 07:48:22,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:22,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3041 transitions. [2023-11-19 07:48:22,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3041 transitions. [2023-11-19 07:48:22,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:22,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4747817652764306) internal successors, (3041), 2061 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:22,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3041 transitions. [2023-11-19 07:48:22,996 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3041 transitions. [2023-11-19 07:48:22,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:22,998 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3041 transitions. [2023-11-19 07:48:22,998 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:48:22,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3041 transitions. [2023-11-19 07:48:23,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:23,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:23,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:23,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:23,012 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:23,012 INFO L748 eck$LassoCheckResult]: Stem: 37550#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 37551#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 38482#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38483#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39244#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 38087#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38088#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37800#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37801#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39053#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38379#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38380#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38918#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38285#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38286#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37710#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37711#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38057#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38239#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 37293#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37294#L1342 assume !(0 == ~M_E~0); 37460#L1342-2 assume !(0 == ~T1_E~0); 38024#L1347-1 assume !(0 == ~T2_E~0); 39034#L1352-1 assume !(0 == ~T3_E~0); 38825#L1357-1 assume !(0 == ~T4_E~0); 38046#L1362-1 assume !(0 == ~T5_E~0); 38047#L1367-1 assume !(0 == ~T6_E~0); 37625#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37626#L1377-1 assume !(0 == ~T8_E~0); 37964#L1382-1 assume !(0 == ~T9_E~0); 37965#L1387-1 assume !(0 == ~T10_E~0); 38706#L1392-1 assume !(0 == ~T11_E~0); 38007#L1397-1 assume !(0 == ~T12_E~0); 38008#L1402-1 assume !(0 == ~T13_E~0); 37649#L1407-1 assume !(0 == ~T14_E~0); 37650#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 38950#L1417-1 assume !(0 == ~E_2~0); 38951#L1422-1 assume !(0 == ~E_3~0); 39188#L1427-1 assume !(0 == ~E_4~0); 37829#L1432-1 assume !(0 == ~E_5~0); 37830#L1437-1 assume !(0 == ~E_6~0); 38870#L1442-1 assume !(0 == ~E_7~0); 38871#L1447-1 assume !(0 == ~E_8~0); 38700#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 37429#L1457-1 assume !(0 == ~E_10~0); 37430#L1462-1 assume !(0 == ~E_11~0); 38900#L1467-1 assume !(0 == ~E_12~0); 38913#L1472-1 assume !(0 == ~E_13~0); 38914#L1477-1 assume !(0 == ~E_14~0); 38649#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37614#L646 assume 1 == ~m_pc~0; 37615#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38295#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38310#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37712#L1666 assume !(0 != activate_threads_~tmp~1#1); 37713#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39209#L665 assume !(1 == ~t1_pc~0); 38190#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38191#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38799#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38800#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 38531#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38532#L684 assume 1 == ~t2_pc~0; 38646#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38572#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37698#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37699#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 39039#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39222#L703 assume !(1 == ~t3_pc~0); 37854#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37855#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38786#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37263#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 37264#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37742#L722 assume 1 == ~t4_pc~0; 38489#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37929#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37374#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37375#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 38331#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37461#L741 assume 1 == ~t5_pc~0; 37462#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37764#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38564#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38616#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 38617#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38025#L760 assume !(1 == ~t6_pc~0); 37853#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37852#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37690#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37691#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38446#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38447#L779 assume 1 == ~t7_pc~0; 37498#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37345#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37346#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39071#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 37776#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37777#L798 assume !(1 == ~t8_pc~0); 39081#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 38998#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38999#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39163#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 39211#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37324#L817 assume 1 == ~t9_pc~0; 37325#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38123#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37746#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37747#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 37724#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37725#L836 assume !(1 == ~t10_pc~0); 37748#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37674#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37675#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37930#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 37931#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39011#L855 assume 1 == ~t11_pc~0; 38306#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38307#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38894#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38697#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 38537#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37611#L874 assume !(1 == ~t12_pc~0); 37612#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37785#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37313#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37314#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 37299#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37300#L893 assume 1 == ~t13_pc~0; 39146#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37652#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37963#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 39094#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 39086#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 39087#L912 assume 1 == ~t14_pc~0; 38877#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 38878#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 38947#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37548#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 37549#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38324#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 38755#L1495-2 assume !(1 == ~T1_E~0); 38756#L1500-1 assume !(1 == ~T2_E~0); 38440#L1505-1 assume !(1 == ~T3_E~0); 38441#L1510-1 assume !(1 == ~T4_E~0); 38499#L1515-1 assume !(1 == ~T5_E~0); 38500#L1520-1 assume !(1 == ~T6_E~0); 39082#L1525-1 assume !(1 == ~T7_E~0); 38787#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37717#L1535-1 assume !(1 == ~T9_E~0); 37718#L1540-1 assume !(1 == ~T10_E~0); 37224#L1545-1 assume !(1 == ~T11_E~0); 37225#L1550-1 assume !(1 == ~T12_E~0); 37471#L1555-1 assume !(1 == ~T13_E~0); 37472#L1560-1 assume !(1 == ~T14_E~0); 37767#L1565-1 assume !(1 == ~E_1~0); 39197#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 38670#L1575-1 assume !(1 == ~E_3~0); 38052#L1580-1 assume !(1 == ~E_4~0); 38053#L1585-1 assume !(1 == ~E_5~0); 38523#L1590-1 assume !(1 == ~E_6~0); 38081#L1595-1 assume !(1 == ~E_7~0); 38082#L1600-1 assume !(1 == ~E_8~0); 38454#L1605-1 assume !(1 == ~E_9~0); 38455#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 38985#L1615-1 assume !(1 == ~E_11~0); 37903#L1620-1 assume !(1 == ~E_12~0); 37904#L1625-1 assume !(1 == ~E_13~0); 38701#L1630-1 assume !(1 == ~E_14~0); 38080#L1635-1 assume { :end_inline_reset_delta_events } true; 38026#L2017-2 [2023-11-19 07:48:23,013 INFO L750 eck$LassoCheckResult]: Loop: 38026#L2017-2 assume !false; 37297#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37298#L1316-1 assume !false; 37686#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38696#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37237#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37574#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38720#L1115 assume !(0 != eval_~tmp~0#1); 38253#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37898#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37899#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38305#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38832#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38485#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38486#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39065#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39237#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39229#L1372-3 assume !(0 == ~T7_E~0); 37277#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37278#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37943#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37944#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38880#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39183#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38432#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 37572#L1412-3 assume !(0 == ~E_1~0); 37573#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38334#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38335#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39063#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38743#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38448#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38449#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37341#L1452-3 assume !(0 == ~E_9~0); 37342#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38996#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38997#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 38804#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38805#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 37570#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37571#L646-42 assume 1 == ~m_pc~0; 38166#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39035#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38034#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38035#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39167#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38967#L665-42 assume 1 == ~t1_pc~0; 38926#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38928#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39142#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37749#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37750#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39236#L684-42 assume 1 == ~t2_pc~0; 38613#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38614#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38365#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38366#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38375#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38511#L703-42 assume 1 == ~t3_pc~0; 38712#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38713#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38776#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38777#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38809#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38415#L722-42 assume 1 == ~t4_pc~0; 38416#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38845#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38841#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37891#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37892#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39203#L741-42 assume !(1 == ~t5_pc~0); 38821#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 38270#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38271#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38442#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38184#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38185#L760-42 assume !(1 == ~t6_pc~0); 38312#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 38461#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37663#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37664#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 38139#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38140#L779-42 assume !(1 == ~t7_pc~0); 38932#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 38933#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38469#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38470#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37672#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37673#L798-42 assume 1 == ~t8_pc~0; 38132#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37290#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38631#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38479#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37504#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37505#L817-42 assume 1 == ~t9_pc~0; 38279#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37787#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37788#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38931#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38735#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38736#L836-42 assume 1 == ~t10_pc~0; 38837#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37824#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37825#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38610#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39148#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39191#L855-42 assume 1 == ~t11_pc~0; 39201#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37378#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37379#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38910#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38911#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37999#L874-42 assume !(1 == ~t12_pc~0); 38000#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 38229#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38420#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38421#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37544#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37545#L893-42 assume !(1 == ~t13_pc~0); 38550#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 38551#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37966#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37967#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 37926#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 37927#L912-42 assume 1 == ~t14_pc~0; 39184#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 37245#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 37246#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38040#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 37669#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37670#L1495-3 assume !(1 == ~M_E~0); 38282#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38726#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38822#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37896#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37856#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37857#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38536#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38752#L1530-3 assume !(1 == ~T8_E~0); 37706#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37707#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37745#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39026#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39133#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38154#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 38155#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38782#L1570-3 assume !(1 == ~E_2~0); 38730#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38731#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39095#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39137#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39182#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38558#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38559#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39040#L1610-3 assume !(1 == ~E_10~0); 37907#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37908#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38524#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38525#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 38418#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 37840#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37456#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37645#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37646#L2036 assume !(0 == start_simulation_~tmp~3#1); 38753#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38917#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 38065#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37291#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 37292#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38462#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39084#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 39085#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 38026#L2017-2 [2023-11-19 07:48:23,015 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:23,015 INFO L85 PathProgramCache]: Analyzing trace with hash -383452696, now seen corresponding path program 1 times [2023-11-19 07:48:23,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:23,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601392539] [2023-11-19 07:48:23,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:23,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:23,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:23,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:23,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:23,114 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601392539] [2023-11-19 07:48:23,114 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601392539] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:23,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:23,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:23,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936373905] [2023-11-19 07:48:23,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:23,117 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:23,117 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:23,117 INFO L85 PathProgramCache]: Analyzing trace with hash 596088560, now seen corresponding path program 2 times [2023-11-19 07:48:23,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:23,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452515651] [2023-11-19 07:48:23,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:23,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:23,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:23,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:23,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:23,213 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1452515651] [2023-11-19 07:48:23,213 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1452515651] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:23,214 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:23,214 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:23,214 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406525410] [2023-11-19 07:48:23,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:23,215 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:23,215 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:23,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:23,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:23,216 INFO L87 Difference]: Start difference. First operand 2062 states and 3041 transitions. cyclomatic complexity: 980 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:23,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:23,262 INFO L93 Difference]: Finished difference Result 2062 states and 3040 transitions. [2023-11-19 07:48:23,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3040 transitions. [2023-11-19 07:48:23,273 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:23,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3040 transitions. [2023-11-19 07:48:23,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:23,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:23,288 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3040 transitions. [2023-11-19 07:48:23,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:23,291 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3040 transitions. [2023-11-19 07:48:23,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3040 transitions. [2023-11-19 07:48:23,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:23,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4742967992240543) internal successors, (3040), 2061 states have internal predecessors, (3040), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:23,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3040 transitions. [2023-11-19 07:48:23,338 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3040 transitions. [2023-11-19 07:48:23,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:23,339 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3040 transitions. [2023-11-19 07:48:23,339 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:48:23,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3040 transitions. [2023-11-19 07:48:23,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:23,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:23,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:23,352 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:23,352 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:23,353 INFO L748 eck$LassoCheckResult]: Stem: 41681#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 41682#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 42613#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42614#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43375#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 42218#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42219#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41931#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41932#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43184#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42510#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42511#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43049#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42416#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42417#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41841#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41842#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 42188#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42370#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 41424#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41425#L1342 assume !(0 == ~M_E~0); 41591#L1342-2 assume !(0 == ~T1_E~0); 42155#L1347-1 assume !(0 == ~T2_E~0); 43165#L1352-1 assume !(0 == ~T3_E~0); 42956#L1357-1 assume !(0 == ~T4_E~0); 42177#L1362-1 assume !(0 == ~T5_E~0); 42178#L1367-1 assume !(0 == ~T6_E~0); 41756#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41757#L1377-1 assume !(0 == ~T8_E~0); 42095#L1382-1 assume !(0 == ~T9_E~0); 42096#L1387-1 assume !(0 == ~T10_E~0); 42837#L1392-1 assume !(0 == ~T11_E~0); 42138#L1397-1 assume !(0 == ~T12_E~0); 42139#L1402-1 assume !(0 == ~T13_E~0); 41780#L1407-1 assume !(0 == ~T14_E~0); 41781#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 43081#L1417-1 assume !(0 == ~E_2~0); 43082#L1422-1 assume !(0 == ~E_3~0); 43319#L1427-1 assume !(0 == ~E_4~0); 41960#L1432-1 assume !(0 == ~E_5~0); 41961#L1437-1 assume !(0 == ~E_6~0); 43001#L1442-1 assume !(0 == ~E_7~0); 43002#L1447-1 assume !(0 == ~E_8~0); 42831#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 41560#L1457-1 assume !(0 == ~E_10~0); 41561#L1462-1 assume !(0 == ~E_11~0); 43031#L1467-1 assume !(0 == ~E_12~0); 43044#L1472-1 assume !(0 == ~E_13~0); 43045#L1477-1 assume !(0 == ~E_14~0); 42780#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41745#L646 assume 1 == ~m_pc~0; 41746#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42426#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42441#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41843#L1666 assume !(0 != activate_threads_~tmp~1#1); 41844#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43340#L665 assume !(1 == ~t1_pc~0); 42321#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42322#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42930#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42931#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 42662#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42663#L684 assume 1 == ~t2_pc~0; 42779#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42703#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41829#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41830#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 43170#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43353#L703 assume !(1 == ~t3_pc~0); 41985#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41986#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42917#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41394#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 41395#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41873#L722 assume 1 == ~t4_pc~0; 42620#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42060#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41505#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41506#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 42462#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41592#L741 assume 1 == ~t5_pc~0; 41593#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41895#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42695#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42747#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 42748#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42156#L760 assume !(1 == ~t6_pc~0); 41984#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41983#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41821#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41822#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42577#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42578#L779 assume 1 == ~t7_pc~0; 41629#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41476#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41477#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43202#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 41907#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41908#L798 assume !(1 == ~t8_pc~0); 43212#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43129#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43130#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43294#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 43342#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41455#L817 assume 1 == ~t9_pc~0; 41456#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42254#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41877#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41878#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 41855#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41856#L836 assume !(1 == ~t10_pc~0); 41879#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41805#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41806#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42061#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 42062#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43142#L855 assume 1 == ~t11_pc~0; 42437#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42438#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43025#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42828#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 42668#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41742#L874 assume !(1 == ~t12_pc~0); 41743#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41916#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41444#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41445#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 41430#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41431#L893 assume 1 == ~t13_pc~0; 43277#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41783#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42094#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 43225#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 43217#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 43218#L912 assume 1 == ~t14_pc~0; 43008#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 43009#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 43078#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41679#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 41680#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42455#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 42886#L1495-2 assume !(1 == ~T1_E~0); 42887#L1500-1 assume !(1 == ~T2_E~0); 42571#L1505-1 assume !(1 == ~T3_E~0); 42572#L1510-1 assume !(1 == ~T4_E~0); 42630#L1515-1 assume !(1 == ~T5_E~0); 42631#L1520-1 assume !(1 == ~T6_E~0); 43213#L1525-1 assume !(1 == ~T7_E~0); 42918#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41848#L1535-1 assume !(1 == ~T9_E~0); 41849#L1540-1 assume !(1 == ~T10_E~0); 41355#L1545-1 assume !(1 == ~T11_E~0); 41356#L1550-1 assume !(1 == ~T12_E~0); 41602#L1555-1 assume !(1 == ~T13_E~0); 41603#L1560-1 assume !(1 == ~T14_E~0); 41900#L1565-1 assume !(1 == ~E_1~0); 43328#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 42801#L1575-1 assume !(1 == ~E_3~0); 42183#L1580-1 assume !(1 == ~E_4~0); 42184#L1585-1 assume !(1 == ~E_5~0); 42654#L1590-1 assume !(1 == ~E_6~0); 42212#L1595-1 assume !(1 == ~E_7~0); 42213#L1600-1 assume !(1 == ~E_8~0); 42585#L1605-1 assume !(1 == ~E_9~0); 42586#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 43116#L1615-1 assume !(1 == ~E_11~0); 42034#L1620-1 assume !(1 == ~E_12~0); 42035#L1625-1 assume !(1 == ~E_13~0); 42832#L1630-1 assume !(1 == ~E_14~0); 42211#L1635-1 assume { :end_inline_reset_delta_events } true; 42157#L2017-2 [2023-11-19 07:48:23,353 INFO L750 eck$LassoCheckResult]: Loop: 42157#L2017-2 assume !false; 41428#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41429#L1316-1 assume !false; 41817#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 42827#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41368#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41707#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42851#L1115 assume !(0 != eval_~tmp~0#1); 42384#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42029#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42030#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42436#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42963#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42616#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42617#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43196#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43368#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43360#L1372-3 assume !(0 == ~T7_E~0); 41408#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41409#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42074#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 42075#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43011#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43314#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42563#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 41703#L1412-3 assume !(0 == ~E_1~0); 41704#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42465#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42466#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43194#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42874#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42579#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42580#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41472#L1452-3 assume !(0 == ~E_9~0); 41473#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43127#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43128#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 42935#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42936#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 41701#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41702#L646-42 assume 1 == ~m_pc~0; 42297#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43166#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42165#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42166#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43298#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43098#L665-42 assume 1 == ~t1_pc~0; 43057#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43059#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43273#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41880#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41881#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43367#L684-42 assume 1 == ~t2_pc~0; 42744#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42745#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42496#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42497#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42506#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42642#L703-42 assume 1 == ~t3_pc~0; 42843#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42844#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42907#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42908#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42940#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42546#L722-42 assume 1 == ~t4_pc~0; 42547#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42976#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42972#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42022#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42023#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43334#L741-42 assume !(1 == ~t5_pc~0); 42952#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42401#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42402#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42573#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42315#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42316#L760-42 assume !(1 == ~t6_pc~0); 42443#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 42592#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41794#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41795#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 42270#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42271#L779-42 assume !(1 == ~t7_pc~0); 43063#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43064#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42600#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42601#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41803#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41804#L798-42 assume 1 == ~t8_pc~0; 42263#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41421#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42762#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42610#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41635#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41636#L817-42 assume 1 == ~t9_pc~0; 42410#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41918#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41919#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43062#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42866#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42867#L836-42 assume 1 == ~t10_pc~0; 42965#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41955#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41956#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42741#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43279#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43322#L855-42 assume 1 == ~t11_pc~0; 43332#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41509#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41510#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43041#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43042#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42130#L874-42 assume !(1 == ~t12_pc~0); 42131#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 42360#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42551#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42552#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41675#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41676#L893-42 assume !(1 == ~t13_pc~0); 42681#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 42682#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42097#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42098#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42057#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 42058#L912-42 assume 1 == ~t14_pc~0; 43315#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 41376#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 41377#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42171#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 41800#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41801#L1495-3 assume !(1 == ~M_E~0); 42413#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42857#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42953#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42027#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41987#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41988#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42667#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42883#L1530-3 assume !(1 == ~T8_E~0); 41837#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41838#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41876#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43157#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43264#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42285#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 42286#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42913#L1570-3 assume !(1 == ~E_2~0); 42861#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42862#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43226#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43268#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43313#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42689#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42690#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43171#L1610-3 assume !(1 == ~E_10~0); 42038#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 42039#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42655#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42656#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 42549#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 41971#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41587#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41776#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41777#L2036 assume !(0 == start_simulation_~tmp~3#1); 42884#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 43048#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 42196#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41422#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 41423#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42593#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43215#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 43216#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 42157#L2017-2 [2023-11-19 07:48:23,354 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:23,354 INFO L85 PathProgramCache]: Analyzing trace with hash -1364407510, now seen corresponding path program 1 times [2023-11-19 07:48:23,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:23,355 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742211402] [2023-11-19 07:48:23,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:23,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:23,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:23,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:23,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:23,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742211402] [2023-11-19 07:48:23,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742211402] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:23,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:23,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:23,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132580904] [2023-11-19 07:48:23,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:23,423 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:23,425 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:23,425 INFO L85 PathProgramCache]: Analyzing trace with hash 596088560, now seen corresponding path program 3 times [2023-11-19 07:48:23,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:23,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299513093] [2023-11-19 07:48:23,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:23,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:23,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:23,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:23,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:23,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299513093] [2023-11-19 07:48:23,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299513093] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:23,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:23,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:23,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657740947] [2023-11-19 07:48:23,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:23,537 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:23,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:23,538 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:23,538 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:23,539 INFO L87 Difference]: Start difference. First operand 2062 states and 3040 transitions. cyclomatic complexity: 979 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:23,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:23,585 INFO L93 Difference]: Finished difference Result 2062 states and 3039 transitions. [2023-11-19 07:48:23,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3039 transitions. [2023-11-19 07:48:23,597 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:23,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3039 transitions. [2023-11-19 07:48:23,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:23,611 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:23,611 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3039 transitions. [2023-11-19 07:48:23,614 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:23,614 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3039 transitions. [2023-11-19 07:48:23,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3039 transitions. [2023-11-19 07:48:23,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:23,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.473811833171678) internal successors, (3039), 2061 states have internal predecessors, (3039), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:23,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3039 transitions. [2023-11-19 07:48:23,662 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3039 transitions. [2023-11-19 07:48:23,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:23,662 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3039 transitions. [2023-11-19 07:48:23,663 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:48:23,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3039 transitions. [2023-11-19 07:48:23,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:23,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:23,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:23,676 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:23,677 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:23,677 INFO L748 eck$LassoCheckResult]: Stem: 45812#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 45813#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 46744#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46745#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47506#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 46349#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46350#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46062#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46063#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47315#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46641#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46642#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47180#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46547#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46548#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45972#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45973#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 46319#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46501#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 45555#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45556#L1342 assume !(0 == ~M_E~0); 45722#L1342-2 assume !(0 == ~T1_E~0); 46286#L1347-1 assume !(0 == ~T2_E~0); 47296#L1352-1 assume !(0 == ~T3_E~0); 47087#L1357-1 assume !(0 == ~T4_E~0); 46308#L1362-1 assume !(0 == ~T5_E~0); 46309#L1367-1 assume !(0 == ~T6_E~0); 45887#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45888#L1377-1 assume !(0 == ~T8_E~0); 46226#L1382-1 assume !(0 == ~T9_E~0); 46227#L1387-1 assume !(0 == ~T10_E~0); 46968#L1392-1 assume !(0 == ~T11_E~0); 46269#L1397-1 assume !(0 == ~T12_E~0); 46270#L1402-1 assume !(0 == ~T13_E~0); 45911#L1407-1 assume !(0 == ~T14_E~0); 45912#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 47212#L1417-1 assume !(0 == ~E_2~0); 47213#L1422-1 assume !(0 == ~E_3~0); 47450#L1427-1 assume !(0 == ~E_4~0); 46091#L1432-1 assume !(0 == ~E_5~0); 46092#L1437-1 assume !(0 == ~E_6~0); 47132#L1442-1 assume !(0 == ~E_7~0); 47133#L1447-1 assume !(0 == ~E_8~0); 46962#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 45691#L1457-1 assume !(0 == ~E_10~0); 45692#L1462-1 assume !(0 == ~E_11~0); 47162#L1467-1 assume !(0 == ~E_12~0); 47175#L1472-1 assume !(0 == ~E_13~0); 47176#L1477-1 assume !(0 == ~E_14~0); 46911#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45876#L646 assume 1 == ~m_pc~0; 45877#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46557#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46572#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45974#L1666 assume !(0 != activate_threads_~tmp~1#1); 45975#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47471#L665 assume !(1 == ~t1_pc~0); 46452#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46453#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47061#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47062#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 46793#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46794#L684 assume 1 == ~t2_pc~0; 46910#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46834#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45960#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45961#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 47301#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47484#L703 assume !(1 == ~t3_pc~0); 46116#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46117#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45525#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 45526#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46004#L722 assume 1 == ~t4_pc~0; 46751#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46191#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45636#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45637#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 46593#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45723#L741 assume 1 == ~t5_pc~0; 45724#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46026#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46826#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46878#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 46879#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46287#L760 assume !(1 == ~t6_pc~0); 46115#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46114#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45952#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45953#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46708#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46709#L779 assume 1 == ~t7_pc~0; 45760#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45607#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45608#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47333#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 46038#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46039#L798 assume !(1 == ~t8_pc~0); 47343#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47260#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47261#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47425#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 47473#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45586#L817 assume 1 == ~t9_pc~0; 45587#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46385#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46008#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46009#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 45986#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45987#L836 assume !(1 == ~t10_pc~0); 46010#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45936#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45937#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46192#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 46193#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47273#L855 assume 1 == ~t11_pc~0; 46568#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46569#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47156#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46959#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 46799#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45873#L874 assume !(1 == ~t12_pc~0); 45874#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 46047#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45575#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45576#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 45561#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45562#L893 assume 1 == ~t13_pc~0; 47408#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45914#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46225#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 47356#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 47348#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 47349#L912 assume 1 == ~t14_pc~0; 47139#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 47140#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 47209#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45810#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 45811#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46586#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 47017#L1495-2 assume !(1 == ~T1_E~0); 47018#L1500-1 assume !(1 == ~T2_E~0); 46702#L1505-1 assume !(1 == ~T3_E~0); 46703#L1510-1 assume !(1 == ~T4_E~0); 46761#L1515-1 assume !(1 == ~T5_E~0); 46762#L1520-1 assume !(1 == ~T6_E~0); 47344#L1525-1 assume !(1 == ~T7_E~0); 47049#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45979#L1535-1 assume !(1 == ~T9_E~0); 45980#L1540-1 assume !(1 == ~T10_E~0); 45486#L1545-1 assume !(1 == ~T11_E~0); 45487#L1550-1 assume !(1 == ~T12_E~0); 45733#L1555-1 assume !(1 == ~T13_E~0); 45734#L1560-1 assume !(1 == ~T14_E~0); 46031#L1565-1 assume !(1 == ~E_1~0); 47459#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 46932#L1575-1 assume !(1 == ~E_3~0); 46314#L1580-1 assume !(1 == ~E_4~0); 46315#L1585-1 assume !(1 == ~E_5~0); 46785#L1590-1 assume !(1 == ~E_6~0); 46343#L1595-1 assume !(1 == ~E_7~0); 46344#L1600-1 assume !(1 == ~E_8~0); 46716#L1605-1 assume !(1 == ~E_9~0); 46717#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 47247#L1615-1 assume !(1 == ~E_11~0); 46165#L1620-1 assume !(1 == ~E_12~0); 46166#L1625-1 assume !(1 == ~E_13~0); 46963#L1630-1 assume !(1 == ~E_14~0); 46342#L1635-1 assume { :end_inline_reset_delta_events } true; 46288#L2017-2 [2023-11-19 07:48:23,678 INFO L750 eck$LassoCheckResult]: Loop: 46288#L2017-2 assume !false; 45559#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45560#L1316-1 assume !false; 45948#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46958#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45499#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45838#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46982#L1115 assume !(0 != eval_~tmp~0#1); 46515#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46160#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46161#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46567#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47094#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46747#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46748#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47327#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47499#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47491#L1372-3 assume !(0 == ~T7_E~0); 45539#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45540#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46205#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46206#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47142#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47445#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46694#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 45834#L1412-3 assume !(0 == ~E_1~0); 45835#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46596#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46597#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47325#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47005#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46710#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46711#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45603#L1452-3 assume !(0 == ~E_9~0); 45604#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47258#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47259#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47066#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47067#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 45832#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45833#L646-42 assume 1 == ~m_pc~0; 46428#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 47297#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46296#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46297#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47429#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47229#L665-42 assume 1 == ~t1_pc~0; 47188#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47190#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47404#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46011#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46012#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47498#L684-42 assume 1 == ~t2_pc~0; 46875#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46876#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46627#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46628#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46637#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46773#L703-42 assume !(1 == ~t3_pc~0); 46976#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46975#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47038#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47039#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47071#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46677#L722-42 assume 1 == ~t4_pc~0; 46678#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47107#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47103#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46153#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46154#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47465#L741-42 assume 1 == ~t5_pc~0; 47409#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46532#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46533#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46704#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46446#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46447#L760-42 assume !(1 == ~t6_pc~0); 46574#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 46723#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45925#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45926#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 46401#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46402#L779-42 assume 1 == ~t7_pc~0; 47248#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47195#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46731#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46732#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45934#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45935#L798-42 assume 1 == ~t8_pc~0; 46394#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45552#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46893#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46741#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45766#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45767#L817-42 assume 1 == ~t9_pc~0; 46541#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46049#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46050#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47193#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46997#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46998#L836-42 assume 1 == ~t10_pc~0; 47096#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46086#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46087#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46872#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47410#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47453#L855-42 assume 1 == ~t11_pc~0; 47463#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45640#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45641#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47172#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47173#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46261#L874-42 assume !(1 == ~t12_pc~0); 46262#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 46491#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46682#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46683#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45806#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45807#L893-42 assume !(1 == ~t13_pc~0); 46812#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 46813#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46228#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46229#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46188#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 46189#L912-42 assume 1 == ~t14_pc~0; 47446#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 45507#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45508#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46302#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 45931#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45932#L1495-3 assume !(1 == ~M_E~0); 46544#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46988#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47084#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46158#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46118#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46119#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46798#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47014#L1530-3 assume !(1 == ~T8_E~0); 45968#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45969#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46007#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47288#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47395#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46416#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 46417#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47045#L1570-3 assume !(1 == ~E_2~0); 46992#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46993#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47357#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47399#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47444#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46820#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46821#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47302#L1610-3 assume !(1 == ~E_10~0); 46169#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46170#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46786#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46787#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 46680#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46102#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45718#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45907#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 45908#L2036 assume !(0 == start_simulation_~tmp~3#1); 47015#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 47179#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 46327#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45553#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 45554#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46724#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47346#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 47347#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 46288#L2017-2 [2023-11-19 07:48:23,678 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:23,679 INFO L85 PathProgramCache]: Analyzing trace with hash 405064104, now seen corresponding path program 1 times [2023-11-19 07:48:23,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:23,681 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736691772] [2023-11-19 07:48:23,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:23,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:23,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:23,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:23,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:23,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736691772] [2023-11-19 07:48:23,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [736691772] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:23,743 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:23,743 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:23,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2033080114] [2023-11-19 07:48:23,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:23,745 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:23,745 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:23,746 INFO L85 PathProgramCache]: Analyzing trace with hash -345840495, now seen corresponding path program 1 times [2023-11-19 07:48:23,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:23,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [938834397] [2023-11-19 07:48:23,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:23,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:23,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:23,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:23,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:23,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [938834397] [2023-11-19 07:48:23,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [938834397] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:23,869 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:23,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:23,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [801637610] [2023-11-19 07:48:23,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:23,870 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:23,870 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:23,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:23,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:23,871 INFO L87 Difference]: Start difference. First operand 2062 states and 3039 transitions. cyclomatic complexity: 978 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:23,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:23,917 INFO L93 Difference]: Finished difference Result 2062 states and 3038 transitions. [2023-11-19 07:48:23,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3038 transitions. [2023-11-19 07:48:23,929 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:23,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3038 transitions. [2023-11-19 07:48:23,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:23,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:23,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3038 transitions. [2023-11-19 07:48:23,957 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:23,957 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3038 transitions. [2023-11-19 07:48:23,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3038 transitions. [2023-11-19 07:48:23,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:23,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4733268671193016) internal successors, (3038), 2061 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:24,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3038 transitions. [2023-11-19 07:48:24,003 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3038 transitions. [2023-11-19 07:48:24,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:24,004 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3038 transitions. [2023-11-19 07:48:24,004 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:48:24,004 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3038 transitions. [2023-11-19 07:48:24,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:24,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:24,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:24,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:24,019 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:24,019 INFO L748 eck$LassoCheckResult]: Stem: 49943#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 49944#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 50875#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50876#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51637#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 50480#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50481#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50193#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50194#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51446#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50772#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50773#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 51311#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50678#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50679#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50103#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50104#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50450#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50632#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 49686#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49687#L1342 assume !(0 == ~M_E~0); 49853#L1342-2 assume !(0 == ~T1_E~0); 50417#L1347-1 assume !(0 == ~T2_E~0); 51427#L1352-1 assume !(0 == ~T3_E~0); 51218#L1357-1 assume !(0 == ~T4_E~0); 50439#L1362-1 assume !(0 == ~T5_E~0); 50440#L1367-1 assume !(0 == ~T6_E~0); 50018#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50019#L1377-1 assume !(0 == ~T8_E~0); 50357#L1382-1 assume !(0 == ~T9_E~0); 50358#L1387-1 assume !(0 == ~T10_E~0); 51099#L1392-1 assume !(0 == ~T11_E~0); 50400#L1397-1 assume !(0 == ~T12_E~0); 50401#L1402-1 assume !(0 == ~T13_E~0); 50042#L1407-1 assume !(0 == ~T14_E~0); 50043#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 51343#L1417-1 assume !(0 == ~E_2~0); 51344#L1422-1 assume !(0 == ~E_3~0); 51581#L1427-1 assume !(0 == ~E_4~0); 50222#L1432-1 assume !(0 == ~E_5~0); 50223#L1437-1 assume !(0 == ~E_6~0); 51263#L1442-1 assume !(0 == ~E_7~0); 51264#L1447-1 assume !(0 == ~E_8~0); 51093#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 49822#L1457-1 assume !(0 == ~E_10~0); 49823#L1462-1 assume !(0 == ~E_11~0); 51293#L1467-1 assume !(0 == ~E_12~0); 51306#L1472-1 assume !(0 == ~E_13~0); 51307#L1477-1 assume !(0 == ~E_14~0); 51042#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50007#L646 assume 1 == ~m_pc~0; 50008#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50688#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50703#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50105#L1666 assume !(0 != activate_threads_~tmp~1#1); 50106#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51602#L665 assume !(1 == ~t1_pc~0); 50583#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50584#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51192#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51193#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 50924#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50925#L684 assume 1 == ~t2_pc~0; 51041#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50965#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50091#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50092#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 51432#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51615#L703 assume !(1 == ~t3_pc~0); 50247#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50248#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51179#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49656#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 49657#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50135#L722 assume 1 == ~t4_pc~0; 50882#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50322#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49767#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49768#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 50724#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49854#L741 assume 1 == ~t5_pc~0; 49855#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50157#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50957#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51009#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 51010#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50418#L760 assume !(1 == ~t6_pc~0); 50246#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50245#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50083#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50084#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50839#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50840#L779 assume 1 == ~t7_pc~0; 49891#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49738#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49739#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51464#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 50169#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50170#L798 assume !(1 == ~t8_pc~0); 51474#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 51391#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51392#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51556#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 51604#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49717#L817 assume 1 == ~t9_pc~0; 49718#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50516#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50139#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50140#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 50117#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50118#L836 assume !(1 == ~t10_pc~0); 50141#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50067#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50068#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50323#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 50324#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51404#L855 assume 1 == ~t11_pc~0; 50699#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50700#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51287#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51090#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 50930#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50004#L874 assume !(1 == ~t12_pc~0); 50005#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 50178#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49706#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49707#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 49692#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49693#L893 assume 1 == ~t13_pc~0; 51539#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50045#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50356#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51487#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 51479#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 51480#L912 assume 1 == ~t14_pc~0; 51270#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 51271#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 51342#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 49941#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 49942#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50717#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 51148#L1495-2 assume !(1 == ~T1_E~0); 51149#L1500-1 assume !(1 == ~T2_E~0); 50833#L1505-1 assume !(1 == ~T3_E~0); 50834#L1510-1 assume !(1 == ~T4_E~0); 50892#L1515-1 assume !(1 == ~T5_E~0); 50893#L1520-1 assume !(1 == ~T6_E~0); 51475#L1525-1 assume !(1 == ~T7_E~0); 51180#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50110#L1535-1 assume !(1 == ~T9_E~0); 50111#L1540-1 assume !(1 == ~T10_E~0); 49617#L1545-1 assume !(1 == ~T11_E~0); 49618#L1550-1 assume !(1 == ~T12_E~0); 49864#L1555-1 assume !(1 == ~T13_E~0); 49865#L1560-1 assume !(1 == ~T14_E~0); 50162#L1565-1 assume !(1 == ~E_1~0); 51590#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 51063#L1575-1 assume !(1 == ~E_3~0); 50445#L1580-1 assume !(1 == ~E_4~0); 50446#L1585-1 assume !(1 == ~E_5~0); 50916#L1590-1 assume !(1 == ~E_6~0); 50474#L1595-1 assume !(1 == ~E_7~0); 50475#L1600-1 assume !(1 == ~E_8~0); 50847#L1605-1 assume !(1 == ~E_9~0); 50848#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 51378#L1615-1 assume !(1 == ~E_11~0); 50296#L1620-1 assume !(1 == ~E_12~0); 50297#L1625-1 assume !(1 == ~E_13~0); 51094#L1630-1 assume !(1 == ~E_14~0); 50473#L1635-1 assume { :end_inline_reset_delta_events } true; 50419#L2017-2 [2023-11-19 07:48:24,020 INFO L750 eck$LassoCheckResult]: Loop: 50419#L2017-2 assume !false; 49690#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49691#L1316-1 assume !false; 50079#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 51089#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49630#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 49969#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 51113#L1115 assume !(0 != eval_~tmp~0#1); 50646#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50291#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50292#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50698#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51225#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50878#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50879#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51458#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51630#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51622#L1372-3 assume !(0 == ~T7_E~0); 49670#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49671#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50336#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50337#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51273#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51576#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50825#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 49965#L1412-3 assume !(0 == ~E_1~0); 49966#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50727#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50728#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51456#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51136#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50841#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50842#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49734#L1452-3 assume !(0 == ~E_9~0); 49735#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51389#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51390#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 51197#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51198#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 49963#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49964#L646-42 assume !(1 == ~m_pc~0); 50560#L646-44 is_master_triggered_~__retres1~0#1 := 0; 51428#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50427#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50428#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51560#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51360#L665-42 assume 1 == ~t1_pc~0; 51319#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51321#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51535#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50142#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50143#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51629#L684-42 assume !(1 == ~t2_pc~0); 51008#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 51007#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50758#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50759#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50768#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50904#L703-42 assume 1 == ~t3_pc~0; 51105#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51106#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51169#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51170#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51202#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50808#L722-42 assume 1 == ~t4_pc~0; 50809#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51238#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51234#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50284#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50285#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51596#L741-42 assume 1 == ~t5_pc~0; 51540#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50663#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50664#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50835#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50577#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50578#L760-42 assume !(1 == ~t6_pc~0); 50705#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 50854#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50056#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50057#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 50532#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50533#L779-42 assume 1 == ~t7_pc~0; 51379#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51326#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50862#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50863#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50065#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50066#L798-42 assume !(1 == ~t8_pc~0); 49682#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 49683#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51024#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50872#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49897#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49898#L817-42 assume 1 == ~t9_pc~0; 50672#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50180#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50181#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51324#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51128#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51129#L836-42 assume 1 == ~t10_pc~0; 51227#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50217#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50218#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51003#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51541#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51584#L855-42 assume 1 == ~t11_pc~0; 51594#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49771#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49772#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51303#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51304#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50392#L874-42 assume !(1 == ~t12_pc~0); 50393#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50622#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50813#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50814#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49937#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49938#L893-42 assume 1 == ~t13_pc~0; 51154#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50944#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50359#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50360#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50319#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 50320#L912-42 assume 1 == ~t14_pc~0; 51577#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 49638#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 49639#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50433#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 50062#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50063#L1495-3 assume !(1 == ~M_E~0); 50675#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51119#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51215#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50289#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50249#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50250#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50929#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51145#L1530-3 assume !(1 == ~T8_E~0); 50099#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50100#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50138#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51419#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51526#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50547#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 50548#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51176#L1570-3 assume !(1 == ~E_2~0); 51123#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51124#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51488#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51530#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51575#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50951#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50952#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51433#L1610-3 assume !(1 == ~E_10~0); 50300#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50301#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50917#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50918#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 50811#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 50233#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49849#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 50038#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50039#L2036 assume !(0 == start_simulation_~tmp~3#1); 51146#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 51310#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 50458#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 49684#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 49685#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50855#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51477#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 51478#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 50419#L2017-2 [2023-11-19 07:48:24,020 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:24,021 INFO L85 PathProgramCache]: Analyzing trace with hash 1016333162, now seen corresponding path program 1 times [2023-11-19 07:48:24,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:24,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587084072] [2023-11-19 07:48:24,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:24,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:24,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:24,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:24,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:24,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587084072] [2023-11-19 07:48:24,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1587084072] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:24,082 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:24,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:24,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300973807] [2023-11-19 07:48:24,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:24,084 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:24,084 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:24,085 INFO L85 PathProgramCache]: Analyzing trace with hash 88761904, now seen corresponding path program 1 times [2023-11-19 07:48:24,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:24,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345093498] [2023-11-19 07:48:24,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:24,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:24,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:24,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:24,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:24,166 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345093498] [2023-11-19 07:48:24,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345093498] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:24,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:24,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:24,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423315327] [2023-11-19 07:48:24,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:24,168 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:24,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:24,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:24,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:24,170 INFO L87 Difference]: Start difference. First operand 2062 states and 3038 transitions. cyclomatic complexity: 977 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:24,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:24,214 INFO L93 Difference]: Finished difference Result 2062 states and 3037 transitions. [2023-11-19 07:48:24,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3037 transitions. [2023-11-19 07:48:24,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:24,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3037 transitions. [2023-11-19 07:48:24,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:24,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:24,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3037 transitions. [2023-11-19 07:48:24,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:24,244 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3037 transitions. [2023-11-19 07:48:24,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3037 transitions. [2023-11-19 07:48:24,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:24,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4728419010669254) internal successors, (3037), 2061 states have internal predecessors, (3037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:24,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3037 transitions. [2023-11-19 07:48:24,291 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3037 transitions. [2023-11-19 07:48:24,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:24,293 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3037 transitions. [2023-11-19 07:48:24,293 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:48:24,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3037 transitions. [2023-11-19 07:48:24,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:24,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:24,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:24,307 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:24,307 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:24,307 INFO L748 eck$LassoCheckResult]: Stem: 54074#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 54075#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 55006#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55007#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55768#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 54611#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54612#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54324#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54325#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55577#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54903#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54904#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55442#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54809#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54810#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54234#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54235#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54581#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54763#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 53817#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53818#L1342 assume !(0 == ~M_E~0); 53984#L1342-2 assume !(0 == ~T1_E~0); 54548#L1347-1 assume !(0 == ~T2_E~0); 55558#L1352-1 assume !(0 == ~T3_E~0); 55349#L1357-1 assume !(0 == ~T4_E~0); 54570#L1362-1 assume !(0 == ~T5_E~0); 54571#L1367-1 assume !(0 == ~T6_E~0); 54149#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54150#L1377-1 assume !(0 == ~T8_E~0); 54488#L1382-1 assume !(0 == ~T9_E~0); 54489#L1387-1 assume !(0 == ~T10_E~0); 55230#L1392-1 assume !(0 == ~T11_E~0); 54531#L1397-1 assume !(0 == ~T12_E~0); 54532#L1402-1 assume !(0 == ~T13_E~0); 54173#L1407-1 assume !(0 == ~T14_E~0); 54174#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 55474#L1417-1 assume !(0 == ~E_2~0); 55475#L1422-1 assume !(0 == ~E_3~0); 55712#L1427-1 assume !(0 == ~E_4~0); 54353#L1432-1 assume !(0 == ~E_5~0); 54354#L1437-1 assume !(0 == ~E_6~0); 55394#L1442-1 assume !(0 == ~E_7~0); 55395#L1447-1 assume !(0 == ~E_8~0); 55224#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 53953#L1457-1 assume !(0 == ~E_10~0); 53954#L1462-1 assume !(0 == ~E_11~0); 55424#L1467-1 assume !(0 == ~E_12~0); 55437#L1472-1 assume !(0 == ~E_13~0); 55438#L1477-1 assume !(0 == ~E_14~0); 55173#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54138#L646 assume 1 == ~m_pc~0; 54139#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 54819#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54834#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54236#L1666 assume !(0 != activate_threads_~tmp~1#1); 54237#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55733#L665 assume !(1 == ~t1_pc~0); 54714#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54715#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55323#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55324#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 55055#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55056#L684 assume 1 == ~t2_pc~0; 55172#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55096#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54224#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54225#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 55563#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55746#L703 assume !(1 == ~t3_pc~0); 54378#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54379#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55310#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53787#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 53788#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54266#L722 assume 1 == ~t4_pc~0; 55013#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54453#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53898#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53899#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 54855#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53985#L741 assume 1 == ~t5_pc~0; 53986#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54288#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55088#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55140#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 55141#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54549#L760 assume !(1 == ~t6_pc~0); 54377#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 54376#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54214#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54215#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54970#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54971#L779 assume 1 == ~t7_pc~0; 54022#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53869#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53870#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55595#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 54300#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54301#L798 assume !(1 == ~t8_pc~0); 55605#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 55522#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55523#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55687#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 55735#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53848#L817 assume 1 == ~t9_pc~0; 53849#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54647#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54270#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54271#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 54248#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54249#L836 assume !(1 == ~t10_pc~0); 54272#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 54198#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54199#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54454#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 54455#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55535#L855 assume 1 == ~t11_pc~0; 54830#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54831#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55418#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55221#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 55061#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54135#L874 assume !(1 == ~t12_pc~0); 54136#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54309#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53837#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53838#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 53823#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53824#L893 assume 1 == ~t13_pc~0; 55670#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54176#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54487#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 55618#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 55610#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 55611#L912 assume 1 == ~t14_pc~0; 55401#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 55402#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 55473#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54072#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 54073#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54848#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 55279#L1495-2 assume !(1 == ~T1_E~0); 55280#L1500-1 assume !(1 == ~T2_E~0); 54964#L1505-1 assume !(1 == ~T3_E~0); 54965#L1510-1 assume !(1 == ~T4_E~0); 55023#L1515-1 assume !(1 == ~T5_E~0); 55024#L1520-1 assume !(1 == ~T6_E~0); 55606#L1525-1 assume !(1 == ~T7_E~0); 55311#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54241#L1535-1 assume !(1 == ~T9_E~0); 54242#L1540-1 assume !(1 == ~T10_E~0); 53748#L1545-1 assume !(1 == ~T11_E~0); 53749#L1550-1 assume !(1 == ~T12_E~0); 53995#L1555-1 assume !(1 == ~T13_E~0); 53996#L1560-1 assume !(1 == ~T14_E~0); 54293#L1565-1 assume !(1 == ~E_1~0); 55721#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 55194#L1575-1 assume !(1 == ~E_3~0); 54576#L1580-1 assume !(1 == ~E_4~0); 54577#L1585-1 assume !(1 == ~E_5~0); 55047#L1590-1 assume !(1 == ~E_6~0); 54605#L1595-1 assume !(1 == ~E_7~0); 54606#L1600-1 assume !(1 == ~E_8~0); 54978#L1605-1 assume !(1 == ~E_9~0); 54979#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 55509#L1615-1 assume !(1 == ~E_11~0); 54427#L1620-1 assume !(1 == ~E_12~0); 54428#L1625-1 assume !(1 == ~E_13~0); 55225#L1630-1 assume !(1 == ~E_14~0); 54604#L1635-1 assume { :end_inline_reset_delta_events } true; 54550#L2017-2 [2023-11-19 07:48:24,308 INFO L750 eck$LassoCheckResult]: Loop: 54550#L2017-2 assume !false; 53821#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53822#L1316-1 assume !false; 54210#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55220#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53761#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 54100#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55244#L1115 assume !(0 != eval_~tmp~0#1); 54777#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54422#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54423#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54829#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55356#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55009#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55010#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55589#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55761#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55753#L1372-3 assume !(0 == ~T7_E~0); 53801#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53802#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54467#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54468#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55404#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 55707#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 54956#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 54096#L1412-3 assume !(0 == ~E_1~0); 54097#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54858#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54859#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55587#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55267#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54972#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54973#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53865#L1452-3 assume !(0 == ~E_9~0); 53866#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55520#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55521#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 55328#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 55329#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 54094#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54095#L646-42 assume 1 == ~m_pc~0; 54690#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 55559#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54558#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54559#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55691#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55491#L665-42 assume 1 == ~t1_pc~0; 55450#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55452#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55666#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54273#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54274#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55760#L684-42 assume 1 == ~t2_pc~0; 55137#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55138#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54889#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54890#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54899#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55035#L703-42 assume 1 == ~t3_pc~0; 55236#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55237#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55300#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55301#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55333#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54939#L722-42 assume 1 == ~t4_pc~0; 54940#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 55369#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55365#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54415#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54416#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55727#L741-42 assume !(1 == ~t5_pc~0); 55345#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 54794#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54795#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54966#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54708#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54709#L760-42 assume !(1 == ~t6_pc~0); 54836#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 54985#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54187#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54188#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 54663#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54664#L779-42 assume !(1 == ~t7_pc~0); 55456#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 55457#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54993#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54994#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54196#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54197#L798-42 assume 1 == ~t8_pc~0; 54656#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53814#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55155#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55003#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54028#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54029#L817-42 assume 1 == ~t9_pc~0; 54801#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54311#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54312#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55455#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55259#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55260#L836-42 assume 1 == ~t10_pc~0; 55358#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 54348#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54349#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55134#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55672#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55715#L855-42 assume 1 == ~t11_pc~0; 55725#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53902#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53903#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55434#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 55435#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54526#L874-42 assume 1 == ~t12_pc~0; 54528#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54753#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54944#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54945#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54068#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54069#L893-42 assume !(1 == ~t13_pc~0); 55074#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 55075#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54490#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54491#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54450#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 54451#L912-42 assume 1 == ~t14_pc~0; 55708#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 53769#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53770#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54564#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 54193#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54194#L1495-3 assume !(1 == ~M_E~0); 54806#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55250#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55346#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54420#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54380#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54381#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55060#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55276#L1530-3 assume !(1 == ~T8_E~0); 54230#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54231#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54269#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 55550#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55657#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54678#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 54679#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55307#L1570-3 assume !(1 == ~E_2~0); 55254#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55255#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55619#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55661#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55706#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 55082#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 55083#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 55564#L1610-3 assume !(1 == ~E_10~0); 54431#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54432#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 55048#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 55049#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 54942#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 54364#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53980#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 54169#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54170#L2036 assume !(0 == start_simulation_~tmp~3#1); 55277#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55441#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 54589#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 53815#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 53816#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54986#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55608#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 55609#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 54550#L2017-2 [2023-11-19 07:48:24,309 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:24,309 INFO L85 PathProgramCache]: Analyzing trace with hash -1873442456, now seen corresponding path program 1 times [2023-11-19 07:48:24,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:24,310 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412441910] [2023-11-19 07:48:24,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:24,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:24,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:24,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:24,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:24,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412441910] [2023-11-19 07:48:24,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412441910] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:24,371 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:24,371 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:24,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435781292] [2023-11-19 07:48:24,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:24,373 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:24,374 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:24,374 INFO L85 PathProgramCache]: Analyzing trace with hash -1792394543, now seen corresponding path program 1 times [2023-11-19 07:48:24,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:24,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [732332351] [2023-11-19 07:48:24,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:24,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:24,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:24,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:24,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:24,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [732332351] [2023-11-19 07:48:24,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [732332351] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:24,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:24,453 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:24,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206583446] [2023-11-19 07:48:24,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:24,454 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:24,454 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:24,455 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:24,455 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:24,455 INFO L87 Difference]: Start difference. First operand 2062 states and 3037 transitions. cyclomatic complexity: 976 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:24,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:24,506 INFO L93 Difference]: Finished difference Result 2062 states and 3036 transitions. [2023-11-19 07:48:24,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3036 transitions. [2023-11-19 07:48:24,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:24,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3036 transitions. [2023-11-19 07:48:24,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2023-11-19 07:48:24,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2023-11-19 07:48:24,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3036 transitions. [2023-11-19 07:48:24,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:24,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3036 transitions. [2023-11-19 07:48:24,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3036 transitions. [2023-11-19 07:48:24,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2023-11-19 07:48:24,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.472356935014549) internal successors, (3036), 2061 states have internal predecessors, (3036), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:24,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3036 transitions. [2023-11-19 07:48:24,619 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3036 transitions. [2023-11-19 07:48:24,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:24,620 INFO L428 stractBuchiCegarLoop]: Abstraction has 2062 states and 3036 transitions. [2023-11-19 07:48:24,620 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:48:24,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3036 transitions. [2023-11-19 07:48:24,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2023-11-19 07:48:24,634 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:24,634 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:24,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:24,638 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:24,638 INFO L748 eck$LassoCheckResult]: Stem: 58205#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 58206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 59137#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59138#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59899#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 58742#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58743#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58455#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58456#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59708#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59034#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59035#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59573#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58940#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58941#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 58365#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 58366#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 58712#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 58894#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 57948#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57949#L1342 assume !(0 == ~M_E~0); 58115#L1342-2 assume !(0 == ~T1_E~0); 58679#L1347-1 assume !(0 == ~T2_E~0); 59689#L1352-1 assume !(0 == ~T3_E~0); 59480#L1357-1 assume !(0 == ~T4_E~0); 58701#L1362-1 assume !(0 == ~T5_E~0); 58702#L1367-1 assume !(0 == ~T6_E~0); 58280#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58281#L1377-1 assume !(0 == ~T8_E~0); 58619#L1382-1 assume !(0 == ~T9_E~0); 58620#L1387-1 assume !(0 == ~T10_E~0); 59361#L1392-1 assume !(0 == ~T11_E~0); 58662#L1397-1 assume !(0 == ~T12_E~0); 58663#L1402-1 assume !(0 == ~T13_E~0); 58304#L1407-1 assume !(0 == ~T14_E~0); 58305#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 59605#L1417-1 assume !(0 == ~E_2~0); 59606#L1422-1 assume !(0 == ~E_3~0); 59843#L1427-1 assume !(0 == ~E_4~0); 58484#L1432-1 assume !(0 == ~E_5~0); 58485#L1437-1 assume !(0 == ~E_6~0); 59525#L1442-1 assume !(0 == ~E_7~0); 59526#L1447-1 assume !(0 == ~E_8~0); 59355#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 58084#L1457-1 assume !(0 == ~E_10~0); 58085#L1462-1 assume !(0 == ~E_11~0); 59555#L1467-1 assume !(0 == ~E_12~0); 59568#L1472-1 assume !(0 == ~E_13~0); 59569#L1477-1 assume !(0 == ~E_14~0); 59304#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58269#L646 assume 1 == ~m_pc~0; 58270#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58950#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58965#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58367#L1666 assume !(0 != activate_threads_~tmp~1#1); 58368#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59864#L665 assume !(1 == ~t1_pc~0); 58845#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58846#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59454#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59455#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 59186#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59187#L684 assume 1 == ~t2_pc~0; 59303#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59227#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58355#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58356#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 59694#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59877#L703 assume !(1 == ~t3_pc~0); 58509#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58510#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59441#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57918#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 57919#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58397#L722 assume 1 == ~t4_pc~0; 59144#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58584#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58029#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58030#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 58986#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58116#L741 assume 1 == ~t5_pc~0; 58117#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58419#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59219#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59271#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 59272#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58680#L760 assume !(1 == ~t6_pc~0); 58508#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 58507#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58346#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59101#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59102#L779 assume 1 == ~t7_pc~0; 58153#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58000#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58001#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59726#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 58431#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58432#L798 assume !(1 == ~t8_pc~0); 59736#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 59653#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59654#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59818#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 59866#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57979#L817 assume 1 == ~t9_pc~0; 57980#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58778#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58401#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58402#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 58379#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58380#L836 assume !(1 == ~t10_pc~0); 58403#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58329#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58330#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58585#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 58586#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59666#L855 assume 1 == ~t11_pc~0; 58961#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58962#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59549#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59352#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 59192#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58266#L874 assume !(1 == ~t12_pc~0); 58267#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58440#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57968#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57969#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 57954#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57955#L893 assume 1 == ~t13_pc~0; 59801#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 58307#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58618#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59749#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 59741#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 59742#L912 assume 1 == ~t14_pc~0; 59532#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 59533#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 59604#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 58203#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 58204#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58979#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 59410#L1495-2 assume !(1 == ~T1_E~0); 59411#L1500-1 assume !(1 == ~T2_E~0); 59095#L1505-1 assume !(1 == ~T3_E~0); 59096#L1510-1 assume !(1 == ~T4_E~0); 59154#L1515-1 assume !(1 == ~T5_E~0); 59155#L1520-1 assume !(1 == ~T6_E~0); 59737#L1525-1 assume !(1 == ~T7_E~0); 59442#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 58372#L1535-1 assume !(1 == ~T9_E~0); 58373#L1540-1 assume !(1 == ~T10_E~0); 57879#L1545-1 assume !(1 == ~T11_E~0); 57880#L1550-1 assume !(1 == ~T12_E~0); 58126#L1555-1 assume !(1 == ~T13_E~0); 58127#L1560-1 assume !(1 == ~T14_E~0); 58424#L1565-1 assume !(1 == ~E_1~0); 59852#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 59325#L1575-1 assume !(1 == ~E_3~0); 58707#L1580-1 assume !(1 == ~E_4~0); 58708#L1585-1 assume !(1 == ~E_5~0); 59178#L1590-1 assume !(1 == ~E_6~0); 58736#L1595-1 assume !(1 == ~E_7~0); 58737#L1600-1 assume !(1 == ~E_8~0); 59111#L1605-1 assume !(1 == ~E_9~0); 59112#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 59640#L1615-1 assume !(1 == ~E_11~0); 58558#L1620-1 assume !(1 == ~E_12~0); 58559#L1625-1 assume !(1 == ~E_13~0); 59356#L1630-1 assume !(1 == ~E_14~0); 58735#L1635-1 assume { :end_inline_reset_delta_events } true; 58681#L2017-2 [2023-11-19 07:48:24,639 INFO L750 eck$LassoCheckResult]: Loop: 58681#L2017-2 assume !false; 57952#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57953#L1316-1 assume !false; 58341#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 59351#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 57892#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 58232#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 59375#L1115 assume !(0 != eval_~tmp~0#1); 58908#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58553#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58554#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 58960#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59487#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59140#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59141#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59720#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59892#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59884#L1372-3 assume !(0 == ~T7_E~0); 57932#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57933#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 58598#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58599#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59535#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59838#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 59087#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 58227#L1412-3 assume !(0 == ~E_1~0); 58228#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58989#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58990#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59718#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 59398#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59103#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59104#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57996#L1452-3 assume !(0 == ~E_9~0); 57997#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59651#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59652#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 59459#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59460#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 58225#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58226#L646-42 assume 1 == ~m_pc~0; 58821#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 59690#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58689#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58690#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59822#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59622#L665-42 assume 1 == ~t1_pc~0; 59581#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59583#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59797#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58404#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58405#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59891#L684-42 assume 1 == ~t2_pc~0; 59268#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59269#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59020#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59021#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59030#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59166#L703-42 assume 1 == ~t3_pc~0; 59367#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 59368#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59431#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59432#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59464#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59070#L722-42 assume !(1 == ~t4_pc~0); 59072#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 59500#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59496#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58546#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58547#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59858#L741-42 assume !(1 == ~t5_pc~0); 59476#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 58925#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58926#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59097#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58839#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58840#L760-42 assume !(1 == ~t6_pc~0); 58967#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 59116#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58318#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58319#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 58794#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58795#L779-42 assume !(1 == ~t7_pc~0); 59587#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 59588#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59124#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59125#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58327#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58328#L798-42 assume 1 == ~t8_pc~0; 58787#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 57945#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59286#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59134#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58155#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58156#L817-42 assume 1 == ~t9_pc~0; 58932#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58442#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58443#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59586#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59390#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59391#L836-42 assume 1 == ~t10_pc~0; 59489#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58479#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58480#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59265#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59803#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59846#L855-42 assume 1 == ~t11_pc~0; 59856#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58033#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58034#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59565#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59566#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58657#L874-42 assume !(1 == ~t12_pc~0); 58658#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 58884#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59075#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59076#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 58199#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58200#L893-42 assume !(1 == ~t13_pc~0); 59205#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 59206#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58621#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58622#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58581#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 58582#L912-42 assume !(1 == ~t14_pc~0); 59394#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 57900#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 57901#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 58695#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 58324#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58325#L1495-3 assume !(1 == ~M_E~0); 58937#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59381#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59477#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58551#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58511#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58512#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 59191#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 59407#L1530-3 assume !(1 == ~T8_E~0); 58361#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 58362#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 58400#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59681#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59788#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58809#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 58810#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59438#L1570-3 assume !(1 == ~E_2~0); 59385#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59386#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59750#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59792#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59837#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59213#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59214#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59695#L1610-3 assume !(1 == ~E_10~0); 58562#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58563#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 59179#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 59180#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 59073#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 58495#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 58111#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 58300#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 58301#L2036 assume !(0 == start_simulation_~tmp~3#1); 59408#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 59572#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 58720#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 57946#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 57947#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59117#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59739#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 59740#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 58681#L2017-2 [2023-11-19 07:48:24,640 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:24,640 INFO L85 PathProgramCache]: Analyzing trace with hash 527190954, now seen corresponding path program 1 times [2023-11-19 07:48:24,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:24,641 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320137498] [2023-11-19 07:48:24,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:24,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:24,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:24,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:24,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:24,756 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320137498] [2023-11-19 07:48:24,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320137498] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:24,756 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:24,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:24,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038433591] [2023-11-19 07:48:24,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:24,758 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:24,758 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:24,758 INFO L85 PathProgramCache]: Analyzing trace with hash 1582164910, now seen corresponding path program 1 times [2023-11-19 07:48:24,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:24,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096548380] [2023-11-19 07:48:24,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:24,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:24,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:24,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:24,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:24,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2096548380] [2023-11-19 07:48:24,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2096548380] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:24,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:24,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:24,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1011522052] [2023-11-19 07:48:24,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:24,838 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:24,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:24,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:24,839 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:24,839 INFO L87 Difference]: Start difference. First operand 2062 states and 3036 transitions. cyclomatic complexity: 975 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:25,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:25,110 INFO L93 Difference]: Finished difference Result 3966 states and 5830 transitions. [2023-11-19 07:48:25,110 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3966 states and 5830 transitions. [2023-11-19 07:48:25,132 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3754 [2023-11-19 07:48:25,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3966 states to 3966 states and 5830 transitions. [2023-11-19 07:48:25,148 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3966 [2023-11-19 07:48:25,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3966 [2023-11-19 07:48:25,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3966 states and 5830 transitions. [2023-11-19 07:48:25,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:25,159 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3966 states and 5830 transitions. [2023-11-19 07:48:25,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3966 states and 5830 transitions. [2023-11-19 07:48:25,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3966 to 3966. [2023-11-19 07:48:25,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3966 states, 3966 states have (on average 1.469994957135653) internal successors, (5830), 3965 states have internal predecessors, (5830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:25,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3966 states to 3966 states and 5830 transitions. [2023-11-19 07:48:25,269 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3966 states and 5830 transitions. [2023-11-19 07:48:25,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:48:25,270 INFO L428 stractBuchiCegarLoop]: Abstraction has 3966 states and 5830 transitions. [2023-11-19 07:48:25,271 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:48:25,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3966 states and 5830 transitions. [2023-11-19 07:48:25,288 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3754 [2023-11-19 07:48:25,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:25,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:25,292 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:25,293 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:25,293 INFO L748 eck$LassoCheckResult]: Stem: 64243#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 64244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 65185#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65186#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66082#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 64784#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64785#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64494#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64495#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65813#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65079#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65080#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65659#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64984#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64985#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 64404#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 64405#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 64753#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 64937#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 63984#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63985#L1342 assume !(0 == ~M_E~0); 64153#L1342-2 assume !(0 == ~T1_E~0); 64720#L1347-1 assume !(0 == ~T2_E~0); 65790#L1352-1 assume !(0 == ~T3_E~0); 65551#L1357-1 assume !(0 == ~T4_E~0); 64742#L1362-1 assume !(0 == ~T5_E~0); 64743#L1367-1 assume !(0 == ~T6_E~0); 64318#L1372-1 assume !(0 == ~T7_E~0); 64319#L1377-1 assume !(0 == ~T8_E~0); 64660#L1382-1 assume !(0 == ~T9_E~0); 64661#L1387-1 assume !(0 == ~T10_E~0); 65422#L1392-1 assume !(0 == ~T11_E~0); 64701#L1397-1 assume !(0 == ~T12_E~0); 64702#L1402-1 assume !(0 == ~T13_E~0); 64342#L1407-1 assume !(0 == ~T14_E~0); 64343#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 65694#L1417-1 assume !(0 == ~E_2~0); 65695#L1422-1 assume !(0 == ~E_3~0); 65993#L1427-1 assume !(0 == ~E_4~0); 64523#L1432-1 assume !(0 == ~E_5~0); 64524#L1437-1 assume !(0 == ~E_6~0); 65603#L1442-1 assume !(0 == ~E_7~0); 65604#L1447-1 assume !(0 == ~E_8~0); 65416#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 64122#L1457-1 assume !(0 == ~E_10~0); 64123#L1462-1 assume !(0 == ~E_11~0); 65637#L1467-1 assume !(0 == ~E_12~0); 65653#L1472-1 assume !(0 == ~E_13~0); 65654#L1477-1 assume !(0 == ~E_14~0); 65361#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64307#L646 assume 1 == ~m_pc~0; 64308#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 64995#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65010#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64406#L1666 assume !(0 != activate_threads_~tmp~1#1); 64407#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66024#L665 assume !(1 == ~t1_pc~0); 64887#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64888#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65521#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65522#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 65235#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65236#L684 assume 1 == ~t2_pc~0; 65358#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65278#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64392#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64393#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 65795#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66046#L703 assume !(1 == ~t3_pc~0); 64548#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64549#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65508#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63956#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 63957#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64436#L722 assume 1 == ~t4_pc~0; 65192#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64624#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64067#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64068#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 65031#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64154#L741 assume 1 == ~t5_pc~0; 64155#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64458#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65271#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65326#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 65327#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64721#L760 assume !(1 == ~t6_pc~0); 64547#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64546#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64384#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64385#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65147#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65148#L779 assume 1 == ~t7_pc~0; 64191#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64038#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64039#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65836#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 64470#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64471#L798 assume !(1 == ~t8_pc~0); 65847#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 65748#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65749#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65962#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 66026#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64017#L817 assume 1 == ~t9_pc~0; 64018#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64820#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64440#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64441#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 64418#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64419#L836 assume !(1 == ~t10_pc~0); 64442#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 64367#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64368#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64625#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 64626#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65763#L855 assume 1 == ~t11_pc~0; 65006#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65007#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65629#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65413#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 65242#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64304#L874 assume !(1 == ~t12_pc~0); 64305#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 64479#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64006#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64007#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 63992#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 63993#L893 assume 1 == ~t13_pc~0; 65930#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 64345#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64659#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 65865#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 65853#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 65854#L912 assume 1 == ~t14_pc~0; 65611#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 65612#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 65691#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 64241#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 64242#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65024#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 65475#L1495-2 assume !(1 == ~T1_E~0); 65476#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65141#L1505-1 assume !(1 == ~T3_E~0); 65142#L1510-1 assume !(1 == ~T4_E~0); 65202#L1515-1 assume !(1 == ~T5_E~0); 65203#L1520-1 assume !(1 == ~T6_E~0); 65848#L1525-1 assume !(1 == ~T7_E~0); 65849#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66518#L1535-1 assume !(1 == ~T9_E~0); 66055#L1540-1 assume !(1 == ~T10_E~0); 63917#L1545-1 assume !(1 == ~T11_E~0); 63918#L1550-1 assume !(1 == ~T12_E~0); 64164#L1555-1 assume !(1 == ~T13_E~0); 64165#L1560-1 assume !(1 == ~T14_E~0); 64461#L1565-1 assume !(1 == ~E_1~0); 66005#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 66084#L1575-1 assume !(1 == ~E_3~0); 66434#L1580-1 assume !(1 == ~E_4~0); 65226#L1585-1 assume !(1 == ~E_5~0); 65227#L1590-1 assume !(1 == ~E_6~0); 66433#L1595-1 assume !(1 == ~E_7~0); 66075#L1600-1 assume !(1 == ~E_8~0); 65155#L1605-1 assume !(1 == ~E_9~0); 65156#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65734#L1615-1 assume !(1 == ~E_11~0); 64597#L1620-1 assume !(1 == ~E_12~0); 64598#L1625-1 assume !(1 == ~E_13~0); 65417#L1630-1 assume !(1 == ~E_14~0); 64776#L1635-1 assume { :end_inline_reset_delta_events } true; 64777#L2017-2 [2023-11-19 07:48:25,294 INFO L750 eck$LassoCheckResult]: Loop: 64777#L2017-2 assume !false; 66129#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64379#L1316-1 assume !false; 64380#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 66124#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 66113#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 65767#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 65768#L1115 assume !(0 != eval_~tmp~0#1); 66111#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66110#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66109#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65558#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65559#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66108#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67668#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67666#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67664#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67662#L1372-3 assume !(0 == ~T7_E~0); 67659#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67657#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67655#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67653#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 67651#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 67649#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 67646#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 67645#L1412-3 assume !(0 == ~E_1~0); 67644#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67643#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67642#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67641#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67640#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67639#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67638#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67637#L1452-3 assume !(0 == ~E_9~0); 67636#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 67635#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67634#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 67633#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 67632#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 67631#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67630#L646-42 assume !(1 == ~m_pc~0); 67629#L646-44 is_master_triggered_~__retres1~0#1 := 0; 67120#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67119#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67118#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67117#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67116#L665-42 assume 1 == ~t1_pc~0; 65667#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65669#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65926#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64443#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64444#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66070#L684-42 assume 1 == ~t2_pc~0; 65322#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65323#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65065#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65066#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65075#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65214#L703-42 assume 1 == ~t3_pc~0; 66021#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 67101#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67100#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67099#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67098#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67097#L722-42 assume 1 == ~t4_pc~0; 65576#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65577#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65572#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64585#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64586#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66083#L741-42 assume 1 == ~t5_pc~0; 65931#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64968#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64969#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65143#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64881#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64882#L760-42 assume !(1 == ~t6_pc~0); 65012#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 66688#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66687#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66686#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 66683#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65802#L779-42 assume 1 == ~t7_pc~0; 65735#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65676#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65170#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65171#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64365#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64366#L798-42 assume 1 == ~t8_pc~0; 64829#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 63983#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65877#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66624#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66622#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65832#L817-42 assume 1 == ~t9_pc~0; 65833#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66599#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66593#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66592#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66591#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66590#L836-42 assume 1 == ~t10_pc~0; 65563#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64518#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64519#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65933#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65934#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66576#L855-42 assume !(1 == ~t11_pc~0); 66011#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 64073#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64074#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65651#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65652#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64698#L874-42 assume !(1 == ~t12_pc~0); 64699#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 64928#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65121#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 65122#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64237#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 64238#L893-42 assume !(1 == ~t13_pc~0); 66101#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 66544#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66542#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 66541#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66540#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 66539#L912-42 assume 1 == ~t14_pc~0; 65985#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 63940#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 63941#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 64736#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 64362#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64363#L1495-3 assume !(1 == ~M_E~0); 64981#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65444#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65547#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64590#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64550#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64551#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66526#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65470#L1530-3 assume !(1 == ~T8_E~0); 66524#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 66517#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65781#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65782#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 65924#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 66499#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 66497#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66496#L1570-3 assume !(1 == ~E_2~0); 66495#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66494#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66493#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66492#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 66491#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66490#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65796#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65797#L1610-3 assume !(1 == ~E_10~0); 66485#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 66483#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 65228#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 65229#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 66105#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 66448#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 66438#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 66436#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 65472#L2036 assume !(0 == start_simulation_~tmp~3#1); 65473#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 65972#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 64767#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 63986#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 63987#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65163#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66017#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 66051#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 64777#L2017-2 [2023-11-19 07:48:25,294 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:25,295 INFO L85 PathProgramCache]: Analyzing trace with hash 1463218542, now seen corresponding path program 1 times [2023-11-19 07:48:25,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:25,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487314540] [2023-11-19 07:48:25,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:25,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:25,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:25,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:25,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:25,437 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487314540] [2023-11-19 07:48:25,437 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [487314540] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:25,437 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:25,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:25,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346393262] [2023-11-19 07:48:25,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:25,439 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:25,439 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:25,439 INFO L85 PathProgramCache]: Analyzing trace with hash 696783792, now seen corresponding path program 1 times [2023-11-19 07:48:25,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:25,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581590514] [2023-11-19 07:48:25,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:25,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:25,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:25,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:25,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:25,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581590514] [2023-11-19 07:48:25,539 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581590514] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:25,539 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:25,539 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:25,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222526550] [2023-11-19 07:48:25,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:25,540 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:25,540 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:25,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:25,541 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:25,541 INFO L87 Difference]: Start difference. First operand 3966 states and 5830 transitions. cyclomatic complexity: 1866 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:25,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:25,856 INFO L93 Difference]: Finished difference Result 7544 states and 11081 transitions. [2023-11-19 07:48:25,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7544 states and 11081 transitions. [2023-11-19 07:48:25,904 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7292 [2023-11-19 07:48:25,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7544 states to 7544 states and 11081 transitions. [2023-11-19 07:48:25,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7544 [2023-11-19 07:48:25,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7544 [2023-11-19 07:48:25,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7544 states and 11081 transitions. [2023-11-19 07:48:25,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:25,951 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7544 states and 11081 transitions. [2023-11-19 07:48:25,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7544 states and 11081 transitions. [2023-11-19 07:48:26,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7544 to 7540. [2023-11-19 07:48:26,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7540 states, 7540 states have (on average 1.4690981432360743) internal successors, (11077), 7539 states have internal predecessors, (11077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:26,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7540 states to 7540 states and 11077 transitions. [2023-11-19 07:48:26,126 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7540 states and 11077 transitions. [2023-11-19 07:48:26,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:48:26,127 INFO L428 stractBuchiCegarLoop]: Abstraction has 7540 states and 11077 transitions. [2023-11-19 07:48:26,127 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:48:26,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7540 states and 11077 transitions. [2023-11-19 07:48:26,162 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7292 [2023-11-19 07:48:26,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:26,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:26,166 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:26,167 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:26,167 INFO L748 eck$LassoCheckResult]: Stem: 75764#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 75765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 76729#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76730#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77619#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 76316#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76317#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76024#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76025#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77342#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76617#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76618#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77191#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76522#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76523#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75929#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 75930#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 76284#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 76473#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 75504#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75505#L1342 assume !(0 == ~M_E~0); 75673#L1342-2 assume !(0 == ~T1_E~0); 76249#L1347-1 assume !(0 == ~T2_E~0); 77322#L1352-1 assume !(0 == ~T3_E~0); 77092#L1357-1 assume !(0 == ~T4_E~0); 76273#L1362-1 assume !(0 == ~T5_E~0); 76274#L1367-1 assume !(0 == ~T6_E~0); 75841#L1372-1 assume !(0 == ~T7_E~0); 75842#L1377-1 assume !(0 == ~T8_E~0); 76189#L1382-1 assume !(0 == ~T9_E~0); 76190#L1387-1 assume !(0 == ~T10_E~0); 76962#L1392-1 assume !(0 == ~T11_E~0); 76230#L1397-1 assume !(0 == ~T12_E~0); 76231#L1402-1 assume !(0 == ~T13_E~0); 75866#L1407-1 assume !(0 == ~T14_E~0); 75867#L1412-1 assume !(0 == ~E_1~0); 77224#L1417-1 assume !(0 == ~E_2~0); 77225#L1422-1 assume !(0 == ~E_3~0); 77526#L1427-1 assume !(0 == ~E_4~0); 76053#L1432-1 assume !(0 == ~E_5~0); 76054#L1437-1 assume !(0 == ~E_6~0); 77137#L1442-1 assume !(0 == ~E_7~0); 77138#L1447-1 assume !(0 == ~E_8~0); 76956#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 75642#L1457-1 assume !(0 == ~E_10~0); 75643#L1462-1 assume !(0 == ~E_11~0); 77170#L1467-1 assume !(0 == ~E_12~0); 77185#L1472-1 assume !(0 == ~E_13~0); 77186#L1477-1 assume !(0 == ~E_14~0); 76901#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75830#L646 assume 1 == ~m_pc~0; 75831#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 76532#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76547#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75931#L1666 assume !(0 != activate_threads_~tmp~1#1); 75932#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77553#L665 assume !(1 == ~t1_pc~0); 76422#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76423#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77065#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77066#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 76779#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76780#L684 assume 1 == ~t2_pc~0; 76897#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76819#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75917#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75918#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 77327#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77571#L703 assume !(1 == ~t3_pc~0); 76078#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76079#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77049#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75476#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 75477#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75962#L722 assume 1 == ~t4_pc~0; 76736#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76153#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75587#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75588#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 76569#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75674#L741 assume 1 == ~t5_pc~0; 75675#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75984#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76813#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76865#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 76866#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76250#L760 assume !(1 == ~t6_pc~0); 76077#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76076#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75909#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75910#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76689#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76690#L779 assume 1 == ~t7_pc~0; 75711#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75558#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75559#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77367#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 75998#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75999#L798 assume !(1 == ~t8_pc~0); 77379#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 77279#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77280#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77490#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 77555#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75537#L817 assume 1 == ~t9_pc~0; 75538#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76353#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75966#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75967#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 75943#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75944#L836 assume !(1 == ~t10_pc~0); 75968#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75891#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75892#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76154#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 76155#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77295#L855 assume 1 == ~t11_pc~0; 76543#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76544#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77162#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76953#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 76785#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75827#L874 assume !(1 == ~t12_pc~0); 75828#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76007#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75526#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75527#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 75512#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 75513#L893 assume 1 == ~t13_pc~0; 77464#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 75869#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76188#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77394#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 77385#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 77386#L912 assume 1 == ~t14_pc~0; 77144#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 77145#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 77221#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 75762#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 75763#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76562#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 77014#L1495-2 assume !(1 == ~T1_E~0); 77015#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77518#L1505-1 assume !(1 == ~T3_E~0); 77907#L1510-1 assume !(1 == ~T4_E~0); 77906#L1515-1 assume !(1 == ~T5_E~0); 77905#L1520-1 assume !(1 == ~T6_E~0); 77904#L1525-1 assume !(1 == ~T7_E~0); 77903#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75936#L1535-1 assume !(1 == ~T9_E~0); 75937#L1540-1 assume !(1 == ~T10_E~0); 75437#L1545-1 assume !(1 == ~T11_E~0); 75438#L1550-1 assume !(1 == ~T12_E~0); 77628#L1555-1 assume !(1 == ~T13_E~0); 75987#L1560-1 assume !(1 == ~T14_E~0); 75988#L1565-1 assume !(1 == ~E_1~0); 77823#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 77789#L1575-1 assume !(1 == ~E_3~0); 77786#L1580-1 assume !(1 == ~E_4~0); 77775#L1585-1 assume !(1 == ~E_5~0); 77769#L1590-1 assume !(1 == ~E_6~0); 77765#L1595-1 assume !(1 == ~E_7~0); 77759#L1600-1 assume !(1 == ~E_8~0); 77741#L1605-1 assume !(1 == ~E_9~0); 77717#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 77715#L1615-1 assume !(1 == ~E_11~0); 77713#L1620-1 assume !(1 == ~E_12~0); 77703#L1625-1 assume !(1 == ~E_13~0); 77694#L1630-1 assume !(1 == ~E_14~0); 77686#L1635-1 assume { :end_inline_reset_delta_events } true; 77679#L2017-2 [2023-11-19 07:48:26,168 INFO L750 eck$LassoCheckResult]: Loop: 77679#L2017-2 assume !false; 77675#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77674#L1316-1 assume !false; 77673#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77668#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77657#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77656#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 77654#L1115 assume !(0 != eval_~tmp~0#1); 77653#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77652#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77651#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77650#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77648#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77649#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82866#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82865#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82864#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 82863#L1372-3 assume !(0 == ~T7_E~0); 82862#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 82861#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 82860#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 82859#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 77625#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 77516#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 76674#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 75786#L1412-3 assume !(0 == ~E_1~0); 75787#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76572#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76573#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 77353#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76997#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76691#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 76692#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 75554#L1452-3 assume !(0 == ~E_9~0); 75555#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77277#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77278#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 77070#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 77071#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 75784#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75785#L646-42 assume !(1 == ~m_pc~0); 76399#L646-44 is_master_triggered_~__retres1~0#1 := 0; 77323#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76260#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76261#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77496#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77244#L665-42 assume !(1 == ~t1_pc~0); 77199#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 77200#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77460#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75969#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75970#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77596#L684-42 assume 1 == ~t2_pc~0; 76861#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76862#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81333#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81332#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81038#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81034#L703-42 assume 1 == ~t3_pc~0; 81031#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81027#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81023#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81020#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81017#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81013#L722-42 assume 1 == ~t4_pc~0; 81009#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 81006#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81002#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80999#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 80996#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80992#L741-42 assume 1 == ~t5_pc~0; 80989#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 80986#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80983#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80954#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 80953#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80952#L760-42 assume !(1 == ~t6_pc~0); 80951#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 80949#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80948#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80947#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 80946#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 80945#L779-42 assume !(1 == ~t7_pc~0); 80944#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 80942#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80941#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 80940#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 80939#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 80938#L798-42 assume !(1 == ~t8_pc~0); 80937#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 80934#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80931#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80929#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 80927#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80925#L817-42 assume !(1 == ~t9_pc~0); 80923#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 80920#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 80917#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 80915#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 76992#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76993#L836-42 assume !(1 == ~t10_pc~0); 77104#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 76048#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76049#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76860#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77471#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77531#L855-42 assume !(1 == ~t11_pc~0); 77647#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 79241#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 79213#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 79211#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 79198#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 79197#L874-42 assume !(1 == ~t12_pc~0); 79175#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 79172#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 79170#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 79168#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 79166#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 79164#L893-42 assume 1 == ~t13_pc~0; 79161#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 79160#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 79157#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 79155#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 79154#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 79153#L912-42 assume 1 == ~t14_pc~0; 79113#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 79110#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 79108#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 79106#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 79104#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79102#L1495-3 assume !(1 == ~M_E~0); 79099#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 79097#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77480#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 79086#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 79079#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 79078#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 79077#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 79017#L1530-3 assume !(1 == ~T8_E~0); 79042#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 79039#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 79037#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78102#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78061#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 78023#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 78021#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78018#L1570-3 assume !(1 == ~E_2~0); 78016#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78014#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77977#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77937#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77896#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77894#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77892#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77891#L1610-3 assume !(1 == ~E_10~0); 77890#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 77888#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 77861#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 77859#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 77857#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77815#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77805#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77785#L2036 assume !(0 == start_simulation_~tmp~3#1); 77758#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77735#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77716#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77714#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 77712#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77702#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77693#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 77685#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 77679#L2017-2 [2023-11-19 07:48:26,169 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:26,169 INFO L85 PathProgramCache]: Analyzing trace with hash -1432795152, now seen corresponding path program 1 times [2023-11-19 07:48:26,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:26,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320498900] [2023-11-19 07:48:26,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:26,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:26,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:26,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:26,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:26,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320498900] [2023-11-19 07:48:26,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320498900] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:26,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:26,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:26,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758431591] [2023-11-19 07:48:26,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:26,264 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:26,264 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:26,265 INFO L85 PathProgramCache]: Analyzing trace with hash -989565012, now seen corresponding path program 1 times [2023-11-19 07:48:26,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:26,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236359157] [2023-11-19 07:48:26,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:26,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:26,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:26,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:26,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:26,337 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236359157] [2023-11-19 07:48:26,337 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236359157] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:26,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:26,338 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:26,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [776990242] [2023-11-19 07:48:26,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:26,339 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:26,339 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:26,339 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:26,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:26,340 INFO L87 Difference]: Start difference. First operand 7540 states and 11077 transitions. cyclomatic complexity: 3541 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:26,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:26,666 INFO L93 Difference]: Finished difference Result 14440 states and 21190 transitions. [2023-11-19 07:48:26,666 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14440 states and 21190 transitions. [2023-11-19 07:48:26,737 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14156 [2023-11-19 07:48:26,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14440 states to 14440 states and 21190 transitions. [2023-11-19 07:48:26,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14440 [2023-11-19 07:48:26,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14440 [2023-11-19 07:48:26,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14440 states and 21190 transitions. [2023-11-19 07:48:26,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:26,824 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14440 states and 21190 transitions. [2023-11-19 07:48:26,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14440 states and 21190 transitions. [2023-11-19 07:48:27,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14440 to 14436. [2023-11-19 07:48:27,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14436 states, 14436 states have (on average 1.467581047381546) internal successors, (21186), 14435 states have internal predecessors, (21186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:27,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14436 states to 14436 states and 21186 transitions. [2023-11-19 07:48:27,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14436 states and 21186 transitions. [2023-11-19 07:48:27,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:48:27,078 INFO L428 stractBuchiCegarLoop]: Abstraction has 14436 states and 21186 transitions. [2023-11-19 07:48:27,078 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 07:48:27,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14436 states and 21186 transitions. [2023-11-19 07:48:27,125 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14156 [2023-11-19 07:48:27,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:27,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:27,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:27,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:27,129 INFO L748 eck$LassoCheckResult]: Stem: 97755#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 97756#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 98701#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 98702#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 99508#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 98296#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98297#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98005#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98006#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 99294#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98596#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 98597#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 99153#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 98500#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 98501#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97915#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97916#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 98265#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 98453#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 97494#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 97495#L1342 assume !(0 == ~M_E~0); 97663#L1342-2 assume !(0 == ~T1_E~0); 98232#L1347-1 assume !(0 == ~T2_E~0); 99272#L1352-1 assume !(0 == ~T3_E~0); 99054#L1357-1 assume !(0 == ~T4_E~0); 98254#L1362-1 assume !(0 == ~T5_E~0); 98255#L1367-1 assume !(0 == ~T6_E~0); 97830#L1372-1 assume !(0 == ~T7_E~0); 97831#L1377-1 assume !(0 == ~T8_E~0); 98171#L1382-1 assume !(0 == ~T9_E~0); 98172#L1387-1 assume !(0 == ~T10_E~0); 98932#L1392-1 assume !(0 == ~T11_E~0); 98213#L1397-1 assume !(0 == ~T12_E~0); 98214#L1402-1 assume !(0 == ~T13_E~0); 97854#L1407-1 assume !(0 == ~T14_E~0); 97855#L1412-1 assume !(0 == ~E_1~0); 99185#L1417-1 assume !(0 == ~E_2~0); 99186#L1422-1 assume !(0 == ~E_3~0); 99443#L1427-1 assume !(0 == ~E_4~0); 98036#L1432-1 assume !(0 == ~E_5~0); 98037#L1437-1 assume !(0 == ~E_6~0); 99099#L1442-1 assume !(0 == ~E_7~0); 99100#L1447-1 assume !(0 == ~E_8~0); 98924#L1452-1 assume !(0 == ~E_9~0); 97632#L1457-1 assume !(0 == ~E_10~0); 97633#L1462-1 assume !(0 == ~E_11~0); 99131#L1467-1 assume !(0 == ~E_12~0); 99147#L1472-1 assume !(0 == ~E_13~0); 99148#L1477-1 assume !(0 == ~E_14~0); 98870#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97819#L646 assume 1 == ~m_pc~0; 97820#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 98510#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98525#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97917#L1666 assume !(0 != activate_threads_~tmp~1#1); 97918#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99468#L665 assume !(1 == ~t1_pc~0); 98402#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 98403#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99026#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 99027#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 98750#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98751#L684 assume 1 == ~t2_pc~0; 98867#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 98791#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97903#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97904#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 99277#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99482#L703 assume !(1 == ~t3_pc~0); 98061#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 98062#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99013#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97466#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 97467#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97947#L722 assume 1 == ~t4_pc~0; 98708#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 98136#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97577#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97578#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 98547#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97664#L741 assume 1 == ~t5_pc~0; 97665#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 97969#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98785#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 98837#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 98838#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98233#L760 assume !(1 == ~t6_pc~0); 98060#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 98059#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97895#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97896#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 98663#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 98664#L779 assume 1 == ~t7_pc~0; 97703#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 97548#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97549#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99316#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 97981#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97982#L798 assume !(1 == ~t8_pc~0); 99326#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 99234#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99235#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99417#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 99470#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97527#L817 assume 1 == ~t9_pc~0; 97528#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 98334#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97951#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97952#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 97929#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97930#L836 assume !(1 == ~t10_pc~0); 97953#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 97879#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97880#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 98137#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 98138#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 99249#L855 assume 1 == ~t11_pc~0; 98521#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 98522#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99125#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 98921#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 98756#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97816#L874 assume !(1 == ~t12_pc~0); 97817#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 97990#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 97516#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 97517#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 97502#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 97503#L893 assume 1 == ~t13_pc~0; 99397#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 97857#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 98170#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 99340#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 99332#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 99333#L912 assume 1 == ~t14_pc~0; 99107#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 99108#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 99182#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 97753#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 97754#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98540#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 98982#L1495-2 assume !(1 == ~T1_E~0); 98983#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98657#L1505-1 assume !(1 == ~T3_E~0); 98658#L1510-1 assume !(1 == ~T4_E~0); 98718#L1515-1 assume !(1 == ~T5_E~0); 98719#L1520-1 assume !(1 == ~T6_E~0); 99327#L1525-1 assume !(1 == ~T7_E~0); 99328#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 100052#L1535-1 assume !(1 == ~T9_E~0); 100050#L1540-1 assume !(1 == ~T10_E~0); 100048#L1545-1 assume !(1 == ~T11_E~0); 99894#L1550-1 assume !(1 == ~T12_E~0); 99891#L1555-1 assume !(1 == ~T13_E~0); 99889#L1560-1 assume !(1 == ~T14_E~0); 99887#L1565-1 assume !(1 == ~E_1~0); 99788#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 99786#L1575-1 assume !(1 == ~E_3~0); 99783#L1580-1 assume !(1 == ~E_4~0); 99781#L1585-1 assume !(1 == ~E_5~0); 99779#L1590-1 assume !(1 == ~E_6~0); 99777#L1595-1 assume !(1 == ~E_7~0); 99775#L1600-1 assume !(1 == ~E_8~0); 99632#L1605-1 assume !(1 == ~E_9~0); 99614#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 99602#L1615-1 assume !(1 == ~E_11~0); 99592#L1620-1 assume !(1 == ~E_12~0); 99582#L1625-1 assume !(1 == ~E_13~0); 99573#L1630-1 assume !(1 == ~E_14~0); 99565#L1635-1 assume { :end_inline_reset_delta_events } true; 99558#L2017-2 [2023-11-19 07:48:27,130 INFO L750 eck$LassoCheckResult]: Loop: 99558#L2017-2 assume !false; 99554#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99553#L1316-1 assume !false; 99552#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 99547#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 99536#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 99535#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 99533#L1115 assume !(0 != eval_~tmp~0#1); 99532#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 99531#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 99530#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 99529#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 99527#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 99528#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 102551#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 102549#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 102547#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 102544#L1372-3 assume !(0 == ~T7_E~0); 102542#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 102540#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 102538#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 102536#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 102534#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 102531#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 102529#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 102527#L1412-3 assume !(0 == ~E_1~0); 102525#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 102523#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 102521#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 102518#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102516#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 102514#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 102512#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 102510#L1452-3 assume !(0 == ~E_9~0); 102508#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 102505#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 102503#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 102501#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 102499#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 102497#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102495#L646-42 assume 1 == ~m_pc~0; 102491#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 102489#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102487#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 102485#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 102483#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102481#L665-42 assume !(1 == ~t1_pc~0); 102477#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 102475#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102473#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102471#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 102469#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102467#L684-42 assume !(1 == ~t2_pc~0); 102464#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 102461#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102459#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102457#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 102455#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102454#L703-42 assume !(1 == ~t3_pc~0); 102449#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 102447#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102445#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102444#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 102443#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102442#L722-42 assume !(1 == ~t4_pc~0); 102441#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 102439#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102438#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 102437#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 102436#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102435#L741-42 assume !(1 == ~t5_pc~0); 102433#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 102432#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102431#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 102430#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 102429#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102428#L760-42 assume 1 == ~t6_pc~0; 102425#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 102422#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102420#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 102418#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 102416#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 102414#L779-42 assume 1 == ~t7_pc~0; 102411#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 102410#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102407#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 102405#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 102403#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102401#L798-42 assume !(1 == ~t8_pc~0); 102399#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 102396#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 102393#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 102391#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102389#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102387#L817-42 assume !(1 == ~t9_pc~0); 102384#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 101610#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 101607#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 101605#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 101603#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 101601#L836-42 assume 1 == ~t10_pc~0; 101599#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 101596#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 101593#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 101591#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101589#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 101587#L855-42 assume !(1 == ~t11_pc~0); 101584#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 101580#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 101578#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 101576#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 101574#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 101572#L874-42 assume !(1 == ~t12_pc~0); 101569#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 101568#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 101565#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 101563#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 101561#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 101559#L893-42 assume !(1 == ~t13_pc~0); 101557#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 101554#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 101551#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 101549#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 101547#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 101545#L912-42 assume 1 == ~t14_pc~0; 101533#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 101530#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 101528#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 101526#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 101523#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101521#L1495-3 assume !(1 == ~M_E~0); 101519#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101517#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 99407#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101514#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101511#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101510#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100878#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 98978#L1530-3 assume !(1 == ~T8_E~0); 100874#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 100872#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100870#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 100868#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 100866#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 100863#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 100537#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 100533#L1570-3 assume !(1 == ~E_2~0); 100531#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 100529#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 100295#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 100293#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 100290#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 100288#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 100286#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 100282#L1610-3 assume !(1 == ~E_10~0); 100280#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 100278#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 100275#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 100273#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 100271#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 100034#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 100024#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 99880#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 99876#L2036 assume !(0 == start_simulation_~tmp~3#1); 99746#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 99624#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 99613#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 99601#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 99591#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 99581#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 99572#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 99564#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 99558#L2017-2 [2023-11-19 07:48:27,131 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:27,131 INFO L85 PathProgramCache]: Analyzing trace with hash -1867300750, now seen corresponding path program 1 times [2023-11-19 07:48:27,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:27,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335320981] [2023-11-19 07:48:27,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:27,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:27,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:27,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:27,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:27,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335320981] [2023-11-19 07:48:27,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335320981] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:27,320 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:27,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:27,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648992122] [2023-11-19 07:48:27,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:27,321 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:27,321 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:27,321 INFO L85 PathProgramCache]: Analyzing trace with hash 2109817291, now seen corresponding path program 1 times [2023-11-19 07:48:27,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:27,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896756651] [2023-11-19 07:48:27,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:27,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:27,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:27,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:27,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:27,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896756651] [2023-11-19 07:48:27,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896756651] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:27,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:27,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:27,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680193850] [2023-11-19 07:48:27,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:27,399 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:27,399 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:27,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:27,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:27,400 INFO L87 Difference]: Start difference. First operand 14436 states and 21186 transitions. cyclomatic complexity: 6758 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:27,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:27,624 INFO L93 Difference]: Finished difference Result 21593 states and 31472 transitions. [2023-11-19 07:48:27,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21593 states and 31472 transitions. [2023-11-19 07:48:27,725 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21306 [2023-11-19 07:48:27,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21593 states to 21593 states and 31472 transitions. [2023-11-19 07:48:27,807 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21593 [2023-11-19 07:48:27,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21593 [2023-11-19 07:48:27,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21593 states and 31472 transitions. [2023-11-19 07:48:27,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:27,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21593 states and 31472 transitions. [2023-11-19 07:48:27,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21593 states and 31472 transitions. [2023-11-19 07:48:28,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21593 to 21165. [2023-11-19 07:48:28,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21165 states, 21165 states have (on average 1.4586345381526105) internal successors, (30872), 21164 states have internal predecessors, (30872), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:28,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21165 states to 21165 states and 30872 transitions. [2023-11-19 07:48:28,346 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21165 states and 30872 transitions. [2023-11-19 07:48:28,347 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:28,347 INFO L428 stractBuchiCegarLoop]: Abstraction has 21165 states and 30872 transitions. [2023-11-19 07:48:28,347 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 07:48:28,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21165 states and 30872 transitions. [2023-11-19 07:48:28,413 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 20882 [2023-11-19 07:48:28,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:28,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:28,416 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:28,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:28,417 INFO L748 eck$LassoCheckResult]: Stem: 133788#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 133789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 134738#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134739#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 135615#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 134332#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 134333#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 134041#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 134042#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 135354#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 134630#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 134631#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 135207#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 134533#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 134534#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 133948#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 133949#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 134301#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 134485#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 133532#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 133533#L1342 assume !(0 == ~M_E~0); 133699#L1342-2 assume !(0 == ~T1_E~0); 134268#L1347-1 assume !(0 == ~T2_E~0); 135331#L1352-1 assume !(0 == ~T3_E~0); 135103#L1357-1 assume !(0 == ~T4_E~0); 134290#L1362-1 assume !(0 == ~T5_E~0); 134291#L1367-1 assume !(0 == ~T6_E~0); 133862#L1372-1 assume !(0 == ~T7_E~0); 133863#L1377-1 assume !(0 == ~T8_E~0); 134208#L1382-1 assume !(0 == ~T9_E~0); 134209#L1387-1 assume !(0 == ~T10_E~0); 134976#L1392-1 assume !(0 == ~T11_E~0); 134251#L1397-1 assume !(0 == ~T12_E~0); 134252#L1402-1 assume !(0 == ~T13_E~0); 133886#L1407-1 assume !(0 == ~T14_E~0); 133887#L1412-1 assume !(0 == ~E_1~0); 135239#L1417-1 assume !(0 == ~E_2~0); 135240#L1422-1 assume !(0 == ~E_3~0); 135528#L1427-1 assume !(0 == ~E_4~0); 134070#L1432-1 assume !(0 == ~E_5~0); 134071#L1437-1 assume !(0 == ~E_6~0); 135153#L1442-1 assume !(0 == ~E_7~0); 135154#L1447-1 assume !(0 == ~E_8~0); 134970#L1452-1 assume !(0 == ~E_9~0); 133668#L1457-1 assume !(0 == ~E_10~0); 133669#L1462-1 assume !(0 == ~E_11~0); 135186#L1467-1 assume !(0 == ~E_12~0); 135201#L1472-1 assume !(0 == ~E_13~0); 135202#L1477-1 assume !(0 == ~E_14~0); 134912#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133852#L646 assume !(1 == ~m_pc~0); 133853#L646-2 is_master_triggered_~__retres1~0#1 := 0; 134560#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134561#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 133950#L1666 assume !(0 != activate_threads_~tmp~1#1); 133951#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 135557#L665 assume !(1 == ~t1_pc~0); 134435#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 134436#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135075#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 135076#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 134789#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134790#L684 assume 1 == ~t2_pc~0; 134911#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 134831#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133936#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 133937#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 135336#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 135574#L703 assume !(1 == ~t3_pc~0); 134095#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 134096#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135061#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 133502#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 133503#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 133981#L722 assume 1 == ~t4_pc~0; 134745#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 134172#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 133613#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 133614#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 134582#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133700#L741 assume 1 == ~t5_pc~0; 133701#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 134003#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 134822#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 134879#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 134880#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134269#L760 assume !(1 == ~t6_pc~0); 134094#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 134093#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 133928#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 133929#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 134698#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 134699#L779 assume 1 == ~t7_pc~0; 133736#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 133584#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 133585#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 135382#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 134016#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 134017#L798 assume !(1 == ~t8_pc~0); 135392#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 135292#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 135293#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 135495#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 135559#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133563#L817 assume 1 == ~t9_pc~0; 133564#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 134368#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 133985#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 133986#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 133962#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133963#L836 assume !(1 == ~t10_pc~0); 133987#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 133911#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133912#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 134173#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 134174#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 135306#L855 assume 1 == ~t11_pc~0; 134556#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 134557#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 135179#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 134967#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 134795#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 133849#L874 assume !(1 == ~t12_pc~0); 133850#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 134025#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 133552#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 133553#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 133538#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 133539#L893 assume 1 == ~t13_pc~0; 135475#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 133889#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 134207#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 135411#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 135398#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 135399#L912 assume 1 == ~t14_pc~0; 135161#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 135162#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 135236#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 133786#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 133787#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134575#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 135028#L1495-2 assume !(1 == ~T1_E~0); 135029#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 135519#L1505-1 assume !(1 == ~T3_E~0); 135611#L1510-1 assume !(1 == ~T4_E~0); 135612#L1515-1 assume !(1 == ~T5_E~0); 135549#L1520-1 assume !(1 == ~T6_E~0); 135550#L1525-1 assume !(1 == ~T7_E~0); 142836#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 142835#L1535-1 assume !(1 == ~T9_E~0); 142834#L1540-1 assume !(1 == ~T10_E~0); 142833#L1545-1 assume !(1 == ~T11_E~0); 142832#L1550-1 assume !(1 == ~T12_E~0); 142831#L1555-1 assume !(1 == ~T13_E~0); 142830#L1560-1 assume !(1 == ~T14_E~0); 142829#L1565-1 assume !(1 == ~E_1~0); 142828#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 142827#L1575-1 assume !(1 == ~E_3~0); 142826#L1580-1 assume !(1 == ~E_4~0); 142825#L1585-1 assume !(1 == ~E_5~0); 142824#L1590-1 assume !(1 == ~E_6~0); 142823#L1595-1 assume !(1 == ~E_7~0); 142822#L1600-1 assume !(1 == ~E_8~0); 142821#L1605-1 assume !(1 == ~E_9~0); 142817#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 142816#L1615-1 assume !(1 == ~E_11~0); 142814#L1620-1 assume !(1 == ~E_12~0); 142815#L1625-1 assume !(1 == ~E_13~0); 143790#L1630-1 assume !(1 == ~E_14~0); 143789#L1635-1 assume { :end_inline_reset_delta_events } true; 142764#L2017-2 [2023-11-19 07:48:28,418 INFO L750 eck$LassoCheckResult]: Loop: 142764#L2017-2 assume !false; 142765#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 142753#L1316-1 assume !false; 142754#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 142734#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 142724#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 142717#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 142718#L1115 assume !(0 != eval_~tmp~0#1); 143773#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 143771#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 143769#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 143767#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 143764#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 143762#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 143760#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 143758#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 143756#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 143753#L1372-3 assume !(0 == ~T7_E~0); 143751#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 143749#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 143747#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 143745#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 143743#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 143740#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 143738#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 143736#L1412-3 assume !(0 == ~E_1~0); 143734#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 143732#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 143730#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 143727#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 143725#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 143723#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 143721#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 143719#L1452-3 assume !(0 == ~E_9~0); 143717#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 143714#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 143712#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 143710#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 143708#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 143706#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 143704#L646-42 assume !(1 == ~m_pc~0); 143701#L646-44 is_master_triggered_~__retres1~0#1 := 0; 143699#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 143697#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 143695#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 143693#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 143692#L665-42 assume !(1 == ~t1_pc~0); 143686#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 143684#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143682#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 143680#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 143679#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143678#L684-42 assume 1 == ~t2_pc~0; 143676#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 143673#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143669#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 143665#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 143661#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 143657#L703-42 assume !(1 == ~t3_pc~0); 143652#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 143651#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 143650#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 143649#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 143648#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143647#L722-42 assume !(1 == ~t4_pc~0); 143646#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 143644#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143643#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 143642#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 143641#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143640#L741-42 assume !(1 == ~t5_pc~0); 143638#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 143637#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143636#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 143635#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 143634#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143633#L760-42 assume !(1 == ~t6_pc~0); 143632#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 143631#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 147094#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 143626#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 143625#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 143624#L779-42 assume 1 == ~t7_pc~0; 143622#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 143621#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 143620#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 143619#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 143618#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 143616#L798-42 assume 1 == ~t8_pc~0; 143612#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 143610#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 143608#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 143606#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 143604#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 143601#L817-42 assume 1 == ~t9_pc~0; 143598#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 143596#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 143594#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 143592#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 143590#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 143585#L836-42 assume !(1 == ~t10_pc~0); 143586#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 147064#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 147063#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 147062#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 147061#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 147060#L855-42 assume 1 == ~t11_pc~0; 147058#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 147057#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 147056#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 147055#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 147054#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 147053#L874-42 assume !(1 == ~t12_pc~0); 147051#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 147050#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 147049#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 147048#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 147047#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 147046#L893-42 assume 1 == ~t13_pc~0; 147044#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 147043#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 147042#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 147041#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 147040#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 147039#L912-42 assume !(1 == ~t14_pc~0); 143112#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 143110#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 143107#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 143108#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 143100#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143101#L1495-3 assume !(1 == ~M_E~0); 143094#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 143095#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 135486#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143089#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 143082#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 143083#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 143077#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 143075#L1530-3 assume !(1 == ~T8_E~0); 143068#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 143069#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 143061#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 143062#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 143055#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 143056#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 143049#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 143050#L1570-3 assume !(1 == ~E_2~0); 143042#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 143043#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 143036#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 143037#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 143030#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 143031#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 143023#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 143024#L1610-3 assume !(1 == ~E_10~0); 143015#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 143016#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 143009#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 143010#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 143000#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 143001#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 144889#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 144886#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 142946#L2036 assume !(0 == start_simulation_~tmp~3#1); 142943#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 142944#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 143795#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 143794#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 143793#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143792#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 142805#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 142806#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 142764#L2017-2 [2023-11-19 07:48:28,419 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:28,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1199377425, now seen corresponding path program 1 times [2023-11-19 07:48:28,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:28,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17666938] [2023-11-19 07:48:28,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:28,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:28,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:28,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:28,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:28,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17666938] [2023-11-19 07:48:28,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17666938] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:28,634 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:28,634 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:28,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821373520] [2023-11-19 07:48:28,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:28,635 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:28,636 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:28,636 INFO L85 PathProgramCache]: Analyzing trace with hash -1765330324, now seen corresponding path program 1 times [2023-11-19 07:48:28,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:28,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706980731] [2023-11-19 07:48:28,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:28,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:28,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:28,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:28,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:28,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706980731] [2023-11-19 07:48:28,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706980731] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:28,723 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:28,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:28,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051466142] [2023-11-19 07:48:28,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:28,725 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:28,725 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:28,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:28,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:28,726 INFO L87 Difference]: Start difference. First operand 21165 states and 30872 transitions. cyclomatic complexity: 9719 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:29,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:29,406 INFO L93 Difference]: Finished difference Result 54744 states and 79330 transitions. [2023-11-19 07:48:29,406 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54744 states and 79330 transitions. [2023-11-19 07:48:30,033 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 53990 [2023-11-19 07:48:30,217 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54744 states to 54744 states and 79330 transitions. [2023-11-19 07:48:30,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54744 [2023-11-19 07:48:30,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54744 [2023-11-19 07:48:30,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54744 states and 79330 transitions. [2023-11-19 07:48:30,303 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:30,303 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54744 states and 79330 transitions. [2023-11-19 07:48:30,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54744 states and 79330 transitions. [2023-11-19 07:48:30,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54744 to 40584. [2023-11-19 07:48:31,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40584 states, 40584 states have (on average 1.452912477823773) internal successors, (58965), 40583 states have internal predecessors, (58965), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:31,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40584 states to 40584 states and 58965 transitions. [2023-11-19 07:48:31,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40584 states and 58965 transitions. [2023-11-19 07:48:31,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:48:31,213 INFO L428 stractBuchiCegarLoop]: Abstraction has 40584 states and 58965 transitions. [2023-11-19 07:48:31,213 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-19 07:48:31,214 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40584 states and 58965 transitions. [2023-11-19 07:48:31,457 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 40298 [2023-11-19 07:48:31,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:31,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:31,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:31,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:31,462 INFO L748 eck$LassoCheckResult]: Stem: 209706#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 209707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 210654#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 210655#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 211538#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 210247#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 210248#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 209955#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 209956#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 211274#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 210545#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 210546#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 211133#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 210448#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 210449#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 209864#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 209865#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 210216#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 210401#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 209449#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 209450#L1342 assume !(0 == ~M_E~0); 209618#L1342-2 assume !(0 == ~T1_E~0); 210183#L1347-1 assume !(0 == ~T2_E~0); 211254#L1352-1 assume !(0 == ~T3_E~0); 211023#L1357-1 assume !(0 == ~T4_E~0); 210205#L1362-1 assume !(0 == ~T5_E~0); 210206#L1367-1 assume !(0 == ~T6_E~0); 209779#L1372-1 assume !(0 == ~T7_E~0); 209780#L1377-1 assume !(0 == ~T8_E~0); 210123#L1382-1 assume !(0 == ~T9_E~0); 210124#L1387-1 assume !(0 == ~T10_E~0); 210890#L1392-1 assume !(0 == ~T11_E~0); 210164#L1397-1 assume !(0 == ~T12_E~0); 210165#L1402-1 assume !(0 == ~T13_E~0); 209803#L1407-1 assume !(0 == ~T14_E~0); 209804#L1412-1 assume !(0 == ~E_1~0); 211166#L1417-1 assume !(0 == ~E_2~0); 211167#L1422-1 assume !(0 == ~E_3~0); 211447#L1427-1 assume !(0 == ~E_4~0); 209985#L1432-1 assume !(0 == ~E_5~0); 209986#L1437-1 assume !(0 == ~E_6~0); 211073#L1442-1 assume !(0 == ~E_7~0); 211074#L1447-1 assume !(0 == ~E_8~0); 210884#L1452-1 assume !(0 == ~E_9~0); 209587#L1457-1 assume !(0 == ~E_10~0); 209588#L1462-1 assume !(0 == ~E_11~0); 211109#L1467-1 assume !(0 == ~E_12~0); 211127#L1472-1 assume !(0 == ~E_13~0); 211128#L1477-1 assume !(0 == ~E_14~0); 210828#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 209769#L646 assume !(1 == ~m_pc~0); 209770#L646-2 is_master_triggered_~__retres1~0#1 := 0; 210476#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 210477#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 209866#L1666 assume !(0 != activate_threads_~tmp~1#1); 209867#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 211477#L665 assume !(1 == ~t1_pc~0); 210350#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 210351#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 210990#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 210991#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 210705#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210706#L684 assume !(1 == ~t2_pc~0); 210744#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 210745#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209852#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 209853#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 211259#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 211490#L703 assume !(1 == ~t3_pc~0); 210010#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 210011#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 210975#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 209421#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 209422#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 209896#L722 assume 1 == ~t4_pc~0; 210661#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 210087#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 209532#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 209533#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 210498#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 209619#L741 assume 1 == ~t5_pc~0; 209620#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 209918#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 210739#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 210796#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 210797#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 210184#L760 assume !(1 == ~t6_pc~0); 210009#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 210008#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 209844#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 209845#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 210615#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 210616#L779 assume 1 == ~t7_pc~0; 209655#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 209503#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 209504#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 211299#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 209931#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 209932#L798 assume !(1 == ~t8_pc~0); 211309#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 211213#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 211214#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 211417#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 211479#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 209482#L817 assume 1 == ~t9_pc~0; 209483#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 210283#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 209900#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 209901#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 209878#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 209879#L836 assume !(1 == ~t10_pc~0); 209902#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 209828#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 209829#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 210088#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 210089#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 211230#L855 assume 1 == ~t11_pc~0; 210472#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 210473#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 211102#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 210881#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 210711#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 209766#L874 assume !(1 == ~t12_pc~0); 209767#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 209940#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 209471#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 209472#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 209457#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 209458#L893 assume 1 == ~t13_pc~0; 211388#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 209806#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 210122#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 211324#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 211314#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 211315#L912 assume 1 == ~t14_pc~0; 211081#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 211082#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 211163#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 209704#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 209705#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 210491#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 210943#L1495-2 assume !(1 == ~T1_E~0); 210944#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 210609#L1505-1 assume !(1 == ~T3_E~0); 210610#L1510-1 assume !(1 == ~T4_E~0); 210671#L1515-1 assume !(1 == ~T5_E~0); 210672#L1520-1 assume !(1 == ~T6_E~0); 211310#L1525-1 assume !(1 == ~T7_E~0); 210976#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 210977#L1535-1 assume !(1 == ~T9_E~0); 211508#L1540-1 assume !(1 == ~T10_E~0); 211509#L1545-1 assume !(1 == ~T11_E~0); 211551#L1550-1 assume !(1 == ~T12_E~0); 211552#L1555-1 assume !(1 == ~T13_E~0); 209921#L1560-1 assume !(1 == ~T14_E~0); 209922#L1565-1 assume !(1 == ~E_1~0); 239138#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 239137#L1575-1 assume !(1 == ~E_3~0); 239136#L1580-1 assume !(1 == ~E_4~0); 239135#L1585-1 assume !(1 == ~E_5~0); 239134#L1590-1 assume !(1 == ~E_6~0); 239133#L1595-1 assume !(1 == ~E_7~0); 239132#L1600-1 assume !(1 == ~E_8~0); 239131#L1605-1 assume !(1 == ~E_9~0); 239128#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 239127#L1615-1 assume !(1 == ~E_11~0); 239126#L1620-1 assume !(1 == ~E_12~0); 239125#L1625-1 assume !(1 == ~E_13~0); 239124#L1630-1 assume !(1 == ~E_14~0); 239123#L1635-1 assume { :end_inline_reset_delta_events } true; 238892#L2017-2 [2023-11-19 07:48:31,463 INFO L750 eck$LassoCheckResult]: Loop: 238892#L2017-2 assume !false; 238883#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 238877#L1316-1 assume !false; 238873#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 238541#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 238523#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 238517#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 238512#L1115 assume !(0 != eval_~tmp~0#1); 238513#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 247169#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 247168#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 247167#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 247166#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 247165#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 247163#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 247161#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 247159#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 247157#L1372-3 assume !(0 == ~T7_E~0); 247155#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 247153#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 247151#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 247149#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 247147#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 247145#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 247143#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 247141#L1412-3 assume !(0 == ~E_1~0); 247139#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 247137#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 247135#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 247133#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 247131#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 247129#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 247127#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 247125#L1452-3 assume !(0 == ~E_9~0); 247123#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 247121#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 247119#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 247117#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 247115#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 247113#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247111#L646-42 assume !(1 == ~m_pc~0); 247109#L646-44 is_master_triggered_~__retres1~0#1 := 0; 247107#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247105#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 247103#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 247101#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247099#L665-42 assume 1 == ~t1_pc~0; 247097#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 247094#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247092#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247090#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 247088#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247085#L684-42 assume !(1 == ~t2_pc~0); 227857#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 247082#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247080#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 247068#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 247024#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247017#L703-42 assume 1 == ~t3_pc~0; 247014#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 247011#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247009#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 247007#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 247005#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247003#L722-42 assume !(1 == ~t4_pc~0); 247002#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 246999#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 246997#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 246995#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 246993#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 246991#L741-42 assume !(1 == ~t5_pc~0); 246987#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 246985#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 246983#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 246981#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 246979#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 246977#L760-42 assume !(1 == ~t6_pc~0); 246974#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 246971#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 246969#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 246967#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 246965#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246963#L779-42 assume !(1 == ~t7_pc~0); 246960#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 246957#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 246954#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 246952#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 246950#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 246948#L798-42 assume !(1 == ~t8_pc~0); 246946#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 246943#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 246940#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 246938#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 246936#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 246930#L817-42 assume !(1 == ~t9_pc~0); 246921#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 246917#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 246915#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 246913#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 246911#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 246909#L836-42 assume 1 == ~t10_pc~0; 246907#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 246903#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 246901#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 246899#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 246897#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 246895#L855-42 assume !(1 == ~t11_pc~0); 246893#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 246889#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 246887#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 246885#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 246883#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 246881#L874-42 assume 1 == ~t12_pc~0; 246879#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 246875#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 246873#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 246871#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 246869#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 246867#L893-42 assume !(1 == ~t13_pc~0); 246865#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 246863#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 246862#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 246861#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 246860#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 246859#L912-42 assume !(1 == ~t14_pc~0); 246855#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 246853#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 246851#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 246849#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 246847#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246845#L1495-3 assume !(1 == ~M_E~0); 246819#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 246816#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 211403#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 246813#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 246811#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 246809#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 246807#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 210939#L1530-3 assume !(1 == ~T8_E~0); 246805#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 246803#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 246801#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 246799#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 246797#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 246731#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 246728#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 246725#L1570-3 assume !(1 == ~E_2~0); 246723#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 246721#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 246719#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 246717#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 246714#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 246712#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 246710#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 243906#L1610-3 assume !(1 == ~E_10~0); 246707#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 246705#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 246704#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 246703#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 246700#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 246394#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 246384#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 246382#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 246139#L2036 assume !(0 == start_simulation_~tmp~3#1); 243344#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 239167#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 239156#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 239154#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 239152#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 239149#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 239147#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 239122#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 238892#L2017-2 [2023-11-19 07:48:31,463 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:31,464 INFO L85 PathProgramCache]: Analyzing trace with hash 752619056, now seen corresponding path program 1 times [2023-11-19 07:48:31,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:31,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398806268] [2023-11-19 07:48:31,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:31,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:31,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:31,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:31,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:31,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398806268] [2023-11-19 07:48:31,570 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [398806268] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:31,570 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:31,570 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:31,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [299677035] [2023-11-19 07:48:31,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:31,571 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:31,572 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:31,572 INFO L85 PathProgramCache]: Analyzing trace with hash -1273423190, now seen corresponding path program 1 times [2023-11-19 07:48:31,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:31,573 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315982740] [2023-11-19 07:48:31,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:31,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:31,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:31,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:31,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:31,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1315982740] [2023-11-19 07:48:31,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1315982740] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:31,658 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:31,659 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:31,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749417967] [2023-11-19 07:48:31,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:31,660 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:31,660 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:31,660 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:31,660 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:31,661 INFO L87 Difference]: Start difference. First operand 40584 states and 58965 transitions. cyclomatic complexity: 18393 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:32,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:32,266 INFO L93 Difference]: Finished difference Result 78029 states and 112964 transitions. [2023-11-19 07:48:32,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78029 states and 112964 transitions. [2023-11-19 07:48:32,945 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 77688 [2023-11-19 07:48:33,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78029 states to 78029 states and 112964 transitions. [2023-11-19 07:48:33,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78029 [2023-11-19 07:48:33,276 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78029 [2023-11-19 07:48:33,276 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78029 states and 112964 transitions. [2023-11-19 07:48:33,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:33,366 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78029 states and 112964 transitions. [2023-11-19 07:48:33,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78029 states and 112964 transitions. [2023-11-19 07:48:34,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78029 to 77981. [2023-11-19 07:48:34,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77981 states, 77981 states have (on average 1.4479937420653748) internal successors, (112916), 77980 states have internal predecessors, (112916), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:34,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77981 states to 77981 states and 112916 transitions. [2023-11-19 07:48:34,943 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77981 states and 112916 transitions. [2023-11-19 07:48:34,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:34,944 INFO L428 stractBuchiCegarLoop]: Abstraction has 77981 states and 112916 transitions. [2023-11-19 07:48:34,944 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-19 07:48:34,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77981 states and 112916 transitions. [2023-11-19 07:48:35,366 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 77640 [2023-11-19 07:48:35,366 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:35,366 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:35,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:35,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:35,372 INFO L748 eck$LassoCheckResult]: Stem: 328324#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 328325#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 329276#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 329277#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 330179#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 328867#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 328868#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 328576#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 328577#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 329901#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 329168#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 329169#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 329758#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 329073#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 329074#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 328483#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 328484#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 328834#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 329025#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 328071#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 328072#L1342 assume !(0 == ~M_E~0); 328237#L1342-2 assume !(0 == ~T1_E~0); 328799#L1347-1 assume !(0 == ~T2_E~0); 329880#L1352-1 assume !(0 == ~T3_E~0); 329648#L1357-1 assume !(0 == ~T4_E~0); 328821#L1362-1 assume !(0 == ~T5_E~0); 328822#L1367-1 assume !(0 == ~T6_E~0); 328401#L1372-1 assume !(0 == ~T7_E~0); 328402#L1377-1 assume !(0 == ~T8_E~0); 328739#L1382-1 assume !(0 == ~T9_E~0); 328740#L1387-1 assume !(0 == ~T10_E~0); 329513#L1392-1 assume !(0 == ~T11_E~0); 328782#L1397-1 assume !(0 == ~T12_E~0); 328783#L1402-1 assume !(0 == ~T13_E~0); 328422#L1407-1 assume !(0 == ~T14_E~0); 328423#L1412-1 assume !(0 == ~E_1~0); 329793#L1417-1 assume !(0 == ~E_2~0); 329794#L1422-1 assume !(0 == ~E_3~0); 330084#L1427-1 assume !(0 == ~E_4~0); 328603#L1432-1 assume !(0 == ~E_5~0); 328604#L1437-1 assume !(0 == ~E_6~0); 329700#L1442-1 assume !(0 == ~E_7~0); 329701#L1447-1 assume !(0 == ~E_8~0); 329506#L1452-1 assume !(0 == ~E_9~0); 328208#L1457-1 assume !(0 == ~E_10~0); 328209#L1462-1 assume !(0 == ~E_11~0); 329736#L1467-1 assume !(0 == ~E_12~0); 329752#L1472-1 assume !(0 == ~E_13~0); 329753#L1477-1 assume !(0 == ~E_14~0); 329451#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 328391#L646 assume !(1 == ~m_pc~0); 328392#L646-2 is_master_triggered_~__retres1~0#1 := 0; 329100#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 329101#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 328485#L1666 assume !(0 != activate_threads_~tmp~1#1); 328486#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 330113#L665 assume !(1 == ~t1_pc~0); 328973#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 328974#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 329617#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 329618#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 329325#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329326#L684 assume !(1 == ~t2_pc~0); 329367#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 329368#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 328473#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 328474#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 329885#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 330128#L703 assume !(1 == ~t3_pc~0); 328628#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 328629#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 329603#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 328041#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 328042#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 328516#L722 assume !(1 == ~t4_pc~0); 328703#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 328704#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 328151#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 328152#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 329121#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 328238#L741 assume 1 == ~t5_pc~0; 328239#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 328536#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 329360#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 329418#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 329419#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 328800#L760 assume !(1 == ~t6_pc~0); 328627#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 328626#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 328463#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 328464#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 329239#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 329240#L779 assume 1 == ~t7_pc~0; 328274#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 328123#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 328124#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 329928#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 328549#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 328550#L798 assume !(1 == ~t8_pc~0); 329939#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 329843#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 329844#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 330049#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 330115#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 328104#L817 assume 1 == ~t9_pc~0; 328105#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 328906#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 328518#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 328519#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 328496#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 328497#L836 assume !(1 == ~t10_pc~0); 328520#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 328447#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 328448#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 328705#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 328706#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 329856#L855 assume 1 == ~t11_pc~0; 329096#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 329097#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 329727#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 329503#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 329331#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 328384#L874 assume !(1 == ~t12_pc~0); 328385#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 328559#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 328091#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 328092#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 328079#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 328080#L893 assume 1 == ~t13_pc~0; 330022#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 328425#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 328738#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 329952#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 329944#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 329945#L912 assume 1 == ~t14_pc~0; 329709#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 329710#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 329789#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 328322#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 328323#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 329116#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 329566#L1495-2 assume !(1 == ~T1_E~0); 329567#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 329233#L1505-1 assume !(1 == ~T3_E~0); 329234#L1510-1 assume !(1 == ~T4_E~0); 329292#L1515-1 assume !(1 == ~T5_E~0); 329293#L1520-1 assume !(1 == ~T6_E~0); 329940#L1525-1 assume !(1 == ~T7_E~0); 329604#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 329605#L1535-1 assume !(1 == ~T9_E~0); 330144#L1540-1 assume !(1 == ~T10_E~0); 330145#L1545-1 assume !(1 == ~T11_E~0); 330190#L1550-1 assume !(1 == ~T12_E~0); 330191#L1555-1 assume !(1 == ~T13_E~0); 328541#L1560-1 assume !(1 == ~T14_E~0); 328542#L1565-1 assume !(1 == ~E_1~0); 349422#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 329474#L1575-1 assume !(1 == ~E_3~0); 328827#L1580-1 assume !(1 == ~E_4~0); 328828#L1585-1 assume !(1 == ~E_5~0); 329316#L1590-1 assume !(1 == ~E_6~0); 328861#L1595-1 assume !(1 == ~E_7~0); 328862#L1600-1 assume !(1 == ~E_8~0); 329249#L1605-1 assume !(1 == ~E_9~0); 329250#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 363076#L1615-1 assume !(1 == ~E_11~0); 363073#L1620-1 assume !(1 == ~E_12~0); 363071#L1625-1 assume !(1 == ~E_13~0); 363069#L1630-1 assume !(1 == ~E_14~0); 363067#L1635-1 assume { :end_inline_reset_delta_events } true; 353320#L2017-2 [2023-11-19 07:48:35,373 INFO L750 eck$LassoCheckResult]: Loop: 353320#L2017-2 assume !false; 353321#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 362748#L1316-1 assume !false; 362747#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 352838#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 352828#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 348078#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 347610#L1115 assume !(0 != eval_~tmp~0#1); 347611#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 368371#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 368368#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 368365#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 368362#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 368359#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 368355#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 368351#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 368348#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 368345#L1372-3 assume !(0 == ~T7_E~0); 368342#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 368339#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 368335#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 368331#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 368328#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 368325#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 368322#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 368319#L1412-3 assume !(0 == ~E_1~0); 368315#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 368311#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 368308#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 368305#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 368302#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 368300#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 368298#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 368293#L1452-3 assume !(0 == ~E_9~0); 368289#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 368285#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 368281#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 368275#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 368269#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 368262#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 368255#L646-42 assume !(1 == ~m_pc~0); 368249#L646-44 is_master_triggered_~__retres1~0#1 := 0; 367644#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 367600#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 367123#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 364895#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 364894#L665-42 assume 1 == ~t1_pc~0; 364893#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 364877#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364875#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 364873#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 364872#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 353816#L684-42 assume !(1 == ~t2_pc~0); 353814#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 353812#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 353810#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 353808#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 353806#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 353804#L703-42 assume !(1 == ~t3_pc~0); 353801#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 353798#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 353796#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 353794#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 353792#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 353790#L722-42 assume !(1 == ~t4_pc~0); 353788#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 353785#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 353783#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 353781#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 353779#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 353777#L741-42 assume 1 == ~t5_pc~0; 353775#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 353771#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 353769#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 353767#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 353765#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 353763#L760-42 assume !(1 == ~t6_pc~0); 353761#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 353757#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 353755#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 353753#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 353751#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 353749#L779-42 assume !(1 == ~t7_pc~0); 353747#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 353743#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 353741#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 353739#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 353737#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 353735#L798-42 assume !(1 == ~t8_pc~0); 353733#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 353729#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 353727#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 353725#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 353723#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 353721#L817-42 assume !(1 == ~t9_pc~0); 353719#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 353715#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 353713#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 353711#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 353709#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 353707#L836-42 assume 1 == ~t10_pc~0; 353705#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 353701#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 353699#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 353697#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 353695#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 353693#L855-42 assume !(1 == ~t11_pc~0); 353691#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 353687#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 353685#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 353683#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 353681#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 353679#L874-42 assume 1 == ~t12_pc~0; 353677#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 353673#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 353671#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 353669#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 353667#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 353665#L893-42 assume !(1 == ~t13_pc~0); 353663#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 353660#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 353658#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 353657#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 353655#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 353653#L912-42 assume !(1 == ~t14_pc~0); 353649#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 353647#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 353646#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 353644#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 353642#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 353640#L1495-3 assume !(1 == ~M_E~0); 353638#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 353636#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 343550#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 353632#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 353630#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 353628#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 353625#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 351991#L1530-3 assume !(1 == ~T8_E~0); 353622#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 353619#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 353617#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 353615#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 353612#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 353609#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 353606#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 353603#L1570-3 assume !(1 == ~E_2~0); 353600#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 353599#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 353598#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 353597#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 353596#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 353595#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 353594#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 349839#L1610-3 assume !(1 == ~E_10~0); 353591#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 353592#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 364641#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 353584#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 353581#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 353582#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 353551#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 353552#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 353545#L2036 assume !(0 == start_simulation_~tmp~3#1); 353544#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 353377#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 353366#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 353367#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 363083#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 363081#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 363079#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 363066#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 353320#L2017-2 [2023-11-19 07:48:35,374 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:35,374 INFO L85 PathProgramCache]: Analyzing trace with hash 1108215503, now seen corresponding path program 1 times [2023-11-19 07:48:35,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:35,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582746584] [2023-11-19 07:48:35,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:35,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:35,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:35,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:35,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:35,502 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582746584] [2023-11-19 07:48:35,502 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582746584] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:35,502 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:35,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:35,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [401507616] [2023-11-19 07:48:35,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:35,504 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:35,504 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:35,504 INFO L85 PathProgramCache]: Analyzing trace with hash 2042168362, now seen corresponding path program 1 times [2023-11-19 07:48:35,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:35,505 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58677211] [2023-11-19 07:48:35,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:35,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:35,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:35,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:35,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:35,598 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58677211] [2023-11-19 07:48:35,598 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58677211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:35,598 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:35,599 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:35,599 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [543836769] [2023-11-19 07:48:35,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:35,600 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:35,600 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:35,601 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:35,601 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:35,601 INFO L87 Difference]: Start difference. First operand 77981 states and 112916 transitions. cyclomatic complexity: 34959 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:36,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:36,412 INFO L93 Difference]: Finished difference Result 150012 states and 216513 transitions. [2023-11-19 07:48:36,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 150012 states and 216513 transitions. [2023-11-19 07:48:37,613 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 149512 [2023-11-19 07:48:38,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 150012 states to 150012 states and 216513 transitions. [2023-11-19 07:48:38,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 150012 [2023-11-19 07:48:38,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 150012 [2023-11-19 07:48:38,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150012 states and 216513 transitions. [2023-11-19 07:48:38,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:38,391 INFO L218 hiAutomatonCegarLoop]: Abstraction has 150012 states and 216513 transitions. [2023-11-19 07:48:38,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150012 states and 216513 transitions. [2023-11-19 07:48:40,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150012 to 149916. [2023-11-19 07:48:40,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149916 states, 149916 states have (on average 1.4435884095093252) internal successors, (216417), 149915 states have internal predecessors, (216417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:41,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149916 states to 149916 states and 216417 transitions. [2023-11-19 07:48:41,482 INFO L240 hiAutomatonCegarLoop]: Abstraction has 149916 states and 216417 transitions. [2023-11-19 07:48:41,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:41,483 INFO L428 stractBuchiCegarLoop]: Abstraction has 149916 states and 216417 transitions. [2023-11-19 07:48:41,483 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-19 07:48:41,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149916 states and 216417 transitions. [2023-11-19 07:48:41,987 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 149416 [2023-11-19 07:48:41,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:41,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:41,992 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:41,993 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:41,993 INFO L748 eck$LassoCheckResult]: Stem: 556324#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 556325#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 557291#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 557292#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 558287#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 556869#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 556870#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 556574#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 556575#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 557952#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 557180#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 557181#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 557789#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 557080#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 557081#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 556482#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 556483#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 556838#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 557031#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 556071#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 556072#L1342 assume !(0 == ~M_E~0); 556237#L1342-2 assume !(0 == ~T1_E~0); 556803#L1347-1 assume !(0 == ~T2_E~0); 557929#L1352-1 assume !(0 == ~T3_E~0); 557673#L1357-1 assume !(0 == ~T4_E~0); 556826#L1362-1 assume !(0 == ~T5_E~0); 556827#L1367-1 assume !(0 == ~T6_E~0); 556398#L1372-1 assume !(0 == ~T7_E~0); 556399#L1377-1 assume !(0 == ~T8_E~0); 556741#L1382-1 assume !(0 == ~T9_E~0); 556742#L1387-1 assume !(0 == ~T10_E~0); 557533#L1392-1 assume !(0 == ~T11_E~0); 556786#L1397-1 assume !(0 == ~T12_E~0); 556787#L1402-1 assume !(0 == ~T13_E~0); 556420#L1407-1 assume !(0 == ~T14_E~0); 556421#L1412-1 assume !(0 == ~E_1~0); 557824#L1417-1 assume !(0 == ~E_2~0); 557825#L1422-1 assume !(0 == ~E_3~0); 558168#L1427-1 assume !(0 == ~E_4~0); 556604#L1432-1 assume !(0 == ~E_5~0); 556605#L1437-1 assume !(0 == ~E_6~0); 557729#L1442-1 assume !(0 == ~E_7~0); 557730#L1447-1 assume !(0 == ~E_8~0); 557526#L1452-1 assume !(0 == ~E_9~0); 556206#L1457-1 assume !(0 == ~E_10~0); 556207#L1462-1 assume !(0 == ~E_11~0); 557767#L1467-1 assume !(0 == ~E_12~0); 557782#L1472-1 assume !(0 == ~E_13~0); 557783#L1477-1 assume !(0 == ~E_14~0); 557469#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 556386#L646 assume !(1 == ~m_pc~0); 556387#L646-2 is_master_triggered_~__retres1~0#1 := 0; 557109#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 557110#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 556484#L1666 assume !(0 != activate_threads_~tmp~1#1); 556485#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558205#L665 assume !(1 == ~t1_pc~0); 556979#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 556980#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 557639#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 557640#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 557342#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 557343#L684 assume !(1 == ~t2_pc~0); 557385#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 557386#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 556472#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 556473#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 557937#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 558227#L703 assume !(1 == ~t3_pc~0); 556630#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 556631#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 557623#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 556041#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 556042#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 556514#L722 assume !(1 == ~t4_pc~0); 556705#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 556706#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 556150#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 556151#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 557131#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 556238#L741 assume !(1 == ~t5_pc~0); 556239#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 557376#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 557377#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 557437#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 557438#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 556804#L760 assume !(1 == ~t6_pc~0); 556629#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 556628#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 556462#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 556463#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 557250#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 557251#L779 assume 1 == ~t7_pc~0; 556273#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 556123#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 556124#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 557984#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 556548#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 556549#L798 assume !(1 == ~t8_pc~0); 557996#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 557883#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 557884#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 558132#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 558207#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 556104#L817 assume 1 == ~t9_pc~0; 556105#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 556907#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 556518#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 556519#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 556495#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 556496#L836 assume !(1 == ~t10_pc~0); 556520#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 556446#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 556447#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 556707#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 556708#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 557901#L855 assume 1 == ~t11_pc~0; 557104#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 557105#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 557757#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 557523#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 557348#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 556383#L874 assume !(1 == ~t12_pc~0); 556384#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 556557#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 556091#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 556092#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 556077#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 556078#L893 assume 1 == ~t13_pc~0; 558094#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 556423#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 556740#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 558015#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 558002#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 558003#L912 assume 1 == ~t14_pc~0; 557737#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 557738#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 557823#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 556322#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 556323#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 557125#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 557589#L1495-2 assume !(1 == ~T1_E~0); 557590#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 558159#L1505-1 assume !(1 == ~T3_E~0); 577280#L1510-1 assume !(1 == ~T4_E~0); 577277#L1515-1 assume !(1 == ~T5_E~0); 577275#L1520-1 assume !(1 == ~T6_E~0); 577273#L1525-1 assume !(1 == ~T7_E~0); 577271#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 577269#L1535-1 assume !(1 == ~T9_E~0); 577267#L1540-1 assume !(1 == ~T10_E~0); 577264#L1545-1 assume !(1 == ~T11_E~0); 558305#L1550-1 assume !(1 == ~T12_E~0); 556246#L1555-1 assume !(1 == ~T13_E~0); 556247#L1560-1 assume !(1 == ~T14_E~0); 556539#L1565-1 assume !(1 == ~E_1~0); 558182#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 557493#L1575-1 assume !(1 == ~E_3~0); 556833#L1580-1 assume !(1 == ~E_4~0); 556834#L1585-1 assume !(1 == ~E_5~0); 557334#L1590-1 assume !(1 == ~E_6~0); 556863#L1595-1 assume !(1 == ~E_7~0); 556864#L1600-1 assume !(1 == ~E_8~0); 557260#L1605-1 assume !(1 == ~E_9~0); 557261#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 557871#L1615-1 assume !(1 == ~E_11~0); 556679#L1620-1 assume !(1 == ~E_12~0); 556680#L1625-1 assume !(1 == ~E_13~0); 557527#L1630-1 assume !(1 == ~E_14~0); 556861#L1635-1 assume { :end_inline_reset_delta_events } true; 556862#L2017-2 [2023-11-19 07:48:41,994 INFO L750 eck$LassoCheckResult]: Loop: 556862#L2017-2 assume !false; 580314#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 580315#L1316-1 assume !false; 588312#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 580287#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 580276#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 580260#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 580257#L1115 assume !(0 != eval_~tmp~0#1); 580258#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 600527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 600526#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 600525#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 600524#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 600523#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 600522#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 600521#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 600520#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 600519#L1372-3 assume !(0 == ~T7_E~0); 600518#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 600517#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 600516#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 600515#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 600514#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 600513#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 600512#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 600511#L1412-3 assume !(0 == ~E_1~0); 600510#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 600509#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 600508#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 600507#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 600506#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 600505#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 600504#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 600503#L1452-3 assume !(0 == ~E_9~0); 600502#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 600501#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 600500#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 600499#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 600498#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 600497#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 600496#L646-42 assume !(1 == ~m_pc~0); 600494#L646-44 is_master_triggered_~__retres1~0#1 := 0; 600492#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 600490#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 600488#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 600486#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 600484#L665-42 assume !(1 == ~t1_pc~0); 600481#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 600478#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600476#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 600474#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 600472#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 581403#L684-42 assume !(1 == ~t2_pc~0); 581402#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 581401#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 581400#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 581399#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 581398#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 581397#L703-42 assume !(1 == ~t3_pc~0); 581395#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 581394#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 581393#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 581392#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 581391#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 581390#L722-42 assume !(1 == ~t4_pc~0); 581389#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 581388#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 581387#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 581386#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 581385#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 581384#L741-42 assume !(1 == ~t5_pc~0); 581383#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 581382#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 581381#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 581380#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 581379#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 581378#L760-42 assume 1 == ~t6_pc~0; 581375#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 581373#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 581371#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 581369#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 581367#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 581365#L779-42 assume 1 == ~t7_pc~0; 581362#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 581360#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 581358#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 581356#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 581354#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 581352#L798-42 assume 1 == ~t8_pc~0; 581348#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 581346#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 581344#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 581342#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 581340#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 581338#L817-42 assume 1 == ~t9_pc~0; 581334#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 581332#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 581330#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 581328#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 581326#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 581324#L836-42 assume !(1 == ~t10_pc~0); 581320#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 581318#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 581316#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 581314#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 581312#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 581310#L855-42 assume 1 == ~t11_pc~0; 581306#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 581304#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 581302#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 581300#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 581298#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 581296#L874-42 assume !(1 == ~t12_pc~0); 581292#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 581290#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 581288#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 581286#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 581284#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 581282#L893-42 assume 1 == ~t13_pc~0; 581278#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 581276#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 581274#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 581272#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 581270#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 581268#L912-42 assume !(1 == ~t14_pc~0); 581264#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 581262#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 581260#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 581258#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 581256#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 581254#L1495-3 assume !(1 == ~M_E~0); 581251#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 581249#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 577739#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 581246#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 581244#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 581242#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 581239#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 579601#L1530-3 assume !(1 == ~T8_E~0); 581236#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 581234#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 581232#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 581230#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 581228#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 581226#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 581225#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 581223#L1570-3 assume !(1 == ~E_2~0); 581221#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 581219#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 581217#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 581216#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 581214#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 581212#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 581210#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 577690#L1610-3 assume !(1 == ~E_10~0); 581207#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 581205#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 581203#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 581201#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 581199#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 581184#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 581174#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 581172#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 581170#L2036 assume !(0 == start_simulation_~tmp~3#1); 581168#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 580496#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 580485#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 580483#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 580481#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 580479#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 580351#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 580348#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 556862#L2017-2 [2023-11-19 07:48:41,995 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:41,996 INFO L85 PathProgramCache]: Analyzing trace with hash 1070768814, now seen corresponding path program 1 times [2023-11-19 07:48:41,996 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:41,996 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399789202] [2023-11-19 07:48:41,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:41,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:42,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:42,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:42,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:42,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399789202] [2023-11-19 07:48:42,123 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1399789202] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:42,123 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:42,124 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:42,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434216959] [2023-11-19 07:48:42,124 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:42,125 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:42,126 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:42,126 INFO L85 PathProgramCache]: Analyzing trace with hash 945751404, now seen corresponding path program 1 times [2023-11-19 07:48:42,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:42,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844777729] [2023-11-19 07:48:42,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:42,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:42,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:42,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:42,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:42,222 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844777729] [2023-11-19 07:48:42,222 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844777729] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:42,222 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:42,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:42,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [733013294] [2023-11-19 07:48:42,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:42,224 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:42,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:42,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:48:42,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:48:42,225 INFO L87 Difference]: Start difference. First operand 149916 states and 216417 transitions. cyclomatic complexity: 66549 Second operand has 5 states, 5 states have (on average 34.0) internal successors, (170), 5 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:44,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:44,380 INFO L93 Difference]: Finished difference Result 363734 states and 521584 transitions. [2023-11-19 07:48:44,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 363734 states and 521584 transitions. [2023-11-19 07:48:46,437 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 362768 [2023-11-19 07:48:47,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 363734 states to 363734 states and 521584 transitions. [2023-11-19 07:48:47,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 363734 [2023-11-19 07:48:47,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 363734 [2023-11-19 07:48:47,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 363734 states and 521584 transitions. [2023-11-19 07:48:48,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:48,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 363734 states and 521584 transitions. [2023-11-19 07:48:48,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 363734 states and 521584 transitions. [2023-11-19 07:48:51,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 363734 to 153471. [2023-11-19 07:48:51,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 153471 states, 153471 states have (on average 1.4333131340774479) internal successors, (219972), 153470 states have internal predecessors, (219972), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:51,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153471 states to 153471 states and 219972 transitions. [2023-11-19 07:48:51,783 INFO L240 hiAutomatonCegarLoop]: Abstraction has 153471 states and 219972 transitions. [2023-11-19 07:48:51,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:48:51,784 INFO L428 stractBuchiCegarLoop]: Abstraction has 153471 states and 219972 transitions. [2023-11-19 07:48:51,784 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-19 07:48:51,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 153471 states and 219972 transitions. [2023-11-19 07:48:52,194 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 152968 [2023-11-19 07:48:52,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:52,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:52,197 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:52,197 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:52,197 INFO L748 eck$LassoCheckResult]: Stem: 1069986#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1069987#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 1070957#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1070958#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1071980#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 1070534#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1070535#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1070237#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1070238#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1071625#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1070841#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1070842#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1071465#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1070740#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1070741#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1070146#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1070147#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1070503#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1070691#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 1069734#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1069735#L1342 assume !(0 == ~M_E~0); 1069900#L1342-2 assume !(0 == ~T1_E~0); 1070470#L1347-1 assume !(0 == ~T2_E~0); 1071602#L1352-1 assume !(0 == ~T3_E~0); 1071352#L1357-1 assume !(0 == ~T4_E~0); 1070492#L1362-1 assume !(0 == ~T5_E~0); 1070493#L1367-1 assume !(0 == ~T6_E~0); 1070060#L1372-1 assume !(0 == ~T7_E~0); 1070061#L1377-1 assume !(0 == ~T8_E~0); 1070407#L1382-1 assume !(0 == ~T9_E~0); 1070408#L1387-1 assume !(0 == ~T10_E~0); 1071209#L1392-1 assume !(0 == ~T11_E~0); 1070451#L1397-1 assume !(0 == ~T12_E~0); 1070452#L1402-1 assume !(0 == ~T13_E~0); 1070084#L1407-1 assume !(0 == ~T14_E~0); 1070085#L1412-1 assume !(0 == ~E_1~0); 1071498#L1417-1 assume !(0 == ~E_2~0); 1071499#L1422-1 assume !(0 == ~E_3~0); 1071853#L1427-1 assume !(0 == ~E_4~0); 1070267#L1432-1 assume !(0 == ~E_5~0); 1070268#L1437-1 assume !(0 == ~E_6~0); 1071410#L1442-1 assume !(0 == ~E_7~0); 1071411#L1447-1 assume !(0 == ~E_8~0); 1071203#L1452-1 assume !(0 == ~E_9~0); 1069869#L1457-1 assume !(0 == ~E_10~0); 1069870#L1462-1 assume !(0 == ~E_11~0); 1071445#L1467-1 assume !(0 == ~E_12~0); 1071459#L1472-1 assume !(0 == ~E_13~0); 1071460#L1477-1 assume !(0 == ~E_14~0); 1071142#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1070050#L646 assume !(1 == ~m_pc~0); 1070051#L646-2 is_master_triggered_~__retres1~0#1 := 0; 1070767#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1070768#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1070148#L1666 assume !(0 != activate_threads_~tmp~1#1); 1070149#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1071890#L665 assume !(1 == ~t1_pc~0); 1070640#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1070641#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1071315#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1071316#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 1071006#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1071007#L684 assume !(1 == ~t2_pc~0); 1071052#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1071053#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1070134#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1070135#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 1071607#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1071918#L703 assume !(1 == ~t3_pc~0); 1070291#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1070292#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1071302#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1069704#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 1069705#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1070177#L722 assume !(1 == ~t4_pc~0); 1070371#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1070372#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1069814#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1069815#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 1070793#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1069901#L741 assume !(1 == ~t5_pc~0); 1069902#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1071045#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1071046#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1071105#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 1071106#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1070471#L760 assume !(1 == ~t6_pc~0); 1070290#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1070944#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1071251#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1071836#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 1070914#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1070915#L779 assume 1 == ~t7_pc~0; 1069935#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1069786#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1069787#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1071656#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 1070213#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1070214#L798 assume !(1 == ~t8_pc~0); 1071666#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1071552#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1071553#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1071809#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 1071892#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1069765#L817 assume 1 == ~t9_pc~0; 1069766#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1070570#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1070182#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1070183#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 1070159#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1070160#L836 assume !(1 == ~t10_pc~0); 1070184#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1070109#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1070110#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1070373#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 1070374#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1071570#L855 assume 1 == ~t11_pc~0; 1070763#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1070764#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1071437#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1071200#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 1071012#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1070047#L874 assume !(1 == ~t12_pc~0); 1070048#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1070222#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1069754#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1069755#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 1069740#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1069741#L893 assume 1 == ~t13_pc~0; 1071766#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1070087#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1070406#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1071684#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 1071673#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1071674#L912 assume 1 == ~t14_pc~0; 1071419#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1071420#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1071495#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1069984#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 1069985#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1070785#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 1071263#L1495-2 assume !(1 == ~T1_E~0); 1071264#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1071843#L1505-1 assume !(1 == ~T3_E~0); 1071975#L1510-1 assume !(1 == ~T4_E~0); 1071976#L1515-1 assume !(1 == ~T5_E~0); 1071875#L1520-1 assume !(1 == ~T6_E~0); 1071876#L1525-1 assume !(1 == ~T7_E~0); 1124109#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1124106#L1535-1 assume !(1 == ~T9_E~0); 1124107#L1540-1 assume !(1 == ~T10_E~0); 1069665#L1545-1 assume !(1 == ~T11_E~0); 1069666#L1550-1 assume !(1 == ~T12_E~0); 1069909#L1555-1 assume !(1 == ~T13_E~0); 1069910#L1560-1 assume !(1 == ~T14_E~0); 1071862#L1565-1 assume !(1 == ~E_1~0); 1071863#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1071166#L1575-1 assume !(1 == ~E_3~0); 1070498#L1580-1 assume !(1 == ~E_4~0); 1070499#L1585-1 assume !(1 == ~E_5~0); 1070998#L1590-1 assume !(1 == ~E_6~0); 1070528#L1595-1 assume !(1 == ~E_7~0); 1070529#L1600-1 assume !(1 == ~E_8~0); 1070922#L1605-1 assume !(1 == ~E_9~0); 1070923#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1071538#L1615-1 assume !(1 == ~E_11~0); 1070343#L1620-1 assume !(1 == ~E_12~0); 1070344#L1625-1 assume !(1 == ~E_13~0); 1071204#L1630-1 assume !(1 == ~E_14~0); 1070526#L1635-1 assume { :end_inline_reset_delta_events } true; 1070527#L2017-2 [2023-11-19 07:48:52,198 INFO L750 eck$LassoCheckResult]: Loop: 1070527#L2017-2 assume !false; 1134828#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1134829#L1316-1 assume !false; 1134823#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1134824#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1134428#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1134429#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1134395#L1115 assume !(0 != eval_~tmp~0#1); 1134397#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1203734#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1203733#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1203732#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1203731#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1203730#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1203729#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1203728#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1203727#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1203726#L1372-3 assume !(0 == ~T7_E~0); 1203725#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1203724#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1203723#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1203722#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1203721#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1203720#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1203719#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 1203718#L1412-3 assume !(0 == ~E_1~0); 1203717#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1203716#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1203715#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1203714#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1203713#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1203712#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1203711#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1203710#L1452-3 assume !(0 == ~E_9~0); 1203709#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1203708#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1203707#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1203706#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1203705#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 1203704#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1203703#L646-42 assume !(1 == ~m_pc~0); 1203702#L646-44 is_master_triggered_~__retres1~0#1 := 0; 1203701#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1203700#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1203699#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1203698#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1203697#L665-42 assume 1 == ~t1_pc~0; 1203696#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1203694#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1203693#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1203692#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1203691#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1203690#L684-42 assume !(1 == ~t2_pc~0); 1170472#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1170473#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1170463#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1170464#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1170455#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1170456#L703-42 assume !(1 == ~t3_pc~0); 1170444#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1170445#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1170435#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1170436#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1170427#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1170428#L722-42 assume !(1 == ~t4_pc~0); 1170419#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1170420#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1170411#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1170412#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1170403#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1170404#L741-42 assume !(1 == ~t5_pc~0); 1170394#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1170395#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1170385#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1170386#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1170306#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1170307#L760-42 assume !(1 == ~t6_pc~0); 1170281#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1170282#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1170258#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1170259#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 1167688#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1167689#L779-42 assume 1 == ~t7_pc~0; 1167579#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1167580#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1167556#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1167557#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1167530#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1167531#L798-42 assume 1 == ~t8_pc~0; 1167361#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1167362#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1160320#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1160321#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1160316#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1160317#L817-42 assume 1 == ~t9_pc~0; 1160307#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1160308#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1160301#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1160302#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1160294#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1160295#L836-42 assume 1 == ~t10_pc~0; 1160288#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1160287#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1160115#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1160116#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1159983#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1159984#L855-42 assume 1 == ~t11_pc~0; 1159938#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1159939#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1159926#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1159927#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1159920#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1159921#L874-42 assume !(1 == ~t12_pc~0); 1159912#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1159913#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1159905#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1159906#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1159899#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1159900#L893-42 assume 1 == ~t13_pc~0; 1159776#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1159777#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1159770#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1159771#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1159764#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1159765#L912-42 assume !(1 == ~t14_pc~0); 1159686#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 1159687#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1159678#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1159679#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 1187700#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1187699#L1495-3 assume !(1 == ~M_E~0); 1187698#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1187697#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1071785#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1187694#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1187693#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1187692#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1187691#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1187689#L1530-3 assume !(1 == ~T8_E~0); 1187688#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1187687#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1187686#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1187685#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1187684#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1187683#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 1187682#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1135100#L1570-3 assume !(1 == ~E_2~0); 1187681#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1187680#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1187679#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1187678#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1187677#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1187676#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1187675#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1187673#L1610-3 assume !(1 == ~E_10~0); 1187672#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1187671#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1187670#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1187669#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 1187668#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1187660#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1187651#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1187650#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1187648#L2036 assume !(0 == start_simulation_~tmp~3#1); 1187647#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1135009#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1134998#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1134997#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1134991#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1134992#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1187565#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1134984#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 1070527#L2017-2 [2023-11-19 07:48:52,199 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:52,199 INFO L85 PathProgramCache]: Analyzing trace with hash -71733652, now seen corresponding path program 1 times [2023-11-19 07:48:52,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:52,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362427554] [2023-11-19 07:48:52,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:52,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:52,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:52,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:52,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:52,298 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362427554] [2023-11-19 07:48:52,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362427554] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:52,298 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:52,298 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:52,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281026199] [2023-11-19 07:48:52,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:52,299 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:52,299 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:52,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1115389965, now seen corresponding path program 1 times [2023-11-19 07:48:52,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:52,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543986058] [2023-11-19 07:48:52,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:52,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:52,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:52,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:52,360 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:52,360 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1543986058] [2023-11-19 07:48:52,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1543986058] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:52,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:52,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:52,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [38779495] [2023-11-19 07:48:52,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:52,362 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:52,362 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:52,362 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:52,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:52,363 INFO L87 Difference]: Start difference. First operand 153471 states and 219972 transitions. cyclomatic complexity: 66549 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:54,938 INFO L93 Difference]: Finished difference Result 395638 states and 564337 transitions. [2023-11-19 07:48:54,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 395638 states and 564337 transitions.