./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:37:49,348 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:37:49,435 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:37:49,440 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:37:49,440 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:37:49,468 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:37:49,469 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:37:49,470 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:37:49,471 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:37:49,471 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:37:49,472 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:37:49,473 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:37:49,473 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:37:49,474 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:37:49,474 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:37:49,475 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:37:49,476 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:37:49,476 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:37:49,477 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:37:49,477 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:37:49,478 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:37:49,478 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:37:49,479 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:37:49,479 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:37:49,480 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:37:49,480 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:37:49,481 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:37:49,481 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:37:49,482 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:37:49,482 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:37:49,483 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:37:49,483 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:37:49,484 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:37:49,484 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:37:49,485 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:37:49,485 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:37:49,486 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2023-11-19 07:37:49,769 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:37:49,802 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:37:49,805 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:37:49,807 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:37:49,808 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:37:49,809 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/transmitter.02.cil.c [2023-11-19 07:37:52,998 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:37:53,262 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:37:53,263 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/sv-benchmarks/c/systemc/transmitter.02.cil.c [2023-11-19 07:37:53,279 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/data/869c76e39/26f8289a2d7c4460b897ed9f7588d11f/FLAG6ccaa77b5 [2023-11-19 07:37:53,295 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/data/869c76e39/26f8289a2d7c4460b897ed9f7588d11f [2023-11-19 07:37:53,298 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:37:53,300 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:37:53,302 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:37:53,302 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:37:53,308 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:37:53,309 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,310 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@173b77ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53, skipping insertion in model container [2023-11-19 07:37:53,310 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,353 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:37:53,564 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:37:53,580 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:37:53,652 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:37:53,672 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:37:53,672 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53 WrapperNode [2023-11-19 07:37:53,673 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:37:53,674 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:37:53,674 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:37:53,675 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:37:53,683 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,711 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,752 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 45, statements flattened = 536 [2023-11-19 07:37:53,753 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:37:53,754 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:37:53,754 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:37:53,754 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:37:53,762 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,763 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,767 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,767 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,778 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,788 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,791 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,794 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,800 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:37:53,801 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:37:53,801 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:37:53,801 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:37:53,802 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (1/1) ... [2023-11-19 07:37:53,811 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:37:53,854 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:37:53,877 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:37:53,894 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:37:53,926 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:37:53,927 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:37:53,927 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:37:53,927 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:37:54,056 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:37:54,058 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:37:54,624 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:37:54,638 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:37:54,638 INFO L302 CfgBuilder]: Removed 6 assume(true) statements. [2023-11-19 07:37:54,645 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:37:54 BoogieIcfgContainer [2023-11-19 07:37:54,645 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:37:54,646 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:37:54,646 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:37:54,651 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:37:54,652 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:37:54,652 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:37:53" (1/3) ... [2023-11-19 07:37:54,653 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f56210a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:37:54, skipping insertion in model container [2023-11-19 07:37:54,653 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:37:54,653 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:53" (2/3) ... [2023-11-19 07:37:54,654 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f56210a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:37:54, skipping insertion in model container [2023-11-19 07:37:54,654 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:37:54,654 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:37:54" (3/3) ... [2023-11-19 07:37:54,656 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2023-11-19 07:37:54,724 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:37:54,725 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:37:54,725 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:37:54,725 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:37:54,725 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:37:54,726 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:37:54,726 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:37:54,726 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:37:54,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:54,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2023-11-19 07:37:54,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:54,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:54,781 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,782 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,782 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:37:54,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:54,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2023-11-19 07:37:54,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:54,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:54,809 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,809 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,818 INFO L748 eck$LassoCheckResult]: Stem: 147#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 158#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 205#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 182#L221true assume !(1 == ~m_i~0);~m_st~0 := 2; 60#L221-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 42#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 162#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33#L334true assume !(0 == ~M_E~0); 169#L334-2true assume !(0 == ~T1_E~0); 113#L339-1true assume !(0 == ~T2_E~0); 108#L344-1true assume 0 == ~E_1~0;~E_1~0 := 1; 143#L349-1true assume !(0 == ~E_2~0); 41#L354-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117#L156true assume !(1 == ~m_pc~0); 154#L156-2true is_master_triggered_~__retres1~0#1 := 0; 136#L167true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128#is_master_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 78#L405true assume !(0 != activate_threads_~tmp~1#1); 63#L405-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126#L175true assume 1 == ~t1_pc~0; 161#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64#L186true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 115#L413true assume !(0 != activate_threads_~tmp___0~0#1); 185#L413-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187#L194true assume !(1 == ~t2_pc~0); 203#L194-2true is_transmit2_triggered_~__retres1~2#1 := 0; 70#L205true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27#L421true assume !(0 != activate_threads_~tmp___1~0#1); 85#L421-2true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12#L367true assume !(1 == ~M_E~0); 186#L367-2true assume !(1 == ~T1_E~0); 130#L372-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 132#L377-1true assume !(1 == ~E_1~0); 25#L382-1true assume !(1 == ~E_2~0); 80#L387-1true assume { :end_inline_reset_delta_events } true; 107#L528-2true [2023-11-19 07:37:54,820 INFO L750 eck$LassoCheckResult]: Loop: 107#L528-2true assume !false; 88#L529true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17#L309-1true assume false; 82#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 207#L334-3true assume 0 == ~M_E~0;~M_E~0 := 1; 159#L334-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 116#L339-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 183#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 76#L349-3true assume !(0 == ~E_2~0); 32#L354-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101#L156-9true assume !(1 == ~m_pc~0); 4#L156-11true is_master_triggered_~__retres1~0#1 := 0; 57#L167-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135#is_master_triggered_returnLabel#4true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 118#L405-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21#L405-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192#L175-9true assume !(1 == ~t1_pc~0); 141#L175-11true is_transmit1_triggered_~__retres1~1#1 := 0; 14#L186-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201#is_transmit1_triggered_returnLabel#4true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 153#L413-9true assume !(0 != activate_threads_~tmp___0~0#1); 146#L413-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190#L194-9true assume !(1 == ~t2_pc~0); 28#L194-11true is_transmit2_triggered_~__retres1~2#1 := 0; 196#L205-3true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5#is_transmit2_triggered_returnLabel#4true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 110#L421-9true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 144#L421-11true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54#L367-3true assume 1 == ~M_E~0;~M_E~0 := 2; 7#L367-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 34#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 18#L377-3true assume !(1 == ~E_1~0); 30#L382-3true assume 1 == ~E_2~0;~E_2~0 := 2; 111#L387-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 145#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 180#L261-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 188#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 152#L547true assume !(0 == start_simulation_~tmp~3#1); 166#L547-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 149#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 52#L261-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 37#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 40#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49#L509true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 20#L560true assume !(0 != start_simulation_~tmp___0~1#1); 107#L528-2true [2023-11-19 07:37:54,826 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:54,827 INFO L85 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2023-11-19 07:37:54,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:54,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160452196] [2023-11-19 07:37:54,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:54,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:54,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160452196] [2023-11-19 07:37:55,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1160452196] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,044 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,044 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940024444] [2023-11-19 07:37:55,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,052 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:55,053 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,053 INFO L85 PathProgramCache]: Analyzing trace with hash -294698413, now seen corresponding path program 1 times [2023-11-19 07:37:55,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8368553] [2023-11-19 07:37:55,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,096 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [8368553] [2023-11-19 07:37:55,096 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [8368553] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,096 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,097 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:37:55,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1063903500] [2023-11-19 07:37:55,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,099 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:55,100 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:55,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:55,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:55,135 INFO L87 Difference]: Start difference. First operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:55,180 INFO L93 Difference]: Finished difference Result 207 states and 302 transitions. [2023-11-19 07:37:55,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 207 states and 302 transitions. [2023-11-19 07:37:55,188 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-19 07:37:55,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 207 states to 201 states and 296 transitions. [2023-11-19 07:37:55,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2023-11-19 07:37:55,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2023-11-19 07:37:55,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 296 transitions. [2023-11-19 07:37:55,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:55,201 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2023-11-19 07:37:55,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 296 transitions. [2023-11-19 07:37:55,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2023-11-19 07:37:55,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.472636815920398) internal successors, (296), 200 states have internal predecessors, (296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 296 transitions. [2023-11-19 07:37:55,255 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2023-11-19 07:37:55,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:55,263 INFO L428 stractBuchiCegarLoop]: Abstraction has 201 states and 296 transitions. [2023-11-19 07:37:55,263 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:37:55,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 296 transitions. [2023-11-19 07:37:55,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-19 07:37:55,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:55,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:55,269 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,269 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,270 INFO L748 eck$LassoCheckResult]: Stem: 608#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 617#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 616#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 530#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 505#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 506#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 489#L334 assume !(0 == ~M_E~0); 490#L334-2 assume !(0 == ~T1_E~0); 585#L339-1 assume !(0 == ~T2_E~0); 579#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 580#L349-1 assume !(0 == ~E_2~0); 503#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 504#L156 assume !(1 == ~m_pc~0); 436#L156-2 is_master_triggered_~__retres1~0#1 := 0; 435#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 597#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 552#L405 assume !(0 != activate_threads_~tmp~1#1); 534#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 535#L175 assume 1 == ~t1_pc~0; 594#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 536#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 500#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 501#L413 assume !(0 != activate_threads_~tmp___0~0#1); 587#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 624#L194 assume !(1 == ~t2_pc~0); 578#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 546#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 478#L421 assume !(0 != activate_threads_~tmp___1~0#1); 479#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 448#L367 assume !(1 == ~M_E~0); 449#L367-2 assume !(1 == ~T1_E~0); 598#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 599#L377-1 assume !(1 == ~E_1~0); 475#L382-1 assume !(1 == ~E_2~0); 476#L387-1 assume { :end_inline_reset_delta_events } true; 465#L528-2 [2023-11-19 07:37:55,271 INFO L750 eck$LassoCheckResult]: Loop: 465#L528-2 assume !false; 559#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 458#L309-1 assume !false; 459#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 439#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 440#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 447#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 425#L276 assume !(0 != eval_~tmp~0#1); 427#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 584#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 618#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 588#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 589#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 551#L349-3 assume !(0 == ~E_2~0); 487#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488#L156-9 assume 1 == ~m_pc~0; 573#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 431#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 527#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 590#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 466#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 467#L175-9 assume 1 == ~t1_pc~0; 512#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 452#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 453#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 614#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 606#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607#L194-9 assume !(1 == ~t2_pc~0); 480#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 481#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 432#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 433#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 582#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 523#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 437#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 438#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 460#L377-3 assume !(1 == ~E_1~0); 461#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 484#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 583#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 492#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 613#L547 assume !(0 == start_simulation_~tmp~3#1); 600#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 610#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 521#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 495#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 496#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 502#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 517#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 464#L560 assume !(0 != start_simulation_~tmp___0~1#1); 465#L528-2 [2023-11-19 07:37:55,271 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2023-11-19 07:37:55,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664216236] [2023-11-19 07:37:55,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664216236] [2023-11-19 07:37:55,393 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664216236] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,393 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,393 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [253988243] [2023-11-19 07:37:55,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,394 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:55,395 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,395 INFO L85 PathProgramCache]: Analyzing trace with hash -724130786, now seen corresponding path program 1 times [2023-11-19 07:37:55,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538572931] [2023-11-19 07:37:55,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,492 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,493 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538572931] [2023-11-19 07:37:55,493 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538572931] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,493 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,493 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467381162] [2023-11-19 07:37:55,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,494 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:55,495 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:55,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:55,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:55,498 INFO L87 Difference]: Start difference. First operand 201 states and 296 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:55,540 INFO L93 Difference]: Finished difference Result 201 states and 295 transitions. [2023-11-19 07:37:55,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201 states and 295 transitions. [2023-11-19 07:37:55,544 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-19 07:37:55,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201 states to 201 states and 295 transitions. [2023-11-19 07:37:55,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2023-11-19 07:37:55,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2023-11-19 07:37:55,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 295 transitions. [2023-11-19 07:37:55,556 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:55,556 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2023-11-19 07:37:55,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 295 transitions. [2023-11-19 07:37:55,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2023-11-19 07:37:55,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.4676616915422886) internal successors, (295), 200 states have internal predecessors, (295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 295 transitions. [2023-11-19 07:37:55,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2023-11-19 07:37:55,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:55,583 INFO L428 stractBuchiCegarLoop]: Abstraction has 201 states and 295 transitions. [2023-11-19 07:37:55,583 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:37:55,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 295 transitions. [2023-11-19 07:37:55,585 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-19 07:37:55,586 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:55,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:55,587 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,588 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,588 INFO L748 eck$LassoCheckResult]: Stem: 1017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1025#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 939#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 914#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 915#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 898#L334 assume !(0 == ~M_E~0); 899#L334-2 assume !(0 == ~T1_E~0); 994#L339-1 assume !(0 == ~T2_E~0); 988#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 989#L349-1 assume !(0 == ~E_2~0); 912#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 913#L156 assume !(1 == ~m_pc~0); 845#L156-2 is_master_triggered_~__retres1~0#1 := 0; 844#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 961#L405 assume !(0 != activate_threads_~tmp~1#1); 943#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 944#L175 assume 1 == ~t1_pc~0; 1003#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 945#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 909#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 910#L413 assume !(0 != activate_threads_~tmp___0~0#1); 996#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1033#L194 assume !(1 == ~t2_pc~0); 987#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 955#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 887#L421 assume !(0 != activate_threads_~tmp___1~0#1); 888#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 857#L367 assume !(1 == ~M_E~0); 858#L367-2 assume !(1 == ~T1_E~0); 1007#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1008#L377-1 assume !(1 == ~E_1~0); 884#L382-1 assume !(1 == ~E_2~0); 885#L387-1 assume { :end_inline_reset_delta_events } true; 874#L528-2 [2023-11-19 07:37:55,588 INFO L750 eck$LassoCheckResult]: Loop: 874#L528-2 assume !false; 968#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 867#L309-1 assume !false; 868#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 848#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 849#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 856#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 834#L276 assume !(0 != eval_~tmp~0#1); 836#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 964#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 993#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1027#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 997#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 998#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 960#L349-3 assume !(0 == ~E_2~0); 896#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 897#L156-9 assume 1 == ~m_pc~0; 982#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 840#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 936#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 999#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 875#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 876#L175-9 assume 1 == ~t1_pc~0; 921#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 861#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 862#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1023#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 1015#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1016#L194-9 assume 1 == ~t2_pc~0; 963#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 890#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 841#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 842#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 991#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 932#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 846#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 847#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 869#L377-3 assume !(1 == ~E_1~0); 870#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 893#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 992#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 901#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1032#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1022#L547 assume !(0 == start_simulation_~tmp~3#1); 1009#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1019#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 930#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 904#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 905#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 911#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 926#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 873#L560 assume !(0 != start_simulation_~tmp___0~1#1); 874#L528-2 [2023-11-19 07:37:55,589 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,589 INFO L85 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2023-11-19 07:37:55,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,590 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408322245] [2023-11-19 07:37:55,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408322245] [2023-11-19 07:37:55,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1408322245] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724230539] [2023-11-19 07:37:55,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,715 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:55,715 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,715 INFO L85 PathProgramCache]: Analyzing trace with hash 866264191, now seen corresponding path program 1 times [2023-11-19 07:37:55,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955766394] [2023-11-19 07:37:55,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955766394] [2023-11-19 07:37:55,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1955766394] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110929388] [2023-11-19 07:37:55,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,771 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:55,771 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:55,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:37:55,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:37:55,772 INFO L87 Difference]: Start difference. First operand 201 states and 295 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:55,901 INFO L93 Difference]: Finished difference Result 342 states and 498 transitions. [2023-11-19 07:37:55,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 498 transitions. [2023-11-19 07:37:55,905 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2023-11-19 07:37:55,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 498 transitions. [2023-11-19 07:37:55,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 342 [2023-11-19 07:37:55,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 342 [2023-11-19 07:37:55,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 498 transitions. [2023-11-19 07:37:55,911 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:55,911 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 498 transitions. [2023-11-19 07:37:55,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 498 transitions. [2023-11-19 07:37:55,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 340. [2023-11-19 07:37:55,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 340 states, 340 states have (on average 1.4588235294117646) internal successors, (496), 339 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 496 transitions. [2023-11-19 07:37:55,928 INFO L240 hiAutomatonCegarLoop]: Abstraction has 340 states and 496 transitions. [2023-11-19 07:37:55,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:37:55,930 INFO L428 stractBuchiCegarLoop]: Abstraction has 340 states and 496 transitions. [2023-11-19 07:37:55,930 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:37:55,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 340 states and 496 transitions. [2023-11-19 07:37:55,932 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2023-11-19 07:37:55,933 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:55,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:55,934 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,934 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,935 INFO L748 eck$LassoCheckResult]: Stem: 1591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1602#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1599#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1600#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1501#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1472#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1473#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1454#L334 assume !(0 == ~M_E~0); 1455#L334-2 assume !(0 == ~T1_E~0); 1561#L339-1 assume !(0 == ~T2_E~0); 1554#L344-1 assume !(0 == ~E_1~0); 1555#L349-1 assume !(0 == ~E_2~0); 1470#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1471#L156 assume !(1 == ~m_pc~0); 1398#L156-2 is_master_triggered_~__retres1~0#1 := 0; 1397#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1578#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1525#L405 assume !(0 != activate_threads_~tmp~1#1); 1505#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1506#L175 assume 1 == ~t1_pc~0; 1575#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1507#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1466#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1467#L413 assume !(0 != activate_threads_~tmp___0~0#1); 1563#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1612#L194 assume !(1 == ~t2_pc~0); 1552#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1517#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1442#L421 assume !(0 != activate_threads_~tmp___1~0#1); 1443#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1411#L367 assume !(1 == ~M_E~0); 1412#L367-2 assume !(1 == ~T1_E~0); 1579#L372-1 assume !(1 == ~T2_E~0); 1580#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1439#L382-1 assume !(1 == ~E_2~0); 1440#L387-1 assume { :end_inline_reset_delta_events } true; 1429#L528-2 [2023-11-19 07:37:55,935 INFO L750 eck$LassoCheckResult]: Loop: 1429#L528-2 assume !false; 1553#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1421#L309-1 assume !false; 1422#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1401#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1402#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1409#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1410#L276 assume !(0 != eval_~tmp~0#1); 1528#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1529#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1619#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1603#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1604#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1620#L344-3 assume !(0 == ~E_1~0); 1695#L349-3 assume !(0 == ~E_2~0); 1694#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1693#L156-9 assume !(1 == ~m_pc~0); 1691#L156-11 is_master_triggered_~__retres1~0#1 := 0; 1690#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1689#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1688#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1687#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1686#L175-9 assume 1 == ~t1_pc~0; 1481#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1415#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1416#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1598#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 1589#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1590#L194-9 assume 1 == ~t2_pc~0; 1613#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1680#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1679#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1678#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1677#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1676#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1675#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1674#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L377-3 assume !(1 == ~E_1~0); 1425#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1673#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1672#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1669#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1668#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1666#L547 assume !(0 == start_simulation_~tmp~3#1); 1664#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1593#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1595#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1462#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1486#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1487#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1428#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1429#L528-2 [2023-11-19 07:37:55,936 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,936 INFO L85 PathProgramCache]: Analyzing trace with hash -1288865440, now seen corresponding path program 1 times [2023-11-19 07:37:55,936 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133800362] [2023-11-19 07:37:55,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,997 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133800362] [2023-11-19 07:37:55,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133800362] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,998 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,998 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999150319] [2023-11-19 07:37:55,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,998 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:55,999 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,999 INFO L85 PathProgramCache]: Analyzing trace with hash 1551047712, now seen corresponding path program 1 times [2023-11-19 07:37:55,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,000 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433290533] [2023-11-19 07:37:56,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,038 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433290533] [2023-11-19 07:37:56,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433290533] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,039 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,039 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:56,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880116829] [2023-11-19 07:37:56,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,040 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:56,040 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:56,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:37:56,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:37:56,041 INFO L87 Difference]: Start difference. First operand 340 states and 496 transitions. cyclomatic complexity: 158 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:56,150 INFO L93 Difference]: Finished difference Result 841 states and 1201 transitions. [2023-11-19 07:37:56,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 841 states and 1201 transitions. [2023-11-19 07:37:56,159 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 763 [2023-11-19 07:37:56,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 841 states to 841 states and 1201 transitions. [2023-11-19 07:37:56,167 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 841 [2023-11-19 07:37:56,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 841 [2023-11-19 07:37:56,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 841 states and 1201 transitions. [2023-11-19 07:37:56,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:56,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 841 states and 1201 transitions. [2023-11-19 07:37:56,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 841 states and 1201 transitions. [2023-11-19 07:37:56,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 841 to 780. [2023-11-19 07:37:56,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 780 states, 780 states have (on average 1.441025641025641) internal successors, (1124), 779 states have internal predecessors, (1124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 780 states to 780 states and 1124 transitions. [2023-11-19 07:37:56,216 INFO L240 hiAutomatonCegarLoop]: Abstraction has 780 states and 1124 transitions. [2023-11-19 07:37:56,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:37:56,219 INFO L428 stractBuchiCegarLoop]: Abstraction has 780 states and 1124 transitions. [2023-11-19 07:37:56,221 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:37:56,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 780 states and 1124 transitions. [2023-11-19 07:37:56,229 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 733 [2023-11-19 07:37:56,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:56,229 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:56,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,233 INFO L748 eck$LassoCheckResult]: Stem: 2790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2800#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2801#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2683#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2655#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2656#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2639#L334 assume !(0 == ~M_E~0); 2640#L334-2 assume !(0 == ~T1_E~0); 2749#L339-1 assume !(0 == ~T2_E~0); 2742#L344-1 assume !(0 == ~E_1~0); 2743#L349-1 assume !(0 == ~E_2~0); 2653#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2654#L156 assume !(1 == ~m_pc~0); 2754#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2778#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2768#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2709#L405 assume !(0 != activate_threads_~tmp~1#1); 2691#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2692#L175 assume !(1 == ~t1_pc~0); 2696#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2693#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2650#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2651#L413 assume !(0 != activate_threads_~tmp___0~0#1); 2753#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2822#L194 assume !(1 == ~t2_pc~0); 2740#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2701#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2702#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2628#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2629#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2600#L367 assume !(1 == ~M_E~0); 2601#L367-2 assume !(1 == ~T1_E~0); 2769#L372-1 assume !(1 == ~T2_E~0); 2770#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2625#L382-1 assume !(1 == ~E_2~0); 2626#L387-1 assume { :end_inline_reset_delta_events } true; 3143#L528-2 [2023-11-19 07:37:56,233 INFO L750 eck$LassoCheckResult]: Loop: 3143#L528-2 assume !false; 2720#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2706#L309-1 assume !false; 3134#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2589#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2590#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2596#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2597#L276 assume !(0 != eval_~tmp~0#1); 3130#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3128#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3126#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3124#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3121#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3122#L344-3 assume !(0 == ~E_1~0); 3115#L349-3 assume !(0 == ~E_2~0); 3116#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2734#L156-9 assume !(1 == ~m_pc~0); 2583#L156-11 is_master_triggered_~__retres1~0#1 := 0; 2584#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2679#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2756#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2616#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2617#L175-9 assume !(1 == ~t1_pc~0); 2782#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2602#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2603#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2799#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 2785#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2786#L194-9 assume !(1 == ~t2_pc~0); 2630#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 2631#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2585#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2586#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2745#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2675#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2587#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2588#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2610#L377-3 assume !(1 == ~E_1~0); 2611#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2634#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2746#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2642#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2818#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2797#L547 assume !(0 == start_simulation_~tmp~3#1); 2773#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2792#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2673#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2645#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 2646#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2652#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2669#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3144#L560 assume !(0 != start_simulation_~tmp___0~1#1); 3143#L528-2 [2023-11-19 07:37:56,234 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,239 INFO L85 PathProgramCache]: Analyzing trace with hash -148513729, now seen corresponding path program 1 times [2023-11-19 07:37:56,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131389322] [2023-11-19 07:37:56,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,308 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,309 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1131389322] [2023-11-19 07:37:56,309 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1131389322] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,309 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,309 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:56,309 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1088148906] [2023-11-19 07:37:56,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,310 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:56,310 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,310 INFO L85 PathProgramCache]: Analyzing trace with hash -96491490, now seen corresponding path program 1 times [2023-11-19 07:37:56,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27340678] [2023-11-19 07:37:56,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,368 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [27340678] [2023-11-19 07:37:56,368 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [27340678] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,368 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,369 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:37:56,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [756814802] [2023-11-19 07:37:56,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,369 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:56,370 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:56,370 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:37:56,370 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:37:56,370 INFO L87 Difference]: Start difference. First operand 780 states and 1124 transitions. cyclomatic complexity: 348 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:56,442 INFO L93 Difference]: Finished difference Result 694 states and 973 transitions. [2023-11-19 07:37:56,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 694 states and 973 transitions. [2023-11-19 07:37:56,448 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 646 [2023-11-19 07:37:56,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 694 states to 694 states and 973 transitions. [2023-11-19 07:37:56,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 694 [2023-11-19 07:37:56,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 694 [2023-11-19 07:37:56,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 694 states and 973 transitions. [2023-11-19 07:37:56,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:56,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 694 states and 973 transitions. [2023-11-19 07:37:56,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states and 973 transitions. [2023-11-19 07:37:56,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 678. [2023-11-19 07:37:56,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 678 states, 678 states have (on average 1.4056047197640118) internal successors, (953), 677 states have internal predecessors, (953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678 states to 678 states and 953 transitions. [2023-11-19 07:37:56,472 INFO L240 hiAutomatonCegarLoop]: Abstraction has 678 states and 953 transitions. [2023-11-19 07:37:56,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:37:56,474 INFO L428 stractBuchiCegarLoop]: Abstraction has 678 states and 953 transitions. [2023-11-19 07:37:56,474 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:37:56,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 678 states and 953 transitions. [2023-11-19 07:37:56,478 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 634 [2023-11-19 07:37:56,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:56,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:56,479 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,480 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,480 INFO L748 eck$LassoCheckResult]: Stem: 4254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4269#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4265#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4266#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 4165#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4140#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4141#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4124#L334 assume !(0 == ~M_E~0); 4125#L334-2 assume !(0 == ~T1_E~0); 4227#L339-1 assume !(0 == ~T2_E~0); 4220#L344-1 assume !(0 == ~E_1~0); 4221#L349-1 assume !(0 == ~E_2~0); 4138#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4139#L156 assume !(1 == ~m_pc~0); 4232#L156-2 is_master_triggered_~__retres1~0#1 := 0; 4245#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4239#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4187#L405 assume !(0 != activate_threads_~tmp~1#1); 4169#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4170#L175 assume !(1 == ~t1_pc~0); 4177#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4171#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4136#L413 assume !(0 != activate_threads_~tmp___0~0#1); 4229#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4281#L194 assume !(1 == ~t2_pc~0); 4219#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4181#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4182#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4113#L421 assume !(0 != activate_threads_~tmp___1~0#1); 4114#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4083#L367 assume !(1 == ~M_E~0); 4084#L367-2 assume !(1 == ~T1_E~0); 4240#L372-1 assume !(1 == ~T2_E~0); 4241#L377-1 assume !(1 == ~E_1~0); 4110#L382-1 assume !(1 == ~E_2~0); 4111#L387-1 assume { :end_inline_reset_delta_events } true; 4190#L528-2 [2023-11-19 07:37:56,480 INFO L750 eck$LassoCheckResult]: Loop: 4190#L528-2 assume !false; 4323#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4321#L309-1 assume !false; 4320#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4318#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4316#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4315#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4313#L276 assume !(0 != eval_~tmp~0#1); 4314#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4407#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4406#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4405#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4404#L339-3 assume !(0 == ~T2_E~0); 4403#L344-3 assume !(0 == ~E_1~0); 4402#L349-3 assume !(0 == ~E_2~0); 4401#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4400#L156-9 assume !(1 == ~m_pc~0); 4399#L156-11 is_master_triggered_~__retres1~0#1 := 0; 4398#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4397#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4396#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4394#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4392#L175-9 assume !(1 == ~t1_pc~0); 4390#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4388#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4386#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4384#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 4382#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4380#L194-9 assume 1 == ~t2_pc~0; 4377#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4375#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4373#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4371#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4369#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4366#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4364#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4362#L372-3 assume !(1 == ~T2_E~0); 4360#L377-3 assume !(1 == ~E_1~0); 4358#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4356#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4354#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4350#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4345#L547 assume !(0 == start_simulation_~tmp~3#1); 4343#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4342#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4339#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4338#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 4337#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4336#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4334#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4331#L560 assume !(0 != start_simulation_~tmp___0~1#1); 4190#L528-2 [2023-11-19 07:37:56,481 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,481 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2023-11-19 07:37:56,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219750371] [2023-11-19 07:37:56,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:56,490 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:56,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:56,541 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:56,542 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,542 INFO L85 PathProgramCache]: Analyzing trace with hash -898972165, now seen corresponding path program 1 times [2023-11-19 07:37:56,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,542 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688684275] [2023-11-19 07:37:56,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [688684275] [2023-11-19 07:37:56,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [688684275] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,594 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,594 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:37:56,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670906386] [2023-11-19 07:37:56,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,595 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:56,595 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:56,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:37:56,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:37:56,596 INFO L87 Difference]: Start difference. First operand 678 states and 953 transitions. cyclomatic complexity: 278 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:56,697 INFO L93 Difference]: Finished difference Result 1146 states and 1580 transitions. [2023-11-19 07:37:56,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1146 states and 1580 transitions. [2023-11-19 07:37:56,707 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1097 [2023-11-19 07:37:56,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1146 states to 1146 states and 1580 transitions. [2023-11-19 07:37:56,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1146 [2023-11-19 07:37:56,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1146 [2023-11-19 07:37:56,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1146 states and 1580 transitions. [2023-11-19 07:37:56,721 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:56,721 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1146 states and 1580 transitions. [2023-11-19 07:37:56,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1146 states and 1580 transitions. [2023-11-19 07:37:56,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1146 to 693. [2023-11-19 07:37:56,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.3968253968253967) internal successors, (968), 692 states have internal predecessors, (968), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 968 transitions. [2023-11-19 07:37:56,740 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 968 transitions. [2023-11-19 07:37:56,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-19 07:37:56,741 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 968 transitions. [2023-11-19 07:37:56,742 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:37:56,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 968 transitions. [2023-11-19 07:37:56,746 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 649 [2023-11-19 07:37:56,746 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:56,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:56,748 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,748 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,748 INFO L748 eck$LassoCheckResult]: Stem: 6113#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6127#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6123#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6124#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 6012#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5984#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5985#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5966#L334 assume !(0 == ~M_E~0); 5967#L334-2 assume !(0 == ~T1_E~0); 6075#L339-1 assume !(0 == ~T2_E~0); 6066#L344-1 assume !(0 == ~E_1~0); 6067#L349-1 assume !(0 == ~E_2~0); 5982#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5983#L156 assume !(1 == ~m_pc~0); 6080#L156-2 is_master_triggered_~__retres1~0#1 := 0; 6099#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6090#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6035#L405 assume !(0 != activate_threads_~tmp~1#1); 6017#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6018#L175 assume !(1 == ~t1_pc~0); 6025#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6019#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5980#L413 assume !(0 != activate_threads_~tmp___0~0#1); 6077#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6141#L194 assume !(1 == ~t2_pc~0); 6064#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6029#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6030#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5954#L421 assume !(0 != activate_threads_~tmp___1~0#1); 5955#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5924#L367 assume !(1 == ~M_E~0); 5925#L367-2 assume !(1 == ~T1_E~0); 6091#L372-1 assume !(1 == ~T2_E~0); 6092#L377-1 assume !(1 == ~E_1~0); 5951#L382-1 assume !(1 == ~E_2~0); 5952#L387-1 assume { :end_inline_reset_delta_events } true; 6037#L528-2 [2023-11-19 07:37:56,748 INFO L750 eck$LassoCheckResult]: Loop: 6037#L528-2 assume !false; 6044#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5934#L309-1 assume !false; 5935#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6443#L244 assume !(0 == ~m_st~0); 6444#L248 assume !(0 == ~t1_st~0); 6441#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 6442#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6378#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6379#L276 assume !(0 != eval_~tmp~0#1); 6438#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6437#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6436#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6435#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6434#L339-3 assume !(0 == ~T2_E~0); 6433#L344-3 assume !(0 == ~E_1~0); 6432#L349-3 assume !(0 == ~E_2~0); 5964#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5965#L156-9 assume !(1 == ~m_pc~0); 6058#L156-11 is_master_triggered_~__retres1~0#1 := 0; 6008#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6009#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6081#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6082#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6146#L175-9 assume !(1 == ~t1_pc~0); 6147#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 5928#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5929#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6121#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 6122#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6142#L194-9 assume !(1 == ~t2_pc~0); 6144#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 6151#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6152#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6069#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6070#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6003#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6004#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5968#L372-3 assume !(1 == ~T2_E~0); 5969#L377-3 assume !(1 == ~E_1~0); 5960#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5961#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6109#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5971#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6139#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 6119#L547 assume !(0 == start_simulation_~tmp~3#1); 6120#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6131#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6571#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6569#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 6567#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6566#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6563#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6561#L560 assume !(0 != start_simulation_~tmp___0~1#1); 6037#L528-2 [2023-11-19 07:37:56,749 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,749 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2023-11-19 07:37:56,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2048565901] [2023-11-19 07:37:56,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:56,761 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:56,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:56,784 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:56,786 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,786 INFO L85 PathProgramCache]: Analyzing trace with hash -975167437, now seen corresponding path program 1 times [2023-11-19 07:37:56,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18292119] [2023-11-19 07:37:56,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18292119] [2023-11-19 07:37:56,892 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18292119] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,892 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,892 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:37:56,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446322159] [2023-11-19 07:37:56,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,893 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:56,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:56,894 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:37:56,894 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:37:56,895 INFO L87 Difference]: Start difference. First operand 693 states and 968 transitions. cyclomatic complexity: 278 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:57,006 INFO L93 Difference]: Finished difference Result 1379 states and 1895 transitions. [2023-11-19 07:37:57,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1379 states and 1895 transitions. [2023-11-19 07:37:57,019 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1335 [2023-11-19 07:37:57,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1379 states to 1379 states and 1895 transitions. [2023-11-19 07:37:57,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1379 [2023-11-19 07:37:57,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1379 [2023-11-19 07:37:57,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1379 states and 1895 transitions. [2023-11-19 07:37:57,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:57,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1379 states and 1895 transitions. [2023-11-19 07:37:57,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1379 states and 1895 transitions. [2023-11-19 07:37:57,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1379 to 729. [2023-11-19 07:37:57,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 729 states have (on average 1.373113854595336) internal successors, (1001), 728 states have internal predecessors, (1001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1001 transitions. [2023-11-19 07:37:57,057 INFO L240 hiAutomatonCegarLoop]: Abstraction has 729 states and 1001 transitions. [2023-11-19 07:37:57,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:37:57,059 INFO L428 stractBuchiCegarLoop]: Abstraction has 729 states and 1001 transitions. [2023-11-19 07:37:57,060 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:37:57,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 729 states and 1001 transitions. [2023-11-19 07:37:57,064 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 685 [2023-11-19 07:37:57,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:57,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:57,065 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,066 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,066 INFO L748 eck$LassoCheckResult]: Stem: 8199#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 8200#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8212#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8207#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8208#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 8097#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8066#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8067#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8049#L334 assume !(0 == ~M_E~0); 8050#L334-2 assume !(0 == ~T1_E~0); 8167#L339-1 assume !(0 == ~T2_E~0); 8161#L344-1 assume !(0 == ~E_1~0); 8162#L349-1 assume !(0 == ~E_2~0); 8064#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8065#L156 assume !(1 == ~m_pc~0); 8172#L156-2 is_master_triggered_~__retres1~0#1 := 0; 8190#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8183#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8123#L405 assume !(0 != activate_threads_~tmp~1#1); 8101#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8102#L175 assume !(1 == ~t1_pc~0); 8109#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8103#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8061#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8062#L413 assume !(0 != activate_threads_~tmp___0~0#1); 8169#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8234#L194 assume !(1 == ~t2_pc~0); 8160#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8113#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8114#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8038#L421 assume !(0 != activate_threads_~tmp___1~0#1); 8039#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8008#L367 assume !(1 == ~M_E~0); 8009#L367-2 assume !(1 == ~T1_E~0); 8184#L372-1 assume !(1 == ~T2_E~0); 8185#L377-1 assume !(1 == ~E_1~0); 8035#L382-1 assume !(1 == ~E_2~0); 8036#L387-1 assume { :end_inline_reset_delta_events } true; 8126#L528-2 [2023-11-19 07:37:57,066 INFO L750 eck$LassoCheckResult]: Loop: 8126#L528-2 assume !false; 8273#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8271#L309-1 assume !false; 8270#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8268#L244 assume !(0 == ~m_st~0); 8269#L248 assume !(0 == ~t1_st~0); 8266#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 8267#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8262#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8263#L276 assume !(0 != eval_~tmp~0#1); 8358#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8357#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8356#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8355#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8354#L339-3 assume !(0 == ~T2_E~0); 8353#L344-3 assume !(0 == ~E_1~0); 8352#L349-3 assume !(0 == ~E_2~0); 8351#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8350#L156-9 assume !(1 == ~m_pc~0); 8349#L156-11 is_master_triggered_~__retres1~0#1 := 0; 8348#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8347#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8346#L405-9 assume !(0 != activate_threads_~tmp~1#1); 8344#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8342#L175-9 assume !(1 == ~t1_pc~0); 8340#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 8338#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8336#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8334#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 8332#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8330#L194-9 assume 1 == ~t2_pc~0; 8327#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8325#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8323#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8321#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8319#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8316#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8314#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8312#L372-3 assume !(1 == ~T2_E~0); 8310#L377-3 assume !(1 == ~E_1~0); 8308#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8306#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8304#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8300#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8298#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 8295#L547 assume !(0 == start_simulation_~tmp~3#1); 8293#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8292#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8289#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 8287#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8286#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8284#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8281#L560 assume !(0 != start_simulation_~tmp___0~1#1); 8126#L528-2 [2023-11-19 07:37:57,067 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,067 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 3 times [2023-11-19 07:37:57,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,067 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973434037] [2023-11-19 07:37:57,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,079 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:57,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,100 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:57,101 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,101 INFO L85 PathProgramCache]: Analyzing trace with hash 889987154, now seen corresponding path program 1 times [2023-11-19 07:37:57,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164288449] [2023-11-19 07:37:57,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:57,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:57,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:57,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164288449] [2023-11-19 07:37:57,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [164288449] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:57,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:57,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:57,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767978802] [2023-11-19 07:37:57,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:57,187 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:57,188 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:57,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:57,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:57,190 INFO L87 Difference]: Start difference. First operand 729 states and 1001 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:57,235 INFO L93 Difference]: Finished difference Result 1186 states and 1597 transitions. [2023-11-19 07:37:57,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1186 states and 1597 transitions. [2023-11-19 07:37:57,245 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1140 [2023-11-19 07:37:57,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1186 states to 1186 states and 1597 transitions. [2023-11-19 07:37:57,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1186 [2023-11-19 07:37:57,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1186 [2023-11-19 07:37:57,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1186 states and 1597 transitions. [2023-11-19 07:37:57,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:57,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1186 states and 1597 transitions. [2023-11-19 07:37:57,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1186 states and 1597 transitions. [2023-11-19 07:37:57,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1186 to 1151. [2023-11-19 07:37:57,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1151 states, 1151 states have (on average 1.3483927019982624) internal successors, (1552), 1150 states have internal predecessors, (1552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1151 states to 1151 states and 1552 transitions. [2023-11-19 07:37:57,287 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1151 states and 1552 transitions. [2023-11-19 07:37:57,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:57,290 INFO L428 stractBuchiCegarLoop]: Abstraction has 1151 states and 1552 transitions. [2023-11-19 07:37:57,291 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:37:57,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1151 states and 1552 transitions. [2023-11-19 07:37:57,304 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1105 [2023-11-19 07:37:57,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:57,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:57,305 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,305 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,305 INFO L748 eck$LassoCheckResult]: Stem: 10109#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 10110#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10121#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10118#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10119#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 10013#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9985#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9986#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9969#L334 assume !(0 == ~M_E~0); 9970#L334-2 assume !(0 == ~T1_E~0); 10077#L339-1 assume !(0 == ~T2_E~0); 10071#L344-1 assume !(0 == ~E_1~0); 10072#L349-1 assume !(0 == ~E_2~0); 9983#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9984#L156 assume !(1 == ~m_pc~0); 10082#L156-2 is_master_triggered_~__retres1~0#1 := 0; 10099#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10093#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10040#L405 assume !(0 != activate_threads_~tmp~1#1); 10019#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10020#L175 assume !(1 == ~t1_pc~0); 10027#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10021#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9980#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9981#L413 assume !(0 != activate_threads_~tmp___0~0#1); 10079#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10142#L194 assume !(1 == ~t2_pc~0); 10070#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10031#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10032#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9958#L421 assume !(0 != activate_threads_~tmp___1~0#1); 9959#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9928#L367 assume !(1 == ~M_E~0); 9929#L367-2 assume !(1 == ~T1_E~0); 10094#L372-1 assume !(1 == ~T2_E~0); 10095#L377-1 assume !(1 == ~E_1~0); 9955#L382-1 assume !(1 == ~E_2~0); 9956#L387-1 assume { :end_inline_reset_delta_events } true; 10043#L528-2 assume !false; 10171#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10169#L309-1 [2023-11-19 07:37:57,306 INFO L750 eck$LassoCheckResult]: Loop: 10169#L309-1 assume !false; 10168#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10167#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10166#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10165#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10164#L276 assume 0 != eval_~tmp~0#1; 10162#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10160#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 10161#L284-2 havoc eval_~tmp_ndt_1~0#1; 10177#L281-1 assume !(0 == ~t1_st~0); 10172#L295-1 assume !(0 == ~t2_st~0); 10169#L309-1 [2023-11-19 07:37:57,306 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,306 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 1 times [2023-11-19 07:37:57,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,307 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299598618] [2023-11-19 07:37:57,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,315 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:57,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,326 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:57,327 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,327 INFO L85 PathProgramCache]: Analyzing trace with hash 993947407, now seen corresponding path program 1 times [2023-11-19 07:37:57,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983672567] [2023-11-19 07:37:57,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,331 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:57,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,335 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:57,335 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,336 INFO L85 PathProgramCache]: Analyzing trace with hash 1252886829, now seen corresponding path program 1 times [2023-11-19 07:37:57,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,336 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555139433] [2023-11-19 07:37:57,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:57,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:57,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:57,368 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555139433] [2023-11-19 07:37:57,369 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555139433] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:57,369 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:57,369 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:57,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418085688] [2023-11-19 07:37:57,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:57,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:57,443 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:57,443 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:57,444 INFO L87 Difference]: Start difference. First operand 1151 states and 1552 transitions. cyclomatic complexity: 405 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:57,495 INFO L93 Difference]: Finished difference Result 2023 states and 2695 transitions. [2023-11-19 07:37:57,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2695 transitions. [2023-11-19 07:37:57,513 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1881 [2023-11-19 07:37:57,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2695 transitions. [2023-11-19 07:37:57,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2023-11-19 07:37:57,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2023-11-19 07:37:57,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2695 transitions. [2023-11-19 07:37:57,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:57,534 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2695 transitions. [2023-11-19 07:37:57,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2695 transitions. [2023-11-19 07:37:57,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 1925. [2023-11-19 07:37:57,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1925 states, 1925 states have (on average 1.3366233766233766) internal successors, (2573), 1924 states have internal predecessors, (2573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1925 states to 1925 states and 2573 transitions. [2023-11-19 07:37:57,578 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1925 states and 2573 transitions. [2023-11-19 07:37:57,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:57,579 INFO L428 stractBuchiCegarLoop]: Abstraction has 1925 states and 2573 transitions. [2023-11-19 07:37:57,579 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:37:57,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1925 states and 2573 transitions. [2023-11-19 07:37:57,591 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1818 [2023-11-19 07:37:57,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:57,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:57,592 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,592 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,592 INFO L748 eck$LassoCheckResult]: Stem: 13306#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 13307#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13321#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13317#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13318#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 13195#L221-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 13196#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13324#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13325#L334 assume !(0 == ~M_E~0); 13334#L334-2 assume !(0 == ~T1_E~0); 13335#L339-1 assume !(0 == ~T2_E~0); 13258#L344-1 assume !(0 == ~E_1~0); 13259#L349-1 assume !(0 == ~E_2~0); 13164#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13165#L156 assume !(1 == ~m_pc~0); 13315#L156-2 is_master_triggered_~__retres1~0#1 := 0; 13316#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13283#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13284#L405 assume !(0 != activate_threads_~tmp~1#1); 13203#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13204#L175 assume !(1 == ~t1_pc~0); 13211#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13212#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13161#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13162#L413 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13270#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13345#L194 assume !(1 == ~t2_pc~0); 13257#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13216#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13217#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13139#L421 assume !(0 != activate_threads_~tmp___1~0#1); 13140#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13111#L367 assume !(1 == ~M_E~0); 13112#L367-2 assume !(1 == ~T1_E~0); 13344#L372-1 assume !(1 == ~T2_E~0); 13288#L377-1 assume !(1 == ~E_1~0); 13136#L382-1 assume !(1 == ~E_2~0); 13137#L387-1 assume { :end_inline_reset_delta_events } true; 13438#L528-2 assume !false; 13420#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13419#L309-1 [2023-11-19 07:37:57,593 INFO L750 eck$LassoCheckResult]: Loop: 13419#L309-1 assume !false; 13414#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13415#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13409#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13410#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13405#L276 assume 0 != eval_~tmp~0#1; 13406#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 13399#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 13401#L284-2 havoc eval_~tmp_ndt_1~0#1; 13434#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 13430#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 13428#L298-2 havoc eval_~tmp_ndt_2~0#1; 13421#L295-1 assume !(0 == ~t2_st~0); 13419#L309-1 [2023-11-19 07:37:57,593 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,593 INFO L85 PathProgramCache]: Analyzing trace with hash -808857497, now seen corresponding path program 1 times [2023-11-19 07:37:57,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113167612] [2023-11-19 07:37:57,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:57,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:57,616 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:57,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113167612] [2023-11-19 07:37:57,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113167612] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:57,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:57,617 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:57,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876063881] [2023-11-19 07:37:57,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:57,617 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:57,618 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,618 INFO L85 PathProgramCache]: Analyzing trace with hash 1697436410, now seen corresponding path program 1 times [2023-11-19 07:37:57,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,619 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443894293] [2023-11-19 07:37:57,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,623 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:57,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,627 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:57,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:57,692 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:57,692 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:57,692 INFO L87 Difference]: Start difference. First operand 1925 states and 2573 transitions. cyclomatic complexity: 653 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:57,708 INFO L93 Difference]: Finished difference Result 1748 states and 2340 transitions. [2023-11-19 07:37:57,709 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1748 states and 2340 transitions. [2023-11-19 07:37:57,722 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1702 [2023-11-19 07:37:57,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1748 states to 1748 states and 2340 transitions. [2023-11-19 07:37:57,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1748 [2023-11-19 07:37:57,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1748 [2023-11-19 07:37:57,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1748 states and 2340 transitions. [2023-11-19 07:37:57,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:57,741 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1748 states and 2340 transitions. [2023-11-19 07:37:57,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1748 states and 2340 transitions. [2023-11-19 07:37:57,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1748 to 1748. [2023-11-19 07:37:57,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1748 states, 1748 states have (on average 1.3386727688787186) internal successors, (2340), 1747 states have internal predecessors, (2340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1748 states to 1748 states and 2340 transitions. [2023-11-19 07:37:57,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1748 states and 2340 transitions. [2023-11-19 07:37:57,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:57,781 INFO L428 stractBuchiCegarLoop]: Abstraction has 1748 states and 2340 transitions. [2023-11-19 07:37:57,781 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:37:57,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1748 states and 2340 transitions. [2023-11-19 07:37:57,792 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1702 [2023-11-19 07:37:57,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:57,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:57,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,793 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,794 INFO L748 eck$LassoCheckResult]: Stem: 16971#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 16972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 16982#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16979#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16980#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 16871#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16845#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16846#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16829#L334 assume !(0 == ~M_E~0); 16830#L334-2 assume !(0 == ~T1_E~0); 16936#L339-1 assume !(0 == ~T2_E~0); 16930#L344-1 assume !(0 == ~E_1~0); 16931#L349-1 assume !(0 == ~E_2~0); 16843#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16844#L156 assume !(1 == ~m_pc~0); 16941#L156-2 is_master_triggered_~__retres1~0#1 := 0; 16959#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16950#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16896#L405 assume !(0 != activate_threads_~tmp~1#1); 16876#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16877#L175 assume !(1 == ~t1_pc~0); 16884#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16878#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16840#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16841#L413 assume !(0 != activate_threads_~tmp___0~0#1); 16938#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17003#L194 assume !(1 == ~t2_pc~0); 16929#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16889#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16890#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16818#L421 assume !(0 != activate_threads_~tmp___1~0#1); 16819#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16790#L367 assume !(1 == ~M_E~0); 16791#L367-2 assume !(1 == ~T1_E~0); 16951#L372-1 assume !(1 == ~T2_E~0); 16952#L377-1 assume !(1 == ~E_1~0); 16815#L382-1 assume !(1 == ~E_2~0); 16816#L387-1 assume { :end_inline_reset_delta_events } true; 16899#L528-2 assume !false; 18500#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18498#L309-1 [2023-11-19 07:37:57,794 INFO L750 eck$LassoCheckResult]: Loop: 18498#L309-1 assume !false; 18497#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18496#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18495#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18494#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18493#L276 assume 0 != eval_~tmp~0#1; 18492#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 16872#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 16874#L284-2 havoc eval_~tmp_ndt_1~0#1; 16913#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 16914#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 16970#L298-2 havoc eval_~tmp_ndt_2~0#1; 18501#L295-1 assume !(0 == ~t2_st~0); 18498#L309-1 [2023-11-19 07:37:57,794 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,794 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 2 times [2023-11-19 07:37:57,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [22991579] [2023-11-19 07:37:57,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,804 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:57,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,814 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:57,815 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,815 INFO L85 PathProgramCache]: Analyzing trace with hash 1697436410, now seen corresponding path program 2 times [2023-11-19 07:37:57,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976036150] [2023-11-19 07:37:57,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,820 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:57,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:57,823 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:57,824 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1430117784, now seen corresponding path program 1 times [2023-11-19 07:37:57,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520285196] [2023-11-19 07:37:57,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:57,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:57,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:57,862 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520285196] [2023-11-19 07:37:57,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1520285196] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:57,862 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:57,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:37:57,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710932330] [2023-11-19 07:37:57,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:57,932 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:57,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:57,933 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:57,933 INFO L87 Difference]: Start difference. First operand 1748 states and 2340 transitions. cyclomatic complexity: 595 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:58,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:58,038 INFO L93 Difference]: Finished difference Result 3097 states and 4118 transitions. [2023-11-19 07:37:58,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3097 states and 4118 transitions. [2023-11-19 07:37:58,060 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3046 [2023-11-19 07:37:58,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3097 states to 3097 states and 4118 transitions. [2023-11-19 07:37:58,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3097 [2023-11-19 07:37:58,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3097 [2023-11-19 07:37:58,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3097 states and 4118 transitions. [2023-11-19 07:37:58,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:58,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3097 states and 4118 transitions. [2023-11-19 07:37:58,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3097 states and 4118 transitions. [2023-11-19 07:37:58,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3097 to 3097. [2023-11-19 07:37:58,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3097 states, 3097 states have (on average 1.3296738779463997) internal successors, (4118), 3096 states have internal predecessors, (4118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:58,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3097 states to 3097 states and 4118 transitions. [2023-11-19 07:37:58,159 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3097 states and 4118 transitions. [2023-11-19 07:37:58,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:58,160 INFO L428 stractBuchiCegarLoop]: Abstraction has 3097 states and 4118 transitions. [2023-11-19 07:37:58,160 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:37:58,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3097 states and 4118 transitions. [2023-11-19 07:37:58,174 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3046 [2023-11-19 07:37:58,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:58,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:58,175 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:58,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:58,175 INFO L748 eck$LassoCheckResult]: Stem: 21829#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 21830#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21845#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21842#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21843#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 21727#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21698#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21699#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21682#L334 assume !(0 == ~M_E~0); 21683#L334-2 assume !(0 == ~T1_E~0); 21798#L339-1 assume !(0 == ~T2_E~0); 21790#L344-1 assume !(0 == ~E_1~0); 21791#L349-1 assume !(0 == ~E_2~0); 21696#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21697#L156 assume !(1 == ~m_pc~0); 21803#L156-2 is_master_triggered_~__retres1~0#1 := 0; 21819#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21813#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21754#L405 assume !(0 != activate_threads_~tmp~1#1); 21731#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21732#L175 assume !(1 == ~t1_pc~0); 21740#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21733#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21694#L413 assume !(0 != activate_threads_~tmp___0~0#1); 21800#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21863#L194 assume !(1 == ~t2_pc~0); 21789#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21744#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21745#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21671#L421 assume !(0 != activate_threads_~tmp___1~0#1); 21672#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21641#L367 assume !(1 == ~M_E~0); 21642#L367-2 assume !(1 == ~T1_E~0); 21814#L372-1 assume !(1 == ~T2_E~0); 21815#L377-1 assume !(1 == ~E_1~0); 21668#L382-1 assume !(1 == ~E_2~0); 21669#L387-1 assume { :end_inline_reset_delta_events } true; 21757#L528-2 assume !false; 24527#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24525#L309-1 [2023-11-19 07:37:58,175 INFO L750 eck$LassoCheckResult]: Loop: 24525#L309-1 assume !false; 24523#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24520#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 24519#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24518#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24516#L276 assume 0 != eval_~tmp~0#1; 24514#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 21728#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 21729#L284-2 havoc eval_~tmp_ndt_1~0#1; 24547#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 24544#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 24543#L298-2 havoc eval_~tmp_ndt_2~0#1; 21779#L295-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 21780#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 21807#L312-2 havoc eval_~tmp_ndt_3~0#1; 24525#L309-1 [2023-11-19 07:37:58,176 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:58,176 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 3 times [2023-11-19 07:37:58,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:58,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [174360667] [2023-11-19 07:37:58,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:58,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:58,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:58,196 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:58,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:58,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:58,214 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:58,214 INFO L85 PathProgramCache]: Analyzing trace with hash -851208175, now seen corresponding path program 1 times [2023-11-19 07:37:58,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:58,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336942490] [2023-11-19 07:37:58,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:58,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:58,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:58,220 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:58,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:58,224 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:58,225 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:58,225 INFO L85 PathProgramCache]: Analyzing trace with hash -46370001, now seen corresponding path program 1 times [2023-11-19 07:37:58,225 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:58,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622633509] [2023-11-19 07:37:58,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:58,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:58,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:58,239 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:58,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:58,254 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:37:59,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:59,206 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:37:59,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:37:59,375 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.11 07:37:59 BoogieIcfgContainer [2023-11-19 07:37:59,384 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-19 07:37:59,384 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-19 07:37:59,384 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-19 07:37:59,385 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-19 07:37:59,385 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:37:54" (3/4) ... [2023-11-19 07:37:59,388 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-19 07:37:59,460 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/witness.graphml [2023-11-19 07:37:59,460 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-19 07:37:59,461 INFO L158 Benchmark]: Toolchain (without parser) took 6160.62ms. Allocated memory was 159.4MB in the beginning and 249.6MB in the end (delta: 90.2MB). Free memory was 115.5MB in the beginning and 174.9MB in the end (delta: -59.3MB). Peak memory consumption was 32.6MB. Max. memory is 16.1GB. [2023-11-19 07:37:59,461 INFO L158 Benchmark]: CDTParser took 0.64ms. Allocated memory is still 159.4MB. Free memory is still 103.2MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-19 07:37:59,462 INFO L158 Benchmark]: CACSL2BoogieTranslator took 371.37ms. Allocated memory is still 159.4MB. Free memory was 115.5MB in the beginning and 101.9MB in the end (delta: 13.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2023-11-19 07:37:59,462 INFO L158 Benchmark]: Boogie Procedure Inliner took 78.91ms. Allocated memory is still 159.4MB. Free memory was 101.9MB in the beginning and 99.1MB in the end (delta: 2.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-19 07:37:59,463 INFO L158 Benchmark]: Boogie Preprocessor took 46.40ms. Allocated memory is still 159.4MB. Free memory was 99.1MB in the beginning and 96.7MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-19 07:37:59,463 INFO L158 Benchmark]: RCFGBuilder took 844.24ms. Allocated memory was 159.4MB in the beginning and 205.5MB in the end (delta: 46.1MB). Free memory was 96.3MB in the beginning and 169.6MB in the end (delta: -73.3MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. [2023-11-19 07:37:59,464 INFO L158 Benchmark]: BuchiAutomizer took 4737.51ms. Allocated memory was 205.5MB in the beginning and 249.6MB in the end (delta: 44.0MB). Free memory was 169.6MB in the beginning and 179.1MB in the end (delta: -9.4MB). Peak memory consumption was 34.6MB. Max. memory is 16.1GB. [2023-11-19 07:37:59,465 INFO L158 Benchmark]: Witness Printer took 75.88ms. Allocated memory is still 249.6MB. Free memory was 179.1MB in the beginning and 174.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-19 07:37:59,467 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.64ms. Allocated memory is still 159.4MB. Free memory is still 103.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 371.37ms. Allocated memory is still 159.4MB. Free memory was 115.5MB in the beginning and 101.9MB in the end (delta: 13.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 78.91ms. Allocated memory is still 159.4MB. Free memory was 101.9MB in the beginning and 99.1MB in the end (delta: 2.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 46.40ms. Allocated memory is still 159.4MB. Free memory was 99.1MB in the beginning and 96.7MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 844.24ms. Allocated memory was 159.4MB in the beginning and 205.5MB in the end (delta: 46.1MB). Free memory was 96.3MB in the beginning and 169.6MB in the end (delta: -73.3MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 4737.51ms. Allocated memory was 205.5MB in the beginning and 249.6MB in the end (delta: 44.0MB). Free memory was 169.6MB in the beginning and 179.1MB in the end (delta: -9.4MB). Peak memory consumption was 34.6MB. Max. memory is 16.1GB. * Witness Printer took 75.88ms. Allocated memory is still 249.6MB. Free memory was 179.1MB in the beginning and 174.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 3097 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.5s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 2.7s. Construction of modules took 0.3s. Büchi inclusion checks took 1.1s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 11 MinimizatonAttempts, 1315 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3876 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3876 mSDsluCounter, 6681 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3296 mSDsCounter, 116 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 326 IncrementalHoareTripleChecker+Invalid, 442 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 116 mSolverCounterUnsat, 3385 mSDtfsCounter, 326 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN1 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L281-L292] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L295-L306] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L309-L320] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L281-L292] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L295-L306] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L309-L320] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-19 07:37:59,566 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f9cb249-d6a6-4b4b-88de-92b1a4f6c0ba/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)