./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 527bcce2 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-527bcce [2023-11-21 22:05:57,060 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-21 22:05:57,131 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-64bit-Automizer_Default.epf [2023-11-21 22:05:57,137 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-21 22:05:57,137 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-21 22:05:57,164 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-21 22:05:57,165 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-21 22:05:57,166 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-21 22:05:57,167 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-21 22:05:57,167 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-21 22:05:57,168 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-21 22:05:57,169 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-21 22:05:57,169 INFO L153 SettingsManager]: * Use SBE=true [2023-11-21 22:05:57,170 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-21 22:05:57,171 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-21 22:05:57,171 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-21 22:05:57,172 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-21 22:05:57,173 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-21 22:05:57,173 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-21 22:05:57,174 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-21 22:05:57,174 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-21 22:05:57,175 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-21 22:05:57,176 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-21 22:05:57,176 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-21 22:05:57,177 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-21 22:05:57,177 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-21 22:05:57,178 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-21 22:05:57,179 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-21 22:05:57,179 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-21 22:05:57,179 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-21 22:05:57,180 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-21 22:05:57,180 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-21 22:05:57,181 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-21 22:05:57,181 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-21 22:05:57,182 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-21 22:05:57,183 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 [2023-11-21 22:05:57,473 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-21 22:05:57,496 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-21 22:05:57,499 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-21 22:05:57,500 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-21 22:05:57,501 INFO L274 PluginConnector]: CDTParser initialized [2023-11-21 22:05:57,503 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2023-11-21 22:06:00,691 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-21 22:06:00,912 INFO L384 CDTParser]: Found 1 translation units. [2023-11-21 22:06:00,913 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2023-11-21 22:06:00,921 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/data/1c179dac4/47690b82e0d6424283fd16f971f9b3d7/FLAG1609850a3 [2023-11-21 22:06:00,938 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/data/1c179dac4/47690b82e0d6424283fd16f971f9b3d7 [2023-11-21 22:06:00,948 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-21 22:06:00,951 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-21 22:06:00,955 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-21 22:06:00,955 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-21 22:06:00,962 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-21 22:06:00,963 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 10:06:00" (1/1) ... [2023-11-21 22:06:00,964 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@691a6c01 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:00, skipping insertion in model container [2023-11-21 22:06:00,965 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 10:06:00" (1/1) ... [2023-11-21 22:06:00,989 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-21 22:06:01,169 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 22:06:01,175 INFO L202 MainTranslator]: Completed pre-run [2023-11-21 22:06:01,186 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 22:06:01,199 INFO L206 MainTranslator]: Completed translation [2023-11-21 22:06:01,199 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01 WrapperNode [2023-11-21 22:06:01,199 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-21 22:06:01,201 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-21 22:06:01,201 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-21 22:06:01,201 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-21 22:06:01,209 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,214 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,231 INFO L138 Inliner]: procedures = 4, calls = 2, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 19 [2023-11-21 22:06:01,232 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-21 22:06:01,233 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-21 22:06:01,233 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-21 22:06:01,233 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-21 22:06:01,245 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,245 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,246 INFO L184 PluginConnector]: Executing the observer HeapSplitter from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,252 INFO L187 HeapSplitter]: Split 0 memory accesses to 0 slices as follows [] [2023-11-21 22:06:01,252 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,252 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,254 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,258 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,259 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,260 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,261 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-21 22:06:01,262 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-21 22:06:01,262 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-21 22:06:01,262 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-21 22:06:01,263 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (1/1) ... [2023-11-21 22:06:01,275 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:01,291 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:01,305 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:01,328 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-21 22:06:01,360 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-21 22:06:01,361 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-21 22:06:01,453 INFO L240 CfgBuilder]: Building ICFG [2023-11-21 22:06:01,455 INFO L266 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-21 22:06:01,567 INFO L281 CfgBuilder]: Performing block encoding [2023-11-21 22:06:01,584 INFO L303 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-21 22:06:01,594 INFO L308 CfgBuilder]: Removed 1 assume(true) statements. [2023-11-21 22:06:01,596 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:06:01 BoogieIcfgContainer [2023-11-21 22:06:01,596 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-21 22:06:01,598 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-21 22:06:01,598 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-21 22:06:01,602 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-21 22:06:01,603 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:06:01,604 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.11 10:06:00" (1/3) ... [2023-11-21 22:06:01,605 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@25a072ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 10:06:01, skipping insertion in model container [2023-11-21 22:06:01,605 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:06:01,606 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:06:01" (2/3) ... [2023-11-21 22:06:01,608 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@25a072ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 10:06:01, skipping insertion in model container [2023-11-21 22:06:01,609 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:06:01,609 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:06:01" (3/3) ... [2023-11-21 22:06:01,614 INFO L332 chiAutomizerObserver]: Analyzing ICFG NarrowKonv.c [2023-11-21 22:06:01,696 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-21 22:06:01,698 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-21 22:06:01,699 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-21 22:06:01,699 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-21 22:06:01,699 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-21 22:06:01,700 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-21 22:06:01,700 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-21 22:06:01,701 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-21 22:06:01,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:01,726 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2023-11-21 22:06:01,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:01,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:01,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-21 22:06:01,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:01,736 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-21 22:06:01,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:01,738 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2023-11-21 22:06:01,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:01,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:01,740 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-21 22:06:01,740 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:01,750 INFO L748 eck$LassoCheckResult]: Stem: 6#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3#L12-1true [2023-11-21 22:06:01,750 INFO L750 eck$LassoCheckResult]: Loop: 3#L12-1true assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9#L12true assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3#L12-1true [2023-11-21 22:06:01,758 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:01,759 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2023-11-21 22:06:01,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:01,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660555574] [2023-11-21 22:06:01,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:01,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:01,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:01,871 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:01,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:01,902 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:01,907 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:01,908 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 1 times [2023-11-21 22:06:01,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:01,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102620163] [2023-11-21 22:06:01,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:01,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:01,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:01,934 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:01,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:01,945 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:01,956 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:01,956 INFO L85 PathProgramCache]: Analyzing trace with hash 925806, now seen corresponding path program 1 times [2023-11-21 22:06:01,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:01,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844427246] [2023-11-21 22:06:01,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:01,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:01,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:02,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:02,085 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:02,085 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844427246] [2023-11-21 22:06:02,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844427246] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:06:02,086 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:06:02,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:06:02,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047255330] [2023-11-21 22:06:02,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:06:02,138 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:02,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:06:02,174 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:06:02,176 INFO L87 Difference]: Start difference. First operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:02,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:02,208 INFO L93 Difference]: Finished difference Result 14 states and 18 transitions. [2023-11-21 22:06:02,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 18 transitions. [2023-11-21 22:06:02,211 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-21 22:06:02,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 8 states and 11 transitions. [2023-11-21 22:06:02,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2023-11-21 22:06:02,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2023-11-21 22:06:02,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 11 transitions. [2023-11-21 22:06:02,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:06:02,217 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8 states and 11 transitions. [2023-11-21 22:06:02,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 11 transitions. [2023-11-21 22:06:02,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 8. [2023-11-21 22:06:02,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.375) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:02,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 11 transitions. [2023-11-21 22:06:02,241 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8 states and 11 transitions. [2023-11-21 22:06:02,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:06:02,247 INFO L428 stractBuchiCegarLoop]: Abstraction has 8 states and 11 transitions. [2023-11-21 22:06:02,248 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-21 22:06:02,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 11 transitions. [2023-11-21 22:06:02,248 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-21 22:06:02,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:02,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:02,249 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-21 22:06:02,249 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:06:02,250 INFO L748 eck$LassoCheckResult]: Stem: 37#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 38#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 39#L12-1 [2023-11-21 22:06:02,250 INFO L750 eck$LassoCheckResult]: Loop: 39#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 40#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 41#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 39#L12-1 [2023-11-21 22:06:02,250 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:02,251 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2023-11-21 22:06:02,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:02,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803977263] [2023-11-21 22:06:02,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:02,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:02,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:02,257 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:02,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:02,260 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:02,261 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:02,261 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 1 times [2023-11-21 22:06:02,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:02,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575815279] [2023-11-21 22:06:02,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:02,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:02,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:02,298 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:02,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:02,309 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:02,310 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:02,310 INFO L85 PathProgramCache]: Analyzing trace with hash 28699757, now seen corresponding path program 1 times [2023-11-21 22:06:02,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:02,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395279502] [2023-11-21 22:06:02,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:02,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:02,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:02,323 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:02,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:02,332 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:02,421 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:06:02,422 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:06:02,422 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:06:02,422 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:06:02,422 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-21 22:06:02,423 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:02,423 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:06:02,423 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:06:02,423 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2023-11-21 22:06:02,423 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:06:02,423 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:06:02,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:02,455 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:02,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:02,588 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:06:02,589 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-21 22:06:02,592 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:02,593 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:02,603 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:02,606 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:06:02,607 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:02,619 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-21 22:06:02,631 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-21 22:06:02,632 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_1=1} Honda state: {v_rep~unnamed0~0~true_1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-21 22:06:02,651 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2023-11-21 22:06:02,651 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:02,651 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:02,654 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:02,664 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-21 22:06:02,665 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:06:02,667 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:02,690 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-21 22:06:02,690 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_1=0} Honda state: {v_rep~unnamed0~0~false_1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-21 22:06:02,714 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:02,714 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:02,714 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:02,717 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:02,719 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-21 22:06:02,720 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:06:02,720 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:02,767 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:02,767 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:02,768 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:02,769 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:02,775 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-21 22:06:02,776 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-21 22:06:02,776 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:02,835 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-21 22:06:02,839 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:02,839 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:06:02,839 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:06:02,839 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:06:02,839 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:06:02,840 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-21 22:06:02,840 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:02,840 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:06:02,840 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:06:02,840 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2023-11-21 22:06:02,840 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:06:02,840 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:06:02,842 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:02,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:02,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:02,925 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:06:02,929 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-21 22:06:02,931 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:02,931 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:02,932 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:02,946 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:06:02,958 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:06:02,959 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:06:02,959 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:06:02,959 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:06:02,966 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-21 22:06:02,966 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-21 22:06:02,972 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-21 22:06:02,983 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:06:02,995 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:02,995 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:02,996 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:02,997 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:02,998 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-21 22:06:02,999 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:06:03,009 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:06:03,009 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:06:03,009 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:06:03,009 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:06:03,013 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-21 22:06:03,013 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-21 22:06:03,027 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:06:03,046 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:03,046 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:03,046 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:03,048 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:03,051 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-21 22:06:03,052 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:06:03,064 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:06:03,064 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:06:03,065 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:06:03,065 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:06:03,065 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:06:03,067 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:06:03,067 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:06:03,070 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-21 22:06:03,096 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-21 22:06:03,096 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-21 22:06:03,097 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:03,098 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:03,144 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:03,146 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-21 22:06:03,146 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-21 22:06:03,146 INFO L513 LassoAnalysis]: Proved termination. [2023-11-21 22:06:03,147 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2023-11-21 22:06:03,164 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-21 22:06:03,171 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:03,175 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-21 22:06:03,203 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:03,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:03,219 INFO L262 TraceCheckSpWp]: Trace formula consists of 5 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-21 22:06:03,220 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:03,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:03,236 WARN L260 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-21 22:06:03,238 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:03,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:03,294 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-21 22:06:03,296 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 11 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:03,354 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 11 transitions. cyclomatic complexity: 5. Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 11 states and 15 transitions. Complement of second has 5 states. [2023-11-21 22:06:03,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-21 22:06:03,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:03,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 5 transitions. [2023-11-21 22:06:03,360 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 2 letters. Loop has 3 letters. [2023-11-21 22:06:03,360 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:03,361 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 5 letters. Loop has 3 letters. [2023-11-21 22:06:03,361 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:03,361 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 2 letters. Loop has 6 letters. [2023-11-21 22:06:03,361 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:03,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 15 transitions. [2023-11-21 22:06:03,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2023-11-21 22:06:03,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 15 transitions. [2023-11-21 22:06:03,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-21 22:06:03,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2023-11-21 22:06:03,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 15 transitions. [2023-11-21 22:06:03,367 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:03,367 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2023-11-21 22:06:03,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 15 transitions. [2023-11-21 22:06:03,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2023-11-21 22:06:03,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:03,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 15 transitions. [2023-11-21 22:06:03,376 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2023-11-21 22:06:03,376 INFO L428 stractBuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2023-11-21 22:06:03,376 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-21 22:06:03,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 15 transitions. [2023-11-21 22:06:03,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2023-11-21 22:06:03,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:03,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:03,384 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2023-11-21 22:06:03,385 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:03,385 INFO L748 eck$LassoCheckResult]: Stem: 95#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 96#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 97#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 92#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 93#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 88#L12-1 [2023-11-21 22:06:03,386 INFO L750 eck$LassoCheckResult]: Loop: 88#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 89#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 88#L12-1 [2023-11-21 22:06:03,386 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:03,386 INFO L85 PathProgramCache]: Analyzing trace with hash 28699755, now seen corresponding path program 1 times [2023-11-21 22:06:03,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:03,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587450752] [2023-11-21 22:06:03,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:03,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:03,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:03,407 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:03,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:03,418 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:03,420 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:03,421 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 2 times [2023-11-21 22:06:03,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:03,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068449369] [2023-11-21 22:06:03,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:03,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:03,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:03,428 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:03,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:03,433 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:03,434 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:03,435 INFO L85 PathProgramCache]: Analyzing trace with hash 1810661142, now seen corresponding path program 1 times [2023-11-21 22:06:03,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:03,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105232416] [2023-11-21 22:06:03,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:03,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:03,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:03,511 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:03,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:03,511 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105232416] [2023-11-21 22:06:03,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2105232416] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:03,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [650663209] [2023-11-21 22:06:03,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:03,512 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:03,513 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:03,515 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:03,539 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2023-11-21 22:06:03,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:03,551 INFO L262 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-21 22:06:03,552 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:03,604 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:03,605 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:03,642 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:03,643 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [650663209] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:03,643 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:03,643 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2023-11-21 22:06:03,643 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336599123] [2023-11-21 22:06:03,644 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:03,668 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:03,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2023-11-21 22:06:03,669 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2023-11-21 22:06:03,669 INFO L87 Difference]: Start difference. First operand 11 states and 15 transitions. cyclomatic complexity: 6 Second operand has 7 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 7 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:03,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:03,737 INFO L93 Difference]: Finished difference Result 23 states and 28 transitions. [2023-11-21 22:06:03,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 28 transitions. [2023-11-21 22:06:03,740 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-21 22:06:03,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 23 states and 28 transitions. [2023-11-21 22:06:03,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2023-11-21 22:06:03,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2023-11-21 22:06:03,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 28 transitions. [2023-11-21 22:06:03,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:03,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 28 transitions. [2023-11-21 22:06:03,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 28 transitions. [2023-11-21 22:06:03,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2023-11-21 22:06:03,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.2173913043478262) internal successors, (28), 22 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:03,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 28 transitions. [2023-11-21 22:06:03,750 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23 states and 28 transitions. [2023-11-21 22:06:03,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-21 22:06:03,752 INFO L428 stractBuchiCegarLoop]: Abstraction has 23 states and 28 transitions. [2023-11-21 22:06:03,752 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-21 22:06:03,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 28 transitions. [2023-11-21 22:06:03,753 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-21 22:06:03,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:03,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:03,754 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1] [2023-11-21 22:06:03,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:06:03,754 INFO L748 eck$LassoCheckResult]: Stem: 180#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 181#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 182#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 183#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 172#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 173#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 177#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 178#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 186#L12-1 [2023-11-21 22:06:03,754 INFO L750 eck$LassoCheckResult]: Loop: 186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 186#L12-1 [2023-11-21 22:06:03,755 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:03,755 INFO L85 PathProgramCache]: Analyzing trace with hash -1805445589, now seen corresponding path program 1 times [2023-11-21 22:06:03,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:03,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308928133] [2023-11-21 22:06:03,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:03,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:03,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:03,780 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:03,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:03,791 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:03,793 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:03,793 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 2 times [2023-11-21 22:06:03,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:03,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492506673] [2023-11-21 22:06:03,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:03,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:03,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:03,799 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:03,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:03,809 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:03,810 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:03,810 INFO L85 PathProgramCache]: Analyzing trace with hash -154083067, now seen corresponding path program 2 times [2023-11-21 22:06:03,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:03,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840933972] [2023-11-21 22:06:03,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:03,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:03,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:03,836 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:03,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:03,852 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:03,901 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:06:03,901 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:06:03,902 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:06:03,902 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:06:03,902 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-21 22:06:03,902 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:03,902 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:06:03,902 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:06:03,903 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2023-11-21 22:06:03,903 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:06:03,903 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:06:03,905 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:03,909 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:03,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:03,985 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:06:03,986 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-21 22:06:03,987 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:03,987 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:03,994 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:04,006 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:06:04,006 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:04,019 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-21 22:06:04,035 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-21 22:06:04,035 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-21 22:06:04,054 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:04,054 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,054 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:04,055 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:04,064 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-21 22:06:04,064 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:06:04,064 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:04,086 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-21 22:06:04,086 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_3=1} Honda state: {v_rep~unnamed0~0~true_3=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-21 22:06:04,100 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:04,101 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,101 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:04,102 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:04,103 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-21 22:06:04,104 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:06:04,104 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:04,132 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:04,132 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,133 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:04,133 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:04,135 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-21 22:06:04,136 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-21 22:06:04,136 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:04,220 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-21 22:06:04,224 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:04,225 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:06:04,225 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:06:04,225 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:06:04,225 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:06:04,225 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-21 22:06:04,225 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,225 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:06:04,226 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:06:04,226 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2023-11-21 22:06:04,226 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:06:04,226 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:06:04,228 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:04,231 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:04,245 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:04,300 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:06:04,300 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-21 22:06:04,300 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,300 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:04,301 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:04,313 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:06:04,326 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:06:04,326 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:06:04,326 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:06:04,326 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:06:04,330 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-21 22:06:04,330 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-21 22:06:04,332 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-21 22:06:04,342 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:06:04,365 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:04,365 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,365 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:04,366 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:04,409 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-21 22:06:04,419 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:04,420 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:06:04,432 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:06:04,432 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:06:04,433 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:06:04,433 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:06:04,433 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:06:04,434 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:06:04,435 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:06:04,444 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-21 22:06:04,448 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-21 22:06:04,448 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-21 22:06:04,448 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,448 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:04,450 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:04,452 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-21 22:06:04,452 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-21 22:06:04,452 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-21 22:06:04,453 INFO L513 LassoAnalysis]: Proved termination. [2023-11-21 22:06:04,453 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2023-11-21 22:06:04,479 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:04,480 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-21 22:06:04,499 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:04,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:04,510 INFO L262 TraceCheckSpWp]: Trace formula consists of 26 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-21 22:06:04,511 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:04,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:04,536 WARN L260 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-21 22:06:04,537 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:04,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:04,565 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-21 22:06:04,566 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 23 states and 28 transitions. cyclomatic complexity: 8 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:04,595 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 23 states and 28 transitions. cyclomatic complexity: 8. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 50 transitions. Complement of second has 5 states. [2023-11-21 22:06:04,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-21 22:06:04,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:04,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2023-11-21 22:06:04,598 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 11 letters. Loop has 3 letters. [2023-11-21 22:06:04,600 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:04,600 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2023-11-21 22:06:04,601 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:04,601 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 11 letters. Loop has 6 letters. [2023-11-21 22:06:04,601 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:04,601 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 50 transitions. [2023-11-21 22:06:04,612 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-21 22:06:04,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 38 states and 44 transitions. [2023-11-21 22:06:04,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2023-11-21 22:06:04,615 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2023-11-21 22:06:04,615 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 44 transitions. [2023-11-21 22:06:04,615 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:04,615 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38 states and 44 transitions. [2023-11-21 22:06:04,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 44 transitions. [2023-11-21 22:06:04,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 34. [2023-11-21 22:06:04,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.1764705882352942) internal successors, (40), 33 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:04,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 40 transitions. [2023-11-21 22:06:04,623 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 40 transitions. [2023-11-21 22:06:04,623 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 40 transitions. [2023-11-21 22:06:04,624 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-21 22:06:04,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 40 transitions. [2023-11-21 22:06:04,626 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-21 22:06:04,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:04,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:04,627 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 1, 1, 1] [2023-11-21 22:06:04,627 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:06:04,628 INFO L748 eck$LassoCheckResult]: Stem: 309#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 310#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 311#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 305#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 308#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 303#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 304#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 320#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 301#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 302#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 306#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 307#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 333#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 331#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 323#L12-1 [2023-11-21 22:06:04,628 INFO L750 eck$LassoCheckResult]: Loop: 323#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 329#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 321#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 323#L12-1 [2023-11-21 22:06:04,628 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:04,628 INFO L85 PathProgramCache]: Analyzing trace with hash 1972849857, now seen corresponding path program 3 times [2023-11-21 22:06:04,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:04,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039992819] [2023-11-21 22:06:04,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:04,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:04,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:04,657 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:04,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:04,667 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:04,667 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:04,668 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 3 times [2023-11-21 22:06:04,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:04,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430860428] [2023-11-21 22:06:04,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:04,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:04,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:04,672 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:04,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:04,682 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:04,683 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:04,683 INFO L85 PathProgramCache]: Analyzing trace with hash 837622447, now seen corresponding path program 4 times [2023-11-21 22:06:04,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:04,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430711128] [2023-11-21 22:06:04,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:04,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:04,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:04,705 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:04,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:04,725 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:04,777 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:06:04,778 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:06:04,778 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:06:04,778 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:06:04,778 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-21 22:06:04,778 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,778 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:06:04,778 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:06:04,779 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2023-11-21 22:06:04,779 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:06:04,779 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:06:04,781 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:04,784 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:04,795 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:04,847 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:06:04,847 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-21 22:06:04,847 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,848 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:04,849 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:04,851 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:06:04,852 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:04,865 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-21 22:06:04,875 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-21 22:06:04,875 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_5=1} Honda state: {v_rep~unnamed0~0~true_5=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-21 22:06:04,895 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:04,895 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,896 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:04,897 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:04,908 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:06:04,908 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:04,909 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-21 22:06:04,951 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:04,951 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:04,951 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:04,952 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:04,961 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-21 22:06:04,962 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:04,974 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-21 22:06:05,041 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-21 22:06:05,050 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:05,050 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:06:05,050 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:06:05,050 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:06:05,051 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:06:05,051 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-21 22:06:05,051 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:05,051 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:06:05,051 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:06:05,051 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2023-11-21 22:06:05,051 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:06:05,051 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:06:05,053 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:05,064 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:05,068 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:05,124 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:06:05,124 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-21 22:06:05,125 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:05,125 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:05,126 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:05,133 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-21 22:06:05,134 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:06:05,146 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:06:05,146 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:06:05,147 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:06:05,147 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:06:05,147 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:06:05,148 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:06:05,148 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:06:05,158 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-21 22:06:05,162 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-21 22:06:05,163 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2023-11-21 22:06:05,163 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:05,163 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:05,173 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:05,175 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-21 22:06:05,175 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-21 22:06:05,175 INFO L513 LassoAnalysis]: Proved termination. [2023-11-21 22:06:05,175 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~range~0#1) = -1*ULTIMATE.start_main_~i~0#1 + 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2023-11-21 22:06:05,192 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-21 22:06:05,195 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:05,196 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-21 22:06:05,213 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:05,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:05,226 INFO L262 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-21 22:06:05,226 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:05,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:05,262 WARN L260 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-21 22:06:05,263 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:05,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:05,294 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-21 22:06:05,294 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:05,324 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 51 transitions. Complement of second has 5 states. [2023-11-21 22:06:05,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-21 22:06:05,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:05,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2023-11-21 22:06:05,329 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2023-11-21 22:06:05,329 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:05,329 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2023-11-21 22:06:05,348 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:05,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:05,365 INFO L262 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-21 22:06:05,367 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:05,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:05,399 WARN L260 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-21 22:06:05,400 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:05,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:05,425 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-21 22:06:05,425 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:05,452 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 51 transitions. Complement of second has 5 states. [2023-11-21 22:06:05,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-21 22:06:05,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:05,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2023-11-21 22:06:05,454 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2023-11-21 22:06:05,454 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:05,454 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2023-11-21 22:06:05,467 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:05,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:05,477 INFO L262 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-21 22:06:05,477 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:05,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:05,500 WARN L260 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-21 22:06:05,501 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:05,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:05,522 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-21 22:06:05,522 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:05,548 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 57 states and 69 transitions. Complement of second has 4 states. [2023-11-21 22:06:05,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-21 22:06:05,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:05,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 13 transitions. [2023-11-21 22:06:05,550 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 14 letters. Loop has 3 letters. [2023-11-21 22:06:05,550 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:05,550 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 17 letters. Loop has 3 letters. [2023-11-21 22:06:05,551 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:05,551 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 14 letters. Loop has 6 letters. [2023-11-21 22:06:05,551 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:05,552 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 69 transitions. [2023-11-21 22:06:05,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 12 [2023-11-21 22:06:05,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 47 states and 58 transitions. [2023-11-21 22:06:05,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2023-11-21 22:06:05,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2023-11-21 22:06:05,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 58 transitions. [2023-11-21 22:06:05,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:05,555 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 58 transitions. [2023-11-21 22:06:05,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 58 transitions. [2023-11-21 22:06:05,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 31. [2023-11-21 22:06:05,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.2903225806451613) internal successors, (40), 30 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:05,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 40 transitions. [2023-11-21 22:06:05,560 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 40 transitions. [2023-11-21 22:06:05,560 INFO L428 stractBuchiCegarLoop]: Abstraction has 31 states and 40 transitions. [2023-11-21 22:06:05,560 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-21 22:06:05,560 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 40 transitions. [2023-11-21 22:06:05,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 11 [2023-11-21 22:06:05,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:05,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:05,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 3, 2, 1, 1] [2023-11-21 22:06:05,562 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 1, 1] [2023-11-21 22:06:05,563 INFO L748 eck$LassoCheckResult]: Stem: 671#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 673#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 665#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 692#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 662#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 663#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 667#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 668#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 674#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 669#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 670#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 690#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 684#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 683#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 682#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 680#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 678#L12-1 [2023-11-21 22:06:05,563 INFO L750 eck$LassoCheckResult]: Loop: 678#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 679#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 688#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 686#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 687#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 685#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 678#L12-1 [2023-11-21 22:06:05,563 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:05,563 INFO L85 PathProgramCache]: Analyzing trace with hash 1031341869, now seen corresponding path program 5 times [2023-11-21 22:06:05,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:05,564 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823882576] [2023-11-21 22:06:05,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:05,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:05,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:05,654 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:05,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:05,655 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [823882576] [2023-11-21 22:06:05,655 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [823882576] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:05,655 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [890443833] [2023-11-21 22:06:05,655 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-21 22:06:05,656 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:05,656 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:05,657 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:05,679 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2023-11-21 22:06:05,700 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2023-11-21 22:06:05,700 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:06:05,701 INFO L262 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-21 22:06:05,703 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:05,795 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:05,795 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:05,876 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:05,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [890443833] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:05,876 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:05,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2023-11-21 22:06:05,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1961890822] [2023-11-21 22:06:05,877 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:05,877 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:06:05,878 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:05,878 INFO L85 PathProgramCache]: Analyzing trace with hash 1215871107, now seen corresponding path program 1 times [2023-11-21 22:06:05,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:05,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453640251] [2023-11-21 22:06:05,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:05,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:05,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:05,884 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:05,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:05,887 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:05,950 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:06:05,950 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:06:05,950 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:06:05,950 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:06:05,951 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-21 22:06:05,951 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:05,951 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:06:05,951 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:06:05,951 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2023-11-21 22:06:05,951 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:06:05,952 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:06:05,953 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:05,965 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:05,969 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:06,058 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:06:06,058 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-21 22:06:06,059 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:06,059 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:06,061 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:06,070 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:06:06,070 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:06,082 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2023-11-21 22:06:06,117 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:06,117 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:06,117 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:06,118 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:06,122 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-21 22:06:06,122 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:06:06,123 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2023-11-21 22:06:06,261 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-21 22:06:06,271 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:06,271 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:06:06,271 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:06:06,271 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:06:06,271 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:06:06,272 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-21 22:06:06,272 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:06,272 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:06:06,272 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:06:06,272 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2023-11-21 22:06:06,272 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:06:06,272 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:06:06,273 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:06,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:06,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:06:06,365 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:06:06,365 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-21 22:06:06,366 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:06,366 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:06,367 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:06,370 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-21 22:06:06,371 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:06:06,384 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:06:06,384 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:06:06,385 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:06:06,385 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:06:06,385 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:06:06,389 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:06:06,389 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:06:06,403 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-21 22:06:06,407 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-21 22:06:06,407 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2023-11-21 22:06:06,407 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:06:06,408 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:06,410 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:06:06,411 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-21 22:06:06,411 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-21 22:06:06,411 INFO L513 LassoAnalysis]: Proved termination. [2023-11-21 22:06:06,412 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1) = 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2023-11-21 22:06:06,429 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-21 22:06:06,431 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:06,432 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-21 22:06:06,445 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:06,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:06,461 INFO L262 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-21 22:06:06,463 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:06,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:06,503 INFO L262 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-21 22:06:06,504 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:06,547 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:06:06,548 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-21 22:06:06,548 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:06,588 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 72 states and 96 transitions. Complement of second has 6 states. [2023-11-21 22:06:06,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2023-11-21 22:06:06,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:06,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 15 transitions. [2023-11-21 22:06:06,593 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 15 transitions. Stem has 17 letters. Loop has 6 letters. [2023-11-21 22:06:06,596 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:06,596 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 15 transitions. Stem has 23 letters. Loop has 6 letters. [2023-11-21 22:06:06,597 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:06,597 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 15 transitions. Stem has 17 letters. Loop has 12 letters. [2023-11-21 22:06:06,598 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:06:06,598 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 96 transitions. [2023-11-21 22:06:06,600 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2023-11-21 22:06:06,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 55 states and 73 transitions. [2023-11-21 22:06:06,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2023-11-21 22:06:06,602 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2023-11-21 22:06:06,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 73 transitions. [2023-11-21 22:06:06,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:06,603 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55 states and 73 transitions. [2023-11-21 22:06:06,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 73 transitions. [2023-11-21 22:06:06,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 47. [2023-11-21 22:06:06,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.3404255319148937) internal successors, (63), 46 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:06,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 63 transitions. [2023-11-21 22:06:06,613 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 63 transitions. [2023-11-21 22:06:06,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:06,614 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2023-11-21 22:06:06,614 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=96, Unknown=0, NotChecked=0, Total=156 [2023-11-21 22:06:06,617 INFO L87 Difference]: Start difference. First operand 47 states and 63 transitions. Second operand has 13 states, 13 states have (on average 3.076923076923077) internal successors, (40), 13 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:06,664 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:06,684 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:06,728 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2023-11-21 22:06:06,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:06,806 INFO L93 Difference]: Finished difference Result 89 states and 105 transitions. [2023-11-21 22:06:06,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 105 transitions. [2023-11-21 22:06:06,814 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2023-11-21 22:06:06,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 75 states and 91 transitions. [2023-11-21 22:06:06,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2023-11-21 22:06:06,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2023-11-21 22:06:06,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 91 transitions. [2023-11-21 22:06:06,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:06,822 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75 states and 91 transitions. [2023-11-21 22:06:06,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 91 transitions. [2023-11-21 22:06:06,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 71. [2023-11-21 22:06:06,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 71 states have (on average 1.2253521126760563) internal successors, (87), 70 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:06,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 87 transitions. [2023-11-21 22:06:06,838 INFO L240 hiAutomatonCegarLoop]: Abstraction has 71 states and 87 transitions. [2023-11-21 22:06:06,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2023-11-21 22:06:06,839 INFO L428 stractBuchiCegarLoop]: Abstraction has 71 states and 87 transitions. [2023-11-21 22:06:06,841 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-21 22:06:06,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 87 transitions. [2023-11-21 22:06:06,842 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2023-11-21 22:06:06,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:06,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:06,844 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 9, 2, 1, 1] [2023-11-21 22:06:06,844 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:06,845 INFO L748 eck$LassoCheckResult]: Stem: 1111#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 1112#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 1113#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1145#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1146#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1144#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1119#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1120#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1160#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1158#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1157#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1156#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1155#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1151#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1150#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1149#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1148#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1147#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1142#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1143#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1141#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1139#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1137#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1117#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1108#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1104#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1105#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1167#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1166#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1138#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1123#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1122#L12 [2023-11-21 22:06:06,845 INFO L750 eck$LassoCheckResult]: Loop: 1122#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1121#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1122#L12 [2023-11-21 22:06:06,846 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:06,846 INFO L85 PathProgramCache]: Analyzing trace with hash -566648130, now seen corresponding path program 6 times [2023-11-21 22:06:06,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:06,847 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34075630] [2023-11-21 22:06:06,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:06,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:06,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:07,114 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2023-11-21 22:06:07,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:07,114 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [34075630] [2023-11-21 22:06:07,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [34075630] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:07,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [736647822] [2023-11-21 22:06:07,116 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-21 22:06:07,116 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:07,117 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:07,118 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:07,143 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2023-11-21 22:06:07,179 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2023-11-21 22:06:07,179 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:06:07,180 INFO L262 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 10 conjunts are in the unsatisfiable core [2023-11-21 22:06:07,182 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:07,366 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2023-11-21 22:06:07,366 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:07,546 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2023-11-21 22:06:07,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [736647822] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:07,547 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:07,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 25 [2023-11-21 22:06:07,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510321805] [2023-11-21 22:06:07,547 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:07,548 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:06:07,548 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:07,548 INFO L85 PathProgramCache]: Analyzing trace with hash 1654, now seen corresponding path program 3 times [2023-11-21 22:06:07,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:07,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393322425] [2023-11-21 22:06:07,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:07,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:07,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:07,559 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:07,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:07,562 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:07,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:07,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2023-11-21 22:06:07,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=356, Unknown=0, NotChecked=0, Total=600 [2023-11-21 22:06:07,585 INFO L87 Difference]: Start difference. First operand 71 states and 87 transitions. cyclomatic complexity: 22 Second operand has 25 states, 25 states have (on average 3.04) internal successors, (76), 25 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:07,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:07,837 INFO L93 Difference]: Finished difference Result 151 states and 167 transitions. [2023-11-21 22:06:07,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 167 transitions. [2023-11-21 22:06:07,843 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2023-11-21 22:06:07,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 123 states and 139 transitions. [2023-11-21 22:06:07,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2023-11-21 22:06:07,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2023-11-21 22:06:07,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 139 transitions. [2023-11-21 22:06:07,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:07,846 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 139 transitions. [2023-11-21 22:06:07,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 139 transitions. [2023-11-21 22:06:07,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 119. [2023-11-21 22:06:07,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119 states, 119 states have (on average 1.134453781512605) internal successors, (135), 118 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:07,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 135 transitions. [2023-11-21 22:06:07,865 INFO L240 hiAutomatonCegarLoop]: Abstraction has 119 states and 135 transitions. [2023-11-21 22:06:07,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2023-11-21 22:06:07,870 INFO L428 stractBuchiCegarLoop]: Abstraction has 119 states and 135 transitions. [2023-11-21 22:06:07,870 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-21 22:06:07,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119 states and 135 transitions. [2023-11-21 22:06:07,871 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2023-11-21 22:06:07,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:07,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:07,876 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 23, 21, 2, 1, 1] [2023-11-21 22:06:07,876 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:07,876 INFO L748 eck$LassoCheckResult]: Stem: 1585#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 1586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 1587#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1593#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1582#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1583#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1636#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1637#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1578#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1579#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1672#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1671#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1670#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1669#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1668#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1667#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1666#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1665#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1664#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1663#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1662#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1661#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1660#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1659#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1658#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1657#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1656#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1655#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1654#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1653#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1652#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1651#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1650#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1649#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1648#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1647#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1646#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1645#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1644#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1643#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1642#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1641#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1640#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1639#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1638#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1613#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1616#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1612#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1611#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1610#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1609#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1591#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1592#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1635#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1634#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1633#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1632#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1631#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1630#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1629#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1628#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1627#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1626#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1625#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1624#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1623#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1622#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1620#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1621#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1617#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1614#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1594#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1595#L12 [2023-11-21 22:06:07,877 INFO L750 eck$LassoCheckResult]: Loop: 1595#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1597#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1595#L12 [2023-11-21 22:06:07,877 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:07,877 INFO L85 PathProgramCache]: Analyzing trace with hash 1262893886, now seen corresponding path program 7 times [2023-11-21 22:06:07,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:07,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464311105] [2023-11-21 22:06:07,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:07,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:07,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:08,388 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2023-11-21 22:06:08,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:08,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464311105] [2023-11-21 22:06:08,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464311105] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:08,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [997157272] [2023-11-21 22:06:08,389 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-21 22:06:08,389 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:08,390 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:08,392 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:08,399 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2023-11-21 22:06:08,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:08,452 INFO L262 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 18 conjunts are in the unsatisfiable core [2023-11-21 22:06:08,455 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:08,930 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2023-11-21 22:06:08,931 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:09,339 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2023-11-21 22:06:09,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [997157272] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:09,339 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:09,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 38 [2023-11-21 22:06:09,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1212264187] [2023-11-21 22:06:09,340 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:09,340 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:06:09,341 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:09,341 INFO L85 PathProgramCache]: Analyzing trace with hash 1654, now seen corresponding path program 4 times [2023-11-21 22:06:09,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:09,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097521903] [2023-11-21 22:06:09,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:09,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:09,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:09,344 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:09,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:09,347 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:09,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:09,364 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2023-11-21 22:06:09,365 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=545, Invalid=861, Unknown=0, NotChecked=0, Total=1406 [2023-11-21 22:06:09,366 INFO L87 Difference]: Start difference. First operand 119 states and 135 transitions. cyclomatic complexity: 22 Second operand has 38 states, 38 states have (on average 3.0526315789473686) internal successors, (116), 38 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:09,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:09,647 INFO L93 Difference]: Finished difference Result 220 states and 236 transitions. [2023-11-21 22:06:09,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 220 states and 236 transitions. [2023-11-21 22:06:09,649 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2023-11-21 22:06:09,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 220 states to 186 states and 202 transitions. [2023-11-21 22:06:09,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2023-11-21 22:06:09,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2023-11-21 22:06:09,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 202 transitions. [2023-11-21 22:06:09,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:09,652 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 202 transitions. [2023-11-21 22:06:09,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 202 transitions. [2023-11-21 22:06:09,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 182. [2023-11-21 22:06:09,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 182 states have (on average 1.0879120879120878) internal successors, (198), 181 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:09,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 198 transitions. [2023-11-21 22:06:09,660 INFO L240 hiAutomatonCegarLoop]: Abstraction has 182 states and 198 transitions. [2023-11-21 22:06:09,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2023-11-21 22:06:09,661 INFO L428 stractBuchiCegarLoop]: Abstraction has 182 states and 198 transitions. [2023-11-21 22:06:09,661 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-21 22:06:09,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182 states and 198 transitions. [2023-11-21 22:06:09,663 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2023-11-21 22:06:09,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:09,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:09,665 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [37, 36, 34, 2, 1, 1] [2023-11-21 22:06:09,666 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:09,666 INFO L748 eck$LassoCheckResult]: Stem: 2399#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 2400#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 2401#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2407#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2396#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2397#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2474#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2475#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2392#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2393#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2525#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2524#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2523#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2522#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2521#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2520#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2519#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2518#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2517#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2516#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2515#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2514#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2513#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2512#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2511#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2510#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2509#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2508#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2507#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2506#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2505#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2504#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2503#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2502#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2501#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2500#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2499#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2498#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2497#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2496#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2495#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2494#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2493#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2492#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2491#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2490#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2489#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2488#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2487#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2486#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2485#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2484#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2483#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2482#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2481#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2480#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2479#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2478#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2477#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2476#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2427#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2430#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2426#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2425#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2424#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2423#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2405#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2406#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2473#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2472#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2471#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2470#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2469#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2468#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2467#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2466#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2465#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2464#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2463#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2462#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2461#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2460#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2459#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2458#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2457#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2456#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2455#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2454#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2453#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2452#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2451#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2450#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2449#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2448#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2447#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2446#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2445#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2444#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2443#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2442#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2441#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2440#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2439#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2438#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2437#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2436#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2434#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2435#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2431#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2428#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2408#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2409#L12 [2023-11-21 22:06:09,667 INFO L750 eck$LassoCheckResult]: Loop: 2409#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2411#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2409#L12 [2023-11-21 22:06:09,667 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:09,667 INFO L85 PathProgramCache]: Analyzing trace with hash -1287581916, now seen corresponding path program 8 times [2023-11-21 22:06:09,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:09,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234637195] [2023-11-21 22:06:09,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:09,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:09,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:09,694 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:09,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:09,738 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:09,738 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:09,739 INFO L85 PathProgramCache]: Analyzing trace with hash 1654, now seen corresponding path program 5 times [2023-11-21 22:06:09,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:09,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245536403] [2023-11-21 22:06:09,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:09,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:09,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:09,742 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:09,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:09,745 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:09,745 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:09,745 INFO L85 PathProgramCache]: Analyzing trace with hash -415639335, now seen corresponding path program 1 times [2023-11-21 22:06:09,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:09,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482442876] [2023-11-21 22:06:09,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:09,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:09,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:09,838 INFO L134 CoverageAnalysis]: Checked inductivity of 1999 backedges. 179 proven. 0 refuted. 0 times theorem prover too weak. 1820 trivial. 0 not checked. [2023-11-21 22:06:09,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:09,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482442876] [2023-11-21 22:06:09,839 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [482442876] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:06:09,839 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:06:09,839 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-21 22:06:09,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613945434] [2023-11-21 22:06:09,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:06:09,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:09,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 22:06:09,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2023-11-21 22:06:09,855 INFO L87 Difference]: Start difference. First operand 182 states and 198 transitions. cyclomatic complexity: 22 Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:09,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:09,872 INFO L93 Difference]: Finished difference Result 180 states and 192 transitions. [2023-11-21 22:06:09,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 180 states and 192 transitions. [2023-11-21 22:06:09,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:09,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 180 states to 132 states and 140 transitions. [2023-11-21 22:06:09,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2023-11-21 22:06:09,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2023-11-21 22:06:09,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132 states and 140 transitions. [2023-11-21 22:06:09,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:09,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 132 states and 140 transitions. [2023-11-21 22:06:09,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states and 140 transitions. [2023-11-21 22:06:09,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 129. [2023-11-21 22:06:09,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129 states, 129 states have (on average 1.062015503875969) internal successors, (137), 128 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:09,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 137 transitions. [2023-11-21 22:06:09,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129 states and 137 transitions. [2023-11-21 22:06:09,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 22:06:09,881 INFO L428 stractBuchiCegarLoop]: Abstraction has 129 states and 137 transitions. [2023-11-21 22:06:09,881 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-21 22:06:09,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129 states and 137 transitions. [2023-11-21 22:06:09,883 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:09,883 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:09,883 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:09,884 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [38, 37, 34, 3, 1, 1, 1] [2023-11-21 22:06:09,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:09,885 INFO L748 eck$LassoCheckResult]: Stem: 2769#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 2770#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 2771#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2774#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2775#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2786#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2787#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2767#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2763#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2764#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2890#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2889#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2888#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2887#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2886#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2885#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2884#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2883#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2882#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2881#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2880#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2879#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2878#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2877#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2876#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2875#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2874#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2873#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2872#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2871#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2870#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2869#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2868#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2867#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2866#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2865#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2864#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2863#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2862#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2861#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2860#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2859#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2858#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2857#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2856#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2855#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2854#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2853#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2852#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2851#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2850#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2849#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2848#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2847#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2846#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2845#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2844#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2843#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2842#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2841#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2839#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2840#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2838#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2837#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2836#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2835#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2834#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2833#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2832#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2831#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2830#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2829#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2828#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2827#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2826#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2825#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2824#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2823#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2822#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2821#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2820#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2819#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2818#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2817#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2816#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2815#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2814#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2813#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2812#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2811#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2810#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2809#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2808#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2807#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2806#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2805#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2804#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2803#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2802#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2801#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2800#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2799#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2798#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2797#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2796#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2795#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2794#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2793#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2792#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2791#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2790#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2788#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2785#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2784#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2780#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2776#L12-1 [2023-11-21 22:06:09,886 INFO L750 eck$LassoCheckResult]: Loop: 2776#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2777#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2776#L12-1 [2023-11-21 22:06:09,886 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:09,886 INFO L85 PathProgramCache]: Analyzing trace with hash 2325394, now seen corresponding path program 2 times [2023-11-21 22:06:09,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:09,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625749191] [2023-11-21 22:06:09,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:09,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:09,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:10,460 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2023-11-21 22:06:10,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:10,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1625749191] [2023-11-21 22:06:10,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1625749191] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:10,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1067972581] [2023-11-21 22:06:10,461 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-21 22:06:10,461 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:10,461 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:10,463 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:10,487 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2023-11-21 22:06:10,543 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-21 22:06:10,543 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:06:10,545 INFO L262 TraceCheckSpWp]: Trace formula consists of 242 conjuncts, 20 conjunts are in the unsatisfiable core [2023-11-21 22:06:10,552 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:11,065 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2023-11-21 22:06:11,066 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:11,553 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2023-11-21 22:06:11,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1067972581] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:11,554 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:11,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 40 [2023-11-21 22:06:11,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274243668] [2023-11-21 22:06:11,554 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:11,555 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:06:11,556 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:11,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 6 times [2023-11-21 22:06:11,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:11,556 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269050464] [2023-11-21 22:06:11,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:11,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:11,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:11,559 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:11,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:11,561 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:11,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:11,578 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2023-11-21 22:06:11,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=556, Invalid=1004, Unknown=0, NotChecked=0, Total=1560 [2023-11-21 22:06:11,579 INFO L87 Difference]: Start difference. First operand 129 states and 137 transitions. cyclomatic complexity: 12 Second operand has 40 states, 40 states have (on average 3.075) internal successors, (123), 40 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:12,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:12,692 INFO L93 Difference]: Finished difference Result 319 states and 329 transitions. [2023-11-21 22:06:12,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 319 states and 329 transitions. [2023-11-21 22:06:12,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:12,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 319 states to 251 states and 261 transitions. [2023-11-21 22:06:12,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2023-11-21 22:06:12,697 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2023-11-21 22:06:12,697 INFO L73 IsDeterministic]: Start isDeterministic. Operand 251 states and 261 transitions. [2023-11-21 22:06:12,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:12,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 251 states and 261 transitions. [2023-11-21 22:06:12,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states and 261 transitions. [2023-11-21 22:06:12,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 243. [2023-11-21 22:06:12,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 243 states, 243 states have (on average 1.0411522633744856) internal successors, (253), 242 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:12,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 253 transitions. [2023-11-21 22:06:12,703 INFO L240 hiAutomatonCegarLoop]: Abstraction has 243 states and 253 transitions. [2023-11-21 22:06:12,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2023-11-21 22:06:12,704 INFO L428 stractBuchiCegarLoop]: Abstraction has 243 states and 253 transitions. [2023-11-21 22:06:12,704 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-21 22:06:12,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 243 states and 253 transitions. [2023-11-21 22:06:12,706 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:12,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:12,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:12,709 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [76, 75, 70, 5, 1, 1, 1] [2023-11-21 22:06:12,709 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:12,710 INFO L748 eck$LassoCheckResult]: Stem: 4020#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 4021#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 4022#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4025#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4026#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4038#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4039#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4018#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4014#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4015#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4255#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4254#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4253#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4252#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4251#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4250#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4249#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4248#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4247#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4246#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4245#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4244#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4243#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4242#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4241#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4240#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4239#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4238#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4237#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4236#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4235#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4234#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4233#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4232#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4231#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4230#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4229#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4228#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4227#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4226#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4225#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4224#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4223#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4222#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4221#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4220#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4219#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4218#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4217#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4216#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4215#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4214#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4213#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4212#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4211#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4210#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4209#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4207#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4206#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4204#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4205#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4203#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4202#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4201#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4200#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4199#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4198#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4197#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4194#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4193#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4192#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4191#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4190#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4189#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4188#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4187#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4186#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4185#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4184#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4183#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4182#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4181#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4180#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4179#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4178#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4177#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4176#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4175#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4174#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4173#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4172#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4171#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4170#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4169#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4168#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4167#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4166#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4165#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4164#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4163#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4162#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4161#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4160#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4159#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4158#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4157#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4156#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4155#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4154#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4153#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4152#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4151#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4150#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4149#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4148#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4146#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4145#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4144#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4143#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4142#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4141#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4140#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4139#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4138#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4137#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4136#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4135#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4134#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4133#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4132#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4131#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4130#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4129#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4128#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4127#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4126#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4125#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4124#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4123#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4122#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4121#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4120#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4119#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4118#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4117#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4116#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4115#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4114#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4113#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4112#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4111#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4110#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4109#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4108#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4107#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4106#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4105#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4104#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4103#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4102#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4101#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4100#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4099#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4098#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4097#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4096#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4095#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4093#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4094#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4092#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4091#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4090#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4089#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4088#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4087#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4086#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4085#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4084#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4083#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4082#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4081#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4080#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4079#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4078#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4077#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4076#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4075#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4074#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4073#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4072#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4071#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4070#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4069#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4068#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4067#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4066#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4065#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4064#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4063#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4062#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4061#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4060#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4059#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4058#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4057#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4056#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4055#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4054#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4053#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4052#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4051#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4050#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4049#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4048#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4047#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4046#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4045#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4044#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4041#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4042#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4040#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4037#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4036#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4035#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4031#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4027#L12-1 [2023-11-21 22:06:12,710 INFO L750 eck$LassoCheckResult]: Loop: 4027#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4028#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4027#L12-1 [2023-11-21 22:06:12,710 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:12,711 INFO L85 PathProgramCache]: Analyzing trace with hash 1383057750, now seen corresponding path program 3 times [2023-11-21 22:06:12,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:12,711 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405335364] [2023-11-21 22:06:12,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:12,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:12,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:13,170 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 0 proven. 6525 refuted. 0 times theorem prover too weak. 1950 trivial. 0 not checked. [2023-11-21 22:06:13,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:13,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405335364] [2023-11-21 22:06:13,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405335364] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:13,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [738466789] [2023-11-21 22:06:13,171 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-21 22:06:13,171 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:13,171 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:13,175 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:13,188 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2023-11-21 22:06:13,242 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2023-11-21 22:06:13,242 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:06:13,243 INFO L262 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 7 conjunts are in the unsatisfiable core [2023-11-21 22:06:13,248 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:13,310 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 730 proven. 5 refuted. 0 times theorem prover too weak. 7740 trivial. 0 not checked. [2023-11-21 22:06:13,311 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:13,372 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 730 proven. 5 refuted. 0 times theorem prover too weak. 7740 trivial. 0 not checked. [2023-11-21 22:06:13,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [738466789] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:13,373 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:13,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5, 5] total 11 [2023-11-21 22:06:13,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411789068] [2023-11-21 22:06:13,374 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:13,375 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:06:13,376 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:13,376 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 7 times [2023-11-21 22:06:13,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:13,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043862122] [2023-11-21 22:06:13,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:13,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:13,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:13,381 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:13,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:13,382 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:13,397 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:13,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2023-11-21 22:06:13,398 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2023-11-21 22:06:13,398 INFO L87 Difference]: Start difference. First operand 243 states and 253 transitions. cyclomatic complexity: 16 Second operand has 12 states, 11 states have (on average 3.5454545454545454) internal successors, (39), 12 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:13,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:13,703 INFO L93 Difference]: Finished difference Result 267 states and 282 transitions. [2023-11-21 22:06:13,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 267 states and 282 transitions. [2023-11-21 22:06:13,706 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:13,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 267 states to 267 states and 282 transitions. [2023-11-21 22:06:13,709 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2023-11-21 22:06:13,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2023-11-21 22:06:13,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 267 states and 282 transitions. [2023-11-21 22:06:13,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:13,709 INFO L218 hiAutomatonCegarLoop]: Abstraction has 267 states and 282 transitions. [2023-11-21 22:06:13,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states and 282 transitions. [2023-11-21 22:06:13,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 256. [2023-11-21 22:06:13,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 256 states, 256 states have (on average 1.046875) internal successors, (268), 255 states have internal predecessors, (268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:13,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256 states to 256 states and 268 transitions. [2023-11-21 22:06:13,715 INFO L240 hiAutomatonCegarLoop]: Abstraction has 256 states and 268 transitions. [2023-11-21 22:06:13,716 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-21 22:06:13,716 INFO L428 stractBuchiCegarLoop]: Abstraction has 256 states and 268 transitions. [2023-11-21 22:06:13,716 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-21 22:06:13,717 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 256 states and 268 transitions. [2023-11-21 22:06:13,718 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:13,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:13,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:13,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [78, 77, 71, 6, 1, 1, 1] [2023-11-21 22:06:13,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:13,723 INFO L748 eck$LassoCheckResult]: Stem: 5951#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 5952#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 5953#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5967#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5963#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5958#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5957#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5949#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5945#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5946#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6198#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6197#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6194#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6193#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6192#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6191#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6190#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6189#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6188#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6187#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6186#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6185#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6184#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6183#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6182#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6181#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6180#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6179#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6178#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6177#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6176#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6175#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6174#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6173#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6172#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6171#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6170#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6169#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6168#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6167#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6166#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6165#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6164#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6163#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6162#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6161#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6160#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6159#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6158#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6157#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6156#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6155#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6154#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6153#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6152#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6151#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6150#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6149#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6148#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6146#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6145#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6144#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6143#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6142#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6141#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6140#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6139#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6138#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6137#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6136#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6135#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6134#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6133#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6132#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6131#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6130#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6129#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6128#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6127#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6126#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6125#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6124#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6123#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6122#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6121#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6120#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6119#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6118#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6117#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6116#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6115#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6114#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6113#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6112#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6111#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6110#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6109#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6108#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6107#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6106#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6105#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6104#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6103#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6102#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6101#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6100#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6099#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6098#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6097#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6096#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6095#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6094#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6093#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6092#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6090#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6091#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6089#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6088#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6087#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6086#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6085#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6084#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6083#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6082#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6081#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6080#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6079#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6078#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6077#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6076#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6075#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6074#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6073#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6072#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6071#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6070#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6069#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6068#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6067#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6066#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6065#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6064#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6063#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6062#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6061#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6060#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6059#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6058#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6057#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6056#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6055#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6054#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6053#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6052#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6051#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6050#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6049#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6048#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6047#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6046#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6045#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6044#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6043#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6042#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6041#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6040#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6039#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6038#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6036#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6037#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6035#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6034#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6033#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6032#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6031#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6030#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6029#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6028#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6027#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6026#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6025#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6024#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6023#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6022#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6021#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6020#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6019#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6018#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6017#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6016#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6015#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6014#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6013#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6012#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6011#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6010#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6009#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6008#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6007#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6006#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6005#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6004#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6003#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6002#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6001#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6000#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5999#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5998#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5997#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5996#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5995#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5994#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5993#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5992#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5991#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5990#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5989#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5988#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5987#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5985#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5986#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5984#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5983#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5982#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5981#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5980#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5975#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5974#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5978#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5969#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5968#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5964#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5961#L12-1 [2023-11-21 22:06:13,723 INFO L750 eck$LassoCheckResult]: Loop: 5961#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5962#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5961#L12-1 [2023-11-21 22:06:13,723 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:13,724 INFO L85 PathProgramCache]: Analyzing trace with hash -2031563884, now seen corresponding path program 4 times [2023-11-21 22:06:13,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:13,724 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762779383] [2023-11-21 22:06:13,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:13,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:13,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:14,156 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 154 proven. 6828 refuted. 0 times theorem prover too weak. 1950 trivial. 0 not checked. [2023-11-21 22:06:14,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:14,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762779383] [2023-11-21 22:06:14,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762779383] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:14,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1142969081] [2023-11-21 22:06:14,158 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-21 22:06:14,158 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:14,158 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:14,163 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:14,183 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2023-11-21 22:06:14,283 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-21 22:06:14,283 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:06:14,286 INFO L262 TraceCheckSpWp]: Trace formula consists of 489 conjuncts, 28 conjunts are in the unsatisfiable core [2023-11-21 22:06:14,291 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:15,108 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 914 proven. 6638 refuted. 0 times theorem prover too weak. 1380 trivial. 0 not checked. [2023-11-21 22:06:15,109 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:15,943 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 914 proven. 6638 refuted. 0 times theorem prover too weak. 1380 trivial. 0 not checked. [2023-11-21 22:06:15,944 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1142969081] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:15,944 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:15,944 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 28, 28] total 50 [2023-11-21 22:06:15,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120603373] [2023-11-21 22:06:15,945 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:15,945 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:06:15,946 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:15,946 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 8 times [2023-11-21 22:06:15,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:15,946 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209230470] [2023-11-21 22:06:15,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:15,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:15,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:15,949 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:15,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:15,950 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:15,970 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:15,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2023-11-21 22:06:15,972 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=683, Invalid=1767, Unknown=0, NotChecked=0, Total=2450 [2023-11-21 22:06:15,972 INFO L87 Difference]: Start difference. First operand 256 states and 268 transitions. cyclomatic complexity: 19 Second operand has 50 states, 50 states have (on average 3.18) internal successors, (159), 50 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:19,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:19,085 INFO L93 Difference]: Finished difference Result 1034 states and 1149 transitions. [2023-11-21 22:06:19,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1034 states and 1149 transitions. [2023-11-21 22:06:19,094 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:19,102 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1034 states to 986 states and 1101 transitions. [2023-11-21 22:06:19,102 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2023-11-21 22:06:19,103 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2023-11-21 22:06:19,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 986 states and 1101 transitions. [2023-11-21 22:06:19,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:19,103 INFO L218 hiAutomatonCegarLoop]: Abstraction has 986 states and 1101 transitions. [2023-11-21 22:06:19,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 986 states and 1101 transitions. [2023-11-21 22:06:19,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 986 to 693. [2023-11-21 22:06:19,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.1096681096681096) internal successors, (769), 692 states have internal predecessors, (769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:19,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 769 transitions. [2023-11-21 22:06:19,119 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 769 transitions. [2023-11-21 22:06:19,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 149 states. [2023-11-21 22:06:19,121 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 769 transitions. [2023-11-21 22:06:19,121 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-21 22:06:19,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 769 transitions. [2023-11-21 22:06:19,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:19,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:19,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:19,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 83, 11, 1, 1, 1] [2023-11-21 22:06:19,130 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:19,131 INFO L748 eck$LassoCheckResult]: Stem: 9118#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 9119#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 9120#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9124#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9115#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9116#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9122#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9123#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9110#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9111#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9527#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9526#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9525#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9524#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9523#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9522#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9521#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9520#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9518#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9517#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9516#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9515#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9514#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9513#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9512#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9511#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9510#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9509#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9508#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9507#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9506#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9505#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9504#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9503#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9502#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9501#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9500#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9499#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9498#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9497#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9496#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9495#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9494#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9493#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9492#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9491#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9490#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9489#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9488#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9487#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9486#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9485#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9484#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9483#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9482#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9481#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9480#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9479#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9478#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9475#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9476#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9474#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9473#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9472#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9471#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9470#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9469#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9468#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9467#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9466#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9465#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9464#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9463#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9462#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9461#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9460#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9459#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9458#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9457#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9456#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9455#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9454#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9453#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9452#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9451#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9450#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9449#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9448#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9447#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9446#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9445#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9444#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9443#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9442#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9441#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9440#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9439#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9438#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9437#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9436#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9435#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9434#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9433#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9432#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9431#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9430#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9429#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9428#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9427#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9426#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9425#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9424#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9423#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9422#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9421#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9420#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9419#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9418#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9416#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9415#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9414#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9413#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9412#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9411#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9410#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9409#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9408#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9407#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9406#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9405#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9404#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9403#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9402#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9401#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9400#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9399#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9398#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9397#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9396#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9395#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9394#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9393#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9392#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9391#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9390#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9389#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9388#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9387#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9386#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9385#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9384#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9383#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9382#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9381#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9380#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9379#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9378#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9377#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9376#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9375#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9374#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9373#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9372#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9371#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9370#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9369#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9368#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9367#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9366#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9365#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9364#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9363#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9361#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9360#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9359#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9358#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9357#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9356#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9355#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9354#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9353#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9352#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9351#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9350#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9349#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9348#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9347#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9346#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9345#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9344#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9343#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9342#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9341#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9340#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9338#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9336#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9334#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9332#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9330#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9328#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9326#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9324#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9322#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9320#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9318#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9316#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9314#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9312#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9310#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9308#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9306#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9283#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9284#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9302#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9300#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9298#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9277#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9275#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9276#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9271#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9272#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9287#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9264#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9263#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9262#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9261#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9260#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9227#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9224#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9218#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9215#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9213#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9209#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9207#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9206#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9188#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9187#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9186#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9185#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9182#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9183#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9184#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9174#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9173#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9172#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9171#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9168#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9166#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9167#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9169#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9161#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9160#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9159#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9158#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9157#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9154#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9155#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9156#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9149#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9148#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9147#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9146#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9145#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9144#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9136#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9143#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9141#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9139#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9138#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9137#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9135#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9134#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9132#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9131#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9130#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9125#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9126#L12-1 [2023-11-21 22:06:19,131 INFO L750 eck$LassoCheckResult]: Loop: 9126#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9129#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9126#L12-1 [2023-11-21 22:06:19,131 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:19,132 INFO L85 PathProgramCache]: Analyzing trace with hash 2005033964, now seen corresponding path program 5 times [2023-11-21 22:06:19,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:19,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2066748314] [2023-11-21 22:06:19,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:19,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:19,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:20,051 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 5787 proven. 5686 refuted. 0 times theorem prover too weak. 1828 trivial. 0 not checked. [2023-11-21 22:06:20,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:20,052 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2066748314] [2023-11-21 22:06:20,052 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2066748314] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:20,052 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [779549374] [2023-11-21 22:06:20,052 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-21 22:06:20,052 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:20,053 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:20,055 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:20,079 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2023-11-21 22:06:20,324 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 73 check-sat command(s) [2023-11-21 22:06:20,324 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:06:20,327 INFO L262 TraceCheckSpWp]: Trace formula consists of 455 conjuncts, 29 conjunts are in the unsatisfiable core [2023-11-21 22:06:20,334 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:20,933 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 7733 proven. 3749 refuted. 0 times theorem prover too weak. 1819 trivial. 0 not checked. [2023-11-21 22:06:20,933 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:21,499 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 7733 proven. 3749 refuted. 0 times theorem prover too weak. 1819 trivial. 0 not checked. [2023-11-21 22:06:21,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [779549374] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:21,499 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:21,500 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 29, 29] total 48 [2023-11-21 22:06:21,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1353775199] [2023-11-21 22:06:21,500 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:21,501 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:06:21,502 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:21,503 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 9 times [2023-11-21 22:06:21,503 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:21,503 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537006542] [2023-11-21 22:06:21,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:21,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:21,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:21,505 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:21,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:21,507 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:21,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:21,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2023-11-21 22:06:21,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=585, Invalid=1671, Unknown=0, NotChecked=0, Total=2256 [2023-11-21 22:06:21,525 INFO L87 Difference]: Start difference. First operand 693 states and 769 transitions. cyclomatic complexity: 82 Second operand has 48 states, 48 states have (on average 3.2291666666666665) internal successors, (155), 48 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:24,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:24,236 INFO L93 Difference]: Finished difference Result 1368 states and 1470 transitions. [2023-11-21 22:06:24,236 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1368 states and 1470 transitions. [2023-11-21 22:06:24,246 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:24,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1368 states to 1240 states and 1342 transitions. [2023-11-21 22:06:24,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2023-11-21 22:06:24,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2023-11-21 22:06:24,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1240 states and 1342 transitions. [2023-11-21 22:06:24,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:24,258 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1240 states and 1342 transitions. [2023-11-21 22:06:24,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1240 states and 1342 transitions. [2023-11-21 22:06:24,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1240 to 609. [2023-11-21 22:06:24,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 609 states, 609 states have (on average 1.083743842364532) internal successors, (660), 608 states have internal predecessors, (660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:24,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 609 states and 660 transitions. [2023-11-21 22:06:24,274 INFO L240 hiAutomatonCegarLoop]: Abstraction has 609 states and 660 transitions. [2023-11-21 22:06:24,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 135 states. [2023-11-21 22:06:24,275 INFO L428 stractBuchiCegarLoop]: Abstraction has 609 states and 660 transitions. [2023-11-21 22:06:24,276 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-21 22:06:24,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 609 states and 660 transitions. [2023-11-21 22:06:24,280 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:24,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:24,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:24,288 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [131, 130, 115, 15, 1, 1, 1] [2023-11-21 22:06:24,288 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:24,288 INFO L748 eck$LassoCheckResult]: Stem: 13190#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 13191#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 13192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13187#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13188#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13182#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13183#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13679#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13678#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13677#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13676#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13675#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13674#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13673#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13672#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13671#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13670#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13669#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13668#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13667#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13666#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13665#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13664#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13663#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13662#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13661#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13660#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13659#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13658#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13657#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13656#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13655#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13654#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13653#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13652#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13651#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13650#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13649#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13648#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13647#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13646#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13645#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13644#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13643#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13642#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13641#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13640#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13639#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13638#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13637#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13636#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13635#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13634#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13633#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13632#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13631#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13630#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13628#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13629#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13627#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13626#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13625#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13624#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13623#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13622#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13621#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13620#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13619#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13618#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13617#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13616#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13615#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13614#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13613#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13612#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13611#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13610#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13609#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13608#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13607#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13606#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13605#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13604#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13603#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13602#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13601#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13600#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13599#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13598#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13597#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13596#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13595#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13594#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13593#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13592#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13591#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13590#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13589#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13588#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13587#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13586#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13585#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13584#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13583#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13582#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13581#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13580#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13579#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13578#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13577#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13576#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13575#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13574#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13573#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13571#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13572#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13570#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13569#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13568#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13567#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13566#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13565#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13564#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13563#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13562#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13561#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13560#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13559#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13558#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13557#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13556#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13555#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13554#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13553#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13552#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13551#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13550#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13549#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13548#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13547#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13546#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13545#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13544#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13543#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13542#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13541#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13540#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13539#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13538#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13537#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13536#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13535#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13534#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13533#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13532#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13531#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13530#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13529#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13528#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13527#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13526#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13525#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13524#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13523#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13522#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13521#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13520#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13519#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13518#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13517#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13515#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13514#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13513#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13512#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13511#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13510#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13509#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13508#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13507#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13506#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13505#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13504#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13503#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13502#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13501#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13500#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13499#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13498#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13497#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13496#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13495#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13493#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13491#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13489#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13487#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13485#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13483#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13481#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13479#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13477#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13475#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13473#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13471#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13469#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13467#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13465#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13462#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13459#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13456#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13453#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13450#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13447#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13444#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13441#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13438#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13435#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13432#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13429#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13426#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13370#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13424#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13417#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13416#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13415#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13414#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13413#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13412#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13411#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13410#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13409#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13408#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13407#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13406#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13405#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13404#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13403#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13402#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13401#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13400#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13398#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13396#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13394#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13392#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13390#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13388#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13386#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13384#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13382#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13380#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13378#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13376#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13374#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13340#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13371#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13372#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13368#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13367#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13366#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13365#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13364#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13363#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13362#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13361#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13360#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13351#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13350#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13348#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13347#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13346#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13345#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13343#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13341#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13342#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13338#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13337#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13336#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13335#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13334#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13333#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13332#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13331#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13330#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13329#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13328#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13322#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13321#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13319#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13317#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13316#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13314#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13315#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13311#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13310#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13309#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13308#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13307#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13306#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13305#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13304#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13303#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13302#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13301#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13300#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13299#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13298#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13293#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13292#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13290#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13291#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13287#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13286#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13285#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13284#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13283#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13282#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13281#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13280#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13279#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13278#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13277#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13276#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13275#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13274#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13272#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13271#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13269#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13270#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13266#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13265#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13264#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13263#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13262#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13261#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13260#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13259#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13258#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13257#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13256#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13255#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13254#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13253#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13252#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13235#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13251#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13249#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13248#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13247#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13246#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13245#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13244#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13243#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13242#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13241#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13240#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13239#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13238#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13237#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13223#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13236#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13234#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13232#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13231#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13230#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13229#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13228#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13227#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13226#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13225#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13214#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13224#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13222#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13220#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13219#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13218#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13217#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13216#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13209#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13215#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13213#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13211#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13210#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13206#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13207#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13204#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13203#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13202#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13197#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13198#L12-1 [2023-11-21 22:06:24,289 INFO L750 eck$LassoCheckResult]: Loop: 13198#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13201#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13198#L12-1 [2023-11-21 22:06:24,289 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:24,290 INFO L85 PathProgramCache]: Analyzing trace with hash -1703910940, now seen corresponding path program 6 times [2023-11-21 22:06:24,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:24,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906319851] [2023-11-21 22:06:24,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:24,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:24,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:25,657 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 12928 proven. 8663 refuted. 0 times theorem prover too weak. 3824 trivial. 0 not checked. [2023-11-21 22:06:25,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:25,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1906319851] [2023-11-21 22:06:25,657 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1906319851] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:25,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1660119737] [2023-11-21 22:06:25,658 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-21 22:06:25,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:25,658 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:25,664 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:25,687 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2023-11-21 22:06:25,918 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 81 check-sat command(s) [2023-11-21 22:06:25,919 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:06:25,921 INFO L262 TraceCheckSpWp]: Trace formula consists of 521 conjuncts, 15 conjunts are in the unsatisfiable core [2023-11-21 22:06:25,927 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:26,266 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 8831 proven. 411 refuted. 0 times theorem prover too weak. 16173 trivial. 0 not checked. [2023-11-21 22:06:26,266 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:26,624 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 8831 proven. 411 refuted. 0 times theorem prover too weak. 16173 trivial. 0 not checked. [2023-11-21 22:06:26,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1660119737] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:26,624 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:26,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 14, 14] total 37 [2023-11-21 22:06:26,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061714518] [2023-11-21 22:06:26,625 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:26,626 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:06:26,627 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:26,627 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 10 times [2023-11-21 22:06:26,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:26,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411226704] [2023-11-21 22:06:26,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:26,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:26,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:26,630 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:26,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:26,632 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:26,645 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:26,646 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2023-11-21 22:06:26,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=1140, Unknown=0, NotChecked=0, Total=1332 [2023-11-21 22:06:26,647 INFO L87 Difference]: Start difference. First operand 609 states and 660 transitions. cyclomatic complexity: 57 Second operand has 37 states, 37 states have (on average 3.324324324324324) internal successors, (123), 37 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:28,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:28,785 INFO L93 Difference]: Finished difference Result 811 states and 861 transitions. [2023-11-21 22:06:28,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 811 states and 861 transitions. [2023-11-21 22:06:28,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:28,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 811 states to 765 states and 813 transitions. [2023-11-21 22:06:28,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2023-11-21 22:06:28,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68 [2023-11-21 22:06:28,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 765 states and 813 transitions. [2023-11-21 22:06:28,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:28,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 765 states and 813 transitions. [2023-11-21 22:06:28,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 765 states and 813 transitions. [2023-11-21 22:06:28,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 765 to 589. [2023-11-21 22:06:28,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 589 states, 589 states have (on average 1.0475382003395586) internal successors, (617), 588 states have internal predecessors, (617), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:28,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 589 states to 589 states and 617 transitions. [2023-11-21 22:06:28,810 INFO L240 hiAutomatonCegarLoop]: Abstraction has 589 states and 617 transitions. [2023-11-21 22:06:28,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2023-11-21 22:06:28,811 INFO L428 stractBuchiCegarLoop]: Abstraction has 589 states and 617 transitions. [2023-11-21 22:06:28,811 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-21 22:06:28,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 589 states and 617 transitions. [2023-11-21 22:06:28,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:28,815 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:28,815 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:28,823 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [140, 140, 125, 15, 1, 1] [2023-11-21 22:06:28,823 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:28,824 INFO L748 eck$LassoCheckResult]: Stem: 17183#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 17184#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 17185#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17326#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17324#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17322#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17320#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17317#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17175#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17615#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17614#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17613#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17612#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17611#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17610#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17609#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17608#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17607#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17606#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17605#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17604#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17603#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17602#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17601#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17600#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17599#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17598#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17597#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17596#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17595#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17594#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17593#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17592#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17591#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17590#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17589#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17588#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17587#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17586#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17585#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17584#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17583#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17582#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17581#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17580#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17579#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17578#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17577#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17576#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17575#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17574#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17573#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17572#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17571#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17570#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17569#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17568#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17567#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17566#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17564#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17565#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17563#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17562#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17561#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17560#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17559#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17558#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17557#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17556#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17555#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17554#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17553#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17552#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17551#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17550#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17549#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17548#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17547#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17546#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17545#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17544#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17543#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17542#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17541#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17540#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17539#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17538#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17537#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17536#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17535#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17534#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17533#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17532#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17531#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17530#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17529#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17528#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17527#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17526#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17525#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17524#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17523#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17522#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17521#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17520#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17519#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17518#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17517#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17516#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17515#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17514#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17513#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17512#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17511#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17510#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17509#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17507#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17508#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17506#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17505#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17504#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17503#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17502#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17501#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17500#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17499#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17498#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17497#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17496#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17495#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17494#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17493#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17492#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17491#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17490#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17489#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17488#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17487#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17486#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17485#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17484#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17483#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17482#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17481#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17480#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17479#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17478#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17477#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17476#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17475#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17474#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17473#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17472#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17471#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17470#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17469#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17468#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17467#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17466#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17465#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17464#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17463#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17462#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17461#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17460#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17459#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17458#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17457#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17456#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17455#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17454#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17453#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17452#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17451#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17450#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17449#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17448#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17447#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17446#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17445#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17444#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17443#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17442#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17441#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17440#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17439#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17438#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17437#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17436#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17435#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17434#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17433#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17432#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17431#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17430#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17429#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17428#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17427#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17426#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17425#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17424#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17423#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17422#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17421#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17420#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17419#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17418#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17417#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17416#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17415#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17414#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17413#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17412#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17411#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17410#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17409#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17408#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17407#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17406#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17405#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17404#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17402#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17401#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17392#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17391#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17390#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17389#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17388#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17387#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17386#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17385#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17384#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17383#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17382#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17381#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17380#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17379#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17378#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17377#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17376#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17375#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17374#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17373#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17372#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17371#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17370#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17369#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17368#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17367#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17366#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17365#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17364#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17363#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17314#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17282#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17313#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17311#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17310#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17309#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17308#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17307#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17306#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17305#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17304#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17303#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17302#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17301#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17300#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17299#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17298#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17297#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17296#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17295#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17294#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17293#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17292#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17291#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17290#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17289#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17288#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17287#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17286#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17285#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17284#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17255#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17283#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17281#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17280#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17279#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17278#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17277#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17276#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17275#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17274#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17273#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17272#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17271#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17270#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17269#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17268#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17267#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17266#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17265#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17264#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17263#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17262#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17261#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17260#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17259#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17258#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17257#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17231#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17256#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17254#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17253#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17252#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17251#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17250#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17249#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17248#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17247#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17246#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17245#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17244#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17243#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17242#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17241#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17240#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17239#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17238#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17237#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17236#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17235#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17234#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17233#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17210#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17230#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17229#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17228#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17227#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17226#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17225#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17224#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17223#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17222#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17221#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17220#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17219#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17218#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17217#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17216#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17215#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17214#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17213#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17212#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17209#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17207#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17206#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17205#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17204#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17203#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17202#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17201#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17200#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17199#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17198#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17197#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17194#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17193#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17192#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17190#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17180#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17181#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17189#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17362#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17361#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17360#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17359#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17358#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17357#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17356#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17355#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17354#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17353#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17352#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17351#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17350#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17349#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17348#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17347#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17346#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17345#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17344#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17343#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17342#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17341#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17340#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17339#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17338#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17337#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17336#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17335#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17334#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17333#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17332#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17331#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17330#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17329#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17327#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17325#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17323#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17321#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17319#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17315#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17316#L12-1 [2023-11-21 22:06:28,824 INFO L750 eck$LassoCheckResult]: Loop: 17316#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17318#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17316#L12-1 [2023-11-21 22:06:28,825 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:28,825 INFO L85 PathProgramCache]: Analyzing trace with hash -1848898559, now seen corresponding path program 9 times [2023-11-21 22:06:28,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:28,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384737682] [2023-11-21 22:06:28,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:28,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:28,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:29,827 INFO L134 CoverageAnalysis]: Checked inductivity of 29190 backedges. 13932 proven. 9015 refuted. 0 times theorem prover too weak. 6243 trivial. 0 not checked. [2023-11-21 22:06:29,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:29,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384737682] [2023-11-21 22:06:29,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1384737682] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:29,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1110137389] [2023-11-21 22:06:29,827 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-21 22:06:29,828 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:29,828 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:29,831 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:29,859 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2023-11-21 22:06:30,323 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 117 check-sat command(s) [2023-11-21 22:06:30,323 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:06:30,328 INFO L262 TraceCheckSpWp]: Trace formula consists of 746 conjuncts, 27 conjunts are in the unsatisfiable core [2023-11-21 22:06:30,334 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:31,207 INFO L134 CoverageAnalysis]: Checked inductivity of 29190 backedges. 14745 proven. 8053 refuted. 0 times theorem prover too weak. 6392 trivial. 0 not checked. [2023-11-21 22:06:31,208 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:32,068 INFO L134 CoverageAnalysis]: Checked inductivity of 29190 backedges. 14745 proven. 8053 refuted. 0 times theorem prover too weak. 6392 trivial. 0 not checked. [2023-11-21 22:06:32,068 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1110137389] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:32,068 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:32,069 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 25, 25] total 44 [2023-11-21 22:06:32,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999091790] [2023-11-21 22:06:32,069 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:32,070 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:06:32,070 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:32,071 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 11 times [2023-11-21 22:06:32,071 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:32,071 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266879618] [2023-11-21 22:06:32,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:32,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:32,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:32,074 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:32,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:32,076 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:32,099 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:32,099 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2023-11-21 22:06:32,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=336, Invalid=1556, Unknown=0, NotChecked=0, Total=1892 [2023-11-21 22:06:32,103 INFO L87 Difference]: Start difference. First operand 589 states and 617 transitions. cyclomatic complexity: 34 Second operand has 44 states, 44 states have (on average 3.4318181818181817) internal successors, (151), 44 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:37,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:06:37,446 INFO L93 Difference]: Finished difference Result 1054 states and 1109 transitions. [2023-11-21 22:06:37,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1054 states and 1109 transitions. [2023-11-21 22:06:37,453 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:37,460 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1054 states to 1011 states and 1066 transitions. [2023-11-21 22:06:37,460 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67 [2023-11-21 22:06:37,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67 [2023-11-21 22:06:37,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1011 states and 1066 transitions. [2023-11-21 22:06:37,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:06:37,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1011 states and 1066 transitions. [2023-11-21 22:06:37,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1011 states and 1066 transitions. [2023-11-21 22:06:37,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1011 to 760. [2023-11-21 22:06:37,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 760 states, 760 states have (on average 1.0460526315789473) internal successors, (795), 759 states have internal predecessors, (795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:06:37,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 760 states to 760 states and 795 transitions. [2023-11-21 22:06:37,476 INFO L240 hiAutomatonCegarLoop]: Abstraction has 760 states and 795 transitions. [2023-11-21 22:06:37,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 177 states. [2023-11-21 22:06:37,477 INFO L428 stractBuchiCegarLoop]: Abstraction has 760 states and 795 transitions. [2023-11-21 22:06:37,478 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-21 22:06:37,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 760 states and 795 transitions. [2023-11-21 22:06:37,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-21 22:06:37,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:06:37,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:06:37,493 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [161, 161, 144, 17, 1, 1] [2023-11-21 22:06:37,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:06:37,495 INFO L748 eck$LassoCheckResult]: Stem: 21741#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 21742#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 21743#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21777#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21776#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21775#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21773#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21770#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21733#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21734#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22393#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22392#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22391#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22390#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22389#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22388#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22387#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22386#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22385#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22384#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22383#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22382#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22381#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22380#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22379#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22378#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22377#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22376#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22375#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22374#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22373#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22372#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22371#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22370#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22369#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22368#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22367#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22366#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22365#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22364#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22363#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22362#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22361#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22360#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22359#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22358#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22357#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22356#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22355#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22354#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22353#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22352#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22351#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22350#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22349#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22348#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22347#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22346#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22345#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22344#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22342#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22343#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22341#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22340#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22339#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22338#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22337#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22336#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22335#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22334#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22333#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22332#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22331#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22330#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22329#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22328#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22327#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22326#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22325#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22324#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22323#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22322#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22321#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22320#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22319#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22318#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22317#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22316#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22315#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22314#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22313#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22312#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22311#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22310#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22309#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22308#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22307#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22306#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22305#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22304#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22303#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22302#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22301#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22300#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22299#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22298#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22297#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22296#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22295#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22294#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22293#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22292#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22291#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22290#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22289#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22288#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22287#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22285#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22286#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22284#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22283#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22282#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22281#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22280#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22279#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22278#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22277#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22276#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22275#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22274#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22273#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22272#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22271#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22270#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22269#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22268#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22267#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22266#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22265#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22264#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22263#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22262#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22261#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22260#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22259#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22258#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22257#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22256#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22255#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22254#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22253#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22252#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22251#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22250#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22249#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22248#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22247#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22246#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22245#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22244#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22243#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22242#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22241#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22240#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22239#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22238#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22237#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22236#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22235#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22234#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22233#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22231#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22230#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22229#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22228#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22227#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22226#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22225#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22224#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22223#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22222#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22221#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22220#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22219#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22218#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22217#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22216#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22215#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22214#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22213#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22212#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22211#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22210#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22209#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22207#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22206#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22205#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22204#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22203#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22202#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22201#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22200#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22199#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22198#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22197#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22194#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22193#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22192#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22191#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22190#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22189#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22188#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22187#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22186#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22185#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22184#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22183#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22179#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22177#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22178#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22174#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22173#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22172#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22171#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22170#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22169#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22168#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22167#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22166#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22165#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22164#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22163#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22162#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22161#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22160#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22159#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22158#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22157#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22156#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22155#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22154#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22153#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22152#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22151#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22150#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22149#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22148#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22146#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22145#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22144#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22142#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22138#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22136#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22134#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22132#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22130#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22128#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22126#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22125#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22123#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22124#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21996#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21995#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21994#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21993#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21992#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21991#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21990#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21989#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21988#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21987#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21986#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21985#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21984#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21983#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21982#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21981#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21980#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21979#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21978#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21977#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21976#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21975#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21974#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21973#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21972#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21971#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21970#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21969#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21968#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21967#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21966#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21965#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21963#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21962#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21961#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21960#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21959#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21958#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21957#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21956#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21955#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21954#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21953#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21952#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21951#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21950#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21949#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21948#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21947#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21946#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21945#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21944#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21943#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21942#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21941#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21940#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21939#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21938#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21937#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21936#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21935#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21934#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21932#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21931#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21930#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21929#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21928#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21927#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21926#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21925#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21924#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21923#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21922#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21921#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21920#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21919#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21918#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21917#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21916#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21915#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21914#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21913#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21912#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21911#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21910#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21909#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21908#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21907#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21906#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21905#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21904#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21903#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21902#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21901#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21900#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21899#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21898#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21897#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21896#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21895#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21894#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21893#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21892#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21891#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21890#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21889#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21888#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21887#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21886#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21885#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21882#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21880#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21878#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21876#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21874#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21872#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21870#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21868#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21866#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21864#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21862#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21860#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21858#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21856#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21854#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21852#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21850#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21848#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21846#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21844#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21842#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21841#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21840#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21839#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21838#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21833#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21832#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21831#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21830#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21829#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21828#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21827#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21826#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21825#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21824#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21823#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21822#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21821#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21820#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21819#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21818#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21817#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21816#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21748#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21815#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21766#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21765#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21764#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21763#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21762#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21761#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21760#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21759#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21758#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21757#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21756#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21755#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21754#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21753#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21752#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21751#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21750#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21749#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21747#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21745#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21738#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21739#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21746#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21814#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21813#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21812#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21811#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21810#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21809#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21808#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21807#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21806#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21805#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21804#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21803#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21802#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21801#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21800#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21799#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21798#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21797#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21796#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21795#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21794#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21793#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21792#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21791#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21790#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21789#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21788#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21787#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21786#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21785#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21784#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21783#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21782#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21781#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21780#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21779#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21778#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21774#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21772#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21768#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21769#L12-1 [2023-11-21 22:06:37,495 INFO L750 eck$LassoCheckResult]: Loop: 21769#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21771#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21769#L12-1 [2023-11-21 22:06:37,496 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:37,496 INFO L85 PathProgramCache]: Analyzing trace with hash 2044987687, now seen corresponding path program 10 times [2023-11-21 22:06:37,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:37,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011461252] [2023-11-21 22:06:37,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:37,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:37,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:06:38,744 INFO L134 CoverageAnalysis]: Checked inductivity of 38640 backedges. 18300 proven. 12627 refuted. 0 times theorem prover too weak. 7713 trivial. 0 not checked. [2023-11-21 22:06:38,745 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:06:38,745 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1011461252] [2023-11-21 22:06:38,745 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1011461252] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:06:38,745 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [144742914] [2023-11-21 22:06:38,745 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-21 22:06:38,746 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:06:38,746 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:06:38,748 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:06:38,771 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9d498c86-7e44-401f-94a6-515a18cab9ce/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2023-11-21 22:06:38,939 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-21 22:06:38,939 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:06:38,943 INFO L262 TraceCheckSpWp]: Trace formula consists of 1020 conjuncts, 40 conjunts are in the unsatisfiable core [2023-11-21 22:06:38,950 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:06:40,082 INFO L134 CoverageAnalysis]: Checked inductivity of 38640 backedges. 20020 proven. 9572 refuted. 0 times theorem prover too weak. 9048 trivial. 0 not checked. [2023-11-21 22:06:40,082 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:06:41,054 INFO L134 CoverageAnalysis]: Checked inductivity of 38640 backedges. 20020 proven. 9572 refuted. 0 times theorem prover too weak. 9048 trivial. 0 not checked. [2023-11-21 22:06:41,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [144742914] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:06:41,054 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:06:41,055 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 40, 40] total 57 [2023-11-21 22:06:41,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096624113] [2023-11-21 22:06:41,056 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:06:41,057 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:06:41,057 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:06:41,058 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 12 times [2023-11-21 22:06:41,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:06:41,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674789043] [2023-11-21 22:06:41,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:06:41,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:06:41,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:41,061 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:06:41,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:06:41,063 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:06:41,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:06:41,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2023-11-21 22:06:41,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=650, Invalid=2542, Unknown=0, NotChecked=0, Total=3192 [2023-11-21 22:06:41,094 INFO L87 Difference]: Start difference. First operand 760 states and 795 transitions. cyclomatic complexity: 42 Second operand has 57 states, 57 states have (on average 3.192982456140351) internal successors, (182), 57 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)