./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 527bcce2 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.2.3-dev-527bcce [2023-11-21 22:08:44,239 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-21 22:08:44,319 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-21 22:08:44,324 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-21 22:08:44,325 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-21 22:08:44,353 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-21 22:08:44,354 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-21 22:08:44,355 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-21 22:08:44,356 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-21 22:08:44,356 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-21 22:08:44,357 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-21 22:08:44,358 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-21 22:08:44,358 INFO L153 SettingsManager]: * Use SBE=true [2023-11-21 22:08:44,359 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-21 22:08:44,359 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-21 22:08:44,360 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-21 22:08:44,361 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-21 22:08:44,361 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-21 22:08:44,362 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-21 22:08:44,362 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-21 22:08:44,363 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-21 22:08:44,363 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-21 22:08:44,364 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-21 22:08:44,364 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-21 22:08:44,365 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-21 22:08:44,365 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-21 22:08:44,366 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-21 22:08:44,366 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-21 22:08:44,367 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-21 22:08:44,367 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-21 22:08:44,367 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-21 22:08:44,368 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-21 22:08:44,368 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-21 22:08:44,369 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-21 22:08:44,369 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-21 22:08:44,370 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-21 22:08:44,370 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-21 22:08:44,371 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-21 22:08:44,371 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2023-11-21 22:08:44,655 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-21 22:08:44,687 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-21 22:08:44,689 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-21 22:08:44,691 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-21 22:08:44,691 INFO L274 PluginConnector]: CDTParser initialized [2023-11-21 22:08:44,693 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2023-11-21 22:08:47,856 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-21 22:08:48,110 INFO L384 CDTParser]: Found 1 translation units. [2023-11-21 22:08:48,111 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2023-11-21 22:08:48,117 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/data/23724b406/ef3c9e840618436b884b4ae52b2992eb/FLAG9c2ccf49b [2023-11-21 22:08:48,135 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/data/23724b406/ef3c9e840618436b884b4ae52b2992eb [2023-11-21 22:08:48,145 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-21 22:08:48,148 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-21 22:08:48,151 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-21 22:08:48,151 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-21 22:08:48,156 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-21 22:08:48,157 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,158 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@14530fac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48, skipping insertion in model container [2023-11-21 22:08:48,158 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,178 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-21 22:08:48,321 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 22:08:48,332 INFO L202 MainTranslator]: Completed pre-run [2023-11-21 22:08:48,351 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 22:08:48,364 INFO L206 MainTranslator]: Completed translation [2023-11-21 22:08:48,365 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48 WrapperNode [2023-11-21 22:08:48,365 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-21 22:08:48,365 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-21 22:08:48,366 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-21 22:08:48,366 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-21 22:08:48,372 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,379 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,405 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 80 [2023-11-21 22:08:48,405 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-21 22:08:48,406 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-21 22:08:48,406 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-21 22:08:48,406 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-21 22:08:48,417 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,417 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,419 INFO L184 PluginConnector]: Executing the observer HeapSplitter from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,431 INFO L187 HeapSplitter]: Split 7 memory accesses to 2 slices as follows [2, 5] [2023-11-21 22:08:48,438 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,440 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,452 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,456 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,458 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,459 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,465 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-21 22:08:48,466 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-21 22:08:48,466 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-21 22:08:48,466 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-21 22:08:48,467 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (1/1) ... [2023-11-21 22:08:48,483 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:48,499 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:48,520 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:48,552 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-21 22:08:48,576 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-21 22:08:48,577 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-21 22:08:48,577 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2023-11-21 22:08:48,577 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2023-11-21 22:08:48,577 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2023-11-21 22:08:48,577 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2023-11-21 22:08:48,578 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-21 22:08:48,578 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-21 22:08:48,578 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2023-11-21 22:08:48,578 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2023-11-21 22:08:48,578 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2023-11-21 22:08:48,710 INFO L240 CfgBuilder]: Building ICFG [2023-11-21 22:08:48,713 INFO L266 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-21 22:08:48,936 INFO L281 CfgBuilder]: Performing block encoding [2023-11-21 22:08:48,946 INFO L303 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-21 22:08:48,946 INFO L308 CfgBuilder]: Removed 3 assume(true) statements. [2023-11-21 22:08:48,948 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:08:48 BoogieIcfgContainer [2023-11-21 22:08:48,948 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-21 22:08:48,950 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-21 22:08:48,950 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-21 22:08:48,954 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-21 22:08:48,955 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:08:48,955 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.11 10:08:48" (1/3) ... [2023-11-21 22:08:48,956 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2afb5461 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 10:08:48, skipping insertion in model container [2023-11-21 22:08:48,956 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:08:48,956 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:08:48" (2/3) ... [2023-11-21 22:08:48,957 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2afb5461 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 10:08:48, skipping insertion in model container [2023-11-21 22:08:48,957 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:08:48,957 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:08:48" (3/3) ... [2023-11-21 22:08:48,958 INFO L332 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2023-11-21 22:08:49,015 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-21 22:08:49,015 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-21 22:08:49,016 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-21 22:08:49,016 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-21 22:08:49,016 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-21 22:08:49,016 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-21 22:08:49,016 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-21 22:08:49,016 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-21 22:08:49,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:49,041 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2023-11-21 22:08:49,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:49,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:49,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-21 22:08:49,047 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:08:49,047 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-21 22:08:49,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:49,050 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2023-11-21 22:08:49,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:49,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:49,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-21 22:08:49,051 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-21 22:08:49,057 INFO L748 eck$LassoCheckResult]: Stem: 27#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 28#L27-3true [2023-11-21 22:08:49,057 INFO L750 eck$LassoCheckResult]: Loop: 28#L27-3true assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5#L27-2true main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28#L27-3true [2023-11-21 22:08:49,062 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:49,062 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2023-11-21 22:08:49,071 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:49,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993011578] [2023-11-21 22:08:49,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:49,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:49,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:49,161 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:49,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:49,190 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:49,194 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:49,194 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2023-11-21 22:08:49,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:49,194 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634284002] [2023-11-21 22:08:49,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:49,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:49,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:49,207 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:49,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:49,217 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:49,219 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:49,219 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2023-11-21 22:08:49,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:49,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741004008] [2023-11-21 22:08:49,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:49,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:49,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:49,265 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:49,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:49,294 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:49,732 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:08:49,732 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:08:49,733 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:08:49,733 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:08:49,733 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-21 22:08:49,733 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:49,733 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:08:49,733 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:08:49,734 INFO L133 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2023-11-21 22:08:49,740 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:08:49,740 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:08:49,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:49,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:49,816 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:49,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:49,837 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:49,840 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:49,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:50,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:50,007 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:50,010 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:50,012 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:50,015 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:08:50,227 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:08:50,232 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-21 22:08:50,233 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:50,234 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:50,236 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:50,245 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:08:50,258 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:08:50,258 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:08:50,259 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:08:50,259 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:08:50,259 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:08:50,261 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:08:50,262 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:08:50,263 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-21 22:08:50,276 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:08:50,301 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-21 22:08:50,301 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:50,302 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:50,304 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:50,317 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:08:50,330 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:08:50,330 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:08:50,330 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:08:50,331 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:08:50,331 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:08:50,332 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-21 22:08:50,333 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:08:50,333 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:08:50,342 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:08:50,365 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-21 22:08:50,365 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:50,366 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:50,367 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:50,370 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:08:50,382 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:08:50,382 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:08:50,382 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:08:50,383 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:08:50,386 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-21 22:08:50,386 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-21 22:08:50,387 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-21 22:08:50,399 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:08:50,421 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-21 22:08:50,422 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:50,422 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:50,424 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:50,432 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:08:50,445 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:08:50,445 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:08:50,445 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:08:50,445 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:08:50,447 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-21 22:08:50,450 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-21 22:08:50,450 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-21 22:08:50,461 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:08:50,485 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-21 22:08:50,486 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:50,486 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:50,488 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:50,491 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-21 22:08:50,492 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:08:50,504 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:08:50,505 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:08:50,505 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:08:50,505 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:08:50,505 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:08:50,506 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:08:50,506 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:08:50,511 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:08:50,534 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-21 22:08:50,535 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:50,535 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:50,537 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:50,539 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-21 22:08:50,540 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:08:50,552 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:08:50,552 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:08:50,552 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:08:50,552 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:08:50,552 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:08:50,554 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:08:50,555 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:08:50,572 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:08:50,595 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-21 22:08:50,596 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:50,596 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:50,597 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:50,610 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:08:50,622 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:08:50,622 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:08:50,622 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:08:50,622 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:08:50,623 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:08:50,623 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:08:50,624 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:08:50,626 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-21 22:08:50,633 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:08:50,656 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-21 22:08:50,656 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:50,656 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:50,658 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:50,665 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:08:50,677 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:08:50,678 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:08:50,678 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:08:50,678 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:08:50,680 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-21 22:08:50,682 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-21 22:08:50,682 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-21 22:08:50,697 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:08:50,721 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-21 22:08:50,721 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:50,722 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:50,723 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:50,733 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:08:50,746 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:08:50,746 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:08:50,746 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:08:50,746 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:08:50,751 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-21 22:08:50,762 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-21 22:08:50,762 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-21 22:08:50,784 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-21 22:08:50,824 INFO L443 ModelExtractionUtils]: Simplification made 10 calls to the SMT solver. [2023-11-21 22:08:50,825 INFO L444 ModelExtractionUtils]: 2 out of 16 variables were initially zero. Simplification set additionally 11 variables to zero. [2023-11-21 22:08:50,826 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:08:50,826 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:50,853 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:08:50,855 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-21 22:08:50,856 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-21 22:08:50,876 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2023-11-21 22:08:50,876 INFO L513 LassoAnalysis]: Proved termination. [2023-11-21 22:08:50,876 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~num~0#1) = -1*ULTIMATE.start_main_~i~0#1 + 1*ULTIMATE.start_main_~num~0#1 Supporting invariants [] [2023-11-21 22:08:50,890 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-21 22:08:50,906 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2023-11-21 22:08:50,929 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:50,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:50,946 INFO L262 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-21 22:08:50,947 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:08:50,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:50,965 INFO L262 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-21 22:08:50,966 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:08:50,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:51,024 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-21 22:08:51,026 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:51,094 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 55 states and 79 transitions. Complement of second has 8 states. [2023-11-21 22:08:51,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2023-11-21 22:08:51,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:51,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 39 transitions. [2023-11-21 22:08:51,102 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 39 transitions. Stem has 2 letters. Loop has 2 letters. [2023-11-21 22:08:51,103 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:08:51,103 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 39 transitions. Stem has 4 letters. Loop has 2 letters. [2023-11-21 22:08:51,103 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:08:51,103 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 39 transitions. Stem has 2 letters. Loop has 4 letters. [2023-11-21 22:08:51,103 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:08:51,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 79 transitions. [2023-11-21 22:08:51,108 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2023-11-21 22:08:51,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 25 states and 35 transitions. [2023-11-21 22:08:51,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2023-11-21 22:08:51,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2023-11-21 22:08:51,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 35 transitions. [2023-11-21 22:08:51,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:08:51,115 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2023-11-21 22:08:51,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 35 transitions. [2023-11-21 22:08:51,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2023-11-21 22:08:51,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.4) internal successors, (35), 24 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:51,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 35 transitions. [2023-11-21 22:08:51,144 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2023-11-21 22:08:51,145 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 35 transitions. [2023-11-21 22:08:51,145 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-21 22:08:51,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 35 transitions. [2023-11-21 22:08:51,147 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2023-11-21 22:08:51,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:51,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:51,148 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2023-11-21 22:08:51,148 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:08:51,151 INFO L748 eck$LassoCheckResult]: Stem: 161#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 149#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 150#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 153#L27-4 main_~i~0#1 := 0; 154#L32-3 [2023-11-21 22:08:51,152 INFO L750 eck$LassoCheckResult]: Loop: 154#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 159#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 148#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 154#L32-3 [2023-11-21 22:08:51,157 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:51,158 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2023-11-21 22:08:51,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:51,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411629758] [2023-11-21 22:08:51,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:51,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:51,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:51,180 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:51,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:51,202 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:51,204 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:51,204 INFO L85 PathProgramCache]: Analyzing trace with hash 54361, now seen corresponding path program 1 times [2023-11-21 22:08:51,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:51,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098898724] [2023-11-21 22:08:51,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:51,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:51,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:51,228 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:51,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:51,241 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:51,242 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:51,243 INFO L85 PathProgramCache]: Analyzing trace with hash 1807958031, now seen corresponding path program 1 times [2023-11-21 22:08:51,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:51,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738298026] [2023-11-21 22:08:51,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:51,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:51,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:51,355 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-21 22:08:51,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:51,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:08:51,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738298026] [2023-11-21 22:08:51,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [738298026] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:08:51,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:08:51,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:08:51,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275317751] [2023-11-21 22:08:51,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:08:51,558 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:08:51,560 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:08:51,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:08:51,562 INFO L87 Difference]: Start difference. First operand 25 states and 35 transitions. cyclomatic complexity: 13 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:51,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:08:51,627 INFO L93 Difference]: Finished difference Result 44 states and 51 transitions. [2023-11-21 22:08:51,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 51 transitions. [2023-11-21 22:08:51,630 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:51,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 32 states and 38 transitions. [2023-11-21 22:08:51,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2023-11-21 22:08:51,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2023-11-21 22:08:51,632 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2023-11-21 22:08:51,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:08:51,632 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 38 transitions. [2023-11-21 22:08:51,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2023-11-21 22:08:51,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 20. [2023-11-21 22:08:51,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.2) internal successors, (24), 19 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:51,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2023-11-21 22:08:51,636 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 24 transitions. [2023-11-21 22:08:51,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 22:08:51,637 INFO L428 stractBuchiCegarLoop]: Abstraction has 20 states and 24 transitions. [2023-11-21 22:08:51,637 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-21 22:08:51,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 24 transitions. [2023-11-21 22:08:51,638 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:51,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:51,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:51,639 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:08:51,639 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:08:51,640 INFO L748 eck$LassoCheckResult]: Stem: 235#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 224#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 227#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 228#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 229#L27-4 main_~i~0#1 := 0; 230#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 234#L34 [2023-11-21 22:08:51,640 INFO L750 eck$LassoCheckResult]: Loop: 234#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 222#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 231#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 234#L34 [2023-11-21 22:08:51,640 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:51,641 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669547, now seen corresponding path program 1 times [2023-11-21 22:08:51,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:51,641 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186510027] [2023-11-21 22:08:51,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:51,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:51,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:51,657 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:51,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:51,681 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:51,682 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:51,682 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 2 times [2023-11-21 22:08:51,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:51,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469765073] [2023-11-21 22:08:51,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:51,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:51,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:51,696 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:51,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:51,711 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:51,712 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:51,712 INFO L85 PathProgramCache]: Analyzing trace with hash 1436021995, now seen corresponding path program 1 times [2023-11-21 22:08:51,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:51,717 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583858857] [2023-11-21 22:08:51,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:51,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:51,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:51,828 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:51,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:08:51,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1583858857] [2023-11-21 22:08:51,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1583858857] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:08:51,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [69053949] [2023-11-21 22:08:51,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:51,830 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:08:51,830 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:51,831 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:08:51,848 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2023-11-21 22:08:51,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:51,931 INFO L262 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-21 22:08:51,932 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:08:52,028 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:52,029 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:08:52,086 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:52,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [69053949] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:08:52,088 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:08:52,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2023-11-21 22:08:52,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885227994] [2023-11-21 22:08:52,088 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:08:52,162 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:08:52,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2023-11-21 22:08:52,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2023-11-21 22:08:52,164 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. cyclomatic complexity: 7 Second operand has 11 states, 10 states have (on average 2.2) internal successors, (22), 11 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:52,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:08:52,327 INFO L93 Difference]: Finished difference Result 63 states and 74 transitions. [2023-11-21 22:08:52,327 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 74 transitions. [2023-11-21 22:08:52,336 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:52,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 46 states and 54 transitions. [2023-11-21 22:08:52,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2023-11-21 22:08:52,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2023-11-21 22:08:52,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 54 transitions. [2023-11-21 22:08:52,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:08:52,343 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46 states and 54 transitions. [2023-11-21 22:08:52,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 54 transitions. [2023-11-21 22:08:52,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 28. [2023-11-21 22:08:52,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1785714285714286) internal successors, (33), 27 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:52,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2023-11-21 22:08:52,350 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 33 transitions. [2023-11-21 22:08:52,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2023-11-21 22:08:52,352 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 33 transitions. [2023-11-21 22:08:52,356 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-21 22:08:52,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 33 transitions. [2023-11-21 22:08:52,358 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:52,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:52,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:52,359 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1] [2023-11-21 22:08:52,359 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:08:52,359 INFO L748 eck$LassoCheckResult]: Stem: 393#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 380#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 381#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 394#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 395#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 384#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 385#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 386#L27-4 main_~i~0#1 := 0; 387#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 399#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 388#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 389#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 392#L34 [2023-11-21 22:08:52,360 INFO L750 eck$LassoCheckResult]: Loop: 392#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 379#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 397#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 392#L34 [2023-11-21 22:08:52,360 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:52,360 INFO L85 PathProgramCache]: Analyzing trace with hash 780824429, now seen corresponding path program 2 times [2023-11-21 22:08:52,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:52,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749781693] [2023-11-21 22:08:52,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:52,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:52,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:52,390 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:52,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:52,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:52,424 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:52,424 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 3 times [2023-11-21 22:08:52,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:52,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076049561] [2023-11-21 22:08:52,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:52,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:52,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:52,433 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:52,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:52,445 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:52,446 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:52,447 INFO L85 PathProgramCache]: Analyzing trace with hash -2264087, now seen corresponding path program 3 times [2023-11-21 22:08:52,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:52,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180455722] [2023-11-21 22:08:52,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:52,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:52,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:52,619 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:52,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:08:52,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180455722] [2023-11-21 22:08:52,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [180455722] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:08:52,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1385005554] [2023-11-21 22:08:52,619 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-21 22:08:52,620 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:08:52,620 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:52,621 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:08:52,644 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2023-11-21 22:08:52,692 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2023-11-21 22:08:52,692 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:08:52,694 INFO L262 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjunts are in the unsatisfiable core [2023-11-21 22:08:52,697 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:08:52,799 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:52,799 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:08:52,881 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:52,881 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1385005554] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:08:52,881 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:08:52,881 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2023-11-21 22:08:52,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015397629] [2023-11-21 22:08:52,882 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:08:52,946 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:08:52,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2023-11-21 22:08:52,947 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2023-11-21 22:08:52,947 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. cyclomatic complexity: 8 Second operand has 14 states, 13 states have (on average 2.3076923076923075) internal successors, (30), 14 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:53,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:08:53,159 INFO L93 Difference]: Finished difference Result 89 states and 104 transitions. [2023-11-21 22:08:53,159 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 104 transitions. [2023-11-21 22:08:53,160 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:53,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 60 states and 70 transitions. [2023-11-21 22:08:53,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2023-11-21 22:08:53,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2023-11-21 22:08:53,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 70 transitions. [2023-11-21 22:08:53,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:08:53,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 70 transitions. [2023-11-21 22:08:53,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 70 transitions. [2023-11-21 22:08:53,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 36. [2023-11-21 22:08:53,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.1666666666666667) internal successors, (42), 35 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:53,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 42 transitions. [2023-11-21 22:08:53,166 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 42 transitions. [2023-11-21 22:08:53,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2023-11-21 22:08:53,169 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 42 transitions. [2023-11-21 22:08:53,169 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-21 22:08:53,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 42 transitions. [2023-11-21 22:08:53,170 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:53,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:53,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:53,171 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1] [2023-11-21 22:08:53,171 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:08:53,171 INFO L748 eck$LassoCheckResult]: Stem: 622#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 606#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 607#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 620#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 621#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 610#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 611#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 626#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 625#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 612#L27-4 main_~i~0#1 := 0; 613#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 634#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 614#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 615#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 619#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 628#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 633#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 618#L34 [2023-11-21 22:08:53,171 INFO L750 eck$LassoCheckResult]: Loop: 618#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 605#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 624#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 618#L34 [2023-11-21 22:08:53,172 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:53,172 INFO L85 PathProgramCache]: Analyzing trace with hash -79873369, now seen corresponding path program 4 times [2023-11-21 22:08:53,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:53,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718099145] [2023-11-21 22:08:53,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:53,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:53,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:53,193 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:53,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:53,215 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:53,215 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:53,215 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 4 times [2023-11-21 22:08:53,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:53,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304089405] [2023-11-21 22:08:53,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:53,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:53,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:53,221 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:53,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:53,225 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:53,227 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:53,227 INFO L85 PathProgramCache]: Analyzing trace with hash -95607185, now seen corresponding path program 5 times [2023-11-21 22:08:53,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:53,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946529873] [2023-11-21 22:08:53,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:53,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:53,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:53,459 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 5 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:53,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:08:53,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946529873] [2023-11-21 22:08:53,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [946529873] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:08:53,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1225034397] [2023-11-21 22:08:53,460 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-21 22:08:53,461 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:08:53,461 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:53,468 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:08:53,480 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2023-11-21 22:08:53,548 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2023-11-21 22:08:53,548 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:08:53,549 INFO L262 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjunts are in the unsatisfiable core [2023-11-21 22:08:53,551 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:08:53,685 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:53,685 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:08:53,784 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:53,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1225034397] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:08:53,785 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:08:53,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2023-11-21 22:08:53,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915841850] [2023-11-21 22:08:53,785 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:08:53,842 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:08:53,842 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2023-11-21 22:08:53,843 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=197, Unknown=0, NotChecked=0, Total=272 [2023-11-21 22:08:53,843 INFO L87 Difference]: Start difference. First operand 36 states and 42 transitions. cyclomatic complexity: 9 Second operand has 17 states, 16 states have (on average 2.375) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:54,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:08:54,077 INFO L93 Difference]: Finished difference Result 115 states and 134 transitions. [2023-11-21 22:08:54,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 134 transitions. [2023-11-21 22:08:54,078 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:54,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 74 states and 86 transitions. [2023-11-21 22:08:54,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2023-11-21 22:08:54,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2023-11-21 22:08:54,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 86 transitions. [2023-11-21 22:08:54,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:08:54,081 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74 states and 86 transitions. [2023-11-21 22:08:54,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 86 transitions. [2023-11-21 22:08:54,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 44. [2023-11-21 22:08:54,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.1590909090909092) internal successors, (51), 43 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:54,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 51 transitions. [2023-11-21 22:08:54,086 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 51 transitions. [2023-11-21 22:08:54,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-21 22:08:54,087 INFO L428 stractBuchiCegarLoop]: Abstraction has 44 states and 51 transitions. [2023-11-21 22:08:54,088 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-21 22:08:54,088 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 51 transitions. [2023-11-21 22:08:54,088 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:54,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:54,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:54,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1] [2023-11-21 22:08:54,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:08:54,090 INFO L748 eck$LassoCheckResult]: Stem: 915#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 902#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 916#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 917#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 905#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 906#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 926#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 925#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 922#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 921#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 907#L27-4 main_~i~0#1 := 0; 908#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 913#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 900#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 910#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 936#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 934#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 933#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 930#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 928#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 927#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 920#L34 [2023-11-21 22:08:54,090 INFO L750 eck$LassoCheckResult]: Loop: 920#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 923#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 919#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 920#L34 [2023-11-21 22:08:54,091 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:54,091 INFO L85 PathProgramCache]: Analyzing trace with hash 1712449137, now seen corresponding path program 6 times [2023-11-21 22:08:54,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:54,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780673601] [2023-11-21 22:08:54,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:54,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:54,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:54,120 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:54,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:54,145 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:54,146 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:54,146 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 5 times [2023-11-21 22:08:54,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:54,147 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286726943] [2023-11-21 22:08:54,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:54,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:54,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:54,151 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:54,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:54,155 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:54,156 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:54,156 INFO L85 PathProgramCache]: Analyzing trace with hash -49254811, now seen corresponding path program 7 times [2023-11-21 22:08:54,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:54,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177868865] [2023-11-21 22:08:54,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:54,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:54,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:54,350 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 12 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:54,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:08:54,351 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177868865] [2023-11-21 22:08:54,351 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177868865] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:08:54,351 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [487687961] [2023-11-21 22:08:54,352 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-21 22:08:54,352 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:08:54,352 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:54,354 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:08:54,359 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2023-11-21 22:08:54,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:54,438 INFO L262 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjunts are in the unsatisfiable core [2023-11-21 22:08:54,440 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:08:54,673 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:54,673 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:08:54,819 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:54,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [487687961] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:08:54,819 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:08:54,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2023-11-21 22:08:54,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179503042] [2023-11-21 22:08:54,820 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:08:54,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:08:54,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2023-11-21 22:08:54,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=279, Unknown=0, NotChecked=0, Total=380 [2023-11-21 22:08:54,887 INFO L87 Difference]: Start difference. First operand 44 states and 51 transitions. cyclomatic complexity: 10 Second operand has 20 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:55,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:08:55,181 INFO L93 Difference]: Finished difference Result 141 states and 164 transitions. [2023-11-21 22:08:55,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141 states and 164 transitions. [2023-11-21 22:08:55,182 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:55,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141 states to 88 states and 102 transitions. [2023-11-21 22:08:55,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77 [2023-11-21 22:08:55,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77 [2023-11-21 22:08:55,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 102 transitions. [2023-11-21 22:08:55,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:08:55,185 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88 states and 102 transitions. [2023-11-21 22:08:55,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 102 transitions. [2023-11-21 22:08:55,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 52. [2023-11-21 22:08:55,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1538461538461537) internal successors, (60), 51 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:55,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 60 transitions. [2023-11-21 22:08:55,189 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 60 transitions. [2023-11-21 22:08:55,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2023-11-21 22:08:55,192 INFO L428 stractBuchiCegarLoop]: Abstraction has 52 states and 60 transitions. [2023-11-21 22:08:55,192 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-21 22:08:55,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 60 transitions. [2023-11-21 22:08:55,193 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:55,193 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:55,193 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:55,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1] [2023-11-21 22:08:55,195 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:08:55,195 INFO L748 eck$LassoCheckResult]: Stem: 1280#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1266#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1281#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1282#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1269#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1270#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1293#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1292#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1291#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1290#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1287#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1286#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1271#L27-4 main_~i~0#1 := 0; 1272#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1277#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1264#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1274#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1279#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1307#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1306#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1303#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1301#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1300#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1297#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1295#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1294#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1285#L34 [2023-11-21 22:08:55,195 INFO L750 eck$LassoCheckResult]: Loop: 1285#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1288#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1284#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1285#L34 [2023-11-21 22:08:55,196 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:55,196 INFO L85 PathProgramCache]: Analyzing trace with hash -240296029, now seen corresponding path program 8 times [2023-11-21 22:08:55,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:55,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504030610] [2023-11-21 22:08:55,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:55,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:55,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:55,224 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:55,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:55,246 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:55,247 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:55,247 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 6 times [2023-11-21 22:08:55,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:55,247 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931312989] [2023-11-21 22:08:55,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:55,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:55,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:55,252 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:55,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:55,255 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:55,256 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:55,256 INFO L85 PathProgramCache]: Analyzing trace with hash 1051529203, now seen corresponding path program 9 times [2023-11-21 22:08:55,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:55,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881248588] [2023-11-21 22:08:55,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:55,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:55,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:55,519 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 22 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:55,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:08:55,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881248588] [2023-11-21 22:08:55,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881248588] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:08:55,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1336398330] [2023-11-21 22:08:55,520 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-21 22:08:55,520 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:08:55,520 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:55,525 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:08:55,537 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2023-11-21 22:08:55,621 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2023-11-21 22:08:55,622 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:08:55,623 INFO L262 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjunts are in the unsatisfiable core [2023-11-21 22:08:55,625 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:08:55,815 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:55,815 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:08:55,960 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:55,961 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1336398330] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:08:55,961 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:08:55,961 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2023-11-21 22:08:55,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1836314383] [2023-11-21 22:08:55,962 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:08:56,040 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:08:56,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2023-11-21 22:08:56,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=375, Unknown=0, NotChecked=0, Total=506 [2023-11-21 22:08:56,041 INFO L87 Difference]: Start difference. First operand 52 states and 60 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.4545454545454546) internal successors, (54), 23 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:56,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:08:56,352 INFO L93 Difference]: Finished difference Result 167 states and 194 transitions. [2023-11-21 22:08:56,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167 states and 194 transitions. [2023-11-21 22:08:56,353 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:56,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167 states to 102 states and 118 transitions. [2023-11-21 22:08:56,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2023-11-21 22:08:56,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2023-11-21 22:08:56,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 118 transitions. [2023-11-21 22:08:56,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:08:56,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102 states and 118 transitions. [2023-11-21 22:08:56,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 118 transitions. [2023-11-21 22:08:56,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 60. [2023-11-21 22:08:56,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.15) internal successors, (69), 59 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:56,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 69 transitions. [2023-11-21 22:08:56,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60 states and 69 transitions. [2023-11-21 22:08:56,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2023-11-21 22:08:56,362 INFO L428 stractBuchiCegarLoop]: Abstraction has 60 states and 69 transitions. [2023-11-21 22:08:56,362 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-21 22:08:56,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 69 transitions. [2023-11-21 22:08:56,362 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:56,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:56,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:56,364 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1] [2023-11-21 22:08:56,364 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:08:56,364 INFO L748 eck$LassoCheckResult]: Stem: 1714#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1698#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1699#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1715#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1716#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1729#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1728#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1727#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1726#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1725#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1724#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1721#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1720#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1704#L27-4 main_~i~0#1 := 0; 1705#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1711#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1697#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1708#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1713#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1748#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1747#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1745#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1742#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1741#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1739#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1737#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1736#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1733#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1731#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1730#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1719#L34 [2023-11-21 22:08:56,364 INFO L750 eck$LassoCheckResult]: Loop: 1719#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1722#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1718#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1719#L34 [2023-11-21 22:08:56,365 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:56,365 INFO L85 PathProgramCache]: Analyzing trace with hash 1967863157, now seen corresponding path program 10 times [2023-11-21 22:08:56,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:56,365 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553060684] [2023-11-21 22:08:56,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:56,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:56,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:56,399 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:56,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:56,428 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:56,428 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:56,428 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 7 times [2023-11-21 22:08:56,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:56,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705762306] [2023-11-21 22:08:56,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:56,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:56,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:56,433 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:56,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:56,436 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:56,437 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:56,437 INFO L85 PathProgramCache]: Analyzing trace with hash -1692233503, now seen corresponding path program 11 times [2023-11-21 22:08:56,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:56,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130531857] [2023-11-21 22:08:56,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:56,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:56,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:56,739 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 35 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:56,740 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:08:56,740 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130531857] [2023-11-21 22:08:56,740 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130531857] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:08:56,740 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [257283539] [2023-11-21 22:08:56,741 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-21 22:08:56,741 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:08:56,741 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:56,744 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:08:56,754 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2023-11-21 22:08:56,875 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2023-11-21 22:08:56,875 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:08:56,877 INFO L262 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 16 conjunts are in the unsatisfiable core [2023-11-21 22:08:56,879 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:08:57,101 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:57,101 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:08:57,321 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:57,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [257283539] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:08:57,322 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:08:57,322 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2023-11-21 22:08:57,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1737872632] [2023-11-21 22:08:57,322 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:08:57,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:08:57,383 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2023-11-21 22:08:57,384 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=485, Unknown=0, NotChecked=0, Total=650 [2023-11-21 22:08:57,384 INFO L87 Difference]: Start difference. First operand 60 states and 69 transitions. cyclomatic complexity: 12 Second operand has 26 states, 25 states have (on average 2.48) internal successors, (62), 26 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:57,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:08:57,764 INFO L93 Difference]: Finished difference Result 193 states and 224 transitions. [2023-11-21 22:08:57,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 224 transitions. [2023-11-21 22:08:57,766 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:57,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 116 states and 134 transitions. [2023-11-21 22:08:57,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2023-11-21 22:08:57,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2023-11-21 22:08:57,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 134 transitions. [2023-11-21 22:08:57,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:08:57,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 134 transitions. [2023-11-21 22:08:57,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 134 transitions. [2023-11-21 22:08:57,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 68. [2023-11-21 22:08:57,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1470588235294117) internal successors, (78), 67 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:57,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 78 transitions. [2023-11-21 22:08:57,786 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 78 transitions. [2023-11-21 22:08:57,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2023-11-21 22:08:57,787 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 78 transitions. [2023-11-21 22:08:57,789 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-21 22:08:57,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 78 transitions. [2023-11-21 22:08:57,790 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:57,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:57,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:57,791 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1] [2023-11-21 22:08:57,791 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:08:57,792 INFO L748 eck$LassoCheckResult]: Stem: 2216#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2200#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2201#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2217#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2218#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2204#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2205#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2233#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2232#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2231#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2230#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2229#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2228#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2227#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2226#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2223#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2222#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2206#L27-4 main_~i~0#1 := 0; 2207#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2213#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2199#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2210#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2215#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2258#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2257#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2255#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2252#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2251#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2249#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2246#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2245#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2243#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2241#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2240#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2237#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2235#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2234#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2221#L34 [2023-11-21 22:08:57,792 INFO L750 eck$LassoCheckResult]: Loop: 2221#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2224#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2220#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2221#L34 [2023-11-21 22:08:57,792 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:57,793 INFO L85 PathProgramCache]: Analyzing trace with hash -664171361, now seen corresponding path program 12 times [2023-11-21 22:08:57,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:57,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144162875] [2023-11-21 22:08:57,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:57,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:57,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:57,850 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:57,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:57,907 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:57,909 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:57,909 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 8 times [2023-11-21 22:08:57,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:57,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004772430] [2023-11-21 22:08:57,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:57,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:57,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:57,915 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:57,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:57,918 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:57,919 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:57,919 INFO L85 PathProgramCache]: Analyzing trace with hash 585363831, now seen corresponding path program 13 times [2023-11-21 22:08:57,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:57,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122622630] [2023-11-21 22:08:57,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:57,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:57,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:58,408 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:58,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:08:58,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1122622630] [2023-11-21 22:08:58,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1122622630] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:08:58,411 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1816580942] [2023-11-21 22:08:58,411 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-21 22:08:58,411 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:08:58,411 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:08:58,413 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:08:58,425 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2023-11-21 22:08:58,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:08:58,513 INFO L262 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjunts are in the unsatisfiable core [2023-11-21 22:08:58,515 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:08:58,803 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:58,803 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:08:59,034 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:08:59,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1816580942] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:08:59,035 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:08:59,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2023-11-21 22:08:59,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191571491] [2023-11-21 22:08:59,035 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:08:59,093 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:08:59,093 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2023-11-21 22:08:59,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=609, Unknown=0, NotChecked=0, Total=812 [2023-11-21 22:08:59,094 INFO L87 Difference]: Start difference. First operand 68 states and 78 transitions. cyclomatic complexity: 13 Second operand has 29 states, 28 states have (on average 2.5) internal successors, (70), 29 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:59,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:08:59,476 INFO L93 Difference]: Finished difference Result 219 states and 254 transitions. [2023-11-21 22:08:59,476 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219 states and 254 transitions. [2023-11-21 22:08:59,478 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:59,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219 states to 130 states and 150 transitions. [2023-11-21 22:08:59,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113 [2023-11-21 22:08:59,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113 [2023-11-21 22:08:59,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130 states and 150 transitions. [2023-11-21 22:08:59,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:08:59,480 INFO L218 hiAutomatonCegarLoop]: Abstraction has 130 states and 150 transitions. [2023-11-21 22:08:59,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states and 150 transitions. [2023-11-21 22:08:59,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 76. [2023-11-21 22:08:59,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.144736842105263) internal successors, (87), 75 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:08:59,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 87 transitions. [2023-11-21 22:08:59,485 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 87 transitions. [2023-11-21 22:08:59,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2023-11-21 22:08:59,487 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 87 transitions. [2023-11-21 22:08:59,487 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-21 22:08:59,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 87 transitions. [2023-11-21 22:08:59,487 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:08:59,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:08:59,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:08:59,489 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1] [2023-11-21 22:08:59,489 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:08:59,490 INFO L748 eck$LassoCheckResult]: Stem: 2787#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2772#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2788#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2789#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2775#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2776#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2806#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2805#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2804#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2803#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2802#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2801#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2800#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2799#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2798#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2797#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2794#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2793#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2777#L27-4 main_~i~0#1 := 0; 2778#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2784#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2770#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2781#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2786#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2837#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2836#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2834#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2831#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2830#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2828#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2825#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2824#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2822#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2819#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2818#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2816#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2814#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2813#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2810#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2808#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2807#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2792#L34 [2023-11-21 22:08:59,490 INFO L750 eck$LassoCheckResult]: Loop: 2792#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2795#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2791#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2792#L34 [2023-11-21 22:08:59,490 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:59,490 INFO L85 PathProgramCache]: Analyzing trace with hash -704996231, now seen corresponding path program 14 times [2023-11-21 22:08:59,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:59,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561851185] [2023-11-21 22:08:59,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:59,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:59,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:59,536 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:59,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:59,583 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:59,583 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:59,584 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 9 times [2023-11-21 22:08:59,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:59,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025795534] [2023-11-21 22:08:59,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:59,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:59,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:59,588 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:08:59,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:08:59,592 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:08:59,593 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:08:59,593 INFO L85 PathProgramCache]: Analyzing trace with hash -152593571, now seen corresponding path program 15 times [2023-11-21 22:08:59,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:08:59,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807649987] [2023-11-21 22:08:59,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:08:59,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:08:59,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:00,112 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 70 proven. 86 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:00,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:00,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807649987] [2023-11-21 22:09:00,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807649987] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:09:00,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1358755205] [2023-11-21 22:09:00,113 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-21 22:09:00,113 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:09:00,113 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:00,121 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:09:00,127 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2023-11-21 22:09:00,259 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2023-11-21 22:09:00,259 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:09:00,261 INFO L262 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjunts are in the unsatisfiable core [2023-11-21 22:09:00,263 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:09:00,626 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:00,626 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:09:00,894 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:00,895 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1358755205] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:09:00,895 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:09:00,895 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2023-11-21 22:09:00,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254907858] [2023-11-21 22:09:00,895 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:09:00,966 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:00,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2023-11-21 22:09:00,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=245, Invalid=747, Unknown=0, NotChecked=0, Total=992 [2023-11-21 22:09:00,968 INFO L87 Difference]: Start difference. First operand 76 states and 87 transitions. cyclomatic complexity: 14 Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 32 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:01,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:01,460 INFO L93 Difference]: Finished difference Result 245 states and 284 transitions. [2023-11-21 22:09:01,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 284 transitions. [2023-11-21 22:09:01,463 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:01,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 144 states and 166 transitions. [2023-11-21 22:09:01,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125 [2023-11-21 22:09:01,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125 [2023-11-21 22:09:01,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 166 transitions. [2023-11-21 22:09:01,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:01,465 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144 states and 166 transitions. [2023-11-21 22:09:01,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 166 transitions. [2023-11-21 22:09:01,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 84. [2023-11-21 22:09:01,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.1428571428571428) internal successors, (96), 83 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:01,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2023-11-21 22:09:01,470 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84 states and 96 transitions. [2023-11-21 22:09:01,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2023-11-21 22:09:01,471 INFO L428 stractBuchiCegarLoop]: Abstraction has 84 states and 96 transitions. [2023-11-21 22:09:01,471 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-21 22:09:01,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 96 transitions. [2023-11-21 22:09:01,472 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:01,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:01,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:01,474 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1] [2023-11-21 22:09:01,474 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:09:01,474 INFO L748 eck$LassoCheckResult]: Stem: 3427#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 3411#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 3412#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3428#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3429#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3415#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3416#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3448#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3447#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3446#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3445#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3444#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3443#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3442#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3441#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3440#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3439#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3438#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3437#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3434#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3433#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 3417#L27-4 main_~i~0#1 := 0; 3418#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3424#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3410#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3421#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3426#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3485#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3484#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3482#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3479#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3478#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3476#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3473#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3472#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3470#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3467#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3466#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3464#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3461#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3460#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3458#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3456#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3455#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3452#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3450#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3449#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3432#L34 [2023-11-21 22:09:01,474 INFO L750 eck$LassoCheckResult]: Loop: 3432#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3435#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3431#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3432#L34 [2023-11-21 22:09:01,475 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:01,475 INFO L85 PathProgramCache]: Analyzing trace with hash -1850900069, now seen corresponding path program 16 times [2023-11-21 22:09:01,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:01,475 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137998756] [2023-11-21 22:09:01,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:01,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:01,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:01,541 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:01,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:01,594 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:01,595 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:01,595 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 10 times [2023-11-21 22:09:01,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:01,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753992827] [2023-11-21 22:09:01,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:01,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:01,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:01,600 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:01,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:01,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:01,605 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:01,605 INFO L85 PathProgramCache]: Analyzing trace with hash -1373762821, now seen corresponding path program 17 times [2023-11-21 22:09:01,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:01,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510688424] [2023-11-21 22:09:01,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:01,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:01,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:02,173 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 92 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:02,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:02,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510688424] [2023-11-21 22:09:02,174 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510688424] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:09:02,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [43978387] [2023-11-21 22:09:02,174 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-21 22:09:02,174 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:09:02,174 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:02,176 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:09:02,177 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2023-11-21 22:09:02,484 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2023-11-21 22:09:02,484 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:09:02,490 INFO L262 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjunts are in the unsatisfiable core [2023-11-21 22:09:02,492 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:09:02,872 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:02,873 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:09:03,155 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:03,156 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [43978387] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:09:03,156 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:09:03,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2023-11-21 22:09:03,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582047145] [2023-11-21 22:09:03,156 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:09:03,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:03,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2023-11-21 22:09:03,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=899, Unknown=0, NotChecked=0, Total=1190 [2023-11-21 22:09:03,209 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. cyclomatic complexity: 15 Second operand has 35 states, 34 states have (on average 2.5294117647058822) internal successors, (86), 35 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:03,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:03,746 INFO L93 Difference]: Finished difference Result 271 states and 314 transitions. [2023-11-21 22:09:03,746 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 314 transitions. [2023-11-21 22:09:03,749 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:03,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 158 states and 182 transitions. [2023-11-21 22:09:03,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137 [2023-11-21 22:09:03,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2023-11-21 22:09:03,751 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 182 transitions. [2023-11-21 22:09:03,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:03,751 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 182 transitions. [2023-11-21 22:09:03,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 182 transitions. [2023-11-21 22:09:03,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 92. [2023-11-21 22:09:03,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.141304347826087) internal successors, (105), 91 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:03,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 105 transitions. [2023-11-21 22:09:03,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 105 transitions. [2023-11-21 22:09:03,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-21 22:09:03,758 INFO L428 stractBuchiCegarLoop]: Abstraction has 92 states and 105 transitions. [2023-11-21 22:09:03,758 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-21 22:09:03,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 105 transitions. [2023-11-21 22:09:03,759 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:03,759 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:03,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:03,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1] [2023-11-21 22:09:03,760 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:09:03,761 INFO L748 eck$LassoCheckResult]: Stem: 4138#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4120#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4121#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4136#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4137#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4124#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4125#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4159#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4158#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4157#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4156#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4155#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4154#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4153#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4152#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4151#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4150#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4149#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4148#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4147#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4146#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4143#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4142#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4126#L27-4 main_~i~0#1 := 0; 4127#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4133#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4119#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4130#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4135#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4202#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4201#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4199#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4196#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4195#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4193#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4190#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4189#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4187#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4184#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4183#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4181#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4178#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4177#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4175#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4172#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4171#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4169#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4167#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4166#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4163#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4161#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4160#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4141#L34 [2023-11-21 22:09:03,761 INFO L750 eck$LassoCheckResult]: Loop: 4141#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4144#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4140#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4141#L34 [2023-11-21 22:09:03,762 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:03,762 INFO L85 PathProgramCache]: Analyzing trace with hash -354133123, now seen corresponding path program 18 times [2023-11-21 22:09:03,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:03,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282973832] [2023-11-21 22:09:03,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:03,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:03,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:03,871 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:03,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:03,980 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:03,981 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:03,981 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 11 times [2023-11-21 22:09:03,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:03,981 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114148979] [2023-11-21 22:09:03,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:03,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:03,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:03,986 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:03,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:03,990 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:03,991 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:03,991 INFO L85 PathProgramCache]: Analyzing trace with hash -1540141607, now seen corresponding path program 19 times [2023-11-21 22:09:03,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:03,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764305112] [2023-11-21 22:09:03,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:03,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:04,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:04,619 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 117 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:04,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:04,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764305112] [2023-11-21 22:09:04,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764305112] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:09:04,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [997378408] [2023-11-21 22:09:04,619 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-21 22:09:04,620 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:09:04,620 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:04,622 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:09:04,628 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2023-11-21 22:09:04,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:04,740 INFO L262 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjunts are in the unsatisfiable core [2023-11-21 22:09:04,743 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:09:05,177 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:05,177 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:09:05,558 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:05,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [997378408] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:09:05,558 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:09:05,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2023-11-21 22:09:05,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909050159] [2023-11-21 22:09:05,558 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:09:05,612 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:05,613 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2023-11-21 22:09:05,614 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=1065, Unknown=0, NotChecked=0, Total=1406 [2023-11-21 22:09:05,614 INFO L87 Difference]: Start difference. First operand 92 states and 105 transitions. cyclomatic complexity: 16 Second operand has 38 states, 37 states have (on average 2.5405405405405403) internal successors, (94), 38 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:06,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:06,182 INFO L93 Difference]: Finished difference Result 297 states and 344 transitions. [2023-11-21 22:09:06,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 297 states and 344 transitions. [2023-11-21 22:09:06,186 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:06,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 297 states to 172 states and 198 transitions. [2023-11-21 22:09:06,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149 [2023-11-21 22:09:06,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149 [2023-11-21 22:09:06,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172 states and 198 transitions. [2023-11-21 22:09:06,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:06,189 INFO L218 hiAutomatonCegarLoop]: Abstraction has 172 states and 198 transitions. [2023-11-21 22:09:06,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states and 198 transitions. [2023-11-21 22:09:06,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 100. [2023-11-21 22:09:06,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.14) internal successors, (114), 99 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:06,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 114 transitions. [2023-11-21 22:09:06,194 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 114 transitions. [2023-11-21 22:09:06,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2023-11-21 22:09:06,195 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 114 transitions. [2023-11-21 22:09:06,195 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-21 22:09:06,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 114 transitions. [2023-11-21 22:09:06,196 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:06,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:06,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:06,198 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1] [2023-11-21 22:09:06,198 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:09:06,198 INFO L748 eck$LassoCheckResult]: Stem: 4914#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4898#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4899#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4915#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4916#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4902#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4903#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4939#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4938#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4937#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4936#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4935#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4934#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4933#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4932#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4931#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4930#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4929#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4928#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4927#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4926#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4925#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4924#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4921#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4920#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4904#L27-4 main_~i~0#1 := 0; 4905#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4911#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4897#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4908#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4913#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4988#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4987#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4985#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4982#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4981#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4979#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4976#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4975#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4973#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4970#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4969#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4967#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4964#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4963#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4961#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4958#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4957#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4955#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4952#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4951#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4949#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4947#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4946#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4943#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4941#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4940#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4919#L34 [2023-11-21 22:09:06,199 INFO L750 eck$LassoCheckResult]: Loop: 4919#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4922#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4918#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4919#L34 [2023-11-21 22:09:06,199 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:06,199 INFO L85 PathProgramCache]: Analyzing trace with hash -726335849, now seen corresponding path program 20 times [2023-11-21 22:09:06,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:06,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889565372] [2023-11-21 22:09:06,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:06,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:06,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:06,267 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:06,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:06,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:06,337 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:06,337 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 12 times [2023-11-21 22:09:06,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:06,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326280662] [2023-11-21 22:09:06,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:06,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:06,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:06,341 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:06,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:06,345 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:06,346 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:06,346 INFO L85 PathProgramCache]: Analyzing trace with hash -225993601, now seen corresponding path program 21 times [2023-11-21 22:09:06,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:06,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049960578] [2023-11-21 22:09:06,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:06,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:06,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:07,056 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 145 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:07,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:07,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049960578] [2023-11-21 22:09:07,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049960578] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:09:07,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2144915792] [2023-11-21 22:09:07,056 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-21 22:09:07,056 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:09:07,057 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:07,061 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:09:07,080 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2023-11-21 22:09:07,338 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2023-11-21 22:09:07,338 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:09:07,341 INFO L262 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjunts are in the unsatisfiable core [2023-11-21 22:09:07,343 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:09:07,889 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:07,889 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:09:08,238 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:08,238 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2144915792] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:09:08,238 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:09:08,238 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2023-11-21 22:09:08,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031375079] [2023-11-21 22:09:08,239 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:09:08,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:08,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2023-11-21 22:09:08,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=395, Invalid=1245, Unknown=0, NotChecked=0, Total=1640 [2023-11-21 22:09:08,299 INFO L87 Difference]: Start difference. First operand 100 states and 114 transitions. cyclomatic complexity: 17 Second operand has 41 states, 40 states have (on average 2.55) internal successors, (102), 41 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:08,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:08,909 INFO L93 Difference]: Finished difference Result 323 states and 374 transitions. [2023-11-21 22:09:08,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 374 transitions. [2023-11-21 22:09:08,917 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:08,919 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 186 states and 214 transitions. [2023-11-21 22:09:08,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161 [2023-11-21 22:09:08,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161 [2023-11-21 22:09:08,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 214 transitions. [2023-11-21 22:09:08,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:08,920 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 214 transitions. [2023-11-21 22:09:08,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 214 transitions. [2023-11-21 22:09:08,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 108. [2023-11-21 22:09:08,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1388888888888888) internal successors, (123), 107 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:08,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 123 transitions. [2023-11-21 22:09:08,941 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 123 transitions. [2023-11-21 22:09:08,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2023-11-21 22:09:08,942 INFO L428 stractBuchiCegarLoop]: Abstraction has 108 states and 123 transitions. [2023-11-21 22:09:08,944 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-21 22:09:08,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 123 transitions. [2023-11-21 22:09:08,945 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:08,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:08,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:08,947 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1] [2023-11-21 22:09:08,957 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:09:08,957 INFO L748 eck$LassoCheckResult]: Stem: 5761#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 5745#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 5746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5762#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5763#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5749#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5750#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5788#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5787#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5786#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5785#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5784#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5783#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5782#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5781#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5780#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5779#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5778#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5777#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5776#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5775#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5774#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5773#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5772#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5771#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5768#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5767#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 5751#L27-4 main_~i~0#1 := 0; 5752#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5758#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5744#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5755#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5760#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5843#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5842#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5840#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5837#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5836#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5834#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5831#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5830#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5828#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5825#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5824#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5822#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5819#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5818#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5816#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5813#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5812#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5810#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5807#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5806#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5804#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5801#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5800#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5798#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5796#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5795#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5792#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5790#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5789#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5766#L34 [2023-11-21 22:09:08,957 INFO L750 eck$LassoCheckResult]: Loop: 5766#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5769#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5765#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5766#L34 [2023-11-21 22:09:08,958 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:08,958 INFO L85 PathProgramCache]: Analyzing trace with hash -2083736959, now seen corresponding path program 22 times [2023-11-21 22:09:08,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:08,958 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1747006637] [2023-11-21 22:09:08,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:08,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:09,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:09,053 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:09,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:09,116 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:09,117 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:09,117 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 13 times [2023-11-21 22:09:09,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:09,117 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301459232] [2023-11-21 22:09:09,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:09,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:09,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:09,121 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:09,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:09,124 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:09,125 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:09,125 INFO L85 PathProgramCache]: Analyzing trace with hash -1445369771, now seen corresponding path program 23 times [2023-11-21 22:09:09,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:09,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460034862] [2023-11-21 22:09:09,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:09,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:09,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:09,900 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 176 proven. 178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:09,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:09,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460034862] [2023-11-21 22:09:09,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1460034862] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:09:09,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2094688019] [2023-11-21 22:09:09,901 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-21 22:09:09,901 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:09:09,901 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:09,904 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:09:09,928 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2023-11-21 22:09:10,396 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2023-11-21 22:09:10,396 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:09:10,400 INFO L262 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjunts are in the unsatisfiable core [2023-11-21 22:09:10,403 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:09:11,006 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:11,006 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:09:11,481 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:11,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2094688019] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:09:11,481 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:09:11,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 43 [2023-11-21 22:09:11,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [134383875] [2023-11-21 22:09:11,482 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:09:11,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:11,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2023-11-21 22:09:11,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=1439, Unknown=0, NotChecked=0, Total=1892 [2023-11-21 22:09:11,535 INFO L87 Difference]: Start difference. First operand 108 states and 123 transitions. cyclomatic complexity: 18 Second operand has 44 states, 43 states have (on average 2.558139534883721) internal successors, (110), 44 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:12,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:12,248 INFO L93 Difference]: Finished difference Result 349 states and 404 transitions. [2023-11-21 22:09:12,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 349 states and 404 transitions. [2023-11-21 22:09:12,251 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:12,253 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 349 states to 200 states and 230 transitions. [2023-11-21 22:09:12,253 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173 [2023-11-21 22:09:12,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173 [2023-11-21 22:09:12,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200 states and 230 transitions. [2023-11-21 22:09:12,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:12,254 INFO L218 hiAutomatonCegarLoop]: Abstraction has 200 states and 230 transitions. [2023-11-21 22:09:12,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states and 230 transitions. [2023-11-21 22:09:12,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 116. [2023-11-21 22:09:12,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1379310344827587) internal successors, (132), 115 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:12,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 132 transitions. [2023-11-21 22:09:12,258 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 132 transitions. [2023-11-21 22:09:12,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2023-11-21 22:09:12,259 INFO L428 stractBuchiCegarLoop]: Abstraction has 116 states and 132 transitions. [2023-11-21 22:09:12,260 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-21 22:09:12,260 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 132 transitions. [2023-11-21 22:09:12,261 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:12,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:12,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:12,262 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1] [2023-11-21 22:09:12,262 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:09:12,262 INFO L748 eck$LassoCheckResult]: Stem: 6677#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 6661#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 6662#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6678#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6679#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6665#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6666#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6706#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6705#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6704#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6701#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6700#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6699#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6698#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6697#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6696#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6695#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6694#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6693#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6692#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6691#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6690#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6689#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6688#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6687#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6684#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6683#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 6667#L27-4 main_~i~0#1 := 0; 6668#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6674#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6660#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6671#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6676#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6767#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6766#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6764#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6761#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6760#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6758#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6755#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6754#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6752#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6749#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6748#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6746#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6743#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6742#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6740#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6737#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6736#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6734#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6731#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6730#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6728#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6725#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6724#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6722#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6719#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6718#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6716#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6714#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6713#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6710#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6708#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6707#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6682#L34 [2023-11-21 22:09:12,263 INFO L750 eck$LassoCheckResult]: Loop: 6682#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6685#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6681#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6682#L34 [2023-11-21 22:09:12,263 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:12,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1447312493, now seen corresponding path program 24 times [2023-11-21 22:09:12,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:12,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507203269] [2023-11-21 22:09:12,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:12,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:12,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:12,341 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:12,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:12,431 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:12,432 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:12,432 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 14 times [2023-11-21 22:09:12,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:12,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677623020] [2023-11-21 22:09:12,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:12,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:12,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:12,437 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:12,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:12,440 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:12,441 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:12,441 INFO L85 PathProgramCache]: Analyzing trace with hash 290252291, now seen corresponding path program 25 times [2023-11-21 22:09:12,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:12,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179233238] [2023-11-21 22:09:12,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:12,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:12,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:13,281 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 210 proven. 206 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:13,281 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:13,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179233238] [2023-11-21 22:09:13,281 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179233238] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:09:13,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1694580551] [2023-11-21 22:09:13,281 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-21 22:09:13,281 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:09:13,282 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:13,288 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:09:13,292 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2023-11-21 22:09:13,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:13,441 INFO L262 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 30 conjunts are in the unsatisfiable core [2023-11-21 22:09:13,443 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:09:13,985 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:13,986 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:09:14,494 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:14,494 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1694580551] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:09:14,494 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:09:14,494 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30] total 46 [2023-11-21 22:09:14,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475983422] [2023-11-21 22:09:14,495 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:09:14,546 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:14,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2023-11-21 22:09:14,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=515, Invalid=1647, Unknown=0, NotChecked=0, Total=2162 [2023-11-21 22:09:14,548 INFO L87 Difference]: Start difference. First operand 116 states and 132 transitions. cyclomatic complexity: 19 Second operand has 47 states, 46 states have (on average 2.5652173913043477) internal successors, (118), 47 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:15,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:15,277 INFO L93 Difference]: Finished difference Result 375 states and 434 transitions. [2023-11-21 22:09:15,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 375 states and 434 transitions. [2023-11-21 22:09:15,281 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:15,283 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 375 states to 214 states and 246 transitions. [2023-11-21 22:09:15,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185 [2023-11-21 22:09:15,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185 [2023-11-21 22:09:15,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 214 states and 246 transitions. [2023-11-21 22:09:15,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:15,284 INFO L218 hiAutomatonCegarLoop]: Abstraction has 214 states and 246 transitions. [2023-11-21 22:09:15,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states and 246 transitions. [2023-11-21 22:09:15,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 124. [2023-11-21 22:09:15,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124 states, 124 states have (on average 1.1370967741935485) internal successors, (141), 123 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:15,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 141 transitions. [2023-11-21 22:09:15,288 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124 states and 141 transitions. [2023-11-21 22:09:15,289 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2023-11-21 22:09:15,290 INFO L428 stractBuchiCegarLoop]: Abstraction has 124 states and 141 transitions. [2023-11-21 22:09:15,290 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-21 22:09:15,290 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124 states and 141 transitions. [2023-11-21 22:09:15,291 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:15,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:15,292 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:15,293 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 14, 13, 13, 1, 1, 1, 1] [2023-11-21 22:09:15,293 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:09:15,293 INFO L748 eck$LassoCheckResult]: Stem: 7662#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 7646#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 7647#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7663#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7664#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7650#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7651#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7693#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7692#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7691#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7690#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7689#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7688#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7687#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7686#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7685#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7683#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7682#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7681#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7680#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7679#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7678#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7677#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7676#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7675#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7674#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7673#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7672#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7669#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7668#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 7652#L27-4 main_~i~0#1 := 0; 7653#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7659#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7645#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7656#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7661#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7760#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7759#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7757#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7754#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7753#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7751#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7748#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7747#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7745#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7742#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7741#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7739#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7736#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7735#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7733#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7730#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7729#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7727#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7724#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7723#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7721#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7718#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7717#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7715#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7712#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7711#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7709#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7706#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7705#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7703#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7701#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7700#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7697#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7695#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7694#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7667#L34 [2023-11-21 22:09:15,293 INFO L750 eck$LassoCheckResult]: Loop: 7667#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7670#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7666#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7667#L34 [2023-11-21 22:09:15,294 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:15,294 INFO L85 PathProgramCache]: Analyzing trace with hash 1635246469, now seen corresponding path program 26 times [2023-11-21 22:09:15,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:15,294 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739047956] [2023-11-21 22:09:15,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:15,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:15,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:15,369 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:15,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:15,448 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:15,449 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:15,449 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 15 times [2023-11-21 22:09:15,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:15,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537737507] [2023-11-21 22:09:15,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:15,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:15,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:15,453 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:15,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:15,456 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:15,458 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:15,458 INFO L85 PathProgramCache]: Analyzing trace with hash 2108533457, now seen corresponding path program 27 times [2023-11-21 22:09:15,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:15,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612816988] [2023-11-21 22:09:15,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:15,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:15,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:16,383 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 247 proven. 236 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:16,383 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:16,383 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1612816988] [2023-11-21 22:09:16,383 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1612816988] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:09:16,383 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [694354663] [2023-11-21 22:09:16,383 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-21 22:09:16,384 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:09:16,384 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:16,391 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:09:16,393 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2023-11-21 22:09:17,026 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2023-11-21 22:09:17,026 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:09:17,029 INFO L262 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 32 conjunts are in the unsatisfiable core [2023-11-21 22:09:17,031 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:09:17,722 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:17,722 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:09:18,236 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:18,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [694354663] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:09:18,236 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:09:18,236 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32] total 49 [2023-11-21 22:09:18,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016099433] [2023-11-21 22:09:18,237 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:09:18,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:18,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2023-11-21 22:09:18,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=581, Invalid=1869, Unknown=0, NotChecked=0, Total=2450 [2023-11-21 22:09:18,290 INFO L87 Difference]: Start difference. First operand 124 states and 141 transitions. cyclomatic complexity: 20 Second operand has 50 states, 49 states have (on average 2.5714285714285716) internal successors, (126), 50 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:19,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:19,138 INFO L93 Difference]: Finished difference Result 401 states and 464 transitions. [2023-11-21 22:09:19,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 401 states and 464 transitions. [2023-11-21 22:09:19,143 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:19,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 401 states to 228 states and 262 transitions. [2023-11-21 22:09:19,145 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2023-11-21 22:09:19,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197 [2023-11-21 22:09:19,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228 states and 262 transitions. [2023-11-21 22:09:19,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:19,146 INFO L218 hiAutomatonCegarLoop]: Abstraction has 228 states and 262 transitions. [2023-11-21 22:09:19,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states and 262 transitions. [2023-11-21 22:09:19,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 132. [2023-11-21 22:09:19,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 132 states, 132 states have (on average 1.1363636363636365) internal successors, (150), 131 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:19,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 150 transitions. [2023-11-21 22:09:19,151 INFO L240 hiAutomatonCegarLoop]: Abstraction has 132 states and 150 transitions. [2023-11-21 22:09:19,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2023-11-21 22:09:19,155 INFO L428 stractBuchiCegarLoop]: Abstraction has 132 states and 150 transitions. [2023-11-21 22:09:19,155 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-21 22:09:19,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 132 states and 150 transitions. [2023-11-21 22:09:19,157 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:19,157 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:19,157 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:19,158 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 15, 14, 14, 1, 1, 1, 1] [2023-11-21 22:09:19,158 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:09:19,159 INFO L748 eck$LassoCheckResult]: Stem: 8716#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 8700#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 8701#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8717#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8718#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8704#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8705#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8749#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8748#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8747#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8745#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8744#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8743#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8742#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8741#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8740#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8739#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8738#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8737#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8736#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8735#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8734#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8733#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8731#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8730#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8729#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8728#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8727#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8726#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8723#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8722#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 8706#L27-4 main_~i~0#1 := 0; 8707#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8713#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8699#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8710#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8715#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8822#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8821#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8819#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8816#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8815#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8813#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8810#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8809#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8807#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8804#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8803#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8801#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8798#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8797#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8795#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8792#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8791#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8789#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8786#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8785#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8783#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8780#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8779#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8777#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8774#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8773#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8771#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8768#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8767#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8765#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8762#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8761#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8759#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8757#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8756#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8753#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8751#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8750#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8721#L34 [2023-11-21 22:09:19,159 INFO L750 eck$LassoCheckResult]: Loop: 8721#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8724#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8720#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8721#L34 [2023-11-21 22:09:19,160 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:19,160 INFO L85 PathProgramCache]: Analyzing trace with hash -436367217, now seen corresponding path program 28 times [2023-11-21 22:09:19,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:19,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1886588668] [2023-11-21 22:09:19,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:19,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:19,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:19,316 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:19,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:19,397 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:19,399 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:19,399 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 16 times [2023-11-21 22:09:19,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:19,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364670787] [2023-11-21 22:09:19,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:19,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:19,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:19,405 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:19,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:19,409 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:19,409 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:19,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1050290055, now seen corresponding path program 29 times [2023-11-21 22:09:19,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:19,410 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1146858739] [2023-11-21 22:09:19,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:19,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:19,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:20,454 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 287 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:20,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:20,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1146858739] [2023-11-21 22:09:20,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1146858739] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:09:20,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1384646583] [2023-11-21 22:09:20,455 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-21 22:09:20,455 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:09:20,455 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:20,456 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:09:20,460 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2023-11-21 22:09:20,985 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2023-11-21 22:09:20,985 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:09:20,989 INFO L262 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 34 conjunts are in the unsatisfiable core [2023-11-21 22:09:20,990 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:09:21,728 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:21,728 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:09:22,271 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:22,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1384646583] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:09:22,271 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:09:22,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34] total 52 [2023-11-21 22:09:22,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2106060686] [2023-11-21 22:09:22,272 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:09:22,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:22,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2023-11-21 22:09:22,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=651, Invalid=2105, Unknown=0, NotChecked=0, Total=2756 [2023-11-21 22:09:22,325 INFO L87 Difference]: Start difference. First operand 132 states and 150 transitions. cyclomatic complexity: 21 Second operand has 53 states, 52 states have (on average 2.576923076923077) internal successors, (134), 53 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:23,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:23,207 INFO L93 Difference]: Finished difference Result 427 states and 494 transitions. [2023-11-21 22:09:23,208 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 427 states and 494 transitions. [2023-11-21 22:09:23,212 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:23,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 427 states to 242 states and 278 transitions. [2023-11-21 22:09:23,214 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 209 [2023-11-21 22:09:23,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 209 [2023-11-21 22:09:23,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 242 states and 278 transitions. [2023-11-21 22:09:23,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:23,215 INFO L218 hiAutomatonCegarLoop]: Abstraction has 242 states and 278 transitions. [2023-11-21 22:09:23,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states and 278 transitions. [2023-11-21 22:09:23,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 140. [2023-11-21 22:09:23,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 140 states have (on average 1.1357142857142857) internal successors, (159), 139 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:23,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 159 transitions. [2023-11-21 22:09:23,220 INFO L240 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2023-11-21 22:09:23,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2023-11-21 22:09:23,221 INFO L428 stractBuchiCegarLoop]: Abstraction has 140 states and 159 transitions. [2023-11-21 22:09:23,221 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-21 22:09:23,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140 states and 159 transitions. [2023-11-21 22:09:23,222 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:23,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:23,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:23,224 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 16, 15, 15, 1, 1, 1, 1] [2023-11-21 22:09:23,224 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:09:23,224 INFO L748 eck$LassoCheckResult]: Stem: 9839#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 9823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 9824#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9840#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9841#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9827#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9828#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9874#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9873#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9872#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9871#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9870#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9869#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9868#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9867#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9866#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9865#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9864#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9863#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9862#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9861#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9860#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9859#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9858#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9857#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9856#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9855#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9854#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9853#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9852#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9851#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9850#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9849#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9846#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9845#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 9829#L27-4 main_~i~0#1 := 0; 9830#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9836#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9822#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9833#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9838#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9953#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9952#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9950#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9947#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9946#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9944#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9941#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9940#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9938#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9935#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9934#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9932#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9929#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9928#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9926#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9923#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9922#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9920#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9917#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9916#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9914#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9911#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9910#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9908#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9905#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9904#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9902#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9899#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9898#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9896#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9893#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9892#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9890#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9887#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9886#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9884#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9882#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9881#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9878#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9876#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9875#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9844#L34 [2023-11-21 22:09:23,224 INFO L750 eck$LassoCheckResult]: Loop: 9844#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9847#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9843#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9844#L34 [2023-11-21 22:09:23,225 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:23,225 INFO L85 PathProgramCache]: Analyzing trace with hash -1180030839, now seen corresponding path program 30 times [2023-11-21 22:09:23,225 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:23,225 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494004266] [2023-11-21 22:09:23,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:23,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:23,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:23,389 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:23,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:23,484 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:23,485 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:23,485 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 17 times [2023-11-21 22:09:23,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:23,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303800404] [2023-11-21 22:09:23,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:23,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:23,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:23,491 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:23,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:23,495 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:23,496 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:23,496 INFO L85 PathProgramCache]: Analyzing trace with hash 8639821, now seen corresponding path program 31 times [2023-11-21 22:09:23,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:23,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51999670] [2023-11-21 22:09:23,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:23,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:23,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:24,662 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 330 proven. 302 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:24,662 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:24,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51999670] [2023-11-21 22:09:24,663 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51999670] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:09:24,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1363832156] [2023-11-21 22:09:24,663 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-21 22:09:24,663 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:09:24,663 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:24,665 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:09:24,673 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2023-11-21 22:09:24,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:24,846 INFO L262 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 36 conjunts are in the unsatisfiable core [2023-11-21 22:09:24,849 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:09:25,703 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:25,704 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-21 22:09:26,430 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:26,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1363832156] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-21 22:09:26,431 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-21 22:09:26,431 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36] total 55 [2023-11-21 22:09:26,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838878964] [2023-11-21 22:09:26,431 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-21 22:09:26,490 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:26,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2023-11-21 22:09:26,492 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=725, Invalid=2355, Unknown=0, NotChecked=0, Total=3080 [2023-11-21 22:09:26,493 INFO L87 Difference]: Start difference. First operand 140 states and 159 transitions. cyclomatic complexity: 22 Second operand has 56 states, 55 states have (on average 2.581818181818182) internal successors, (142), 56 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:27,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:27,589 INFO L93 Difference]: Finished difference Result 453 states and 524 transitions. [2023-11-21 22:09:27,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 453 states and 524 transitions. [2023-11-21 22:09:27,594 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:27,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 453 states to 256 states and 294 transitions. [2023-11-21 22:09:27,597 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2023-11-21 22:09:27,597 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2023-11-21 22:09:27,597 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256 states and 294 transitions. [2023-11-21 22:09:27,598 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:27,598 INFO L218 hiAutomatonCegarLoop]: Abstraction has 256 states and 294 transitions. [2023-11-21 22:09:27,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states and 294 transitions. [2023-11-21 22:09:27,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 148. [2023-11-21 22:09:27,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148 states, 148 states have (on average 1.135135135135135) internal successors, (168), 147 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:27,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 168 transitions. [2023-11-21 22:09:27,604 INFO L240 hiAutomatonCegarLoop]: Abstraction has 148 states and 168 transitions. [2023-11-21 22:09:27,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2023-11-21 22:09:27,605 INFO L428 stractBuchiCegarLoop]: Abstraction has 148 states and 168 transitions. [2023-11-21 22:09:27,605 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-21 22:09:27,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 148 states and 168 transitions. [2023-11-21 22:09:27,606 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-21 22:09:27,607 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:27,607 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:27,608 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 17, 16, 16, 1, 1, 1, 1] [2023-11-21 22:09:27,608 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-21 22:09:27,609 INFO L748 eck$LassoCheckResult]: Stem: 11031#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 11015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 11016#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11032#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11033#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11019#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11020#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11068#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11067#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11066#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11065#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11064#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11063#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11062#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11061#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11060#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11059#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11058#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11057#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11056#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11055#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11054#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11053#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11052#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11051#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11050#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11049#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11048#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11047#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11046#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11045#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11044#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11043#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11042#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11041#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int#1(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11038#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11037#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 11021#L27-4 main_~i~0#1 := 0; 11022#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11028#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11014#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11025#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11030#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11153#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11152#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11150#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11147#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11146#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11144#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11141#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11140#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11138#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11135#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11134#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11132#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11129#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11128#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11126#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11123#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11122#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11120#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11117#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11116#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11114#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11111#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11110#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11108#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11105#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11104#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11102#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11099#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11098#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11096#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11093#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11092#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11090#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11087#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11086#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11084#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11081#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11080#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11078#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11076#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11075#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11072#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11070#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11069#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11036#L34 [2023-11-21 22:09:27,609 INFO L750 eck$LassoCheckResult]: Loop: 11036#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11039#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11035#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11036#L34 [2023-11-21 22:09:27,610 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:27,610 INFO L85 PathProgramCache]: Analyzing trace with hash -1481235061, now seen corresponding path program 32 times [2023-11-21 22:09:27,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:27,610 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074689673] [2023-11-21 22:09:27,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:27,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:27,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:27,776 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:27,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:27,936 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:27,938 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:27,938 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 18 times [2023-11-21 22:09:27,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:27,938 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795568271] [2023-11-21 22:09:27,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:27,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:27,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:27,945 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:09:27,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:09:27,950 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:09:27,951 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:27,951 INFO L85 PathProgramCache]: Analyzing trace with hash -979656437, now seen corresponding path program 33 times [2023-11-21 22:09:27,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:27,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063078771] [2023-11-21 22:09:27,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:27,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:28,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:29,369 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 376 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:29,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:29,369 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1063078771] [2023-11-21 22:09:29,369 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1063078771] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-21 22:09:29,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1098505495] [2023-11-21 22:09:29,370 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-21 22:09:29,370 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-21 22:09:29,370 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:29,372 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-21 22:09:29,374 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26a9fc37-f6eb-44ab-a447-6cf2d08211db/bin/uautomizer-verify-bycVGegfSx/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2023-11-21 22:09:29,955 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2023-11-21 22:09:29,955 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-21 22:09:29,959 INFO L262 TraceCheckSpWp]: Trace formula consists of 398 conjuncts, 38 conjunts are in the unsatisfiable core [2023-11-21 22:09:29,998 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:09:30,984 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:30,985 INFO L327 TraceCheckSpWp]: Computing backward predicates...