./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 527bcce2 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea --- Real Ultimate output --- This is Ultimate 0.2.3-dev-527bcce [2023-11-21 22:10:38,860 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-21 22:10:39,048 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-21 22:10:39,058 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-21 22:10:39,059 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-21 22:10:39,110 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-21 22:10:39,111 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-21 22:10:39,112 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-21 22:10:39,113 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-21 22:10:39,119 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-21 22:10:39,121 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-21 22:10:39,122 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-21 22:10:39,122 INFO L153 SettingsManager]: * Use SBE=true [2023-11-21 22:10:39,125 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-21 22:10:39,125 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-21 22:10:39,126 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-21 22:10:39,126 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-21 22:10:39,127 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-21 22:10:39,127 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-21 22:10:39,128 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-21 22:10:39,128 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-21 22:10:39,129 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-21 22:10:39,130 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-21 22:10:39,130 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-21 22:10:39,130 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-21 22:10:39,131 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-21 22:10:39,131 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-21 22:10:39,132 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-21 22:10:39,132 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-21 22:10:39,133 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-21 22:10:39,134 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-21 22:10:39,135 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-21 22:10:39,135 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-21 22:10:39,135 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-21 22:10:39,136 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-21 22:10:39,136 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-21 22:10:39,136 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-21 22:10:39,137 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-21 22:10:39,137 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea [2023-11-21 22:10:39,581 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-21 22:10:39,627 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-21 22:10:39,630 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-21 22:10:39,632 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-21 22:10:39,633 INFO L274 PluginConnector]: CDTParser initialized [2023-11-21 22:10:39,636 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2023-11-21 22:10:42,903 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-21 22:10:43,200 INFO L384 CDTParser]: Found 1 translation units. [2023-11-21 22:10:43,201 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2023-11-21 22:10:43,217 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/data/666121d58/3cfcc0952d2f434da991bca9509477c3/FLAG34eb10c89 [2023-11-21 22:10:43,238 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/data/666121d58/3cfcc0952d2f434da991bca9509477c3 [2023-11-21 22:10:43,241 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-21 22:10:43,244 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-21 22:10:43,246 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-21 22:10:43,246 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-21 22:10:43,254 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-21 22:10:43,255 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:43,257 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5257a84e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43, skipping insertion in model container [2023-11-21 22:10:43,257 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:43,334 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-21 22:10:43,670 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 22:10:43,689 INFO L202 MainTranslator]: Completed pre-run [2023-11-21 22:10:43,783 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 22:10:43,815 INFO L206 MainTranslator]: Completed translation [2023-11-21 22:10:43,815 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43 WrapperNode [2023-11-21 22:10:43,815 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-21 22:10:43,817 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-21 22:10:43,817 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-21 22:10:43,817 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-21 22:10:43,826 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:43,839 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:43,910 INFO L138 Inliner]: procedures = 36, calls = 45, calls flagged for inlining = 40, calls inlined = 80, statements flattened = 1087 [2023-11-21 22:10:43,911 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-21 22:10:43,912 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-21 22:10:43,912 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-21 22:10:43,912 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-21 22:10:43,927 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:43,927 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:43,936 INFO L184 PluginConnector]: Executing the observer HeapSplitter from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:43,958 INFO L187 HeapSplitter]: Split 2 memory accesses to 1 slices as follows [2] [2023-11-21 22:10:43,959 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:43,959 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:43,983 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:44,000 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:44,005 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:44,010 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:44,018 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-21 22:10:44,019 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-21 22:10:44,019 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-21 22:10:44,024 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-21 22:10:44,029 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (1/1) ... [2023-11-21 22:10:44,036 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:10:44,053 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:10:44,076 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:10:44,092 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-21 22:10:44,122 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-21 22:10:44,123 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-21 22:10:44,123 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-21 22:10:44,123 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-21 22:10:44,281 INFO L240 CfgBuilder]: Building ICFG [2023-11-21 22:10:44,284 INFO L266 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-21 22:10:45,568 INFO L281 CfgBuilder]: Performing block encoding [2023-11-21 22:10:45,603 INFO L303 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-21 22:10:45,604 INFO L308 CfgBuilder]: Removed 7 assume(true) statements. [2023-11-21 22:10:45,606 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:10:45 BoogieIcfgContainer [2023-11-21 22:10:45,606 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-21 22:10:45,612 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-21 22:10:45,612 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-21 22:10:45,617 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-21 22:10:45,618 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:10:45,619 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.11 10:10:43" (1/3) ... [2023-11-21 22:10:45,620 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5fcd97ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 10:10:45, skipping insertion in model container [2023-11-21 22:10:45,620 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:10:45,621 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:10:43" (2/3) ... [2023-11-21 22:10:45,621 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5fcd97ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 10:10:45, skipping insertion in model container [2023-11-21 22:10:45,621 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:10:45,621 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:10:45" (3/3) ... [2023-11-21 22:10:45,623 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2023-11-21 22:10:45,723 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-21 22:10:45,724 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-21 22:10:45,724 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-21 22:10:45,725 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-21 22:10:45,725 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-21 22:10:45,725 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-21 22:10:45,725 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-21 22:10:45,726 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-21 22:10:45,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:45,826 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 374 [2023-11-21 22:10:45,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:45,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:45,853 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:45,853 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:45,853 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-21 22:10:45,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:45,877 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 374 [2023-11-21 22:10:45,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:45,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:45,891 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:45,891 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:45,904 INFO L748 eck$LassoCheckResult]: Stem: 142#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 364#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 220#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 359#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49#L365true assume !(1 == ~m_i~0);~m_st~0 := 2; 334#L365-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 233#L370-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 187#L375-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 341#L380-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 213#L385-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 195#L526true assume !(0 == ~M_E~0); 421#L526-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 236#L531-1true assume !(0 == ~T2_E~0); 185#L536-1true assume !(0 == ~T3_E~0); 296#L541-1true assume !(0 == ~T4_E~0); 183#L546-1true assume !(0 == ~E_M~0); 248#L551-1true assume !(0 == ~E_1~0); 165#L556-1true assume !(0 == ~E_2~0); 192#L561-1true assume !(0 == ~E_3~0); 172#L566-1true assume 0 == ~E_4~0;~E_4~0 := 1; 376#L571-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168#L262true assume 1 == ~m_pc~0; 443#L263true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 380#L273true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 377#L649true assume !(0 != activate_threads_~tmp~1#1); 438#L649-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129#L281true assume !(1 == ~t1_pc~0); 394#L281-2true is_transmit1_triggered_~__retres1~1#1 := 0; 79#L292true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115#L657true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 361#L657-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175#L300true assume 1 == ~t2_pc~0; 308#L301true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 274#L311true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190#L665true assume !(0 != activate_threads_~tmp___1~0#1); 38#L665-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 445#L319true assume !(1 == ~t3_pc~0); 17#L319-2true is_transmit3_triggered_~__retres1~3#1 := 0; 277#L330true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141#L673true assume !(0 != activate_threads_~tmp___2~0#1); 27#L673-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278#L338true assume 1 == ~t4_pc~0; 112#L339true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73#L349true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 384#L681true assume !(0 != activate_threads_~tmp___3~0#1); 2#L681-2true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 374#L584true assume !(1 == ~M_E~0); 113#L584-2true assume !(1 == ~T1_E~0); 88#L589-1true assume !(1 == ~T2_E~0); 262#L594-1true assume !(1 == ~T3_E~0); 144#L599-1true assume !(1 == ~T4_E~0); 16#L604-1true assume !(1 == ~E_M~0); 9#L609-1true assume 1 == ~E_1~0;~E_1~0 := 2; 72#L614-1true assume !(1 == ~E_2~0); 125#L619-1true assume !(1 == ~E_3~0); 188#L624-1true assume !(1 == ~E_4~0); 401#L629-1true assume { :end_inline_reset_delta_events } true; 207#L815-2true [2023-11-21 22:10:45,916 INFO L750 eck$LassoCheckResult]: Loop: 207#L815-2true assume !false; 388#L816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 420#L501-1true assume false; 74#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 325#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 145#L526-3true assume 0 == ~M_E~0;~M_E~0 := 1; 268#L526-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 75#L531-3true assume !(0 == ~T2_E~0); 395#L536-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 13#L541-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 189#L546-3true assume 0 == ~E_M~0;~E_M~0 := 1; 439#L551-3true assume 0 == ~E_1~0;~E_1~0 := 1; 154#L556-3true assume 0 == ~E_2~0;~E_2~0 := 1; 243#L561-3true assume 0 == ~E_3~0;~E_3~0 := 1; 318#L566-3true assume 0 == ~E_4~0;~E_4~0 := 1; 81#L571-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 267#L262-18true assume !(1 == ~m_pc~0); 137#L262-20true is_master_triggered_~__retres1~0#1 := 0; 292#L273-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149#is_master_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 373#L649-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20#L649-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163#L281-18true assume !(1 == ~t1_pc~0); 271#L281-20true is_transmit1_triggered_~__retres1~1#1 := 0; 178#L292-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 368#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 418#L657-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 293#L657-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 333#L300-18true assume !(1 == ~t2_pc~0); 14#L300-20true is_transmit2_triggered_~__retres1~2#1 := 0; 47#L311-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 217#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 255#L665-18true assume !(0 != activate_threads_~tmp___1~0#1); 319#L665-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80#L319-18true assume !(1 == ~t3_pc~0); 247#L319-20true is_transmit3_triggered_~__retres1~3#1 := 0; 96#L330-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 241#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 219#L673-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 204#L673-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128#L338-18true assume !(1 == ~t4_pc~0); 161#L338-20true is_transmit4_triggered_~__retres1~4#1 := 0; 106#L349-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29#L681-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 179#L681-20true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140#L584-3true assume 1 == ~M_E~0;~M_E~0 := 2; 290#L584-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 28#L589-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 135#L594-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 216#L599-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 156#L604-3true assume 1 == ~E_M~0;~E_M~0 := 2; 406#L609-3true assume 1 == ~E_1~0;~E_1~0 := 2; 203#L614-3true assume !(1 == ~E_2~0); 24#L619-3true assume 1 == ~E_3~0;~E_3~0 := 2; 214#L624-3true assume 1 == ~E_4~0;~E_4~0 := 2; 249#L629-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 257#L398-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68#L425-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 199#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 101#L834true assume !(0 == start_simulation_~tmp~3#1); 223#L834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 355#L398-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 218#L425-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 295#L789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 305#L796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 336#stop_simulation_returnLabel#1true start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 205#L847true assume !(0 != start_simulation_~tmp___0~1#1); 207#L815-2true [2023-11-21 22:10:45,924 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:45,929 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2023-11-21 22:10:45,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:45,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056475401] [2023-11-21 22:10:45,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:45,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:46,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:46,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:46,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:46,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056475401] [2023-11-21 22:10:46,337 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1056475401] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:46,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:46,337 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:46,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [405829105] [2023-11-21 22:10:46,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:46,346 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:46,347 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:46,347 INFO L85 PathProgramCache]: Analyzing trace with hash 315649613, now seen corresponding path program 1 times [2023-11-21 22:10:46,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:46,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84753734] [2023-11-21 22:10:46,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:46,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:46,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:46,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:46,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:46,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84753734] [2023-11-21 22:10:46,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [84753734] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:46,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:46,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:10:46,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [387665514] [2023-11-21 22:10:46,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:46,429 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:46,431 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:46,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:46,476 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:46,479 INFO L87 Difference]: Start difference. First operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:46,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:46,545 INFO L93 Difference]: Finished difference Result 441 states and 657 transitions. [2023-11-21 22:10:46,547 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 441 states and 657 transitions. [2023-11-21 22:10:46,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-21 22:10:46,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 441 states to 435 states and 651 transitions. [2023-11-21 22:10:46,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2023-11-21 22:10:46,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2023-11-21 22:10:46,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 651 transitions. [2023-11-21 22:10:46,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:46,577 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 651 transitions. [2023-11-21 22:10:46,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 651 transitions. [2023-11-21 22:10:46,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2023-11-21 22:10:46,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4965517241379311) internal successors, (651), 434 states have internal predecessors, (651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:46,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 651 transitions. [2023-11-21 22:10:46,643 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 651 transitions. [2023-11-21 22:10:46,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:46,649 INFO L428 stractBuchiCegarLoop]: Abstraction has 435 states and 651 transitions. [2023-11-21 22:10:46,649 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-21 22:10:46,650 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 651 transitions. [2023-11-21 22:10:46,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-21 22:10:46,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:46,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:46,657 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:46,657 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:46,658 INFO L748 eck$LassoCheckResult]: Stem: 1142#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1143#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1235#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1236#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 992#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 993#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1244#L370-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1205#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1206#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1230#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1215#L526 assume !(0 == ~M_E~0); 1216#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1246#L531-1 assume !(0 == ~T2_E~0); 1201#L536-1 assume !(0 == ~T3_E~0); 1202#L541-1 assume !(0 == ~T4_E~0); 1197#L546-1 assume !(0 == ~E_M~0); 1198#L551-1 assume !(0 == ~E_1~0); 1173#L556-1 assume !(0 == ~E_2~0); 1174#L561-1 assume !(0 == ~E_3~0); 1184#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1185#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1178#L262 assume 1 == ~m_pc~0; 1179#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1324#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1112#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1113#L649 assume !(0 != activate_threads_~tmp~1#1); 1323#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1122#L281 assume !(1 == ~t1_pc~0); 1123#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1043#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 959#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 960#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1099#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1187#L300 assume 1 == ~t2_pc~0; 1188#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1277#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1238#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1209#L665 assume !(0 != activate_threads_~tmp___1~0#1); 972#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 973#L319 assume !(1 == ~t3_pc~0); 928#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 929#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 915#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 916#L673 assume !(0 != activate_threads_~tmp___2~0#1); 949#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 950#L338 assume 1 == ~t4_pc~0; 1095#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1018#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1023#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1024#L681 assume !(0 != activate_threads_~tmp___3~0#1); 895#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 896#L584 assume !(1 == ~M_E~0); 1096#L584-2 assume !(1 == ~T1_E~0); 1057#L589-1 assume !(1 == ~T2_E~0); 1058#L594-1 assume !(1 == ~T3_E~0); 1146#L599-1 assume !(1 == ~T4_E~0); 927#L604-1 assume !(1 == ~E_M~0); 913#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 914#L614-1 assume !(1 == ~E_2~0); 1032#L619-1 assume !(1 == ~E_3~0); 1114#L624-1 assume !(1 == ~E_4~0); 1207#L629-1 assume { :end_inline_reset_delta_events } true; 1226#L815-2 [2023-11-21 22:10:46,659 INFO L750 eck$LassoCheckResult]: Loop: 1226#L815-2 assume !false; 1227#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1104#L501-1 assume !false; 1320#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1321#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1038#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1251#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1252#L440 assume !(0 != eval_~tmp~0#1); 1033#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1034#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1147#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1148#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1035#L531-3 assume !(0 == ~T2_E~0); 1036#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 921#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 922#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1208#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1159#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1160#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1256#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1047#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1048#L262-18 assume 1 == ~m_pc~0; 1271#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1136#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1153#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1154#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 934#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 935#L281-18 assume 1 == ~t1_pc~0; 1170#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1190#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1191#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1322#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1293#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1294#L300-18 assume 1 == ~t2_pc~0; 1168#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 924#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 991#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1233#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 1262#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1044#L319-18 assume 1 == ~t3_pc~0; 1045#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1050#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1071#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1234#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1224#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1119#L338-18 assume !(1 == ~t4_pc~0); 1120#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1088#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1089#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 953#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 954#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1140#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1141#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 951#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 952#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1133#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1162#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1163#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1223#L614-3 assume !(1 == ~E_2~0); 943#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 944#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1231#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1260#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1026#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1027#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1078#L834 assume !(0 == start_simulation_~tmp~3#1); 1079#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1239#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1200#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 957#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 958#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1295#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1300#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1225#L847 assume !(0 != start_simulation_~tmp___0~1#1); 1226#L815-2 [2023-11-21 22:10:46,660 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:46,660 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2023-11-21 22:10:46,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:46,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435512442] [2023-11-21 22:10:46,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:46,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:46,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:46,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:46,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:46,743 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [435512442] [2023-11-21 22:10:46,743 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [435512442] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:46,744 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:46,744 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:46,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380874455] [2023-11-21 22:10:46,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:46,745 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:46,745 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:46,746 INFO L85 PathProgramCache]: Analyzing trace with hash -1098449818, now seen corresponding path program 1 times [2023-11-21 22:10:46,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:46,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203692589] [2023-11-21 22:10:46,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:46,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:46,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:46,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:46,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:46,884 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203692589] [2023-11-21 22:10:46,884 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203692589] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:46,884 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:46,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:46,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432497211] [2023-11-21 22:10:46,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:46,886 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:46,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:46,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:46,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:46,887 INFO L87 Difference]: Start difference. First operand 435 states and 651 transitions. cyclomatic complexity: 217 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:46,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:46,916 INFO L93 Difference]: Finished difference Result 435 states and 650 transitions. [2023-11-21 22:10:46,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 650 transitions. [2023-11-21 22:10:46,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-21 22:10:46,925 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 650 transitions. [2023-11-21 22:10:46,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2023-11-21 22:10:46,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2023-11-21 22:10:46,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 650 transitions. [2023-11-21 22:10:46,931 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:46,931 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 650 transitions. [2023-11-21 22:10:46,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 650 transitions. [2023-11-21 22:10:46,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2023-11-21 22:10:46,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4942528735632183) internal successors, (650), 434 states have internal predecessors, (650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:46,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 650 transitions. [2023-11-21 22:10:46,951 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 650 transitions. [2023-11-21 22:10:46,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:46,952 INFO L428 stractBuchiCegarLoop]: Abstraction has 435 states and 650 transitions. [2023-11-21 22:10:46,953 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-21 22:10:46,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 650 transitions. [2023-11-21 22:10:46,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-21 22:10:46,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:46,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:46,959 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:46,959 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:46,960 INFO L748 eck$LassoCheckResult]: Stem: 2019#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2112#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2113#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1869#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 1870#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2121#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2082#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2083#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2107#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2092#L526 assume !(0 == ~M_E~0); 2093#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2123#L531-1 assume !(0 == ~T2_E~0); 2078#L536-1 assume !(0 == ~T3_E~0); 2079#L541-1 assume !(0 == ~T4_E~0); 2074#L546-1 assume !(0 == ~E_M~0); 2075#L551-1 assume !(0 == ~E_1~0); 2050#L556-1 assume !(0 == ~E_2~0); 2051#L561-1 assume !(0 == ~E_3~0); 2061#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2062#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2055#L262 assume 1 == ~m_pc~0; 2056#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2201#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1989#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1990#L649 assume !(0 != activate_threads_~tmp~1#1); 2200#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1999#L281 assume !(1 == ~t1_pc~0); 2000#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1920#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1836#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1837#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1976#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2064#L300 assume 1 == ~t2_pc~0; 2065#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2154#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2115#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2086#L665 assume !(0 != activate_threads_~tmp___1~0#1); 1849#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1850#L319 assume !(1 == ~t3_pc~0); 1805#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1806#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1792#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1793#L673 assume !(0 != activate_threads_~tmp___2~0#1); 1826#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1827#L338 assume 1 == ~t4_pc~0; 1972#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1895#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1900#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1901#L681 assume !(0 != activate_threads_~tmp___3~0#1); 1772#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1773#L584 assume !(1 == ~M_E~0); 1973#L584-2 assume !(1 == ~T1_E~0); 1934#L589-1 assume !(1 == ~T2_E~0); 1935#L594-1 assume !(1 == ~T3_E~0); 2023#L599-1 assume !(1 == ~T4_E~0); 1804#L604-1 assume !(1 == ~E_M~0); 1790#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1791#L614-1 assume !(1 == ~E_2~0); 1909#L619-1 assume !(1 == ~E_3~0); 1991#L624-1 assume !(1 == ~E_4~0); 2084#L629-1 assume { :end_inline_reset_delta_events } true; 2103#L815-2 [2023-11-21 22:10:46,960 INFO L750 eck$LassoCheckResult]: Loop: 2103#L815-2 assume !false; 2104#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1981#L501-1 assume !false; 2197#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2198#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1915#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2128#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2129#L440 assume !(0 != eval_~tmp~0#1); 1910#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1911#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2024#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2025#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1912#L531-3 assume !(0 == ~T2_E~0); 1913#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1798#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1799#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2085#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2036#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2037#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2133#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1924#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1925#L262-18 assume 1 == ~m_pc~0; 2148#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2013#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2030#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2031#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1811#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1812#L281-18 assume !(1 == ~t1_pc~0); 2048#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2067#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2068#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2199#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2170#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2171#L300-18 assume !(1 == ~t2_pc~0); 1800#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 1801#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1868#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2110#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 2139#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1921#L319-18 assume 1 == ~t3_pc~0; 1922#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1927#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1948#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2111#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2101#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1996#L338-18 assume !(1 == ~t4_pc~0); 1997#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1965#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1966#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1830#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1831#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2017#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2018#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1828#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1829#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2010#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2039#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2040#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2100#L614-3 assume !(1 == ~E_2~0); 1820#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1821#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2108#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2137#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1903#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1904#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1955#L834 assume !(0 == start_simulation_~tmp~3#1); 1956#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2116#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2077#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1834#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1835#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2172#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2177#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2102#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2103#L815-2 [2023-11-21 22:10:46,961 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:46,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2023-11-21 22:10:46,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:46,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143332899] [2023-11-21 22:10:46,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:46,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:46,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:47,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:47,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:47,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143332899] [2023-11-21 22:10:47,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143332899] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:47,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:47,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:47,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338174235] [2023-11-21 22:10:47,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:47,023 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:47,024 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:47,024 INFO L85 PathProgramCache]: Analyzing trace with hash 817900584, now seen corresponding path program 1 times [2023-11-21 22:10:47,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:47,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27889309] [2023-11-21 22:10:47,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:47,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:47,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:47,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:47,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:47,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [27889309] [2023-11-21 22:10:47,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [27889309] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:47,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:47,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:47,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025506931] [2023-11-21 22:10:47,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:47,103 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:47,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:47,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:47,104 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:47,105 INFO L87 Difference]: Start difference. First operand 435 states and 650 transitions. cyclomatic complexity: 216 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:47,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:47,123 INFO L93 Difference]: Finished difference Result 435 states and 649 transitions. [2023-11-21 22:10:47,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 649 transitions. [2023-11-21 22:10:47,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-21 22:10:47,133 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 649 transitions. [2023-11-21 22:10:47,133 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2023-11-21 22:10:47,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2023-11-21 22:10:47,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 649 transitions. [2023-11-21 22:10:47,135 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:47,136 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 649 transitions. [2023-11-21 22:10:47,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 649 transitions. [2023-11-21 22:10:47,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2023-11-21 22:10:47,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4919540229885058) internal successors, (649), 434 states have internal predecessors, (649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:47,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 649 transitions. [2023-11-21 22:10:47,153 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 649 transitions. [2023-11-21 22:10:47,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:47,155 INFO L428 stractBuchiCegarLoop]: Abstraction has 435 states and 649 transitions. [2023-11-21 22:10:47,155 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-21 22:10:47,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 649 transitions. [2023-11-21 22:10:47,159 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-21 22:10:47,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:47,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:47,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:47,162 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:47,162 INFO L748 eck$LassoCheckResult]: Stem: 2896#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2989#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2990#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2746#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 2747#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2998#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2959#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2960#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2984#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2969#L526 assume !(0 == ~M_E~0); 2970#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3000#L531-1 assume !(0 == ~T2_E~0); 2955#L536-1 assume !(0 == ~T3_E~0); 2956#L541-1 assume !(0 == ~T4_E~0); 2951#L546-1 assume !(0 == ~E_M~0); 2952#L551-1 assume !(0 == ~E_1~0); 2927#L556-1 assume !(0 == ~E_2~0); 2928#L561-1 assume !(0 == ~E_3~0); 2938#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2939#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2932#L262 assume 1 == ~m_pc~0; 2933#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3078#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2866#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2867#L649 assume !(0 != activate_threads_~tmp~1#1); 3077#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2876#L281 assume !(1 == ~t1_pc~0); 2877#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2797#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2714#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2853#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2941#L300 assume 1 == ~t2_pc~0; 2942#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3031#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2992#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2963#L665 assume !(0 != activate_threads_~tmp___1~0#1); 2726#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2727#L319 assume !(1 == ~t3_pc~0); 2682#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2683#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2669#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2670#L673 assume !(0 != activate_threads_~tmp___2~0#1); 2703#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2704#L338 assume 1 == ~t4_pc~0; 2849#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2772#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2777#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2778#L681 assume !(0 != activate_threads_~tmp___3~0#1); 2649#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2650#L584 assume !(1 == ~M_E~0); 2850#L584-2 assume !(1 == ~T1_E~0); 2811#L589-1 assume !(1 == ~T2_E~0); 2812#L594-1 assume !(1 == ~T3_E~0); 2900#L599-1 assume !(1 == ~T4_E~0); 2681#L604-1 assume !(1 == ~E_M~0); 2667#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2668#L614-1 assume !(1 == ~E_2~0); 2786#L619-1 assume !(1 == ~E_3~0); 2868#L624-1 assume !(1 == ~E_4~0); 2961#L629-1 assume { :end_inline_reset_delta_events } true; 2980#L815-2 [2023-11-21 22:10:47,163 INFO L750 eck$LassoCheckResult]: Loop: 2980#L815-2 assume !false; 2981#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2858#L501-1 assume !false; 3074#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3075#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2792#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3005#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3006#L440 assume !(0 != eval_~tmp~0#1); 2787#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2788#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2901#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2902#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2789#L531-3 assume !(0 == ~T2_E~0); 2790#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2675#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2676#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2962#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2913#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2914#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3010#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2801#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2802#L262-18 assume 1 == ~m_pc~0; 3025#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2890#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2907#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2908#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2688#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2689#L281-18 assume 1 == ~t1_pc~0; 2924#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2944#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2945#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3076#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3047#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3048#L300-18 assume !(1 == ~t2_pc~0); 2677#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 2678#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2745#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2987#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 3016#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2798#L319-18 assume !(1 == ~t3_pc~0); 2800#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2804#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2825#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2988#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2978#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2873#L338-18 assume !(1 == ~t4_pc~0); 2874#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 2842#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2843#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2707#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2708#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2894#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2895#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2705#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2706#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2887#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2916#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2917#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2977#L614-3 assume !(1 == ~E_2~0); 2697#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2698#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2985#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3014#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2780#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2781#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2832#L834 assume !(0 == start_simulation_~tmp~3#1); 2833#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2993#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2954#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2712#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3049#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3054#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2979#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2980#L815-2 [2023-11-21 22:10:47,164 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:47,164 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2023-11-21 22:10:47,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:47,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339985535] [2023-11-21 22:10:47,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:47,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:47,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:47,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:47,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:47,218 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339985535] [2023-11-21 22:10:47,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339985535] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:47,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:47,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:47,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264380219] [2023-11-21 22:10:47,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:47,220 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:47,221 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:47,221 INFO L85 PathProgramCache]: Analyzing trace with hash -532175448, now seen corresponding path program 1 times [2023-11-21 22:10:47,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:47,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049085632] [2023-11-21 22:10:47,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:47,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:47,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:47,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:47,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:47,280 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1049085632] [2023-11-21 22:10:47,281 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1049085632] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:47,281 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:47,281 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:47,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394411861] [2023-11-21 22:10:47,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:47,282 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:47,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:47,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:47,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:47,284 INFO L87 Difference]: Start difference. First operand 435 states and 649 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:47,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:47,299 INFO L93 Difference]: Finished difference Result 435 states and 648 transitions. [2023-11-21 22:10:47,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 648 transitions. [2023-11-21 22:10:47,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-21 22:10:47,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 648 transitions. [2023-11-21 22:10:47,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2023-11-21 22:10:47,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2023-11-21 22:10:47,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 648 transitions. [2023-11-21 22:10:47,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:47,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 648 transitions. [2023-11-21 22:10:47,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 648 transitions. [2023-11-21 22:10:47,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2023-11-21 22:10:47,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4896551724137932) internal successors, (648), 434 states have internal predecessors, (648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:47,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 648 transitions. [2023-11-21 22:10:47,322 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 648 transitions. [2023-11-21 22:10:47,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:47,323 INFO L428 stractBuchiCegarLoop]: Abstraction has 435 states and 648 transitions. [2023-11-21 22:10:47,323 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-21 22:10:47,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 648 transitions. [2023-11-21 22:10:47,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-21 22:10:47,327 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:47,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:47,329 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:47,329 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:47,330 INFO L748 eck$LassoCheckResult]: Stem: 3773#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3623#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 3624#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3875#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3836#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3837#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3861#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3846#L526 assume !(0 == ~M_E~0); 3847#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3877#L531-1 assume !(0 == ~T2_E~0); 3832#L536-1 assume !(0 == ~T3_E~0); 3833#L541-1 assume !(0 == ~T4_E~0); 3828#L546-1 assume !(0 == ~E_M~0); 3829#L551-1 assume !(0 == ~E_1~0); 3804#L556-1 assume !(0 == ~E_2~0); 3805#L561-1 assume !(0 == ~E_3~0); 3815#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3816#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3809#L262 assume 1 == ~m_pc~0; 3810#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3955#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3743#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3744#L649 assume !(0 != activate_threads_~tmp~1#1); 3954#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3753#L281 assume !(1 == ~t1_pc~0); 3754#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3674#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3590#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3591#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3730#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3818#L300 assume 1 == ~t2_pc~0; 3819#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3908#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3869#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3840#L665 assume !(0 != activate_threads_~tmp___1~0#1); 3603#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3604#L319 assume !(1 == ~t3_pc~0); 3559#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3560#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3546#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3547#L673 assume !(0 != activate_threads_~tmp___2~0#1); 3580#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3581#L338 assume 1 == ~t4_pc~0; 3726#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3649#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3654#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3655#L681 assume !(0 != activate_threads_~tmp___3~0#1); 3526#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3527#L584 assume !(1 == ~M_E~0); 3727#L584-2 assume !(1 == ~T1_E~0); 3688#L589-1 assume !(1 == ~T2_E~0); 3689#L594-1 assume !(1 == ~T3_E~0); 3777#L599-1 assume !(1 == ~T4_E~0); 3558#L604-1 assume !(1 == ~E_M~0); 3544#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3545#L614-1 assume !(1 == ~E_2~0); 3663#L619-1 assume !(1 == ~E_3~0); 3745#L624-1 assume !(1 == ~E_4~0); 3838#L629-1 assume { :end_inline_reset_delta_events } true; 3857#L815-2 [2023-11-21 22:10:47,330 INFO L750 eck$LassoCheckResult]: Loop: 3857#L815-2 assume !false; 3858#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3735#L501-1 assume !false; 3951#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3952#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3669#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3882#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3883#L440 assume !(0 != eval_~tmp~0#1); 3664#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3665#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3778#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3779#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3666#L531-3 assume !(0 == ~T2_E~0); 3667#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3552#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3553#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3839#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3790#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3791#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3887#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3678#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3679#L262-18 assume !(1 == ~m_pc~0); 3766#L262-20 is_master_triggered_~__retres1~0#1 := 0; 3767#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3784#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3785#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3565#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3566#L281-18 assume 1 == ~t1_pc~0; 3801#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3821#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3822#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3953#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3924#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3925#L300-18 assume !(1 == ~t2_pc~0); 3554#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 3555#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3622#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3864#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 3893#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3675#L319-18 assume 1 == ~t3_pc~0; 3676#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3681#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3702#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3865#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3855#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3750#L338-18 assume !(1 == ~t4_pc~0); 3751#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3719#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3720#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3584#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3585#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3771#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3772#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3582#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3583#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3764#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3793#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3794#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3854#L614-3 assume !(1 == ~E_2~0); 3574#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3575#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3862#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3891#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3657#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3658#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3709#L834 assume !(0 == start_simulation_~tmp~3#1); 3710#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3870#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3831#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3588#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3589#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3926#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3931#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3856#L847 assume !(0 != start_simulation_~tmp___0~1#1); 3857#L815-2 [2023-11-21 22:10:47,331 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:47,332 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2023-11-21 22:10:47,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:47,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600509839] [2023-11-21 22:10:47,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:47,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:47,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:47,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:47,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:47,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600509839] [2023-11-21 22:10:47,453 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600509839] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:47,453 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:47,453 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:10:47,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602009607] [2023-11-21 22:10:47,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:47,454 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:47,454 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:47,454 INFO L85 PathProgramCache]: Analyzing trace with hash -1857403032, now seen corresponding path program 1 times [2023-11-21 22:10:47,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:47,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338768730] [2023-11-21 22:10:47,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:47,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:47,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:47,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:47,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:47,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338768730] [2023-11-21 22:10:47,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338768730] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:47,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:47,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:47,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779250355] [2023-11-21 22:10:47,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:47,538 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:47,538 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:47,538 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:47,543 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:47,544 INFO L87 Difference]: Start difference. First operand 435 states and 648 transitions. cyclomatic complexity: 214 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:47,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:47,587 INFO L93 Difference]: Finished difference Result 435 states and 643 transitions. [2023-11-21 22:10:47,587 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 643 transitions. [2023-11-21 22:10:47,591 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-21 22:10:47,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 643 transitions. [2023-11-21 22:10:47,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2023-11-21 22:10:47,603 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2023-11-21 22:10:47,603 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 643 transitions. [2023-11-21 22:10:47,604 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:47,605 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 643 transitions. [2023-11-21 22:10:47,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 643 transitions. [2023-11-21 22:10:47,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2023-11-21 22:10:47,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4781609195402299) internal successors, (643), 434 states have internal predecessors, (643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:47,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 643 transitions. [2023-11-21 22:10:47,617 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 643 transitions. [2023-11-21 22:10:47,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:47,620 INFO L428 stractBuchiCegarLoop]: Abstraction has 435 states and 643 transitions. [2023-11-21 22:10:47,620 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-21 22:10:47,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 643 transitions. [2023-11-21 22:10:47,623 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-21 22:10:47,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:47,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:47,627 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:47,627 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:47,628 INFO L748 eck$LassoCheckResult]: Stem: 4650#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4743#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4744#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4500#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 4501#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4753#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4713#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4714#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4739#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4723#L526 assume !(0 == ~M_E~0); 4724#L526-2 assume !(0 == ~T1_E~0); 4755#L531-1 assume !(0 == ~T2_E~0); 4709#L536-1 assume !(0 == ~T3_E~0); 4710#L541-1 assume !(0 == ~T4_E~0); 4705#L546-1 assume !(0 == ~E_M~0); 4706#L551-1 assume !(0 == ~E_1~0); 4681#L556-1 assume !(0 == ~E_2~0); 4682#L561-1 assume !(0 == ~E_3~0); 4692#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4693#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4686#L262 assume 1 == ~m_pc~0; 4687#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4832#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4620#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4621#L649 assume !(0 != activate_threads_~tmp~1#1); 4831#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4630#L281 assume !(1 == ~t1_pc~0); 4631#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4551#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4467#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4468#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4607#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4695#L300 assume 1 == ~t2_pc~0; 4696#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4785#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4746#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4717#L665 assume !(0 != activate_threads_~tmp___1~0#1); 4480#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4481#L319 assume !(1 == ~t3_pc~0); 4436#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4437#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4424#L673 assume !(0 != activate_threads_~tmp___2~0#1); 4457#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4458#L338 assume 1 == ~t4_pc~0; 4603#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4526#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4532#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4533#L681 assume !(0 != activate_threads_~tmp___3~0#1); 4403#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4404#L584 assume !(1 == ~M_E~0); 4604#L584-2 assume !(1 == ~T1_E~0); 4565#L589-1 assume !(1 == ~T2_E~0); 4566#L594-1 assume !(1 == ~T3_E~0); 4654#L599-1 assume !(1 == ~T4_E~0); 4435#L604-1 assume !(1 == ~E_M~0); 4421#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4422#L614-1 assume !(1 == ~E_2~0); 4540#L619-1 assume !(1 == ~E_3~0); 4622#L624-1 assume !(1 == ~E_4~0); 4715#L629-1 assume { :end_inline_reset_delta_events } true; 4734#L815-2 [2023-11-21 22:10:47,628 INFO L750 eck$LassoCheckResult]: Loop: 4734#L815-2 assume !false; 4735#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4612#L501-1 assume !false; 4828#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4829#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4546#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4759#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4760#L440 assume !(0 != eval_~tmp~0#1); 4541#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4542#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4655#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4656#L526-5 assume !(0 == ~T1_E~0); 4543#L531-3 assume !(0 == ~T2_E~0); 4544#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4431#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4432#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4716#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4667#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4668#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4763#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4555#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4556#L262-18 assume !(1 == ~m_pc~0); 4642#L262-20 is_master_triggered_~__retres1~0#1 := 0; 4643#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4661#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4662#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4442#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4443#L281-18 assume 1 == ~t1_pc~0; 4678#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4698#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4699#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4830#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4801#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4802#L300-18 assume 1 == ~t2_pc~0; 4676#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4430#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4499#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4741#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 4770#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4552#L319-18 assume 1 == ~t3_pc~0; 4553#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4558#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4579#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4742#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4732#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4627#L338-18 assume !(1 == ~t4_pc~0); 4628#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 4596#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4597#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4461#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4462#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4648#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4649#L584-5 assume !(1 == ~T1_E~0); 4459#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4460#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4641#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4670#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4671#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4731#L614-3 assume !(1 == ~E_2~0); 4451#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4452#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4738#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4768#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4534#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4535#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4586#L834 assume !(0 == start_simulation_~tmp~3#1); 4587#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4747#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4708#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4465#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4466#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4803#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4808#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4733#L847 assume !(0 != start_simulation_~tmp___0~1#1); 4734#L815-2 [2023-11-21 22:10:47,630 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:47,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2023-11-21 22:10:47,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:47,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041556668] [2023-11-21 22:10:47,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:47,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:47,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:47,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:47,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:47,748 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041556668] [2023-11-21 22:10:47,748 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2041556668] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:47,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:47,748 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:47,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143371968] [2023-11-21 22:10:47,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:47,749 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:47,750 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:47,750 INFO L85 PathProgramCache]: Analyzing trace with hash -1570770201, now seen corresponding path program 1 times [2023-11-21 22:10:47,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:47,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1606743103] [2023-11-21 22:10:47,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:47,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:47,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:47,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:47,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:47,789 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1606743103] [2023-11-21 22:10:47,789 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1606743103] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:47,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:47,790 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:47,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858439766] [2023-11-21 22:10:47,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:47,791 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:47,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:47,791 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 22:10:47,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 22:10:47,792 INFO L87 Difference]: Start difference. First operand 435 states and 643 transitions. cyclomatic complexity: 209 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:47,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:47,931 INFO L93 Difference]: Finished difference Result 730 states and 1076 transitions. [2023-11-21 22:10:47,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 730 states and 1076 transitions. [2023-11-21 22:10:47,938 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2023-11-21 22:10:47,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 730 states to 730 states and 1076 transitions. [2023-11-21 22:10:47,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 730 [2023-11-21 22:10:47,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 730 [2023-11-21 22:10:47,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 730 states and 1076 transitions. [2023-11-21 22:10:47,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:47,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 730 states and 1076 transitions. [2023-11-21 22:10:47,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 730 states and 1076 transitions. [2023-11-21 22:10:47,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 730 to 729. [2023-11-21 22:10:47,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 729 states have (on average 1.4746227709190671) internal successors, (1075), 728 states have internal predecessors, (1075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:47,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1075 transitions. [2023-11-21 22:10:47,968 INFO L240 hiAutomatonCegarLoop]: Abstraction has 729 states and 1075 transitions. [2023-11-21 22:10:47,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 22:10:47,971 INFO L428 stractBuchiCegarLoop]: Abstraction has 729 states and 1075 transitions. [2023-11-21 22:10:47,972 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-21 22:10:47,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 729 states and 1075 transitions. [2023-11-21 22:10:47,979 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2023-11-21 22:10:47,979 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:47,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:47,984 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:47,984 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:47,991 INFO L748 eck$LassoCheckResult]: Stem: 5825#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5920#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5921#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5675#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 5676#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5930#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5888#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5889#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5915#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5899#L526 assume !(0 == ~M_E~0); 5900#L526-2 assume !(0 == ~T1_E~0); 5932#L531-1 assume !(0 == ~T2_E~0); 5884#L536-1 assume !(0 == ~T3_E~0); 5885#L541-1 assume !(0 == ~T4_E~0); 5880#L546-1 assume !(0 == ~E_M~0); 5881#L551-1 assume !(0 == ~E_1~0); 5856#L556-1 assume !(0 == ~E_2~0); 5857#L561-1 assume !(0 == ~E_3~0); 5867#L566-1 assume !(0 == ~E_4~0); 5868#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5861#L262 assume 1 == ~m_pc~0; 5862#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6011#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5795#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5796#L649 assume !(0 != activate_threads_~tmp~1#1); 6010#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5805#L281 assume !(1 == ~t1_pc~0); 5806#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5726#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5643#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5782#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5870#L300 assume 1 == ~t2_pc~0; 5871#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5963#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5923#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5892#L665 assume !(0 != activate_threads_~tmp___1~0#1); 5655#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5656#L319 assume !(1 == ~t3_pc~0); 5611#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5612#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5598#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5599#L673 assume !(0 != activate_threads_~tmp___2~0#1); 5632#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5633#L338 assume 1 == ~t4_pc~0; 5778#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5701#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5707#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5708#L681 assume !(0 != activate_threads_~tmp___3~0#1); 5578#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5579#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 6009#L584-2 assume !(1 == ~T1_E~0); 6279#L589-1 assume !(1 == ~T2_E~0); 6278#L594-1 assume !(1 == ~T3_E~0); 5829#L599-1 assume !(1 == ~T4_E~0); 5610#L604-1 assume !(1 == ~E_M~0); 5596#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5597#L614-1 assume !(1 == ~E_2~0); 5715#L619-1 assume !(1 == ~E_3~0); 5797#L624-1 assume !(1 == ~E_4~0); 5890#L629-1 assume { :end_inline_reset_delta_events } true; 5910#L815-2 [2023-11-21 22:10:47,992 INFO L750 eck$LassoCheckResult]: Loop: 5910#L815-2 assume !false; 5911#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5787#L501-1 assume !false; 6006#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6007#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5721#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5936#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5937#L440 assume !(0 != eval_~tmp~0#1); 6015#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6021#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6019#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6020#L526-5 assume !(0 == ~T1_E~0); 6306#L531-3 assume !(0 == ~T2_E~0); 6305#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6304#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6303#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6302#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6301#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6300#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6299#L566-3 assume !(0 == ~E_4~0); 6298#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6297#L262-18 assume 1 == ~m_pc~0; 6295#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6294#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6293#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6292#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6291#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6290#L281-18 assume !(1 == ~t1_pc~0); 6288#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6287#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6286#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6285#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6284#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6283#L300-18 assume 1 == ~t2_pc~0; 6281#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6280#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5917#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5918#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 5947#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5727#L319-18 assume 1 == ~t3_pc~0; 5728#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5733#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5754#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5919#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5908#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5802#L338-18 assume !(1 == ~t4_pc~0); 5803#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 5771#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5772#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5636#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5637#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5821#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5822#L584-5 assume !(1 == ~T1_E~0); 5634#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5635#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5816#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5844#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5845#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5907#L614-3 assume !(1 == ~E_2~0); 5626#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5627#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5914#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5945#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5709#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5710#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5761#L834 assume !(0 == start_simulation_~tmp~3#1); 5762#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5924#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5883#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5641#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5981#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5986#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5909#L847 assume !(0 != start_simulation_~tmp___0~1#1); 5910#L815-2 [2023-11-21 22:10:47,993 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:47,996 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2023-11-21 22:10:47,996 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:47,996 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512170664] [2023-11-21 22:10:47,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:47,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:48,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:48,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:48,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:48,052 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512170664] [2023-11-21 22:10:48,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1512170664] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:48,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:48,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:10:48,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [882097576] [2023-11-21 22:10:48,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:48,054 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:48,054 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:48,055 INFO L85 PathProgramCache]: Analyzing trace with hash -1803648471, now seen corresponding path program 1 times [2023-11-21 22:10:48,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:48,055 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166363152] [2023-11-21 22:10:48,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:48,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:48,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:48,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:48,126 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:48,126 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166363152] [2023-11-21 22:10:48,126 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [166363152] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:48,127 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:48,127 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:48,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [558955709] [2023-11-21 22:10:48,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:48,128 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:48,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:48,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:48,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:48,129 INFO L87 Difference]: Start difference. First operand 729 states and 1075 transitions. cyclomatic complexity: 348 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:48,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:48,210 INFO L93 Difference]: Finished difference Result 1354 states and 1970 transitions. [2023-11-21 22:10:48,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1354 states and 1970 transitions. [2023-11-21 22:10:48,226 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1274 [2023-11-21 22:10:48,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1354 states to 1354 states and 1970 transitions. [2023-11-21 22:10:48,239 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1354 [2023-11-21 22:10:48,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1354 [2023-11-21 22:10:48,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1354 states and 1970 transitions. [2023-11-21 22:10:48,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:48,244 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1354 states and 1970 transitions. [2023-11-21 22:10:48,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1354 states and 1970 transitions. [2023-11-21 22:10:48,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1354 to 1286. [2023-11-21 22:10:48,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1286 states, 1286 states have (on average 1.4587869362363919) internal successors, (1876), 1285 states have internal predecessors, (1876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:48,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1286 states to 1286 states and 1876 transitions. [2023-11-21 22:10:48,283 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1286 states and 1876 transitions. [2023-11-21 22:10:48,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:48,284 INFO L428 stractBuchiCegarLoop]: Abstraction has 1286 states and 1876 transitions. [2023-11-21 22:10:48,284 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-21 22:10:48,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1286 states and 1876 transitions. [2023-11-21 22:10:48,294 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1206 [2023-11-21 22:10:48,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:48,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:48,296 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:48,297 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:48,297 INFO L748 eck$LassoCheckResult]: Stem: 7927#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7928#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8027#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7768#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 7769#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8040#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7993#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7994#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8021#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8005#L526 assume !(0 == ~M_E~0); 8006#L526-2 assume !(0 == ~T1_E~0); 8043#L531-1 assume !(0 == ~T2_E~0); 7989#L536-1 assume !(0 == ~T3_E~0); 7990#L541-1 assume !(0 == ~T4_E~0); 7985#L546-1 assume !(0 == ~E_M~0); 7986#L551-1 assume !(0 == ~E_1~0); 7961#L556-1 assume !(0 == ~E_2~0); 7962#L561-1 assume !(0 == ~E_3~0); 7971#L566-1 assume !(0 == ~E_4~0); 7972#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7966#L262 assume !(1 == ~m_pc~0); 7967#L262-2 is_master_triggered_~__retres1~0#1 := 0; 8157#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7896#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7897#L649 assume !(0 != activate_threads_~tmp~1#1); 8155#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7906#L281 assume !(1 == ~t1_pc~0); 7907#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7820#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7732#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7733#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7880#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7974#L300 assume 1 == ~t2_pc~0; 7975#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8082#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8031#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7997#L665 assume !(0 != activate_threads_~tmp___1~0#1); 7745#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7746#L319 assume !(1 == ~t3_pc~0); 7701#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7702#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7688#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7689#L673 assume !(0 != activate_threads_~tmp___2~0#1); 7722#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7723#L338 assume 1 == ~t4_pc~0; 7876#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7793#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7798#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7799#L681 assume !(0 != activate_threads_~tmp___3~0#1); 7668#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7669#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 7877#L584-2 assume !(1 == ~T1_E~0); 7834#L589-1 assume !(1 == ~T2_E~0); 7835#L594-1 assume !(1 == ~T3_E~0); 7931#L599-1 assume !(1 == ~T4_E~0); 7700#L604-1 assume !(1 == ~E_M~0); 7686#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7687#L614-1 assume !(1 == ~E_2~0); 7808#L619-1 assume !(1 == ~E_3~0); 7898#L624-1 assume !(1 == ~E_4~0); 7995#L629-1 assume { :end_inline_reset_delta_events } true; 8016#L815-2 [2023-11-21 22:10:48,298 INFO L750 eck$LassoCheckResult]: Loop: 8016#L815-2 assume !false; 8018#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7885#L501-1 assume !false; 8149#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8150#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7814#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8048#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8049#L440 assume !(0 != eval_~tmp~0#1); 8172#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8686#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8685#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8075#L526-5 assume !(0 == ~T1_E~0); 8076#L531-3 assume !(0 == ~T2_E~0); 8895#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8892#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8890#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8888#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8886#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8884#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8882#L566-3 assume !(0 == ~E_4~0); 8881#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8878#L262-18 assume !(1 == ~m_pc~0); 8876#L262-20 is_master_triggered_~__retres1~0#1 := 0; 8874#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8872#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8870#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8868#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8865#L281-18 assume !(1 == ~t1_pc~0); 8862#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 8860#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8858#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8856#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8854#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8851#L300-18 assume 1 == ~t2_pc~0; 8848#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8846#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8844#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8843#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 8842#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8841#L319-18 assume 1 == ~t3_pc~0; 8839#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8838#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8837#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8836#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8835#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8834#L338-18 assume !(1 == ~t4_pc~0); 7956#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 7868#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7869#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7726#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7727#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7925#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7926#L584-5 assume !(1 == ~T1_E~0); 7724#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7725#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7916#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7949#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7950#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8013#L614-3 assume !(1 == ~E_2~0); 7716#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7717#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8022#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8059#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7802#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 7858#L834 assume !(0 == start_simulation_~tmp~3#1); 7859#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8032#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7988#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7730#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 7731#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8105#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8113#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 8015#L847 assume !(0 != start_simulation_~tmp___0~1#1); 8016#L815-2 [2023-11-21 22:10:48,298 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:48,299 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2023-11-21 22:10:48,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:48,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514707394] [2023-11-21 22:10:48,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:48,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:48,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:48,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:48,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:48,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514707394] [2023-11-21 22:10:48,359 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514707394] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:48,359 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:48,360 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:10:48,360 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [659884774] [2023-11-21 22:10:48,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:48,360 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:48,361 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:48,361 INFO L85 PathProgramCache]: Analyzing trace with hash -2077426966, now seen corresponding path program 1 times [2023-11-21 22:10:48,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:48,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927975920] [2023-11-21 22:10:48,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:48,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:48,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:48,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:48,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:48,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927975920] [2023-11-21 22:10:48,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927975920] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:48,409 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:48,409 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:48,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1042986255] [2023-11-21 22:10:48,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:48,410 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:48,410 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:48,411 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:10:48,411 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:10:48,412 INFO L87 Difference]: Start difference. First operand 1286 states and 1876 transitions. cyclomatic complexity: 594 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:48,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:48,643 INFO L93 Difference]: Finished difference Result 2982 states and 4291 transitions. [2023-11-21 22:10:48,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2982 states and 4291 transitions. [2023-11-21 22:10:48,675 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2830 [2023-11-21 22:10:48,701 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2982 states to 2982 states and 4291 transitions. [2023-11-21 22:10:48,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2982 [2023-11-21 22:10:48,704 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2982 [2023-11-21 22:10:48,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2982 states and 4291 transitions. [2023-11-21 22:10:48,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:48,710 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2982 states and 4291 transitions. [2023-11-21 22:10:48,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2982 states and 4291 transitions. [2023-11-21 22:10:48,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2982 to 1355. [2023-11-21 22:10:48,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1355 states, 1355 states have (on average 1.4354243542435425) internal successors, (1945), 1354 states have internal predecessors, (1945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:48,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 1355 states and 1945 transitions. [2023-11-21 22:10:48,778 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1355 states and 1945 transitions. [2023-11-21 22:10:48,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-21 22:10:48,782 INFO L428 stractBuchiCegarLoop]: Abstraction has 1355 states and 1945 transitions. [2023-11-21 22:10:48,782 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-21 22:10:48,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1355 states and 1945 transitions. [2023-11-21 22:10:48,791 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1272 [2023-11-21 22:10:48,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:48,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:48,797 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:48,797 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:48,797 INFO L748 eck$LassoCheckResult]: Stem: 12208#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12047#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 12048#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12318#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12274#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12275#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12301#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12285#L526 assume !(0 == ~M_E~0); 12286#L526-2 assume !(0 == ~T1_E~0); 12320#L531-1 assume !(0 == ~T2_E~0); 12270#L536-1 assume !(0 == ~T3_E~0); 12271#L541-1 assume !(0 == ~T4_E~0); 12266#L546-1 assume !(0 == ~E_M~0); 12267#L551-1 assume !(0 == ~E_1~0); 12241#L556-1 assume !(0 == ~E_2~0); 12242#L561-1 assume !(0 == ~E_3~0); 12251#L566-1 assume !(0 == ~E_4~0); 12252#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12246#L262 assume !(1 == ~m_pc~0); 12247#L262-2 is_master_triggered_~__retres1~0#1 := 0; 12441#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12178#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12179#L649 assume !(0 != activate_threads_~tmp~1#1); 12439#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12188#L281 assume !(1 == ~t1_pc~0); 12189#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12100#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12101#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12163#L657 assume !(0 != activate_threads_~tmp___0~0#1); 12164#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12255#L300 assume 1 == ~t2_pc~0; 12256#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12358#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12310#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12279#L665 assume !(0 != activate_threads_~tmp___1~0#1); 12027#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12028#L319 assume !(1 == ~t3_pc~0); 11982#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11983#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11969#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11970#L673 assume !(0 != activate_threads_~tmp___2~0#1); 12004#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12005#L338 assume 1 == ~t4_pc~0; 12159#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12074#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12080#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12081#L681 assume !(0 != activate_threads_~tmp___3~0#1); 11949#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11950#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 12438#L584-2 assume !(1 == ~T1_E~0); 12837#L589-1 assume !(1 == ~T2_E~0); 12836#L594-1 assume !(1 == ~T3_E~0); 12835#L599-1 assume !(1 == ~T4_E~0); 12834#L604-1 assume !(1 == ~E_M~0); 12833#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12832#L614-1 assume !(1 == ~E_2~0); 12831#L619-1 assume !(1 == ~E_3~0); 12276#L624-1 assume !(1 == ~E_4~0); 12277#L629-1 assume { :end_inline_reset_delta_events } true; 12296#L815-2 [2023-11-21 22:10:48,798 INFO L750 eck$LassoCheckResult]: Loop: 12296#L815-2 assume !false; 12298#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12170#L501-1 assume !false; 12432#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12433#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12095#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12326#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12327#L440 assume !(0 != eval_~tmp~0#1); 12090#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12091#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12213#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12214#L526-5 assume !(0 == ~T1_E~0); 12092#L531-3 assume !(0 == ~T2_E~0); 12093#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11975#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11976#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12278#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12225#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12226#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12331#L566-3 assume !(0 == ~E_4~0); 12105#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12106#L262-18 assume !(1 == ~m_pc~0); 12201#L262-20 is_master_triggered_~__retres1~0#1 := 0; 12202#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12219#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12220#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12437#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12237#L281-18 assume 1 == ~t1_pc~0; 12238#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13264#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13262#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13260#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13257#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13240#L300-18 assume 1 == ~t2_pc~0; 13238#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13237#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13160#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13144#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 13139#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13136#L319-18 assume 1 == ~t3_pc~0; 13131#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13114#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13106#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13104#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13101#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13097#L338-18 assume !(1 == ~t4_pc~0); 13081#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 13079#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13061#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12952#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12260#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12206#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12207#L584-5 assume !(1 == ~T1_E~0); 12006#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12007#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12198#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12229#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12230#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12293#L614-3 assume !(1 == ~E_2~0); 11997#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11998#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12302#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12335#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12083#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12084#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12139#L834 assume !(0 == start_simulation_~tmp~3#1); 12140#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12311#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12269#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12012#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 12013#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12382#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12389#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 12295#L847 assume !(0 != start_simulation_~tmp___0~1#1); 12296#L815-2 [2023-11-21 22:10:48,798 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:48,799 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2023-11-21 22:10:48,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:48,799 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470036172] [2023-11-21 22:10:48,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:48,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:48,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:48,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:48,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:48,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470036172] [2023-11-21 22:10:48,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [470036172] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:48,858 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:48,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:10:48,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2002953286] [2023-11-21 22:10:48,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:48,859 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:48,860 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:48,860 INFO L85 PathProgramCache]: Analyzing trace with hash -183984791, now seen corresponding path program 1 times [2023-11-21 22:10:48,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:48,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354657860] [2023-11-21 22:10:48,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:48,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:48,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:48,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:48,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:48,921 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354657860] [2023-11-21 22:10:48,921 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [354657860] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:48,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:48,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:48,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [383278572] [2023-11-21 22:10:48,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:48,922 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:48,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:48,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:48,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:48,924 INFO L87 Difference]: Start difference. First operand 1355 states and 1945 transitions. cyclomatic complexity: 594 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:48,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:48,989 INFO L93 Difference]: Finished difference Result 2450 states and 3494 transitions. [2023-11-21 22:10:48,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2450 states and 3494 transitions. [2023-11-21 22:10:49,007 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2356 [2023-11-21 22:10:49,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2450 states to 2450 states and 3494 transitions. [2023-11-21 22:10:49,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2450 [2023-11-21 22:10:49,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2450 [2023-11-21 22:10:49,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2450 states and 3494 transitions. [2023-11-21 22:10:49,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:49,032 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2450 states and 3494 transitions. [2023-11-21 22:10:49,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2450 states and 3494 transitions. [2023-11-21 22:10:49,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2450 to 2442. [2023-11-21 22:10:49,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2442 states, 2442 states have (on average 1.4275184275184276) internal successors, (3486), 2441 states have internal predecessors, (3486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:49,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2442 states to 2442 states and 3486 transitions. [2023-11-21 22:10:49,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2442 states and 3486 transitions. [2023-11-21 22:10:49,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:49,091 INFO L428 stractBuchiCegarLoop]: Abstraction has 2442 states and 3486 transitions. [2023-11-21 22:10:49,091 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-21 22:10:49,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2442 states and 3486 transitions. [2023-11-21 22:10:49,107 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2348 [2023-11-21 22:10:49,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:49,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:49,108 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:49,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:49,109 INFO L748 eck$LassoCheckResult]: Stem: 16015#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 16016#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16120#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16121#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15856#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 15857#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16136#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16082#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16083#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16114#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16094#L526 assume !(0 == ~M_E~0); 16095#L526-2 assume !(0 == ~T1_E~0); 16138#L531-1 assume !(0 == ~T2_E~0); 16078#L536-1 assume !(0 == ~T3_E~0); 16079#L541-1 assume !(0 == ~T4_E~0); 16074#L546-1 assume !(0 == ~E_M~0); 16075#L551-1 assume !(0 == ~E_1~0); 16052#L556-1 assume !(0 == ~E_2~0); 16053#L561-1 assume !(0 == ~E_3~0); 16062#L566-1 assume !(0 == ~E_4~0); 16063#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16057#L262 assume !(1 == ~m_pc~0); 16058#L262-2 is_master_triggered_~__retres1~0#1 := 0; 16249#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15984#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15985#L649 assume !(0 != activate_threads_~tmp~1#1); 16247#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15994#L281 assume !(1 == ~t1_pc~0); 15995#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15907#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15824#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15825#L657 assume !(0 != activate_threads_~tmp___0~0#1); 15968#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16065#L300 assume !(1 == ~t2_pc~0); 16066#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16176#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16125#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16088#L665 assume !(0 != activate_threads_~tmp___1~0#1); 15837#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15838#L319 assume !(1 == ~t3_pc~0); 15793#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15794#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15779#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15780#L673 assume !(0 != activate_threads_~tmp___2~0#1); 15814#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15815#L338 assume 1 == ~t4_pc~0; 15963#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15881#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15886#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15887#L681 assume !(0 != activate_threads_~tmp___3~0#1); 15761#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15762#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 16246#L584-2 assume !(1 == ~T1_E~0); 15922#L589-1 assume !(1 == ~T2_E~0); 15923#L594-1 assume !(1 == ~T3_E~0); 16166#L599-1 assume !(1 == ~T4_E~0); 15791#L604-1 assume !(1 == ~E_M~0); 15792#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17151#L614-1 assume !(1 == ~E_2~0); 17150#L619-1 assume !(1 == ~E_3~0); 17149#L624-1 assume !(1 == ~E_4~0); 16084#L629-1 assume { :end_inline_reset_delta_events } true; 16260#L815-2 [2023-11-21 22:10:49,109 INFO L750 eck$LassoCheckResult]: Loop: 16260#L815-2 assume !false; 16613#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16614#L501-1 assume !false; 16606#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16607#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16596#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16597#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16589#L440 assume !(0 != eval_~tmp~0#1); 16591#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17594#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17435#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17431#L526-5 assume !(0 == ~T1_E~0); 17429#L531-3 assume !(0 == ~T2_E~0); 17428#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17427#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17426#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17424#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17422#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17420#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17418#L566-3 assume !(0 == ~E_4~0); 17416#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17414#L262-18 assume !(1 == ~m_pc~0); 17412#L262-20 is_master_triggered_~__retres1~0#1 := 0; 17410#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17408#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17406#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17404#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17402#L281-18 assume !(1 == ~t1_pc~0); 17398#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 17396#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17394#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17392#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 17381#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17378#L300-18 assume !(1 == ~t2_pc~0); 17376#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 17374#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17372#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17370#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 17368#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17366#L319-18 assume 1 == ~t3_pc~0; 17363#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17361#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17358#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17356#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17354#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17352#L338-18 assume !(1 == ~t4_pc~0); 17347#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 17343#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17338#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17334#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17330#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17325#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17320#L584-5 assume !(1 == ~T1_E~0); 17314#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17308#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17303#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17298#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17294#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17290#L614-3 assume !(1 == ~E_2~0); 17286#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17282#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17090#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 17091#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16971#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16972#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 15943#L834 assume !(0 == start_simulation_~tmp~3#1); 15944#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16693#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16685#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16686#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 17164#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17161#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17159#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 16678#L847 assume !(0 != start_simulation_~tmp___0~1#1); 16260#L815-2 [2023-11-21 22:10:49,111 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:49,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2023-11-21 22:10:49,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:49,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992642974] [2023-11-21 22:10:49,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:49,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:49,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:49,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:49,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:49,160 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1992642974] [2023-11-21 22:10:49,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1992642974] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:49,163 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:49,163 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:10:49,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962561910] [2023-11-21 22:10:49,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:49,166 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:49,167 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:49,167 INFO L85 PathProgramCache]: Analyzing trace with hash 834972333, now seen corresponding path program 1 times [2023-11-21 22:10:49,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:49,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575041828] [2023-11-21 22:10:49,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:49,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:49,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:49,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:49,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:49,212 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [575041828] [2023-11-21 22:10:49,212 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [575041828] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:49,212 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:49,212 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:49,213 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [798136773] [2023-11-21 22:10:49,213 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:49,213 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:49,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:49,214 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:49,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:49,214 INFO L87 Difference]: Start difference. First operand 2442 states and 3486 transitions. cyclomatic complexity: 1052 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:49,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:49,342 INFO L93 Difference]: Finished difference Result 4453 states and 6327 transitions. [2023-11-21 22:10:49,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4453 states and 6327 transitions. [2023-11-21 22:10:49,372 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4328 [2023-11-21 22:10:49,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4453 states to 4453 states and 6327 transitions. [2023-11-21 22:10:49,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4453 [2023-11-21 22:10:49,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4453 [2023-11-21 22:10:49,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4453 states and 6327 transitions. [2023-11-21 22:10:49,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:49,421 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4453 states and 6327 transitions. [2023-11-21 22:10:49,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4453 states and 6327 transitions. [2023-11-21 22:10:49,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4453 to 4437. [2023-11-21 22:10:49,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4437 states, 4437 states have (on average 1.422357448726617) internal successors, (6311), 4436 states have internal predecessors, (6311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:49,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4437 states to 4437 states and 6311 transitions. [2023-11-21 22:10:49,521 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4437 states and 6311 transitions. [2023-11-21 22:10:49,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:49,523 INFO L428 stractBuchiCegarLoop]: Abstraction has 4437 states and 6311 transitions. [2023-11-21 22:10:49,523 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-21 22:10:49,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4437 states and 6311 transitions. [2023-11-21 22:10:49,542 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4312 [2023-11-21 22:10:49,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:49,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:49,544 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:49,544 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:49,544 INFO L748 eck$LassoCheckResult]: Stem: 22915#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 22916#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 23013#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23014#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22760#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 22761#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23025#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22978#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22979#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23008#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22989#L526 assume !(0 == ~M_E~0); 22990#L526-2 assume !(0 == ~T1_E~0); 23028#L531-1 assume !(0 == ~T2_E~0); 22974#L536-1 assume !(0 == ~T3_E~0); 22975#L541-1 assume !(0 == ~T4_E~0); 22970#L546-1 assume !(0 == ~E_M~0); 22971#L551-1 assume !(0 == ~E_1~0); 22948#L556-1 assume !(0 == ~E_2~0); 22949#L561-1 assume !(0 == ~E_3~0); 22958#L566-1 assume !(0 == ~E_4~0); 22959#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22953#L262 assume !(1 == ~m_pc~0); 22954#L262-2 is_master_triggered_~__retres1~0#1 := 0; 23136#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22885#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22886#L649 assume !(0 != activate_threads_~tmp~1#1); 23134#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22894#L281 assume !(1 == ~t1_pc~0); 22895#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22814#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22725#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22726#L657 assume !(0 != activate_threads_~tmp___0~0#1); 22870#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22961#L300 assume !(1 == ~t2_pc~0); 22962#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23060#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23017#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22983#L665 assume !(0 != activate_threads_~tmp___1~0#1); 22738#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22739#L319 assume !(1 == ~t3_pc~0); 22694#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22695#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22681#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22682#L673 assume !(0 != activate_threads_~tmp___2~0#1); 22715#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22716#L338 assume !(1 == ~t4_pc~0); 22784#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22785#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22790#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22791#L681 assume !(0 != activate_threads_~tmp___3~0#1); 22663#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22664#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 23133#L584-2 assume !(1 == ~T1_E~0); 24692#L589-1 assume !(1 == ~T2_E~0); 24691#L594-1 assume !(1 == ~T3_E~0); 24690#L599-1 assume !(1 == ~T4_E~0); 24689#L604-1 assume !(1 == ~E_M~0); 24688#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 24687#L614-1 assume !(1 == ~E_2~0); 24686#L619-1 assume !(1 == ~E_3~0); 24685#L624-1 assume !(1 == ~E_4~0); 22980#L629-1 assume { :end_inline_reset_delta_events } true; 23144#L815-2 [2023-11-21 22:10:49,544 INFO L750 eck$LassoCheckResult]: Loop: 23144#L815-2 assume !false; 24959#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24958#L501-1 assume !false; 24957#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24956#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24951#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24950#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 24949#L440 assume !(0 != eval_~tmp~0#1); 24948#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24947#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24946#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24945#L526-5 assume !(0 == ~T1_E~0); 24944#L531-3 assume !(0 == ~T2_E~0); 24943#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24942#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24941#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24940#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24939#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24938#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24937#L566-3 assume !(0 == ~E_4~0); 24936#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24935#L262-18 assume !(1 == ~m_pc~0); 24934#L262-20 is_master_triggered_~__retres1~0#1 := 0; 24933#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24932#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24931#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24930#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24929#L281-18 assume !(1 == ~t1_pc~0); 24928#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 24926#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24924#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24922#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 24920#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24919#L300-18 assume !(1 == ~t2_pc~0); 24918#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 24917#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24916#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24915#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 24914#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24913#L319-18 assume !(1 == ~t3_pc~0); 24912#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 24910#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24909#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24908#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24907#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24906#L338-18 assume !(1 == ~t4_pc~0); 24905#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 24904#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24903#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24902#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24901#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24900#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24799#L584-5 assume !(1 == ~T1_E~0); 24899#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24898#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24897#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24896#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24895#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24894#L614-3 assume !(1 == ~E_2~0); 24893#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24892#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24779#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24889#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24886#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24885#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 22850#L834 assume !(0 == start_simulation_~tmp~3#1); 22851#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24996#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24988#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24985#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 24981#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24977#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24973#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 24967#L847 assume !(0 != start_simulation_~tmp___0~1#1); 23144#L815-2 [2023-11-21 22:10:49,545 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:49,545 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2023-11-21 22:10:49,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:49,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130231351] [2023-11-21 22:10:49,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:49,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:49,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:49,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:49,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:49,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130231351] [2023-11-21 22:10:49,596 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130231351] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:49,597 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:49,597 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:10:49,597 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740093483] [2023-11-21 22:10:49,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:49,598 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:49,598 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:49,598 INFO L85 PathProgramCache]: Analyzing trace with hash 1886421422, now seen corresponding path program 1 times [2023-11-21 22:10:49,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:49,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822905467] [2023-11-21 22:10:49,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:49,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:49,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:49,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:49,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:49,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822905467] [2023-11-21 22:10:49,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822905467] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:49,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:49,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:49,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647772236] [2023-11-21 22:10:49,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:49,633 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:49,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:49,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:49,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:49,634 INFO L87 Difference]: Start difference. First operand 4437 states and 6311 transitions. cyclomatic complexity: 1890 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:49,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:49,692 INFO L93 Difference]: Finished difference Result 6648 states and 9441 transitions. [2023-11-21 22:10:49,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6648 states and 9441 transitions. [2023-11-21 22:10:49,770 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6508 [2023-11-21 22:10:49,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6648 states to 6648 states and 9441 transitions. [2023-11-21 22:10:49,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6648 [2023-11-21 22:10:49,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6648 [2023-11-21 22:10:49,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6648 states and 9441 transitions. [2023-11-21 22:10:49,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:49,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6648 states and 9441 transitions. [2023-11-21 22:10:49,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6648 states and 9441 transitions. [2023-11-21 22:10:49,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6648 to 4815. [2023-11-21 22:10:49,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4815 states, 4815 states have (on average 1.4188992731048806) internal successors, (6832), 4814 states have internal predecessors, (6832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:49,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4815 states to 4815 states and 6832 transitions. [2023-11-21 22:10:49,941 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4815 states and 6832 transitions. [2023-11-21 22:10:49,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:49,942 INFO L428 stractBuchiCegarLoop]: Abstraction has 4815 states and 6832 transitions. [2023-11-21 22:10:49,942 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-21 22:10:49,943 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4815 states and 6832 transitions. [2023-11-21 22:10:49,962 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4700 [2023-11-21 22:10:49,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:49,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:49,963 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:49,963 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:49,964 INFO L748 eck$LassoCheckResult]: Stem: 34005#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 34006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34103#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34104#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33853#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 33854#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34115#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34070#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34071#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34099#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34083#L526 assume !(0 == ~M_E~0); 34084#L526-2 assume !(0 == ~T1_E~0); 34118#L531-1 assume !(0 == ~T2_E~0); 34066#L536-1 assume !(0 == ~T3_E~0); 34067#L541-1 assume !(0 == ~T4_E~0); 34062#L546-1 assume !(0 == ~E_M~0); 34063#L551-1 assume !(0 == ~E_1~0); 34038#L556-1 assume !(0 == ~E_2~0); 34039#L561-1 assume !(0 == ~E_3~0); 34048#L566-1 assume !(0 == ~E_4~0); 34049#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34043#L262 assume !(1 == ~m_pc~0); 34044#L262-2 is_master_triggered_~__retres1~0#1 := 0; 34216#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33975#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33976#L649 assume !(0 != activate_threads_~tmp~1#1); 34215#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33985#L281 assume !(1 == ~t1_pc~0); 33986#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33904#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33818#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33819#L657 assume !(0 != activate_threads_~tmp___0~0#1); 33962#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34051#L300 assume !(1 == ~t2_pc~0); 34052#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34152#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34108#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34074#L665 assume !(0 != activate_threads_~tmp___1~0#1); 33831#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33832#L319 assume !(1 == ~t3_pc~0); 33786#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33787#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33773#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33774#L673 assume !(0 != activate_threads_~tmp___2~0#1); 33808#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33809#L338 assume !(1 == ~t4_pc~0); 33878#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33879#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33885#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33886#L681 assume !(0 != activate_threads_~tmp___3~0#1); 33755#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33756#L584 assume !(1 == ~M_E~0); 33959#L584-2 assume !(1 == ~T1_E~0); 33920#L589-1 assume !(1 == ~T2_E~0); 33921#L594-1 assume !(1 == ~T3_E~0); 34011#L599-1 assume !(1 == ~T4_E~0); 33785#L604-1 assume !(1 == ~E_M~0); 33771#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 33772#L614-1 assume !(1 == ~E_2~0); 33893#L619-1 assume !(1 == ~E_3~0); 33977#L624-1 assume !(1 == ~E_4~0); 34072#L629-1 assume { :end_inline_reset_delta_events } true; 34225#L815-2 [2023-11-21 22:10:49,964 INFO L750 eck$LassoCheckResult]: Loop: 34225#L815-2 assume !false; 36168#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36167#L501-1 assume !false; 36166#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 35850#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 35844#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 35842#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35839#L440 assume !(0 != eval_~tmp~0#1); 35837#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35835#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35832#L526-3 assume !(0 == ~M_E~0); 35830#L526-5 assume !(0 == ~T1_E~0); 35828#L531-3 assume !(0 == ~T2_E~0); 35826#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35824#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35760#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35749#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35745#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35741#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35732#L566-3 assume !(0 == ~E_4~0); 35728#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35724#L262-18 assume !(1 == ~m_pc~0); 35719#L262-20 is_master_triggered_~__retres1~0#1 := 0; 35715#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35710#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35706#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35702#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35698#L281-18 assume 1 == ~t1_pc~0; 35693#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35688#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35682#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 35676#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35671#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35666#L300-18 assume !(1 == ~t2_pc~0); 35662#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 35658#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35654#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 35649#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 35645#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35641#L319-18 assume 1 == ~t3_pc~0; 35635#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35630#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35624#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 35618#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35613#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35608#L338-18 assume !(1 == ~t4_pc~0); 35602#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 35598#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35594#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35589#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35585#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35581#L584-3 assume !(1 == ~M_E~0); 35181#L584-5 assume !(1 == ~T1_E~0); 35573#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35570#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35565#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35561#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35557#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35553#L614-3 assume !(1 == ~E_2~0); 35549#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35545#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35543#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 35537#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 35532#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34400#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 34302#L834 assume !(0 == start_simulation_~tmp~3#1); 34303#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36245#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36240#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36238#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 36235#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36233#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36231#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 36230#L847 assume !(0 != start_simulation_~tmp___0~1#1); 34225#L815-2 [2023-11-21 22:10:49,965 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:49,965 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2023-11-21 22:10:49,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:49,965 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836520296] [2023-11-21 22:10:49,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:49,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:49,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:50,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:50,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:50,020 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836520296] [2023-11-21 22:10:50,020 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836520296] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:50,020 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:50,020 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:50,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1448182789] [2023-11-21 22:10:50,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:50,022 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:50,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:50,023 INFO L85 PathProgramCache]: Analyzing trace with hash 1765976554, now seen corresponding path program 1 times [2023-11-21 22:10:50,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:50,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346442276] [2023-11-21 22:10:50,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:50,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:50,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:50,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:50,058 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:50,058 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1346442276] [2023-11-21 22:10:50,058 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1346442276] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:50,058 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:50,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:50,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487669812] [2023-11-21 22:10:50,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:50,059 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:50,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:50,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 22:10:50,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 22:10:50,060 INFO L87 Difference]: Start difference. First operand 4815 states and 6832 transitions. cyclomatic complexity: 2025 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:50,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:50,246 INFO L93 Difference]: Finished difference Result 6567 states and 9149 transitions. [2023-11-21 22:10:50,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6567 states and 9149 transitions. [2023-11-21 22:10:50,286 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6350 [2023-11-21 22:10:50,343 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6567 states to 6567 states and 9149 transitions. [2023-11-21 22:10:50,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6567 [2023-11-21 22:10:50,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6567 [2023-11-21 22:10:50,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6567 states and 9149 transitions. [2023-11-21 22:10:50,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:50,363 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6567 states and 9149 transitions. [2023-11-21 22:10:50,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6567 states and 9149 transitions. [2023-11-21 22:10:50,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6567 to 5402. [2023-11-21 22:10:50,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5402 states, 5402 states have (on average 1.4009626064420584) internal successors, (7568), 5401 states have internal predecessors, (7568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:50,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5402 states to 5402 states and 7568 transitions. [2023-11-21 22:10:50,495 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5402 states and 7568 transitions. [2023-11-21 22:10:50,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 22:10:50,497 INFO L428 stractBuchiCegarLoop]: Abstraction has 5402 states and 7568 transitions. [2023-11-21 22:10:50,497 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-21 22:10:50,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5402 states and 7568 transitions. [2023-11-21 22:10:50,517 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5244 [2023-11-21 22:10:50,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:50,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:50,518 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:50,518 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:50,519 INFO L748 eck$LassoCheckResult]: Stem: 45401#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 45402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 45499#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45500#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45243#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 45244#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45512#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45466#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45467#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45494#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45476#L526 assume !(0 == ~M_E~0); 45477#L526-2 assume !(0 == ~T1_E~0); 45515#L531-1 assume !(0 == ~T2_E~0); 45462#L536-1 assume !(0 == ~T3_E~0); 45463#L541-1 assume !(0 == ~T4_E~0); 45458#L546-1 assume !(0 == ~E_M~0); 45459#L551-1 assume 0 == ~E_1~0;~E_1~0 := 1; 45529#L556-1 assume !(0 == ~E_2~0); 45687#L561-1 assume !(0 == ~E_3~0); 45686#L566-1 assume !(0 == ~E_4~0); 45618#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45441#L262 assume !(1 == ~m_pc~0); 45442#L262-2 is_master_triggered_~__retres1~0#1 := 0; 45623#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45372#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45373#L649 assume !(0 != activate_threads_~tmp~1#1); 45619#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45680#L281 assume !(1 == ~t1_pc~0); 45679#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45678#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45677#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45672#L657 assume !(0 != activate_threads_~tmp___0~0#1); 45671#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45670#L300 assume !(1 == ~t2_pc~0); 45669#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45668#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45667#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45666#L665 assume !(0 != activate_threads_~tmp___1~0#1); 45665#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45664#L319 assume !(1 == ~t3_pc~0); 45662#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45661#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45660#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45659#L673 assume !(0 != activate_threads_~tmp___2~0#1); 45658#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45657#L338 assume !(1 == ~t4_pc~0); 45656#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45655#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45654#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45653#L681 assume !(0 != activate_threads_~tmp___3~0#1); 45652#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45651#L584 assume !(1 == ~M_E~0); 45650#L584-2 assume !(1 == ~T1_E~0); 45649#L589-1 assume !(1 == ~T2_E~0); 45648#L594-1 assume !(1 == ~T3_E~0); 45647#L599-1 assume !(1 == ~T4_E~0); 45646#L604-1 assume !(1 == ~E_M~0); 45645#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 45164#L614-1 assume !(1 == ~E_2~0); 45284#L619-1 assume !(1 == ~E_3~0); 45374#L624-1 assume !(1 == ~E_4~0); 45468#L629-1 assume { :end_inline_reset_delta_events } true; 45630#L815-2 [2023-11-21 22:10:50,519 INFO L750 eck$LassoCheckResult]: Loop: 45630#L815-2 assume !false; 49870#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49868#L501-1 assume !false; 49866#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49865#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49853#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49848#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49489#L440 assume !(0 != eval_~tmp~0#1); 49490#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50441#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50439#L526-3 assume !(0 == ~M_E~0); 50437#L526-5 assume !(0 == ~T1_E~0); 50436#L531-3 assume !(0 == ~T2_E~0); 50434#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50432#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50430#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50427#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50426#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50425#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50424#L566-3 assume !(0 == ~E_4~0); 50423#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50422#L262-18 assume !(1 == ~m_pc~0); 50421#L262-20 is_master_triggered_~__retres1~0#1 := 0; 50420#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50419#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50418#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50417#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50416#L281-18 assume 1 == ~t1_pc~0; 50413#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50411#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50409#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50407#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50406#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50405#L300-18 assume !(1 == ~t2_pc~0); 50404#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 50403#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50402#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50401#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 50400#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50399#L319-18 assume 1 == ~t3_pc~0; 50397#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50396#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50395#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50394#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50393#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50392#L338-18 assume !(1 == ~t4_pc~0); 50391#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 50390#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50389#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50388#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50387#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50386#L584-3 assume !(1 == ~M_E~0); 49148#L584-5 assume !(1 == ~T1_E~0); 50385#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50384#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50383#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50382#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50380#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50378#L614-3 assume !(1 == ~E_2~0); 50376#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50374#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50372#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 50365#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 50362#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 50361#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 48168#L834 assume !(0 == start_simulation_~tmp~3#1); 48169#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49897#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49892#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49889#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 49887#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49885#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49883#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 49881#L847 assume !(0 != start_simulation_~tmp___0~1#1); 45630#L815-2 [2023-11-21 22:10:50,520 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:50,520 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2023-11-21 22:10:50,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:50,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497786512] [2023-11-21 22:10:50,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:50,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:50,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:50,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:50,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:50,568 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497786512] [2023-11-21 22:10:50,568 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497786512] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:50,568 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:50,569 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:50,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789393847] [2023-11-21 22:10:50,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:50,569 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:50,570 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:50,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1765976554, now seen corresponding path program 2 times [2023-11-21 22:10:50,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:50,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029032356] [2023-11-21 22:10:50,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:50,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:50,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:50,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:50,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:50,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029032356] [2023-11-21 22:10:50,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1029032356] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:50,624 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:50,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:50,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749861280] [2023-11-21 22:10:50,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:50,625 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:50,625 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:50,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 22:10:50,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 22:10:50,626 INFO L87 Difference]: Start difference. First operand 5402 states and 7568 transitions. cyclomatic complexity: 2174 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:50,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:50,710 INFO L93 Difference]: Finished difference Result 5518 states and 7683 transitions. [2023-11-21 22:10:50,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5518 states and 7683 transitions. [2023-11-21 22:10:50,735 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5382 [2023-11-21 22:10:50,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5518 states to 5518 states and 7683 transitions. [2023-11-21 22:10:50,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5518 [2023-11-21 22:10:50,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5518 [2023-11-21 22:10:50,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5518 states and 7683 transitions. [2023-11-21 22:10:50,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:50,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5518 states and 7683 transitions. [2023-11-21 22:10:50,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5518 states and 7683 transitions. [2023-11-21 22:10:50,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5518 to 4596. [2023-11-21 22:10:50,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4596 states, 4596 states have (on average 1.3962140992167102) internal successors, (6417), 4595 states have internal predecessors, (6417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:50,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4596 states to 4596 states and 6417 transitions. [2023-11-21 22:10:50,867 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4596 states and 6417 transitions. [2023-11-21 22:10:50,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 22:10:50,868 INFO L428 stractBuchiCegarLoop]: Abstraction has 4596 states and 6417 transitions. [2023-11-21 22:10:50,868 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-21 22:10:50,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4596 states and 6417 transitions. [2023-11-21 22:10:50,885 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4484 [2023-11-21 22:10:50,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:50,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:50,887 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:50,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:50,887 INFO L748 eck$LassoCheckResult]: Stem: 56331#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 56332#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 56433#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56434#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56173#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 56174#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56447#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56397#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56398#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56428#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56407#L526 assume !(0 == ~M_E~0); 56408#L526-2 assume !(0 == ~T1_E~0); 56449#L531-1 assume !(0 == ~T2_E~0); 56393#L536-1 assume !(0 == ~T3_E~0); 56394#L541-1 assume !(0 == ~T4_E~0); 56389#L546-1 assume !(0 == ~E_M~0); 56390#L551-1 assume !(0 == ~E_1~0); 56366#L556-1 assume !(0 == ~E_2~0); 56367#L561-1 assume !(0 == ~E_3~0); 56376#L566-1 assume !(0 == ~E_4~0); 56377#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56371#L262 assume !(1 == ~m_pc~0); 56372#L262-2 is_master_triggered_~__retres1~0#1 := 0; 56563#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56302#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56303#L649 assume !(0 != activate_threads_~tmp~1#1); 56559#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56311#L281 assume !(1 == ~t1_pc~0); 56312#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56225#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56139#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56140#L657 assume !(0 != activate_threads_~tmp___0~0#1); 56283#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56379#L300 assume !(1 == ~t2_pc~0); 56380#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56482#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56437#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56401#L665 assume !(0 != activate_threads_~tmp___1~0#1); 56152#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56153#L319 assume !(1 == ~t3_pc~0); 56108#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56109#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56095#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56096#L673 assume !(0 != activate_threads_~tmp___2~0#1); 56129#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56130#L338 assume !(1 == ~t4_pc~0); 56196#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56197#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56202#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56203#L681 assume !(0 != activate_threads_~tmp___3~0#1); 56077#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56078#L584 assume !(1 == ~M_E~0); 56280#L584-2 assume !(1 == ~T1_E~0); 56239#L589-1 assume !(1 == ~T2_E~0); 56240#L594-1 assume !(1 == ~T3_E~0); 56335#L599-1 assume !(1 == ~T4_E~0); 56107#L604-1 assume !(1 == ~E_M~0); 56093#L609-1 assume !(1 == ~E_1~0); 56094#L614-1 assume !(1 == ~E_2~0); 56213#L619-1 assume !(1 == ~E_3~0); 56304#L624-1 assume !(1 == ~E_4~0); 56399#L629-1 assume { :end_inline_reset_delta_events } true; 56569#L815-2 [2023-11-21 22:10:50,888 INFO L750 eck$LassoCheckResult]: Loop: 56569#L815-2 assume !false; 58604#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58598#L501-1 assume !false; 58596#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 58594#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 58588#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 58586#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 58584#L440 assume !(0 != eval_~tmp~0#1); 56214#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56215#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56336#L526-3 assume !(0 == ~M_E~0); 56337#L526-5 assume !(0 == ~T1_E~0); 56216#L531-3 assume !(0 == ~T2_E~0); 56217#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 56101#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56102#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 56400#L551-3 assume !(0 == ~E_1~0); 56349#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56350#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56459#L566-3 assume !(0 == ~E_4~0); 56229#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56230#L262-18 assume !(1 == ~m_pc~0); 56324#L262-20 is_master_triggered_~__retres1~0#1 := 0; 56325#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56342#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56343#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56114#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56115#L281-18 assume !(1 == ~t1_pc~0); 56364#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 56381#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56382#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56554#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 56503#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56504#L300-18 assume !(1 == ~t2_pc~0); 56103#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 56104#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56172#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56431#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 56466#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56226#L319-18 assume 1 == ~t3_pc~0; 56227#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56232#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56253#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56432#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56420#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56309#L338-18 assume !(1 == ~t4_pc~0); 56310#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 60672#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60671#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 60670#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60669#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56329#L584-3 assume !(1 == ~M_E~0); 56330#L584-5 assume !(1 == ~T1_E~0); 60668#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60667#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60666#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60665#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 60664#L609-3 assume !(1 == ~E_1~0); 60663#L614-3 assume !(1 == ~E_2~0); 60662#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58774#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58752#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 58747#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 58725#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 58575#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 58569#L834 assume !(0 == start_simulation_~tmp~3#1); 58570#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 58706#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 58702#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 58700#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 58698#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 58696#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 58693#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 58691#L847 assume !(0 != start_simulation_~tmp___0~1#1); 56569#L815-2 [2023-11-21 22:10:50,888 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:50,888 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2023-11-21 22:10:50,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:50,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459215344] [2023-11-21 22:10:50,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:50,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:50,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:50,899 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:50,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:50,939 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:50,940 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:50,940 INFO L85 PathProgramCache]: Analyzing trace with hash 2115489581, now seen corresponding path program 1 times [2023-11-21 22:10:50,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:50,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057954792] [2023-11-21 22:10:50,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:50,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:50,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:50,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:50,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:50,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2057954792] [2023-11-21 22:10:50,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2057954792] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:50,975 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:50,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:50,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [135887795] [2023-11-21 22:10:50,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:50,976 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:50,976 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:50,976 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:50,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:50,977 INFO L87 Difference]: Start difference. First operand 4596 states and 6417 transitions. cyclomatic complexity: 1829 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:51,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:51,106 INFO L93 Difference]: Finished difference Result 6857 states and 9490 transitions. [2023-11-21 22:10:51,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6857 states and 9490 transitions. [2023-11-21 22:10:51,139 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6686 [2023-11-21 22:10:51,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6857 states to 6857 states and 9490 transitions. [2023-11-21 22:10:51,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6857 [2023-11-21 22:10:51,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6857 [2023-11-21 22:10:51,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6857 states and 9490 transitions. [2023-11-21 22:10:51,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:51,178 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6857 states and 9490 transitions. [2023-11-21 22:10:51,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6857 states and 9490 transitions. [2023-11-21 22:10:51,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6857 to 6849. [2023-11-21 22:10:51,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6849 states, 6849 states have (on average 1.384435684041466) internal successors, (9482), 6848 states have internal predecessors, (9482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:51,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6849 states to 6849 states and 9482 transitions. [2023-11-21 22:10:51,308 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6849 states and 9482 transitions. [2023-11-21 22:10:51,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:51,309 INFO L428 stractBuchiCegarLoop]: Abstraction has 6849 states and 9482 transitions. [2023-11-21 22:10:51,309 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-21 22:10:51,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6849 states and 9482 transitions. [2023-11-21 22:10:51,333 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6678 [2023-11-21 22:10:51,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:51,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:51,336 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:51,336 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:51,337 INFO L748 eck$LassoCheckResult]: Stem: 67798#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 67799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 67901#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67902#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67635#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 67636#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67915#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67866#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67867#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67896#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67881#L526 assume !(0 == ~M_E~0); 67882#L526-2 assume !(0 == ~T1_E~0); 67918#L531-1 assume !(0 == ~T2_E~0); 67862#L536-1 assume !(0 == ~T3_E~0); 67863#L541-1 assume !(0 == ~T4_E~0); 67858#L546-1 assume !(0 == ~E_M~0); 67859#L551-1 assume !(0 == ~E_1~0); 67834#L556-1 assume 0 == ~E_2~0;~E_2~0 := 1; 67835#L561-1 assume !(0 == ~E_3~0); 67878#L566-1 assume !(0 == ~E_4~0); 68029#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68030#L262 assume !(1 == ~m_pc~0); 68041#L262-2 is_master_triggered_~__retres1~0#1 := 0; 68042#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68084#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68034#L649 assume !(0 != activate_threads_~tmp~1#1); 68035#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68083#L281 assume !(1 == ~t1_pc~0); 68046#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68047#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68081#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68080#L657 assume !(0 != activate_threads_~tmp___0~0#1); 68025#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68026#L300 assume !(1 == ~t2_pc~0); 67997#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67998#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68079#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67870#L665 assume !(0 != activate_threads_~tmp___1~0#1); 67871#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68078#L319 assume !(1 == ~t3_pc~0); 67569#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67570#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 67557#L673 assume !(0 != activate_threads_~tmp___2~0#1); 68077#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67957#L338 assume !(1 == ~t4_pc~0); 67659#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67660#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68075#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68038#L681 assume !(0 != activate_threads_~tmp___3~0#1); 67536#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67537#L584 assume !(1 == ~M_E~0); 68073#L584-2 assume !(1 == ~T1_E~0); 68072#L589-1 assume !(1 == ~T2_E~0); 68071#L594-1 assume !(1 == ~T3_E~0); 68070#L599-1 assume !(1 == ~T4_E~0); 67568#L604-1 assume !(1 == ~E_M~0); 67554#L609-1 assume !(1 == ~E_1~0); 67555#L614-1 assume 1 == ~E_2~0;~E_2~0 := 2; 67675#L619-1 assume !(1 == ~E_3~0); 67767#L624-1 assume !(1 == ~E_4~0); 67868#L629-1 assume { :end_inline_reset_delta_events } true; 68050#L815-2 [2023-11-21 22:10:51,337 INFO L750 eck$LassoCheckResult]: Loop: 68050#L815-2 assume !false; 69442#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69406#L501-1 assume !false; 69439#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69438#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69433#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69427#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 69424#L440 assume !(0 != eval_~tmp~0#1); 69425#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70357#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70352#L526-3 assume !(0 == ~M_E~0); 70347#L526-5 assume !(0 == ~T1_E~0); 70340#L531-3 assume !(0 == ~T2_E~0); 70335#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70330#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70323#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 70317#L551-3 assume !(0 == ~E_1~0); 70311#L556-3 assume !(0 == ~E_2~0); 70308#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69673#L566-3 assume !(0 == ~E_4~0); 69667#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69665#L262-18 assume !(1 == ~m_pc~0); 69663#L262-20 is_master_triggered_~__retres1~0#1 := 0; 69661#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69659#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69657#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69655#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69653#L281-18 assume !(1 == ~t1_pc~0); 69651#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 69650#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69645#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 69643#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 69641#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69635#L300-18 assume !(1 == ~t2_pc~0); 69633#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 69631#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69628#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 69626#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 69624#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69622#L319-18 assume 1 == ~t3_pc~0; 69619#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69617#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69615#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 69613#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69611#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69609#L338-18 assume !(1 == ~t4_pc~0); 69606#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 69604#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69602#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 69600#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69598#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69596#L584-3 assume !(1 == ~M_E~0); 69592#L584-5 assume !(1 == ~T1_E~0); 69590#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69588#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69586#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69583#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69581#L609-3 assume !(1 == ~E_1~0); 69483#L614-3 assume !(1 == ~E_2~0); 69481#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69479#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69477#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69470#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69466#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69464#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 69463#L834 assume !(0 == start_simulation_~tmp~3#1); 69461#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69459#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69455#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69454#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 69452#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69450#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69448#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 69446#L847 assume !(0 != start_simulation_~tmp___0~1#1); 68050#L815-2 [2023-11-21 22:10:51,337 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:51,338 INFO L85 PathProgramCache]: Analyzing trace with hash 652862409, now seen corresponding path program 1 times [2023-11-21 22:10:51,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:51,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482548226] [2023-11-21 22:10:51,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:51,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:51,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:51,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:51,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:51,376 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482548226] [2023-11-21 22:10:51,376 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482548226] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:51,376 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:51,377 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:10:51,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787732205] [2023-11-21 22:10:51,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:51,377 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:51,378 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:51,378 INFO L85 PathProgramCache]: Analyzing trace with hash -918560465, now seen corresponding path program 1 times [2023-11-21 22:10:51,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:51,378 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1890048068] [2023-11-21 22:10:51,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:51,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:51,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:51,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:51,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:51,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1890048068] [2023-11-21 22:10:51,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1890048068] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:51,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:51,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:10:51,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1227290664] [2023-11-21 22:10:51,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:51,457 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:51,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:51,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:51,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:51,458 INFO L87 Difference]: Start difference. First operand 6849 states and 9482 transitions. cyclomatic complexity: 2641 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:51,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:51,571 INFO L93 Difference]: Finished difference Result 4596 states and 6323 transitions. [2023-11-21 22:10:51,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4596 states and 6323 transitions. [2023-11-21 22:10:51,591 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4484 [2023-11-21 22:10:51,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4596 states to 4596 states and 6323 transitions. [2023-11-21 22:10:51,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4596 [2023-11-21 22:10:51,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4596 [2023-11-21 22:10:51,613 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4596 states and 6323 transitions. [2023-11-21 22:10:51,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:51,618 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4596 states and 6323 transitions. [2023-11-21 22:10:51,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4596 states and 6323 transitions. [2023-11-21 22:10:51,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4596 to 4596. [2023-11-21 22:10:51,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4596 states, 4596 states have (on average 1.3757615317667538) internal successors, (6323), 4595 states have internal predecessors, (6323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:51,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4596 states to 4596 states and 6323 transitions. [2023-11-21 22:10:51,699 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4596 states and 6323 transitions. [2023-11-21 22:10:51,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:51,700 INFO L428 stractBuchiCegarLoop]: Abstraction has 4596 states and 6323 transitions. [2023-11-21 22:10:51,700 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-21 22:10:51,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4596 states and 6323 transitions. [2023-11-21 22:10:51,714 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4484 [2023-11-21 22:10:51,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:51,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:51,716 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:51,716 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:51,717 INFO L748 eck$LassoCheckResult]: Stem: 79239#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 79240#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 79337#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 79338#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79084#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 79085#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79349#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79302#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79303#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 79331#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 79312#L526 assume !(0 == ~M_E~0); 79313#L526-2 assume !(0 == ~T1_E~0); 79351#L531-1 assume !(0 == ~T2_E~0); 79298#L536-1 assume !(0 == ~T3_E~0); 79299#L541-1 assume !(0 == ~T4_E~0); 79294#L546-1 assume !(0 == ~E_M~0); 79295#L551-1 assume !(0 == ~E_1~0); 79272#L556-1 assume !(0 == ~E_2~0); 79273#L561-1 assume !(0 == ~E_3~0); 79282#L566-1 assume !(0 == ~E_4~0); 79283#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79277#L262 assume !(1 == ~m_pc~0); 79278#L262-2 is_master_triggered_~__retres1~0#1 := 0; 79455#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79209#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 79210#L649 assume !(0 != activate_threads_~tmp~1#1); 79451#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79219#L281 assume !(1 == ~t1_pc~0); 79220#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 79137#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79051#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 79052#L657 assume !(0 != activate_threads_~tmp___0~0#1); 79193#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79285#L300 assume !(1 == ~t2_pc~0); 79286#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 79386#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79342#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 79306#L665 assume !(0 != activate_threads_~tmp___1~0#1); 79064#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79065#L319 assume !(1 == ~t3_pc~0); 79021#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 79022#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 79009#L673 assume !(0 != activate_threads_~tmp___2~0#1); 79041#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79042#L338 assume !(1 == ~t4_pc~0); 79108#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 79109#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79114#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 79115#L681 assume !(0 != activate_threads_~tmp___3~0#1); 78990#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78991#L584 assume !(1 == ~M_E~0); 79190#L584-2 assume !(1 == ~T1_E~0); 79151#L589-1 assume !(1 == ~T2_E~0); 79152#L594-1 assume !(1 == ~T3_E~0); 79243#L599-1 assume !(1 == ~T4_E~0); 79020#L604-1 assume !(1 == ~E_M~0); 79006#L609-1 assume !(1 == ~E_1~0); 79007#L614-1 assume !(1 == ~E_2~0); 79125#L619-1 assume !(1 == ~E_3~0); 79211#L624-1 assume !(1 == ~E_4~0); 79304#L629-1 assume { :end_inline_reset_delta_events } true; 79466#L815-2 [2023-11-21 22:10:51,717 INFO L750 eck$LassoCheckResult]: Loop: 79466#L815-2 assume !false; 80464#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80463#L501-1 assume !false; 80461#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 80459#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 80448#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 80444#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 80440#L440 assume !(0 != eval_~tmp~0#1); 80441#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 80776#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 80774#L526-3 assume !(0 == ~M_E~0); 80772#L526-5 assume !(0 == ~T1_E~0); 80770#L531-3 assume !(0 == ~T2_E~0); 80768#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 80766#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 80764#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 80762#L551-3 assume !(0 == ~E_1~0); 80760#L556-3 assume !(0 == ~E_2~0); 80758#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80756#L566-3 assume !(0 == ~E_4~0); 80753#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80750#L262-18 assume !(1 == ~m_pc~0); 80747#L262-20 is_master_triggered_~__retres1~0#1 := 0; 80744#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80741#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 80738#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 80735#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80731#L281-18 assume !(1 == ~t1_pc~0); 80722#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 80719#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80716#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 80712#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 80710#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80707#L300-18 assume !(1 == ~t2_pc~0); 80704#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 80701#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80698#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 80695#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 80692#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80688#L319-18 assume !(1 == ~t3_pc~0); 80685#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 80680#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80677#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 80674#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 80671#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80668#L338-18 assume !(1 == ~t4_pc~0); 80665#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 80661#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80657#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 80653#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 80648#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80644#L584-3 assume !(1 == ~M_E~0); 80638#L584-5 assume !(1 == ~T1_E~0); 80635#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80632#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 80629#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 80626#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 80623#L609-3 assume !(1 == ~E_1~0); 80620#L614-3 assume !(1 == ~E_2~0); 80617#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 80613#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 80610#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 80500#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 80496#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 80494#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 80492#L834 assume !(0 == start_simulation_~tmp~3#1); 80490#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 80487#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 80482#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 80480#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 80478#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 80475#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80473#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 80471#L847 assume !(0 != start_simulation_~tmp___0~1#1); 79466#L815-2 [2023-11-21 22:10:51,717 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:51,718 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2023-11-21 22:10:51,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:51,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241581667] [2023-11-21 22:10:51,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:51,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:51,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:51,729 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:51,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:51,766 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:51,766 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:51,767 INFO L85 PathProgramCache]: Analyzing trace with hash 132888624, now seen corresponding path program 1 times [2023-11-21 22:10:51,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:51,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708573479] [2023-11-21 22:10:51,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:51,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:51,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:51,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:51,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:51,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [708573479] [2023-11-21 22:10:51,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [708573479] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:51,821 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:51,821 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:10:51,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209810770] [2023-11-21 22:10:51,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:51,822 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:51,822 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:51,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:10:51,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:10:51,823 INFO L87 Difference]: Start difference. First operand 4596 states and 6323 transitions. cyclomatic complexity: 1735 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:51,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:51,979 INFO L93 Difference]: Finished difference Result 8144 states and 11059 transitions. [2023-11-21 22:10:51,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8144 states and 11059 transitions. [2023-11-21 22:10:52,022 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7984 [2023-11-21 22:10:52,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8144 states to 8144 states and 11059 transitions. [2023-11-21 22:10:52,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8144 [2023-11-21 22:10:52,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8144 [2023-11-21 22:10:52,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8144 states and 11059 transitions. [2023-11-21 22:10:52,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:52,076 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8144 states and 11059 transitions. [2023-11-21 22:10:52,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8144 states and 11059 transitions. [2023-11-21 22:10:52,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8144 to 4644. [2023-11-21 22:10:52,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4644 states, 4644 states have (on average 1.3718776916451334) internal successors, (6371), 4643 states have internal predecessors, (6371), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:52,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4644 states to 4644 states and 6371 transitions. [2023-11-21 22:10:52,200 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4644 states and 6371 transitions. [2023-11-21 22:10:52,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-21 22:10:52,201 INFO L428 stractBuchiCegarLoop]: Abstraction has 4644 states and 6371 transitions. [2023-11-21 22:10:52,202 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-21 22:10:52,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4644 states and 6371 transitions. [2023-11-21 22:10:52,220 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4532 [2023-11-21 22:10:52,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:52,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:52,222 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:52,222 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:52,223 INFO L748 eck$LassoCheckResult]: Stem: 91999#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 92000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 92097#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 92098#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91844#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 91845#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 92108#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92064#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 92065#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 92092#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 92074#L526 assume !(0 == ~M_E~0); 92075#L526-2 assume !(0 == ~T1_E~0); 92112#L531-1 assume !(0 == ~T2_E~0); 92060#L536-1 assume !(0 == ~T3_E~0); 92061#L541-1 assume !(0 == ~T4_E~0); 92056#L546-1 assume !(0 == ~E_M~0); 92057#L551-1 assume !(0 == ~E_1~0); 92033#L556-1 assume !(0 == ~E_2~0); 92034#L561-1 assume !(0 == ~E_3~0); 92043#L566-1 assume !(0 == ~E_4~0); 92044#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92038#L262 assume !(1 == ~m_pc~0); 92039#L262-2 is_master_triggered_~__retres1~0#1 := 0; 92209#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91969#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 91970#L649 assume !(0 != activate_threads_~tmp~1#1); 92205#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91978#L281 assume !(1 == ~t1_pc~0); 91979#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 91895#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91808#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 91809#L657 assume !(0 != activate_threads_~tmp___0~0#1); 91952#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92046#L300 assume !(1 == ~t2_pc~0); 92047#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 92148#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92102#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 92068#L665 assume !(0 != activate_threads_~tmp___1~0#1); 91821#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91822#L319 assume !(1 == ~t3_pc~0); 91778#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 91779#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91765#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 91766#L673 assume !(0 != activate_threads_~tmp___2~0#1); 91798#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91799#L338 assume !(1 == ~t4_pc~0); 91868#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 91869#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91874#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 91875#L681 assume !(0 != activate_threads_~tmp___3~0#1); 91747#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91748#L584 assume !(1 == ~M_E~0); 91949#L584-2 assume !(1 == ~T1_E~0); 91909#L589-1 assume !(1 == ~T2_E~0); 91910#L594-1 assume !(1 == ~T3_E~0); 92003#L599-1 assume !(1 == ~T4_E~0); 91777#L604-1 assume !(1 == ~E_M~0); 91763#L609-1 assume !(1 == ~E_1~0); 91764#L614-1 assume !(1 == ~E_2~0); 91883#L619-1 assume !(1 == ~E_3~0); 91971#L624-1 assume !(1 == ~E_4~0); 92066#L629-1 assume { :end_inline_reset_delta_events } true; 92216#L815-2 [2023-11-21 22:10:52,223 INFO L750 eck$LassoCheckResult]: Loop: 92216#L815-2 assume !false; 94275#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93994#L501-1 assume !false; 93991#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 93988#L398 assume !(0 == ~m_st~0); 93985#L402 assume !(0 == ~t1_st~0); 93986#L406 assume !(0 == ~t2_st~0); 93987#L410 assume !(0 == ~t3_st~0); 93984#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 93976#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 92954#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 92955#L440 assume !(0 != eval_~tmp~0#1); 93970#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 93968#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 93966#L526-3 assume !(0 == ~M_E~0); 93961#L526-5 assume !(0 == ~T1_E~0); 93962#L531-3 assume !(0 == ~T2_E~0); 93955#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 93956#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 93948#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 93949#L551-3 assume !(0 == ~E_1~0); 93942#L556-3 assume !(0 == ~E_2~0); 93943#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 93936#L566-3 assume !(0 == ~E_4~0); 93937#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93929#L262-18 assume !(1 == ~m_pc~0); 93930#L262-20 is_master_triggered_~__retres1~0#1 := 0; 93923#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93924#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 93917#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 93918#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93911#L281-18 assume !(1 == ~t1_pc~0); 93910#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 93903#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93904#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 93896#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 93897#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93883#L300-18 assume !(1 == ~t2_pc~0); 93884#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 91842#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91843#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 92095#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 92132#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91896#L319-18 assume 1 == ~t3_pc~0; 91897#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91902#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91923#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 92096#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 92084#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91976#L338-18 assume !(1 == ~t4_pc~0); 91977#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 94331#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94330#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94329#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94328#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94327#L584-3 assume !(1 == ~M_E~0); 94191#L584-5 assume !(1 == ~T1_E~0); 94326#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94325#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94324#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94323#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 94322#L609-3 assume !(1 == ~E_1~0); 94321#L614-3 assume !(1 == ~E_2~0); 94320#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94319#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 94318#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 94315#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 94310#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 94307#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 94304#L834 assume !(0 == start_simulation_~tmp~3#1); 94301#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 94299#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 94294#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 94292#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 94288#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 94286#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 94284#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 94281#L847 assume !(0 != start_simulation_~tmp___0~1#1); 92216#L815-2 [2023-11-21 22:10:52,224 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:52,224 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2023-11-21 22:10:52,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:52,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607869943] [2023-11-21 22:10:52,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:52,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:52,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:52,240 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:52,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:52,266 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:52,267 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:52,267 INFO L85 PathProgramCache]: Analyzing trace with hash -2030396125, now seen corresponding path program 1 times [2023-11-21 22:10:52,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:52,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600369632] [2023-11-21 22:10:52,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:52,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:52,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:52,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:52,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:52,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600369632] [2023-11-21 22:10:52,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600369632] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:52,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:52,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:10:52,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582936094] [2023-11-21 22:10:52,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:52,379 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:52,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:52,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:10:52,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:10:52,380 INFO L87 Difference]: Start difference. First operand 4644 states and 6371 transitions. cyclomatic complexity: 1735 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:52,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:52,586 INFO L93 Difference]: Finished difference Result 8272 states and 11142 transitions. [2023-11-21 22:10:52,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8272 states and 11142 transitions. [2023-11-21 22:10:52,632 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8144 [2023-11-21 22:10:52,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8272 states to 8272 states and 11142 transitions. [2023-11-21 22:10:52,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8272 [2023-11-21 22:10:52,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8272 [2023-11-21 22:10:52,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8272 states and 11142 transitions. [2023-11-21 22:10:52,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:52,689 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8272 states and 11142 transitions. [2023-11-21 22:10:52,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8272 states and 11142 transitions. [2023-11-21 22:10:52,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8272 to 4776. [2023-11-21 22:10:52,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4776 states, 4776 states have (on average 1.353852596314908) internal successors, (6466), 4775 states have internal predecessors, (6466), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:52,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4776 states to 4776 states and 6466 transitions. [2023-11-21 22:10:52,847 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4776 states and 6466 transitions. [2023-11-21 22:10:52,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-21 22:10:52,848 INFO L428 stractBuchiCegarLoop]: Abstraction has 4776 states and 6466 transitions. [2023-11-21 22:10:52,848 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-21 22:10:52,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4776 states and 6466 transitions. [2023-11-21 22:10:52,864 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4664 [2023-11-21 22:10:52,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:52,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:52,865 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:52,865 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:52,866 INFO L748 eck$LassoCheckResult]: Stem: 104925#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 104926#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 105025#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105026#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 104769#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 104770#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105040#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104989#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104990#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105021#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105003#L526 assume !(0 == ~M_E~0); 105004#L526-2 assume !(0 == ~T1_E~0); 105042#L531-1 assume !(0 == ~T2_E~0); 104985#L536-1 assume !(0 == ~T3_E~0); 104986#L541-1 assume !(0 == ~T4_E~0); 104981#L546-1 assume !(0 == ~E_M~0); 104982#L551-1 assume !(0 == ~E_1~0); 104958#L556-1 assume !(0 == ~E_2~0); 104959#L561-1 assume !(0 == ~E_3~0); 104969#L566-1 assume !(0 == ~E_4~0); 104970#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104963#L262 assume !(1 == ~m_pc~0); 104964#L262-2 is_master_triggered_~__retres1~0#1 := 0; 105157#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104896#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 104897#L649 assume !(0 != activate_threads_~tmp~1#1); 105156#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104905#L281 assume !(1 == ~t1_pc~0); 104906#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 104822#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104736#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 104737#L657 assume !(0 != activate_threads_~tmp___0~0#1); 104880#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104972#L300 assume !(1 == ~t2_pc~0); 104973#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105079#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105030#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 104993#L665 assume !(0 != activate_threads_~tmp___1~0#1); 104749#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104750#L319 assume !(1 == ~t3_pc~0); 104706#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 104707#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104693#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 104694#L673 assume !(0 != activate_threads_~tmp___2~0#1); 104726#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104727#L338 assume !(1 == ~t4_pc~0); 104794#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 104795#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104801#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104802#L681 assume !(0 != activate_threads_~tmp___3~0#1); 104675#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104676#L584 assume !(1 == ~M_E~0); 104877#L584-2 assume !(1 == ~T1_E~0); 104838#L589-1 assume !(1 == ~T2_E~0); 104839#L594-1 assume !(1 == ~T3_E~0); 104931#L599-1 assume !(1 == ~T4_E~0); 104705#L604-1 assume !(1 == ~E_M~0); 104691#L609-1 assume !(1 == ~E_1~0); 104692#L614-1 assume !(1 == ~E_2~0); 104811#L619-1 assume !(1 == ~E_3~0); 104898#L624-1 assume !(1 == ~E_4~0); 104991#L629-1 assume { :end_inline_reset_delta_events } true; 105164#L815-2 [2023-11-21 22:10:52,866 INFO L750 eck$LassoCheckResult]: Loop: 105164#L815-2 assume !false; 105815#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105813#L501-1 assume !false; 105811#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 105809#L398 assume !(0 == ~m_st~0); 105807#L402 assume !(0 == ~t1_st~0); 105805#L406 assume !(0 == ~t2_st~0); 105803#L410 assume !(0 == ~t3_st~0); 105799#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 105797#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 105795#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 105791#L440 assume !(0 != eval_~tmp~0#1); 105789#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105787#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 105785#L526-3 assume !(0 == ~M_E~0); 105783#L526-5 assume !(0 == ~T1_E~0); 105781#L531-3 assume !(0 == ~T2_E~0); 105779#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 105777#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 105775#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 105773#L551-3 assume !(0 == ~E_1~0); 105771#L556-3 assume !(0 == ~E_2~0); 105769#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 105767#L566-3 assume !(0 == ~E_4~0); 105765#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105763#L262-18 assume !(1 == ~m_pc~0); 105761#L262-20 is_master_triggered_~__retres1~0#1 := 0; 105759#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105757#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 105755#L649-18 assume !(0 != activate_threads_~tmp~1#1); 105753#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105750#L281-18 assume !(1 == ~t1_pc~0); 105747#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 105745#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105743#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 105741#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 105739#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105737#L300-18 assume !(1 == ~t2_pc~0); 105735#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 105733#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105731#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105729#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 105727#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105725#L319-18 assume 1 == ~t3_pc~0; 105707#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 105699#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105691#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 105683#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 105677#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105671#L338-18 assume !(1 == ~t4_pc~0); 105665#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 105328#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105329#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105320#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 105321#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105313#L584-3 assume !(1 == ~M_E~0); 105310#L584-5 assume !(1 == ~T1_E~0); 105309#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 105308#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 105307#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 105306#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 105305#L609-3 assume !(1 == ~E_1~0); 105304#L614-3 assume !(1 == ~E_2~0); 105303#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 105302#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 105301#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 105298#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 105295#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 105294#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 105291#L834 assume !(0 == start_simulation_~tmp~3#1); 105292#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 105983#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 105970#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 105962#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 105954#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 105946#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 105940#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 105936#L847 assume !(0 != start_simulation_~tmp___0~1#1); 105164#L815-2 [2023-11-21 22:10:52,867 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:52,867 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2023-11-21 22:10:52,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:52,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791313274] [2023-11-21 22:10:52,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:52,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:52,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:52,879 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:52,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:52,898 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:52,899 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:52,899 INFO L85 PathProgramCache]: Analyzing trace with hash -2045914843, now seen corresponding path program 1 times [2023-11-21 22:10:52,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:52,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740472489] [2023-11-21 22:10:52,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:52,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:52,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:52,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:52,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:52,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740472489] [2023-11-21 22:10:52,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740472489] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:52,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:52,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:52,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414384153] [2023-11-21 22:10:52,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:52,938 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:52,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:52,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:52,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:52,939 INFO L87 Difference]: Start difference. First operand 4776 states and 6466 transitions. cyclomatic complexity: 1698 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:53,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:53,008 INFO L93 Difference]: Finished difference Result 7480 states and 9967 transitions. [2023-11-21 22:10:53,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7480 states and 9967 transitions. [2023-11-21 22:10:53,041 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7350 [2023-11-21 22:10:53,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7480 states to 7480 states and 9967 transitions. [2023-11-21 22:10:53,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7480 [2023-11-21 22:10:53,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7480 [2023-11-21 22:10:53,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7480 states and 9967 transitions. [2023-11-21 22:10:53,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:53,085 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7480 states and 9967 transitions. [2023-11-21 22:10:53,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7480 states and 9967 transitions. [2023-11-21 22:10:53,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7480 to 7224. [2023-11-21 22:10:53,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7224 states, 7224 states have (on average 1.33374861572536) internal successors, (9635), 7223 states have internal predecessors, (9635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:53,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7224 states to 7224 states and 9635 transitions. [2023-11-21 22:10:53,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7224 states and 9635 transitions. [2023-11-21 22:10:53,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:53,200 INFO L428 stractBuchiCegarLoop]: Abstraction has 7224 states and 9635 transitions. [2023-11-21 22:10:53,200 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-21 22:10:53,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7224 states and 9635 transitions. [2023-11-21 22:10:53,224 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7094 [2023-11-21 22:10:53,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:53,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:53,226 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:53,226 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:53,227 INFO L748 eck$LassoCheckResult]: Stem: 117185#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 117186#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 117287#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 117288#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 117032#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 117033#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 117301#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 117249#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 117250#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 117282#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 117263#L526 assume !(0 == ~M_E~0); 117264#L526-2 assume !(0 == ~T1_E~0); 117303#L531-1 assume !(0 == ~T2_E~0); 117245#L536-1 assume !(0 == ~T3_E~0); 117246#L541-1 assume !(0 == ~T4_E~0); 117241#L546-1 assume !(0 == ~E_M~0); 117242#L551-1 assume !(0 == ~E_1~0); 117219#L556-1 assume !(0 == ~E_2~0); 117220#L561-1 assume !(0 == ~E_3~0); 117229#L566-1 assume !(0 == ~E_4~0); 117230#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117224#L262 assume !(1 == ~m_pc~0); 117225#L262-2 is_master_triggered_~__retres1~0#1 := 0; 117417#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117155#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 117156#L649 assume !(0 != activate_threads_~tmp~1#1); 117416#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117165#L281 assume !(1 == ~t1_pc~0); 117166#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 117083#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116998#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 116999#L657 assume !(0 != activate_threads_~tmp___0~0#1); 117139#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117232#L300 assume !(1 == ~t2_pc~0); 117233#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 117337#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117292#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 117253#L665 assume !(0 != activate_threads_~tmp___1~0#1); 117011#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117012#L319 assume !(1 == ~t3_pc~0); 116968#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 116969#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116955#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116956#L673 assume !(0 != activate_threads_~tmp___2~0#1); 116988#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116989#L338 assume !(1 == ~t4_pc~0); 117057#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 117058#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117064#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 117065#L681 assume !(0 != activate_threads_~tmp___3~0#1); 116937#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116938#L584 assume !(1 == ~M_E~0); 117136#L584-2 assume !(1 == ~T1_E~0); 117098#L589-1 assume !(1 == ~T2_E~0); 117099#L594-1 assume !(1 == ~T3_E~0); 117191#L599-1 assume !(1 == ~T4_E~0); 116967#L604-1 assume !(1 == ~E_M~0); 116953#L609-1 assume !(1 == ~E_1~0); 116954#L614-1 assume !(1 == ~E_2~0); 117072#L619-1 assume !(1 == ~E_3~0); 117157#L624-1 assume !(1 == ~E_4~0); 117251#L629-1 assume { :end_inline_reset_delta_events } true; 117423#L815-2 assume !false; 118036#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118031#L501-1 [2023-11-21 22:10:53,227 INFO L750 eck$LassoCheckResult]: Loop: 118031#L501-1 assume !false; 118027#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 118022#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 118018#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 118014#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 118006#L440 assume 0 != eval_~tmp~0#1; 118000#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 117995#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 117994#L448-2 havoc eval_~tmp_ndt_1~0#1; 117987#L445-1 assume !(0 == ~t1_st~0); 117979#L459-1 assume !(0 == ~t2_st~0); 117980#L473-1 assume !(0 == ~t3_st~0); 118038#L487-1 assume !(0 == ~t4_st~0); 118031#L501-1 [2023-11-21 22:10:53,230 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:53,231 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2023-11-21 22:10:53,232 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:53,232 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1044487060] [2023-11-21 22:10:53,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:53,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:53,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:53,248 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:53,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:53,270 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:53,271 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:53,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1697797356, now seen corresponding path program 1 times [2023-11-21 22:10:53,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:53,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469407741] [2023-11-21 22:10:53,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:53,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:53,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:53,275 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:53,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:53,278 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:53,279 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:53,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1780226006, now seen corresponding path program 1 times [2023-11-21 22:10:53,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:53,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409231244] [2023-11-21 22:10:53,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:53,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:53,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:53,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:53,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:53,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409231244] [2023-11-21 22:10:53,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [409231244] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:53,321 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:53,321 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:53,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351756964] [2023-11-21 22:10:53,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:53,420 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:53,420 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:53,421 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:53,421 INFO L87 Difference]: Start difference. First operand 7224 states and 9635 transitions. cyclomatic complexity: 2423 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:53,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:53,556 INFO L93 Difference]: Finished difference Result 11678 states and 15445 transitions. [2023-11-21 22:10:53,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11678 states and 15445 transitions. [2023-11-21 22:10:53,606 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11424 [2023-11-21 22:10:53,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11678 states to 11678 states and 15445 transitions. [2023-11-21 22:10:53,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11678 [2023-11-21 22:10:53,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11678 [2023-11-21 22:10:53,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11678 states and 15445 transitions. [2023-11-21 22:10:53,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:53,669 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11678 states and 15445 transitions. [2023-11-21 22:10:53,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11678 states and 15445 transitions. [2023-11-21 22:10:53,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11678 to 11678. [2023-11-21 22:10:53,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11678 states, 11678 states have (on average 1.3225723582805275) internal successors, (15445), 11677 states have internal predecessors, (15445), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:53,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11678 states to 11678 states and 15445 transitions. [2023-11-21 22:10:53,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11678 states and 15445 transitions. [2023-11-21 22:10:53,842 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:53,842 INFO L428 stractBuchiCegarLoop]: Abstraction has 11678 states and 15445 transitions. [2023-11-21 22:10:53,842 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-21 22:10:53,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11678 states and 15445 transitions. [2023-11-21 22:10:53,879 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11424 [2023-11-21 22:10:53,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:53,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:53,880 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:53,880 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:53,881 INFO L748 eck$LassoCheckResult]: Stem: 136101#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 136102#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 136204#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 136205#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 135942#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 135943#L365-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 136219#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 136167#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 136168#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 136198#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 136181#L526 assume !(0 == ~M_E~0); 136182#L526-2 assume !(0 == ~T1_E~0); 136221#L531-1 assume !(0 == ~T2_E~0); 136163#L536-1 assume !(0 == ~T3_E~0); 136164#L541-1 assume !(0 == ~T4_E~0); 136159#L546-1 assume !(0 == ~E_M~0); 136160#L551-1 assume !(0 == ~E_1~0); 136136#L556-1 assume !(0 == ~E_2~0); 136137#L561-1 assume !(0 == ~E_3~0); 136147#L566-1 assume !(0 == ~E_4~0); 136148#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136141#L262 assume !(1 == ~m_pc~0); 136142#L262-2 is_master_triggered_~__retres1~0#1 := 0; 136328#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136071#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 136072#L649 assume !(0 != activate_threads_~tmp~1#1); 136327#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136080#L281 assume !(1 == ~t1_pc~0); 136081#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 135993#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135908#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 135909#L657 assume !(0 != activate_threads_~tmp___0~0#1); 136051#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136150#L300 assume !(1 == ~t2_pc~0); 136151#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 136256#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136209#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 136171#L665 assume !(0 != activate_threads_~tmp___1~0#1); 135921#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 135922#L319 assume !(1 == ~t3_pc~0); 135878#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 135879#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135865#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 135866#L673 assume !(0 != activate_threads_~tmp___2~0#1); 135898#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 135899#L338 assume !(1 == ~t4_pc~0); 135966#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 135967#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 135973#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 135974#L681 assume !(0 != activate_threads_~tmp___3~0#1); 135847#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 135848#L584 assume !(1 == ~M_E~0); 136047#L584-2 assume !(1 == ~T1_E~0); 136048#L589-1 assume !(1 == ~T2_E~0); 137169#L594-1 assume !(1 == ~T3_E~0); 137167#L599-1 assume !(1 == ~T4_E~0); 137165#L604-1 assume !(1 == ~E_M~0); 137163#L609-1 assume !(1 == ~E_1~0); 135981#L614-1 assume !(1 == ~E_2~0); 135982#L619-1 assume !(1 == ~E_3~0); 136073#L624-1 assume !(1 == ~E_4~0); 136169#L629-1 assume { :end_inline_reset_delta_events } true; 137109#L815-2 assume !false; 137084#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 137076#L501-1 [2023-11-21 22:10:53,881 INFO L750 eck$LassoCheckResult]: Loop: 137076#L501-1 assume !false; 137069#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 137060#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 137055#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 137049#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 137043#L440 assume 0 != eval_~tmp~0#1; 137034#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 137027#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 137023#L448-2 havoc eval_~tmp_ndt_1~0#1; 137017#L445-1 assume !(0 == ~t1_st~0); 137011#L459-1 assume !(0 == ~t2_st~0); 137012#L473-1 assume !(0 == ~t3_st~0); 137086#L487-1 assume !(0 == ~t4_st~0); 137076#L501-1 [2023-11-21 22:10:53,881 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:53,881 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2023-11-21 22:10:53,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:53,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135359432] [2023-11-21 22:10:53,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:53,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:53,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:53,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:53,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:53,910 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135359432] [2023-11-21 22:10:53,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135359432] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:53,910 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:53,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:53,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [46340122] [2023-11-21 22:10:53,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:53,911 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:53,912 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:53,912 INFO L85 PathProgramCache]: Analyzing trace with hash -1697797356, now seen corresponding path program 2 times [2023-11-21 22:10:53,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:53,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433263036] [2023-11-21 22:10:53,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:53,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:53,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:53,918 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:53,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:53,925 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:53,996 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:53,997 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:53,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:53,997 INFO L87 Difference]: Start difference. First operand 11678 states and 15445 transitions. cyclomatic complexity: 3779 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:54,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:54,085 INFO L93 Difference]: Finished difference Result 11618 states and 15367 transitions. [2023-11-21 22:10:54,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11618 states and 15367 transitions. [2023-11-21 22:10:54,134 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11424 [2023-11-21 22:10:54,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11618 states to 11618 states and 15367 transitions. [2023-11-21 22:10:54,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11618 [2023-11-21 22:10:54,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11618 [2023-11-21 22:10:54,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11618 states and 15367 transitions. [2023-11-21 22:10:54,204 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:54,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11618 states and 15367 transitions. [2023-11-21 22:10:54,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11618 states and 15367 transitions. [2023-11-21 22:10:54,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11618 to 11618. [2023-11-21 22:10:54,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11618 states, 11618 states have (on average 1.3226889309691858) internal successors, (15367), 11617 states have internal predecessors, (15367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:54,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11618 states to 11618 states and 15367 transitions. [2023-11-21 22:10:54,344 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11618 states and 15367 transitions. [2023-11-21 22:10:54,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:54,345 INFO L428 stractBuchiCegarLoop]: Abstraction has 11618 states and 15367 transitions. [2023-11-21 22:10:54,345 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-21 22:10:54,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11618 states and 15367 transitions. [2023-11-21 22:10:54,381 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11424 [2023-11-21 22:10:54,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:54,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:54,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:54,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:54,383 INFO L748 eck$LassoCheckResult]: Stem: 159400#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 159401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 159500#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 159501#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 159244#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 159245#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 159510#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 159465#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 159466#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 159494#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 159475#L526 assume !(0 == ~M_E~0); 159476#L526-2 assume !(0 == ~T1_E~0); 159512#L531-1 assume !(0 == ~T2_E~0); 159461#L536-1 assume !(0 == ~T3_E~0); 159462#L541-1 assume !(0 == ~T4_E~0); 159457#L546-1 assume !(0 == ~E_M~0); 159458#L551-1 assume !(0 == ~E_1~0); 159435#L556-1 assume !(0 == ~E_2~0); 159436#L561-1 assume !(0 == ~E_3~0); 159445#L566-1 assume !(0 == ~E_4~0); 159446#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159440#L262 assume !(1 == ~m_pc~0); 159441#L262-2 is_master_triggered_~__retres1~0#1 := 0; 159630#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159370#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 159371#L649 assume !(0 != activate_threads_~tmp~1#1); 159626#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159379#L281 assume !(1 == ~t1_pc~0); 159380#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 159294#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159210#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 159211#L657 assume !(0 != activate_threads_~tmp___0~0#1); 159353#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159448#L300 assume !(1 == ~t2_pc~0); 159449#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 159552#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159504#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159469#L665 assume !(0 != activate_threads_~tmp___1~0#1); 159223#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159224#L319 assume !(1 == ~t3_pc~0); 159180#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 159181#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159167#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 159168#L673 assume !(0 != activate_threads_~tmp___2~0#1); 159200#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159201#L338 assume !(1 == ~t4_pc~0); 159268#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 159269#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159274#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159275#L681 assume !(0 != activate_threads_~tmp___3~0#1); 159149#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 159150#L584 assume !(1 == ~M_E~0); 159350#L584-2 assume !(1 == ~T1_E~0); 159310#L589-1 assume !(1 == ~T2_E~0); 159311#L594-1 assume !(1 == ~T3_E~0); 159404#L599-1 assume !(1 == ~T4_E~0); 159179#L604-1 assume !(1 == ~E_M~0); 159165#L609-1 assume !(1 == ~E_1~0); 159166#L614-1 assume !(1 == ~E_2~0); 159283#L619-1 assume !(1 == ~E_3~0); 159372#L624-1 assume !(1 == ~E_4~0); 159467#L629-1 assume { :end_inline_reset_delta_events } true; 159636#L815-2 assume !false; 166364#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 165119#L501-1 [2023-11-21 22:10:54,383 INFO L750 eck$LassoCheckResult]: Loop: 165119#L501-1 assume !false; 166360#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 166357#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 166355#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 166353#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 166351#L440 assume 0 != eval_~tmp~0#1; 166348#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 166345#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 166341#L448-2 havoc eval_~tmp_ndt_1~0#1; 164980#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 164977#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 164975#L462-2 havoc eval_~tmp_ndt_2~0#1; 164971#L459-1 assume !(0 == ~t2_st~0); 164972#L473-1 assume !(0 == ~t3_st~0); 165118#L487-1 assume !(0 == ~t4_st~0); 165119#L501-1 [2023-11-21 22:10:54,383 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:54,384 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2023-11-21 22:10:54,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:54,384 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023365184] [2023-11-21 22:10:54,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:54,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:54,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:54,400 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:54,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:54,419 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:54,419 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:54,420 INFO L85 PathProgramCache]: Analyzing trace with hash 201422285, now seen corresponding path program 1 times [2023-11-21 22:10:54,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:54,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850253038] [2023-11-21 22:10:54,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:54,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:54,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:54,425 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:54,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:54,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:54,430 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:54,430 INFO L85 PathProgramCache]: Analyzing trace with hash -1703099037, now seen corresponding path program 1 times [2023-11-21 22:10:54,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:54,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350854211] [2023-11-21 22:10:54,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:54,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:54,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:54,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:54,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:54,559 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350854211] [2023-11-21 22:10:54,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350854211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:54,559 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:54,559 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:54,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [142128309] [2023-11-21 22:10:54,560 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:54,646 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:54,646 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:54,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:54,647 INFO L87 Difference]: Start difference. First operand 11618 states and 15367 transitions. cyclomatic complexity: 3761 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:54,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:54,753 INFO L93 Difference]: Finished difference Result 13646 states and 17935 transitions. [2023-11-21 22:10:54,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13646 states and 17935 transitions. [2023-11-21 22:10:54,828 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 13452 [2023-11-21 22:10:54,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13646 states to 13646 states and 17935 transitions. [2023-11-21 22:10:54,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13646 [2023-11-21 22:10:54,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13646 [2023-11-21 22:10:54,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13646 states and 17935 transitions. [2023-11-21 22:10:54,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:54,912 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13646 states and 17935 transitions. [2023-11-21 22:10:54,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13646 states and 17935 transitions. [2023-11-21 22:10:55,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13646 to 13156. [2023-11-21 22:10:55,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13156 states, 13156 states have (on average 1.3153694131955) internal successors, (17305), 13155 states have internal predecessors, (17305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:55,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13156 states to 13156 states and 17305 transitions. [2023-11-21 22:10:55,121 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13156 states and 17305 transitions. [2023-11-21 22:10:55,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:55,122 INFO L428 stractBuchiCegarLoop]: Abstraction has 13156 states and 17305 transitions. [2023-11-21 22:10:55,122 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-21 22:10:55,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13156 states and 17305 transitions. [2023-11-21 22:10:55,175 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12962 [2023-11-21 22:10:55,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:55,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:55,177 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:55,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:55,178 INFO L748 eck$LassoCheckResult]: Stem: 184670#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 184671#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 184776#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 184777#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 184518#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 184519#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 184791#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 184737#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 184738#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 184769#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 184748#L526 assume !(0 == ~M_E~0); 184749#L526-2 assume !(0 == ~T1_E~0); 184793#L531-1 assume !(0 == ~T2_E~0); 184733#L536-1 assume !(0 == ~T3_E~0); 184734#L541-1 assume !(0 == ~T4_E~0); 184729#L546-1 assume !(0 == ~E_M~0); 184730#L551-1 assume !(0 == ~E_1~0); 184706#L556-1 assume !(0 == ~E_2~0); 184707#L561-1 assume !(0 == ~E_3~0); 184716#L566-1 assume !(0 == ~E_4~0); 184717#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 184711#L262 assume !(1 == ~m_pc~0); 184712#L262-2 is_master_triggered_~__retres1~0#1 := 0; 184914#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 184640#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 184641#L649 assume !(0 != activate_threads_~tmp~1#1); 184911#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 184650#L281 assume !(1 == ~t1_pc~0); 184651#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 184568#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 184484#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 184485#L657 assume !(0 != activate_threads_~tmp___0~0#1); 184625#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 184719#L300 assume !(1 == ~t2_pc~0); 184720#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 184834#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 184781#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 184742#L665 assume !(0 != activate_threads_~tmp___1~0#1); 184497#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 184498#L319 assume !(1 == ~t3_pc~0); 184454#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 184455#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 184441#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 184442#L673 assume !(0 != activate_threads_~tmp___2~0#1); 184474#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 184475#L338 assume !(1 == ~t4_pc~0); 184543#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 184544#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 184549#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 184550#L681 assume !(0 != activate_threads_~tmp___3~0#1); 184421#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184422#L584 assume !(1 == ~M_E~0); 184622#L584-2 assume !(1 == ~T1_E~0); 184582#L589-1 assume !(1 == ~T2_E~0); 184583#L594-1 assume !(1 == ~T3_E~0); 184674#L599-1 assume !(1 == ~T4_E~0); 184453#L604-1 assume !(1 == ~E_M~0); 184439#L609-1 assume !(1 == ~E_1~0); 184440#L614-1 assume !(1 == ~E_2~0); 184558#L619-1 assume !(1 == ~E_3~0); 184642#L624-1 assume !(1 == ~E_4~0); 184739#L629-1 assume { :end_inline_reset_delta_events } true; 184919#L815-2 assume !false; 189473#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 188138#L501-1 [2023-11-21 22:10:55,178 INFO L750 eck$LassoCheckResult]: Loop: 188138#L501-1 assume !false; 189469#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 189467#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 189465#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 189463#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 188967#L440 assume 0 != eval_~tmp~0#1; 188606#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 188607#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 188600#L448-2 havoc eval_~tmp_ndt_1~0#1; 188197#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 188190#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 188185#L462-2 havoc eval_~tmp_ndt_2~0#1; 188154#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 188150#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 188148#L476-2 havoc eval_~tmp_ndt_3~0#1; 188145#L473-1 assume !(0 == ~t3_st~0); 188137#L487-1 assume !(0 == ~t4_st~0); 188138#L501-1 [2023-11-21 22:10:55,178 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:55,179 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2023-11-21 22:10:55,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:55,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407733759] [2023-11-21 22:10:55,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:55,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:55,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:55,199 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:55,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:55,222 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:55,223 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:55,223 INFO L85 PathProgramCache]: Analyzing trace with hash 145011028, now seen corresponding path program 1 times [2023-11-21 22:10:55,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:55,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758426380] [2023-11-21 22:10:55,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:55,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:55,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:55,231 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:55,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:55,236 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:55,236 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:55,237 INFO L85 PathProgramCache]: Analyzing trace with hash -443911318, now seen corresponding path program 1 times [2023-11-21 22:10:55,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:55,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142280726] [2023-11-21 22:10:55,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:55,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:55,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:55,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:55,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:55,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142280726] [2023-11-21 22:10:55,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142280726] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:55,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:55,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:55,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085002683] [2023-11-21 22:10:55,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:55,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:55,383 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:55,383 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:55,383 INFO L87 Difference]: Start difference. First operand 13156 states and 17305 transitions. cyclomatic complexity: 4161 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:55,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:55,658 INFO L93 Difference]: Finished difference Result 23326 states and 30563 transitions. [2023-11-21 22:10:55,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23326 states and 30563 transitions. [2023-11-21 22:10:55,750 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 23004 [2023-11-21 22:10:55,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23326 states to 23326 states and 30563 transitions. [2023-11-21 22:10:55,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23326 [2023-11-21 22:10:55,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23326 [2023-11-21 22:10:55,842 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23326 states and 30563 transitions. [2023-11-21 22:10:55,858 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:55,859 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23326 states and 30563 transitions. [2023-11-21 22:10:55,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23326 states and 30563 transitions. [2023-11-21 22:10:56,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23326 to 22570. [2023-11-21 22:10:56,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22570 states, 22570 states have (on average 1.3142667257421357) internal successors, (29663), 22569 states have internal predecessors, (29663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:56,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22570 states to 22570 states and 29663 transitions. [2023-11-21 22:10:56,118 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22570 states and 29663 transitions. [2023-11-21 22:10:56,118 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:56,119 INFO L428 stractBuchiCegarLoop]: Abstraction has 22570 states and 29663 transitions. [2023-11-21 22:10:56,119 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-21 22:10:56,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22570 states and 29663 transitions. [2023-11-21 22:10:56,187 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22248 [2023-11-21 22:10:56,188 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:56,188 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:56,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:56,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:56,189 INFO L748 eck$LassoCheckResult]: Stem: 221168#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 221169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 221270#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 221271#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221009#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 221010#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 221285#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 221232#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 221233#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 221261#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 221243#L526 assume !(0 == ~M_E~0); 221244#L526-2 assume !(0 == ~T1_E~0); 221287#L531-1 assume !(0 == ~T2_E~0); 221228#L536-1 assume !(0 == ~T3_E~0); 221229#L541-1 assume !(0 == ~T4_E~0); 221224#L546-1 assume !(0 == ~E_M~0); 221225#L551-1 assume !(0 == ~E_1~0); 221201#L556-1 assume !(0 == ~E_2~0); 221202#L561-1 assume !(0 == ~E_3~0); 221211#L566-1 assume !(0 == ~E_4~0); 221212#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221206#L262 assume !(1 == ~m_pc~0); 221207#L262-2 is_master_triggered_~__retres1~0#1 := 0; 221415#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221138#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 221139#L649 assume !(0 != activate_threads_~tmp~1#1); 221410#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 221147#L281 assume !(1 == ~t1_pc~0); 221148#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 221062#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220973#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 220974#L657 assume !(0 != activate_threads_~tmp___0~0#1); 221122#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221215#L300 assume !(1 == ~t2_pc~0); 221216#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 221332#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 221275#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 221237#L665 assume !(0 != activate_threads_~tmp___1~0#1); 220986#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 220987#L319 assume !(1 == ~t3_pc~0); 220943#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 220944#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220930#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 220931#L673 assume !(0 != activate_threads_~tmp___2~0#1); 220963#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220964#L338 assume !(1 == ~t4_pc~0); 221034#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 221035#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221040#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 221041#L681 assume !(0 != activate_threads_~tmp___3~0#1); 220911#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 220912#L584 assume !(1 == ~M_E~0); 221119#L584-2 assume !(1 == ~T1_E~0); 221078#L589-1 assume !(1 == ~T2_E~0); 221079#L594-1 assume !(1 == ~T3_E~0); 221172#L599-1 assume !(1 == ~T4_E~0); 220942#L604-1 assume !(1 == ~E_M~0); 220928#L609-1 assume !(1 == ~E_1~0); 220929#L614-1 assume !(1 == ~E_2~0); 221051#L619-1 assume !(1 == ~E_3~0); 221140#L624-1 assume !(1 == ~E_4~0); 221234#L629-1 assume { :end_inline_reset_delta_events } true; 221422#L815-2 assume !false; 227823#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 227821#L501-1 [2023-11-21 22:10:56,190 INFO L750 eck$LassoCheckResult]: Loop: 227821#L501-1 assume !false; 227819#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 227817#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 227812#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 227813#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 227807#L440 assume 0 != eval_~tmp~0#1; 227808#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 227859#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 227857#L448-2 havoc eval_~tmp_ndt_1~0#1; 227853#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 227795#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 227845#L462-2 havoc eval_~tmp_ndt_2~0#1; 227840#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 227834#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 227833#L476-2 havoc eval_~tmp_ndt_3~0#1; 227832#L473-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 226375#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 227828#L490-2 havoc eval_~tmp_ndt_4~0#1; 227825#L487-1 assume !(0 == ~t4_st~0); 227821#L501-1 [2023-11-21 22:10:56,190 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:56,190 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2023-11-21 22:10:56,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:56,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870723958] [2023-11-21 22:10:56,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:56,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:56,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:56,324 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:56,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:56,349 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:56,350 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:56,350 INFO L85 PathProgramCache]: Analyzing trace with hash 1911902797, now seen corresponding path program 1 times [2023-11-21 22:10:56,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:56,350 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34631482] [2023-11-21 22:10:56,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:56,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:56,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:56,355 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:56,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:56,358 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:56,359 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:56,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1401755933, now seen corresponding path program 1 times [2023-11-21 22:10:56,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:56,360 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085581492] [2023-11-21 22:10:56,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:56,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:56,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:56,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:56,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:56,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2085581492] [2023-11-21 22:10:56,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2085581492] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:56,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:56,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:10:56,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [599357114] [2023-11-21 22:10:56,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:56,489 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:56,490 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:56,490 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:56,490 INFO L87 Difference]: Start difference. First operand 22570 states and 29663 transitions. cyclomatic complexity: 7105 Second operand has 3 states, 2 states have (on average 41.5) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:56,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:56,622 INFO L93 Difference]: Finished difference Result 26800 states and 35069 transitions. [2023-11-21 22:10:56,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26800 states and 35069 transitions. [2023-11-21 22:10:56,738 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 26470 [2023-11-21 22:10:56,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26800 states to 26800 states and 35069 transitions. [2023-11-21 22:10:56,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26800 [2023-11-21 22:10:56,849 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26800 [2023-11-21 22:10:56,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26800 states and 35069 transitions. [2023-11-21 22:10:56,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:56,870 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26800 states and 35069 transitions. [2023-11-21 22:10:56,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26800 states and 35069 transitions. [2023-11-21 22:10:57,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26800 to 26512. [2023-11-21 22:10:57,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26512 states, 26512 states have (on average 1.3118964996982498) internal successors, (34781), 26511 states have internal predecessors, (34781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:57,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26512 states to 26512 states and 34781 transitions. [2023-11-21 22:10:57,434 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26512 states and 34781 transitions. [2023-11-21 22:10:57,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:57,436 INFO L428 stractBuchiCegarLoop]: Abstraction has 26512 states and 34781 transitions. [2023-11-21 22:10:57,436 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-21 22:10:57,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26512 states and 34781 transitions. [2023-11-21 22:10:57,525 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 26182 [2023-11-21 22:10:57,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:57,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:57,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:57,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:57,527 INFO L748 eck$LassoCheckResult]: Stem: 270546#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 270547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 270649#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 270650#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 270387#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 270388#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 270664#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 270611#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 270612#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 270642#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 270625#L526 assume !(0 == ~M_E~0); 270626#L526-2 assume !(0 == ~T1_E~0); 270666#L531-1 assume !(0 == ~T2_E~0); 270607#L536-1 assume !(0 == ~T3_E~0); 270608#L541-1 assume !(0 == ~T4_E~0); 270603#L546-1 assume !(0 == ~E_M~0); 270604#L551-1 assume !(0 == ~E_1~0); 270578#L556-1 assume !(0 == ~E_2~0); 270579#L561-1 assume !(0 == ~E_3~0); 270589#L566-1 assume !(0 == ~E_4~0); 270590#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270583#L262 assume !(1 == ~m_pc~0); 270584#L262-2 is_master_triggered_~__retres1~0#1 := 0; 270789#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270514#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 270515#L649 assume !(0 != activate_threads_~tmp~1#1); 270788#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270524#L281 assume !(1 == ~t1_pc~0); 270525#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 270438#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 270353#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 270354#L657 assume !(0 != activate_threads_~tmp___0~0#1); 270496#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270593#L300 assume !(1 == ~t2_pc~0); 270594#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 270705#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270653#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 270616#L665 assume !(0 != activate_threads_~tmp___1~0#1); 270366#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270367#L319 assume !(1 == ~t3_pc~0); 270321#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 270322#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 270308#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 270309#L673 assume !(0 != activate_threads_~tmp___2~0#1); 270342#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270343#L338 assume !(1 == ~t4_pc~0); 270411#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 270412#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 270418#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270419#L681 assume !(0 != activate_threads_~tmp___3~0#1); 270289#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 270290#L584 assume !(1 == ~M_E~0); 270493#L584-2 assume !(1 == ~T1_E~0); 270453#L589-1 assume !(1 == ~T2_E~0); 270454#L594-1 assume !(1 == ~T3_E~0); 270552#L599-1 assume !(1 == ~T4_E~0); 270320#L604-1 assume !(1 == ~E_M~0); 270306#L609-1 assume !(1 == ~E_1~0); 270307#L614-1 assume !(1 == ~E_2~0); 270426#L619-1 assume !(1 == ~E_3~0); 270516#L624-1 assume !(1 == ~E_4~0); 270613#L629-1 assume { :end_inline_reset_delta_events } true; 270799#L815-2 assume !false; 281256#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 281254#L501-1 [2023-11-21 22:10:57,528 INFO L750 eck$LassoCheckResult]: Loop: 281254#L501-1 assume !false; 281253#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 281251#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 281250#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 281249#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 281248#L440 assume 0 != eval_~tmp~0#1; 281246#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 280709#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 280710#L448-2 havoc eval_~tmp_ndt_1~0#1; 280456#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 280453#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 280451#L462-2 havoc eval_~tmp_ndt_2~0#1; 280449#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 280445#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 280443#L476-2 havoc eval_~tmp_ndt_3~0#1; 280441#L473-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 280401#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 280439#L490-2 havoc eval_~tmp_ndt_4~0#1; 281262#L487-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 281259#L504 assume !(0 != eval_~tmp_ndt_5~0#1); 281257#L504-2 havoc eval_~tmp_ndt_5~0#1; 281254#L501-1 [2023-11-21 22:10:57,528 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:57,687 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2023-11-21 22:10:57,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:57,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358833214] [2023-11-21 22:10:57,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:57,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:57,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:57,711 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:57,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:57,744 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:57,745 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:57,745 INFO L85 PathProgramCache]: Analyzing trace with hash -907526252, now seen corresponding path program 1 times [2023-11-21 22:10:57,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:57,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472213385] [2023-11-21 22:10:57,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:57,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:57,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:57,755 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:57,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:57,760 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:57,761 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:57,761 INFO L85 PathProgramCache]: Analyzing trace with hash 1532167850, now seen corresponding path program 1 times [2023-11-21 22:10:57,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:57,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781318646] [2023-11-21 22:10:57,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:57,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:57,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:57,775 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:57,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:57,799 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:10:59,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:59,440 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:10:59,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:10:59,660 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.11 10:10:59 BoogieIcfgContainer [2023-11-21 22:10:59,660 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-21 22:10:59,661 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-21 22:10:59,661 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-21 22:10:59,662 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-21 22:10:59,662 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:10:45" (3/4) ... [2023-11-21 22:10:59,664 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-21 22:10:59,783 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/witness.graphml [2023-11-21 22:10:59,783 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-21 22:10:59,784 INFO L158 Benchmark]: Toolchain (without parser) took 16540.66ms. Allocated memory was 161.5MB in the beginning and 1.9GB in the end (delta: 1.7GB). Free memory was 125.4MB in the beginning and 1.5GB in the end (delta: -1.4GB). Peak memory consumption was 391.9MB. Max. memory is 16.1GB. [2023-11-21 22:10:59,784 INFO L158 Benchmark]: CDTParser took 0.38ms. Allocated memory is still 119.5MB. Free memory is still 90.7MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-21 22:10:59,785 INFO L158 Benchmark]: CACSL2BoogieTranslator took 570.15ms. Allocated memory is still 161.5MB. Free memory was 124.9MB in the beginning and 109.2MB in the end (delta: 15.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-21 22:10:59,785 INFO L158 Benchmark]: Boogie Procedure Inliner took 94.21ms. Allocated memory is still 161.5MB. Free memory was 109.2MB in the beginning and 105.0MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-21 22:10:59,786 INFO L158 Benchmark]: Boogie Preprocessor took 106.56ms. Allocated memory is still 161.5MB. Free memory was 105.0MB in the beginning and 99.8MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-21 22:10:59,786 INFO L158 Benchmark]: RCFGBuilder took 1587.10ms. Allocated memory is still 161.5MB. Free memory was 99.8MB in the beginning and 111.9MB in the end (delta: -12.1MB). Peak memory consumption was 41.5MB. Max. memory is 16.1GB. [2023-11-21 22:10:59,786 INFO L158 Benchmark]: BuchiAutomizer took 14048.36ms. Allocated memory was 161.5MB in the beginning and 1.9GB in the end (delta: 1.7GB). Free memory was 111.9MB in the beginning and 1.5GB in the end (delta: -1.4GB). Peak memory consumption was 367.2MB. Max. memory is 16.1GB. [2023-11-21 22:10:59,787 INFO L158 Benchmark]: Witness Printer took 122.18ms. Allocated memory is still 1.9GB. Free memory was 1.5GB in the beginning and 1.5GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2023-11-21 22:10:59,789 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.38ms. Allocated memory is still 119.5MB. Free memory is still 90.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 570.15ms. Allocated memory is still 161.5MB. Free memory was 124.9MB in the beginning and 109.2MB in the end (delta: 15.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 94.21ms. Allocated memory is still 161.5MB. Free memory was 109.2MB in the beginning and 105.0MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 106.56ms. Allocated memory is still 161.5MB. Free memory was 105.0MB in the beginning and 99.8MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1587.10ms. Allocated memory is still 161.5MB. Free memory was 99.8MB in the beginning and 111.9MB in the end (delta: -12.1MB). Peak memory consumption was 41.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 14048.36ms. Allocated memory was 161.5MB in the beginning and 1.9GB in the end (delta: 1.7GB). Free memory was 111.9MB in the beginning and 1.5GB in the end (delta: -1.4GB). Peak memory consumption was 367.2MB. Max. memory is 16.1GB. * Witness Printer took 122.18ms. Allocated memory is still 1.9GB. Free memory was 1.5GB in the beginning and 1.5GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 26512 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 13.8s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 5.7s. Construction of modules took 0.7s. Büchi inclusion checks took 6.5s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 2.7s AutomataMinimizationTime, 23 MinimizatonAttempts, 14434 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 1.5s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 15201 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 15201 mSDsluCounter, 29700 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 13382 mSDsCounter, 260 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 723 IncrementalHoareTripleChecker+Invalid, 983 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 260 mSolverCounterUnsat, 16318 mSDtfsCounter, 723 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 435]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L445-L456] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L459-L470] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L473-L484] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L487-L498] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L501-L512] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 435]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L445-L456] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L459-L470] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L473-L484] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L487-L498] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L501-L512] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-21 22:10:59,997 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_080b6e02-5ca6-47a9-9cb4-f217b5bcd65f/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)