./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 527bcce2 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-527bcce [2023-11-21 22:04:49,280 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-21 22:04:49,381 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-21 22:04:49,387 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-21 22:04:49,388 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-21 22:04:49,417 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-21 22:04:49,417 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-21 22:04:49,418 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-21 22:04:49,419 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-21 22:04:49,419 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-21 22:04:49,420 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-21 22:04:49,421 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-21 22:04:49,421 INFO L153 SettingsManager]: * Use SBE=true [2023-11-21 22:04:49,422 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-21 22:04:49,423 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-21 22:04:49,423 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-21 22:04:49,424 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-21 22:04:49,424 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-21 22:04:49,425 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-21 22:04:49,426 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-21 22:04:49,426 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-21 22:04:49,428 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-21 22:04:49,429 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-21 22:04:49,429 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-21 22:04:49,430 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-21 22:04:49,430 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-21 22:04:49,431 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-21 22:04:49,431 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-21 22:04:49,432 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-21 22:04:49,433 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-21 22:04:49,433 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-21 22:04:49,434 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-21 22:04:49,434 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-21 22:04:49,435 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-21 22:04:49,436 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-21 22:04:49,436 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-21 22:04:49,437 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-21 22:04:49,438 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-21 22:04:49,438 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 [2023-11-21 22:04:49,787 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-21 22:04:49,822 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-21 22:04:49,825 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-21 22:04:49,826 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-21 22:04:49,827 INFO L274 PluginConnector]: CDTParser initialized [2023-11-21 22:04:49,828 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2023-11-21 22:04:52,874 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-21 22:04:53,224 INFO L384 CDTParser]: Found 1 translation units. [2023-11-21 22:04:53,225 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2023-11-21 22:04:53,257 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/data/f080afbab/ad9cf60e4ebc4fceace839e0a5cb5f4b/FLAGfee8f2ca4 [2023-11-21 22:04:53,497 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/data/f080afbab/ad9cf60e4ebc4fceace839e0a5cb5f4b [2023-11-21 22:04:53,500 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-21 22:04:53,501 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-21 22:04:53,503 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-21 22:04:53,503 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-21 22:04:53,510 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-21 22:04:53,511 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:53,512 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3ffd616d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53, skipping insertion in model container [2023-11-21 22:04:53,513 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:53,577 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-21 22:04:53,877 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 22:04:53,907 INFO L202 MainTranslator]: Completed pre-run [2023-11-21 22:04:53,967 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 22:04:53,990 INFO L206 MainTranslator]: Completed translation [2023-11-21 22:04:53,990 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53 WrapperNode [2023-11-21 22:04:53,991 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-21 22:04:53,992 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-21 22:04:53,992 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-21 22:04:53,992 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-21 22:04:53,999 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,010 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,069 INFO L138 Inliner]: procedures = 38, calls = 47, calls flagged for inlining = 42, calls inlined = 95, statements flattened = 1354 [2023-11-21 22:04:54,069 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-21 22:04:54,070 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-21 22:04:54,070 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-21 22:04:54,070 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-21 22:04:54,083 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,083 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,092 INFO L184 PluginConnector]: Executing the observer HeapSplitter from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,112 INFO L187 HeapSplitter]: Split 2 memory accesses to 1 slices as follows [2] [2023-11-21 22:04:54,113 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,113 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,152 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,179 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,182 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,188 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,196 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-21 22:04:54,197 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-21 22:04:54,197 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-21 22:04:54,197 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-21 22:04:54,198 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (1/1) ... [2023-11-21 22:04:54,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:04:54,220 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:04:54,234 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:04:54,249 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-21 22:04:54,280 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-21 22:04:54,280 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-21 22:04:54,280 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-21 22:04:54,280 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-21 22:04:54,377 INFO L240 CfgBuilder]: Building ICFG [2023-11-21 22:04:54,380 INFO L266 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-21 22:04:55,740 INFO L281 CfgBuilder]: Performing block encoding [2023-11-21 22:04:55,781 INFO L303 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-21 22:04:55,782 INFO L308 CfgBuilder]: Removed 8 assume(true) statements. [2023-11-21 22:04:55,784 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:04:55 BoogieIcfgContainer [2023-11-21 22:04:55,784 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-21 22:04:55,785 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-21 22:04:55,786 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-21 22:04:55,790 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-21 22:04:55,791 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:04:55,791 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.11 10:04:53" (1/3) ... [2023-11-21 22:04:55,792 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7f0de206 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 10:04:55, skipping insertion in model container [2023-11-21 22:04:55,792 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:04:55,794 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:04:53" (2/3) ... [2023-11-21 22:04:55,796 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7f0de206 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 10:04:55, skipping insertion in model container [2023-11-21 22:04:55,796 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:04:55,797 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:04:55" (3/3) ... [2023-11-21 22:04:55,798 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2023-11-21 22:04:55,881 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-21 22:04:55,881 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-21 22:04:55,881 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-21 22:04:55,881 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-21 22:04:55,881 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-21 22:04:55,881 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-21 22:04:55,882 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-21 22:04:55,882 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-21 22:04:55,889 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.521505376344086) internal successors, (849), 558 states have internal predecessors, (849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:55,940 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2023-11-21 22:04:55,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:55,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:55,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:55,955 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:55,955 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-21 22:04:55,957 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.521505376344086) internal successors, (849), 558 states have internal predecessors, (849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:55,976 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2023-11-21 22:04:55,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:55,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:55,982 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:55,983 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:55,992 INFO L748 eck$LassoCheckResult]: Stem: 172#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 464#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 267#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 460#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 551#L414true assume !(1 == ~m_i~0);~m_st~0 := 2; 222#L414-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 415#L419-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 414#L424-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 203#L429-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 406#L434-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 467#L439-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 201#L599true assume 0 == ~M_E~0;~M_E~0 := 1; 360#L599-2true assume !(0 == ~T1_E~0); 10#L604-1true assume !(0 == ~T2_E~0); 5#L609-1true assume !(0 == ~T3_E~0); 83#L614-1true assume !(0 == ~T4_E~0); 155#L619-1true assume !(0 == ~T5_E~0); 226#L624-1true assume !(0 == ~E_M~0); 506#L629-1true assume !(0 == ~E_1~0); 47#L634-1true assume 0 == ~E_2~0;~E_2~0 := 1; 327#L639-1true assume !(0 == ~E_3~0); 400#L644-1true assume !(0 == ~E_4~0); 351#L649-1true assume !(0 == ~E_5~0); 31#L654-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90#L292true assume !(1 == ~m_pc~0); 184#L292-2true is_master_triggered_~__retres1~0#1 := 0; 260#L303true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 486#L743true assume !(0 != activate_threads_~tmp~1#1); 62#L743-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 326#L311true assume 1 == ~t1_pc~0; 140#L312true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 231#L322true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19#L751true assume !(0 != activate_threads_~tmp___0~0#1); 427#L751-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329#L330true assume 1 == ~t2_pc~0; 157#L331true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 91#L341true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 454#L759true assume !(0 != activate_threads_~tmp___1~0#1); 468#L759-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84#L349true assume !(1 == ~t3_pc~0); 510#L349-2true is_transmit3_triggered_~__retres1~3#1 := 0; 298#L360true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 537#L767true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 444#L767-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 538#L368true assume 1 == ~t4_pc~0; 456#L369true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 388#L379true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 435#L775true assume !(0 != activate_threads_~tmp___3~0#1); 12#L775-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475#L387true assume !(1 == ~t5_pc~0); 242#L387-2true is_transmit5_triggered_~__retres1~5#1 := 0; 546#L398true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70#L783true assume !(0 != activate_threads_~tmp___4~0#1); 123#L783-2true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178#L667true assume !(1 == ~M_E~0); 335#L667-2true assume !(1 == ~T1_E~0); 342#L672-1true assume !(1 == ~T2_E~0); 147#L677-1true assume !(1 == ~T3_E~0); 309#L682-1true assume !(1 == ~T4_E~0); 402#L687-1true assume !(1 == ~T5_E~0); 469#L692-1true assume !(1 == ~E_M~0); 297#L697-1true assume 1 == ~E_1~0;~E_1~0 := 2; 527#L702-1true assume !(1 == ~E_2~0); 350#L707-1true assume !(1 == ~E_3~0); 215#L712-1true assume !(1 == ~E_4~0); 334#L717-1true assume !(1 == ~E_5~0); 316#L722-1true assume { :end_inline_reset_delta_events } true; 16#L928-2true [2023-11-21 22:04:55,995 INFO L750 eck$LassoCheckResult]: Loop: 16#L928-2true assume !false; 218#L929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 141#L574-1true assume !true; 85#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 398#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 257#L599-3true assume 0 == ~M_E~0;~M_E~0 := 1; 308#L599-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 190#L604-3true assume !(0 == ~T2_E~0); 515#L609-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 246#L614-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 20#L619-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 255#L624-3true assume 0 == ~E_M~0;~E_M~0 := 1; 305#L629-3true assume 0 == ~E_1~0;~E_1~0 := 1; 397#L634-3true assume 0 == ~E_2~0;~E_2~0 := 1; 317#L639-3true assume 0 == ~E_3~0;~E_3~0 := 1; 447#L644-3true assume !(0 == ~E_4~0); 517#L649-3true assume 0 == ~E_5~0;~E_5~0 := 1; 196#L654-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 295#L292-21true assume 1 == ~m_pc~0; 262#L293-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53#L303-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106#is_master_triggered_returnLabel#8true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 428#L743-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 187#L743-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399#L311-21true assume !(1 == ~t1_pc~0); 136#L311-23true is_transmit1_triggered_~__retres1~1#1 := 0; 35#L322-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 465#L751-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89#L751-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282#L330-21true assume 1 == ~t2_pc~0; 480#L331-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 252#L341-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 183#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 272#L759-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58#L759-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213#L349-21true assume !(1 == ~t3_pc~0); 369#L349-23true is_transmit3_triggered_~__retres1~3#1 := 0; 385#L360-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 477#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 321#L767-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 452#L767-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101#L368-21true assume 1 == ~t4_pc~0; 42#L369-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 383#L379-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 438#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 362#L775-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8#L775-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37#L387-21true assume 1 == ~t5_pc~0; 241#L388-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 338#L398-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 248#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 393#L783-21true assume !(0 != activate_threads_~tmp___4~0#1); 55#L783-23true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 186#L667-3true assume 1 == ~M_E~0;~M_E~0 := 2; 49#L667-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 331#L672-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 88#L677-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 556#L682-3true assume !(1 == ~T4_E~0); 380#L687-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 114#L692-3true assume 1 == ~E_M~0;~E_M~0 := 2; 497#L697-3true assume 1 == ~E_1~0;~E_1~0 := 2; 165#L702-3true assume 1 == ~E_2~0;~E_2~0 := 2; 261#L707-3true assume 1 == ~E_3~0;~E_3~0 := 2; 294#L712-3true assume 1 == ~E_4~0;~E_4~0 := 2; 52#L717-3true assume 1 == ~E_5~0;~E_5~0 := 2; 287#L722-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 451#L452-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 387#L484-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 238#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 192#L947true assume !(0 == start_simulation_~tmp~3#1); 528#L947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 195#L452-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 323#L484-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 27#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 378#L902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 333#L909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 419#stop_simulation_returnLabel#1true start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 278#L960true assume !(0 != start_simulation_~tmp___0~1#1); 16#L928-2true [2023-11-21 22:04:56,001 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:56,002 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2023-11-21 22:04:56,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:56,012 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927673114] [2023-11-21 22:04:56,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:56,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:56,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:56,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:56,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:56,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927673114] [2023-11-21 22:04:56,295 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [927673114] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:56,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:56,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:56,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560672958] [2023-11-21 22:04:56,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:56,303 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:56,304 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:56,304 INFO L85 PathProgramCache]: Analyzing trace with hash 1012277568, now seen corresponding path program 1 times [2023-11-21 22:04:56,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:56,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766829314] [2023-11-21 22:04:56,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:56,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:56,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:56,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:56,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:56,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766829314] [2023-11-21 22:04:56,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1766829314] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:56,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:56,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:04:56,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73762860] [2023-11-21 22:04:56,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:56,390 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:56,391 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:56,441 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:04:56,442 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:04:56,446 INFO L87 Difference]: Start difference. First operand has 559 states, 558 states have (on average 1.521505376344086) internal successors, (849), 558 states have internal predecessors, (849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:56,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:56,525 INFO L93 Difference]: Finished difference Result 557 states and 829 transitions. [2023-11-21 22:04:56,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 829 transitions. [2023-11-21 22:04:56,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-21 22:04:56,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 552 states and 824 transitions. [2023-11-21 22:04:56,549 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2023-11-21 22:04:56,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2023-11-21 22:04:56,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 824 transitions. [2023-11-21 22:04:56,556 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:56,557 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 824 transitions. [2023-11-21 22:04:56,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 824 transitions. [2023-11-21 22:04:56,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2023-11-21 22:04:56,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4927536231884058) internal successors, (824), 551 states have internal predecessors, (824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:56,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 824 transitions. [2023-11-21 22:04:56,628 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 824 transitions. [2023-11-21 22:04:56,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:04:56,633 INFO L428 stractBuchiCegarLoop]: Abstraction has 552 states and 824 transitions. [2023-11-21 22:04:56,633 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-21 22:04:56,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 824 transitions. [2023-11-21 22:04:56,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-21 22:04:56,638 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:56,638 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:56,642 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:56,642 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:56,643 INFO L748 eck$LassoCheckResult]: Stem: 1434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1666#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 1504#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1505#L419-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1650#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1479#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1480#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1646#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1477#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 1478#L599-2 assume !(0 == ~T1_E~0); 1142#L604-1 assume !(0 == ~T2_E~0); 1131#L609-1 assume !(0 == ~T3_E~0); 1132#L614-1 assume !(0 == ~T4_E~0); 1299#L619-1 assume !(0 == ~T5_E~0); 1413#L624-1 assume !(0 == ~E_M~0); 1508#L629-1 assume !(0 == ~E_1~0); 1221#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1222#L639-1 assume !(0 == ~E_3~0); 1609#L644-1 assume !(0 == ~E_4~0); 1624#L649-1 assume !(0 == ~E_5~0); 1185#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1186#L292 assume !(1 == ~m_pc~0); 1312#L292-2 is_master_triggered_~__retres1~0#1 := 0; 1450#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1409#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1410#L743 assume !(0 != activate_threads_~tmp~1#1); 1254#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1255#L311 assume 1 == ~t1_pc~0; 1386#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1387#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1179#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1158#L751 assume !(0 != activate_threads_~tmp___0~0#1); 1159#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1610#L330 assume 1 == ~t2_pc~0; 1415#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1314#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1315#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1559#L759 assume !(0 != activate_threads_~tmp___1~0#1); 1664#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1300#L349 assume !(1 == ~t3_pc~0); 1301#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1350#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1133#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1134#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1659#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1660#L368 assume 1 == ~t4_pc~0; 1665#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1377#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1285#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1286#L775 assume !(0 != activate_threads_~tmp___3~0#1); 1145#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1146#L387 assume !(1 == ~t5_pc~0); 1525#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1526#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1418#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1271#L783 assume !(0 != activate_threads_~tmp___4~0#1); 1272#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1365#L667 assume !(1 == ~M_E~0); 1442#L667-2 assume !(1 == ~T1_E~0); 1616#L672-1 assume !(1 == ~T2_E~0); 1400#L677-1 assume !(1 == ~T3_E~0); 1401#L682-1 assume !(1 == ~T4_E~0); 1593#L687-1 assume !(1 == ~T5_E~0); 1643#L692-1 assume !(1 == ~E_M~0); 1583#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1584#L702-1 assume !(1 == ~E_2~0); 1623#L707-1 assume !(1 == ~E_3~0); 1496#L712-1 assume !(1 == ~E_4~0); 1497#L717-1 assume !(1 == ~E_5~0); 1600#L722-1 assume { :end_inline_reset_delta_events } true; 1153#L928-2 [2023-11-21 22:04:56,643 INFO L750 eck$LassoCheckResult]: Loop: 1153#L928-2 assume !false; 1154#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1389#L574-1 assume !false; 1390#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1658#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1353#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1189#L499 assume !(0 != eval_~tmp~0#1); 1190#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1303#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1548#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1549#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1459#L604-3 assume !(0 == ~T2_E~0); 1460#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1534#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1160#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1161#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1543#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1590#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1601#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1602#L644-3 assume !(0 == ~E_4~0); 1662#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1469#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1470#L292-21 assume !(1 == ~m_pc~0); 1369#L292-23 is_master_triggered_~__retres1~0#1 := 0; 1236#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1237#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1339#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1453#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1454#L311-21 assume !(1 == ~t1_pc~0); 1381#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 1193#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1194#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1262#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1310#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1311#L330-21 assume !(1 == ~t2_pc~0); 1571#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 1540#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1448#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1449#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1246#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1247#L349-21 assume 1 == ~t3_pc~0; 1493#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1633#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1638#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1604#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1605#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1329#L368-21 assume 1 == ~t4_pc~0; 1210#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1211#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1637#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1627#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1138#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1139#L387-21 assume !(1 == ~t5_pc~0); 1198#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 1524#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1532#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1533#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 1238#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1239#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1223#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1224#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1306#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1307#L682-3 assume !(1 == ~T4_E~0); 1636#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1348#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1349#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1423#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1424#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1550#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1230#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1231#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1575#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1168#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1521#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1462#L947 assume !(0 == start_simulation_~tmp~3#1); 1463#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1466#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1427#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1177#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 1178#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1614#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1615#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1563#L960 assume !(0 != start_simulation_~tmp___0~1#1); 1153#L928-2 [2023-11-21 22:04:56,644 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:56,644 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2023-11-21 22:04:56,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:56,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096544946] [2023-11-21 22:04:56,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:56,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:56,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:56,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:56,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:56,752 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2096544946] [2023-11-21 22:04:56,752 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2096544946] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:56,753 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:56,753 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:56,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359187286] [2023-11-21 22:04:56,753 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:56,754 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:56,755 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:56,756 INFO L85 PathProgramCache]: Analyzing trace with hash -1923800974, now seen corresponding path program 1 times [2023-11-21 22:04:56,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:56,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [595973439] [2023-11-21 22:04:56,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:56,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:56,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:56,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:56,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:56,844 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [595973439] [2023-11-21 22:04:56,844 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [595973439] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:56,844 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:56,844 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:56,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962773315] [2023-11-21 22:04:56,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:56,845 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:56,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:56,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:04:56,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:04:56,847 INFO L87 Difference]: Start difference. First operand 552 states and 824 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:56,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:56,884 INFO L93 Difference]: Finished difference Result 552 states and 823 transitions. [2023-11-21 22:04:56,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 823 transitions. [2023-11-21 22:04:56,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-21 22:04:56,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 823 transitions. [2023-11-21 22:04:56,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2023-11-21 22:04:56,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2023-11-21 22:04:56,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 823 transitions. [2023-11-21 22:04:56,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:56,908 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 823 transitions. [2023-11-21 22:04:56,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 823 transitions. [2023-11-21 22:04:56,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2023-11-21 22:04:56,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4909420289855073) internal successors, (823), 551 states have internal predecessors, (823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:56,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 823 transitions. [2023-11-21 22:04:56,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 823 transitions. [2023-11-21 22:04:56,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:04:56,950 INFO L428 stractBuchiCegarLoop]: Abstraction has 552 states and 823 transitions. [2023-11-21 22:04:56,950 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-21 22:04:56,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 823 transitions. [2023-11-21 22:04:56,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-21 22:04:56,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:56,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:56,965 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:56,965 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:56,966 INFO L748 eck$LassoCheckResult]: Stem: 2545#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2665#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2666#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2777#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 2615#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2616#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2761#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2590#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2591#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2757#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2588#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 2589#L599-2 assume !(0 == ~T1_E~0); 2255#L604-1 assume !(0 == ~T2_E~0); 2242#L609-1 assume !(0 == ~T3_E~0); 2243#L614-1 assume !(0 == ~T4_E~0); 2410#L619-1 assume !(0 == ~T5_E~0); 2524#L624-1 assume !(0 == ~E_M~0); 2619#L629-1 assume !(0 == ~E_1~0); 2332#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2333#L639-1 assume !(0 == ~E_3~0); 2720#L644-1 assume !(0 == ~E_4~0); 2735#L649-1 assume !(0 == ~E_5~0); 2296#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2297#L292 assume !(1 == ~m_pc~0); 2423#L292-2 is_master_triggered_~__retres1~0#1 := 0; 2561#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2520#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2521#L743 assume !(0 != activate_threads_~tmp~1#1); 2365#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2366#L311 assume 1 == ~t1_pc~0; 2497#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2498#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2290#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2269#L751 assume !(0 != activate_threads_~tmp___0~0#1); 2270#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2721#L330 assume 1 == ~t2_pc~0; 2526#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2425#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2426#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2670#L759 assume !(0 != activate_threads_~tmp___1~0#1); 2775#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2411#L349 assume !(1 == ~t3_pc~0); 2412#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2461#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2246#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2247#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2770#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2771#L368 assume 1 == ~t4_pc~0; 2776#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2488#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2397#L775 assume !(0 != activate_threads_~tmp___3~0#1); 2256#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2257#L387 assume !(1 == ~t5_pc~0); 2636#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2637#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2529#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2382#L783 assume !(0 != activate_threads_~tmp___4~0#1); 2383#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2478#L667 assume !(1 == ~M_E~0); 2553#L667-2 assume !(1 == ~T1_E~0); 2727#L672-1 assume !(1 == ~T2_E~0); 2511#L677-1 assume !(1 == ~T3_E~0); 2512#L682-1 assume !(1 == ~T4_E~0); 2704#L687-1 assume !(1 == ~T5_E~0); 2754#L692-1 assume !(1 == ~E_M~0); 2694#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2695#L702-1 assume !(1 == ~E_2~0); 2734#L707-1 assume !(1 == ~E_3~0); 2607#L712-1 assume !(1 == ~E_4~0); 2608#L717-1 assume !(1 == ~E_5~0); 2711#L722-1 assume { :end_inline_reset_delta_events } true; 2264#L928-2 [2023-11-21 22:04:56,968 INFO L750 eck$LassoCheckResult]: Loop: 2264#L928-2 assume !false; 2265#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2500#L574-1 assume !false; 2501#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2769#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2464#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2687#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2300#L499 assume !(0 != eval_~tmp~0#1); 2301#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2414#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2659#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2660#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2570#L604-3 assume !(0 == ~T2_E~0); 2571#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2645#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2271#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2272#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2654#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2701#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2712#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2713#L644-3 assume !(0 == ~E_4~0); 2773#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2580#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2581#L292-21 assume !(1 == ~m_pc~0); 2480#L292-23 is_master_triggered_~__retres1~0#1 := 0; 2347#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2348#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2450#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2564#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2565#L311-21 assume 1 == ~t1_pc~0; 2753#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2304#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2305#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2373#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2421#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2422#L330-21 assume !(1 == ~t2_pc~0); 2682#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 2651#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2559#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2560#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2359#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2360#L349-21 assume 1 == ~t3_pc~0; 2604#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2743#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2749#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2715#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2716#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2440#L368-21 assume 1 == ~t4_pc~0; 2321#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2322#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2748#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2738#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2244#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2245#L387-21 assume !(1 == ~t5_pc~0); 2309#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 2635#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2643#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2644#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 2349#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2350#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2334#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2335#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2417#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2418#L682-3 assume !(1 == ~T4_E~0); 2747#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2459#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2460#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2534#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2535#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2661#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2343#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2344#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2686#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2279#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2632#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2573#L947 assume !(0 == start_simulation_~tmp~3#1); 2574#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2577#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2538#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 2289#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2725#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2726#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2674#L960 assume !(0 != start_simulation_~tmp___0~1#1); 2264#L928-2 [2023-11-21 22:04:56,969 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:56,969 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2023-11-21 22:04:56,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:56,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916305241] [2023-11-21 22:04:56,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:56,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:56,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:57,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:57,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:57,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916305241] [2023-11-21 22:04:57,088 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916305241] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:57,088 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:57,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:57,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1678910517] [2023-11-21 22:04:57,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:57,089 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:57,089 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:57,090 INFO L85 PathProgramCache]: Analyzing trace with hash -815672335, now seen corresponding path program 1 times [2023-11-21 22:04:57,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:57,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607927087] [2023-11-21 22:04:57,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:57,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:57,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:57,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:57,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:57,169 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607927087] [2023-11-21 22:04:57,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607927087] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:57,169 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:57,170 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:57,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690470978] [2023-11-21 22:04:57,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:57,171 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:57,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:57,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:04:57,172 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:04:57,172 INFO L87 Difference]: Start difference. First operand 552 states and 823 transitions. cyclomatic complexity: 272 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:57,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:57,201 INFO L93 Difference]: Finished difference Result 552 states and 822 transitions. [2023-11-21 22:04:57,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 822 transitions. [2023-11-21 22:04:57,207 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-21 22:04:57,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 822 transitions. [2023-11-21 22:04:57,213 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2023-11-21 22:04:57,213 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2023-11-21 22:04:57,214 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 822 transitions. [2023-11-21 22:04:57,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:57,215 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 822 transitions. [2023-11-21 22:04:57,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 822 transitions. [2023-11-21 22:04:57,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2023-11-21 22:04:57,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4891304347826086) internal successors, (822), 551 states have internal predecessors, (822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:57,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 822 transitions. [2023-11-21 22:04:57,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 822 transitions. [2023-11-21 22:04:57,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:04:57,232 INFO L428 stractBuchiCegarLoop]: Abstraction has 552 states and 822 transitions. [2023-11-21 22:04:57,232 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-21 22:04:57,232 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 822 transitions. [2023-11-21 22:04:57,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-21 22:04:57,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:57,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:57,240 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:57,240 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:57,241 INFO L748 eck$LassoCheckResult]: Stem: 3656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3776#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3777#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3888#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 3726#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3727#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3872#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3703#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3704#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3868#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3699#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 3700#L599-2 assume !(0 == ~T1_E~0); 3366#L604-1 assume !(0 == ~T2_E~0); 3353#L609-1 assume !(0 == ~T3_E~0); 3354#L614-1 assume !(0 == ~T4_E~0); 3521#L619-1 assume !(0 == ~T5_E~0); 3635#L624-1 assume !(0 == ~E_M~0); 3730#L629-1 assume !(0 == ~E_1~0); 3443#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3444#L639-1 assume !(0 == ~E_3~0); 3831#L644-1 assume !(0 == ~E_4~0); 3846#L649-1 assume !(0 == ~E_5~0); 3407#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3408#L292 assume !(1 == ~m_pc~0); 3534#L292-2 is_master_triggered_~__retres1~0#1 := 0; 3672#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3631#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3632#L743 assume !(0 != activate_threads_~tmp~1#1); 3476#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3477#L311 assume 1 == ~t1_pc~0; 3608#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3609#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3401#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3380#L751 assume !(0 != activate_threads_~tmp___0~0#1); 3381#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3832#L330 assume 1 == ~t2_pc~0; 3637#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3536#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3537#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3781#L759 assume !(0 != activate_threads_~tmp___1~0#1); 3886#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3522#L349 assume !(1 == ~t3_pc~0); 3523#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3572#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3360#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3361#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3881#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3882#L368 assume 1 == ~t4_pc~0; 3887#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3599#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3507#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3508#L775 assume !(0 != activate_threads_~tmp___3~0#1); 3367#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3368#L387 assume !(1 == ~t5_pc~0); 3747#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3748#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3496#L783 assume !(0 != activate_threads_~tmp___4~0#1); 3497#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3589#L667 assume !(1 == ~M_E~0); 3664#L667-2 assume !(1 == ~T1_E~0); 3839#L672-1 assume !(1 == ~T2_E~0); 3622#L677-1 assume !(1 == ~T3_E~0); 3623#L682-1 assume !(1 == ~T4_E~0); 3815#L687-1 assume !(1 == ~T5_E~0); 3865#L692-1 assume !(1 == ~E_M~0); 3805#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3806#L702-1 assume !(1 == ~E_2~0); 3845#L707-1 assume !(1 == ~E_3~0); 3718#L712-1 assume !(1 == ~E_4~0); 3719#L717-1 assume !(1 == ~E_5~0); 3822#L722-1 assume { :end_inline_reset_delta_events } true; 3375#L928-2 [2023-11-21 22:04:57,242 INFO L750 eck$LassoCheckResult]: Loop: 3375#L928-2 assume !false; 3376#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3611#L574-1 assume !false; 3612#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3880#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3575#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3798#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3411#L499 assume !(0 != eval_~tmp~0#1); 3412#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3525#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3770#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3771#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3681#L604-3 assume !(0 == ~T2_E~0); 3682#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3757#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3382#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3383#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3765#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3812#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3823#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3824#L644-3 assume !(0 == ~E_4~0); 3884#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3691#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3692#L292-21 assume !(1 == ~m_pc~0); 3591#L292-23 is_master_triggered_~__retres1~0#1 := 0; 3458#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3459#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3561#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3675#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3676#L311-21 assume !(1 == ~t1_pc~0); 3602#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 3415#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3416#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3484#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3532#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3533#L330-21 assume 1 == ~t2_pc~0; 3792#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3762#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3669#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3670#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3465#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3466#L349-21 assume 1 == ~t3_pc~0; 3715#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3854#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3860#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3826#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3827#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3551#L368-21 assume 1 == ~t4_pc~0; 3432#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3433#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3859#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3849#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3358#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3359#L387-21 assume !(1 == ~t5_pc~0); 3420#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 3746#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3755#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3756#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 3460#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3461#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3448#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3449#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3528#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3529#L682-3 assume !(1 == ~T4_E~0); 3858#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3570#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3571#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3645#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3646#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3772#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3454#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3455#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3797#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3390#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3743#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3684#L947 assume !(0 == start_simulation_~tmp~3#1); 3685#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3688#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3649#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3399#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 3400#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3836#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3837#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3785#L960 assume !(0 != start_simulation_~tmp___0~1#1); 3375#L928-2 [2023-11-21 22:04:57,243 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:57,243 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2023-11-21 22:04:57,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:57,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763572451] [2023-11-21 22:04:57,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:57,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:57,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:57,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:57,331 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:57,331 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1763572451] [2023-11-21 22:04:57,332 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1763572451] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:57,332 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:57,332 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:57,332 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345718422] [2023-11-21 22:04:57,333 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:57,333 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:57,333 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:57,334 INFO L85 PathProgramCache]: Analyzing trace with hash 902962993, now seen corresponding path program 1 times [2023-11-21 22:04:57,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:57,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334401883] [2023-11-21 22:04:57,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:57,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:57,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:57,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:57,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:57,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [334401883] [2023-11-21 22:04:57,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [334401883] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:57,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:57,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:57,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100949583] [2023-11-21 22:04:57,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:57,388 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:57,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:57,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:04:57,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:04:57,389 INFO L87 Difference]: Start difference. First operand 552 states and 822 transitions. cyclomatic complexity: 271 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:57,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:57,408 INFO L93 Difference]: Finished difference Result 552 states and 821 transitions. [2023-11-21 22:04:57,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 821 transitions. [2023-11-21 22:04:57,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-21 22:04:57,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 821 transitions. [2023-11-21 22:04:57,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2023-11-21 22:04:57,420 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2023-11-21 22:04:57,420 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 821 transitions. [2023-11-21 22:04:57,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:57,422 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 821 transitions. [2023-11-21 22:04:57,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 821 transitions. [2023-11-21 22:04:57,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2023-11-21 22:04:57,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4873188405797102) internal successors, (821), 551 states have internal predecessors, (821), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:57,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 821 transitions. [2023-11-21 22:04:57,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 821 transitions. [2023-11-21 22:04:57,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:04:57,438 INFO L428 stractBuchiCegarLoop]: Abstraction has 552 states and 821 transitions. [2023-11-21 22:04:57,438 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-21 22:04:57,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 821 transitions. [2023-11-21 22:04:57,442 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-21 22:04:57,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:57,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:57,444 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:57,445 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:57,445 INFO L748 eck$LassoCheckResult]: Stem: 4767#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4887#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4888#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4999#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 4837#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4838#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4983#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4814#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4815#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4979#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4810#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 4811#L599-2 assume !(0 == ~T1_E~0); 4477#L604-1 assume !(0 == ~T2_E~0); 4464#L609-1 assume !(0 == ~T3_E~0); 4465#L614-1 assume !(0 == ~T4_E~0); 4632#L619-1 assume !(0 == ~T5_E~0); 4746#L624-1 assume !(0 == ~E_M~0); 4841#L629-1 assume !(0 == ~E_1~0); 4554#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4555#L639-1 assume !(0 == ~E_3~0); 4942#L644-1 assume !(0 == ~E_4~0); 4957#L649-1 assume !(0 == ~E_5~0); 4518#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4519#L292 assume !(1 == ~m_pc~0); 4645#L292-2 is_master_triggered_~__retres1~0#1 := 0; 4783#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4744#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4745#L743 assume !(0 != activate_threads_~tmp~1#1); 4587#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4588#L311 assume 1 == ~t1_pc~0; 4719#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4720#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4512#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4491#L751 assume !(0 != activate_threads_~tmp___0~0#1); 4492#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4943#L330 assume 1 == ~t2_pc~0; 4748#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4647#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4648#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4892#L759 assume !(0 != activate_threads_~tmp___1~0#1); 4997#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4633#L349 assume !(1 == ~t3_pc~0); 4634#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4683#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4471#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4472#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4992#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4993#L368 assume 1 == ~t4_pc~0; 4998#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4712#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4618#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4619#L775 assume !(0 != activate_threads_~tmp___3~0#1); 4478#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4479#L387 assume !(1 == ~t5_pc~0); 4858#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4859#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4751#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4607#L783 assume !(0 != activate_threads_~tmp___4~0#1); 4608#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4700#L667 assume !(1 == ~M_E~0); 4775#L667-2 assume !(1 == ~T1_E~0); 4950#L672-1 assume !(1 == ~T2_E~0); 4733#L677-1 assume !(1 == ~T3_E~0); 4734#L682-1 assume !(1 == ~T4_E~0); 4926#L687-1 assume !(1 == ~T5_E~0); 4976#L692-1 assume !(1 == ~E_M~0); 4916#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4917#L702-1 assume !(1 == ~E_2~0); 4956#L707-1 assume !(1 == ~E_3~0); 4829#L712-1 assume !(1 == ~E_4~0); 4830#L717-1 assume !(1 == ~E_5~0); 4933#L722-1 assume { :end_inline_reset_delta_events } true; 4486#L928-2 [2023-11-21 22:04:57,446 INFO L750 eck$LassoCheckResult]: Loop: 4486#L928-2 assume !false; 4487#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4722#L574-1 assume !false; 4723#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4991#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4686#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4909#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4522#L499 assume !(0 != eval_~tmp~0#1); 4523#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4636#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4881#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4882#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4793#L604-3 assume !(0 == ~T2_E~0); 4794#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4868#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4493#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4494#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4876#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4923#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4934#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4935#L644-3 assume !(0 == ~E_4~0); 4995#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4802#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4803#L292-21 assume 1 == ~m_pc~0; 4884#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4569#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4570#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4670#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4786#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4787#L311-21 assume !(1 == ~t1_pc~0); 4713#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 4526#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4527#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4595#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4643#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4644#L330-21 assume !(1 == ~t2_pc~0); 4903#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 4873#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4781#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4782#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4576#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4577#L349-21 assume 1 == ~t3_pc~0; 4826#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4965#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4971#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4937#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4938#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4662#L368-21 assume !(1 == ~t4_pc~0); 4545#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4544#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4970#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4960#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4469#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4470#L387-21 assume !(1 == ~t5_pc~0); 4531#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4857#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4866#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4867#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 4571#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4572#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4559#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4560#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4639#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4640#L682-3 assume !(1 == ~T4_E~0); 4969#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4681#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4682#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4756#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4757#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4883#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4565#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4566#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4908#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4501#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4854#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4795#L947 assume !(0 == start_simulation_~tmp~3#1); 4796#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4799#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4760#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4510#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 4511#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4947#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4948#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4896#L960 assume !(0 != start_simulation_~tmp___0~1#1); 4486#L928-2 [2023-11-21 22:04:57,447 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:57,447 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2023-11-21 22:04:57,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:57,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78886384] [2023-11-21 22:04:57,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:57,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:57,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:57,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:57,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:57,484 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78886384] [2023-11-21 22:04:57,485 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [78886384] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:57,485 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:57,485 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:57,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407836442] [2023-11-21 22:04:57,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:57,486 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:57,486 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:57,487 INFO L85 PathProgramCache]: Analyzing trace with hash -1827073166, now seen corresponding path program 1 times [2023-11-21 22:04:57,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:57,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740014588] [2023-11-21 22:04:57,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:57,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:57,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:57,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:57,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:57,569 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740014588] [2023-11-21 22:04:57,569 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740014588] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:57,569 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:57,569 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:57,570 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915314569] [2023-11-21 22:04:57,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:57,570 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:57,570 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:57,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:04:57,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:04:57,571 INFO L87 Difference]: Start difference. First operand 552 states and 821 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:57,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:57,594 INFO L93 Difference]: Finished difference Result 552 states and 820 transitions. [2023-11-21 22:04:57,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 820 transitions. [2023-11-21 22:04:57,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-21 22:04:57,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 820 transitions. [2023-11-21 22:04:57,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2023-11-21 22:04:57,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2023-11-21 22:04:57,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 820 transitions. [2023-11-21 22:04:57,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:57,609 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 820 transitions. [2023-11-21 22:04:57,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 820 transitions. [2023-11-21 22:04:57,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2023-11-21 22:04:57,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4855072463768115) internal successors, (820), 551 states have internal predecessors, (820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:57,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 820 transitions. [2023-11-21 22:04:57,623 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 820 transitions. [2023-11-21 22:04:57,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:04:57,627 INFO L428 stractBuchiCegarLoop]: Abstraction has 552 states and 820 transitions. [2023-11-21 22:04:57,627 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-21 22:04:57,627 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 820 transitions. [2023-11-21 22:04:57,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-21 22:04:57,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:57,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:57,633 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:57,633 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:57,633 INFO L748 eck$LassoCheckResult]: Stem: 5879#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5998#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5999#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6110#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 5948#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5949#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6094#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5925#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5926#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6090#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5921#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 5922#L599-2 assume !(0 == ~T1_E~0); 5588#L604-1 assume !(0 == ~T2_E~0); 5575#L609-1 assume !(0 == ~T3_E~0); 5576#L614-1 assume !(0 == ~T4_E~0); 5743#L619-1 assume !(0 == ~T5_E~0); 5857#L624-1 assume !(0 == ~E_M~0); 5952#L629-1 assume !(0 == ~E_1~0); 5665#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5666#L639-1 assume !(0 == ~E_3~0); 6053#L644-1 assume !(0 == ~E_4~0); 6068#L649-1 assume !(0 == ~E_5~0); 5629#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5630#L292 assume !(1 == ~m_pc~0); 5756#L292-2 is_master_triggered_~__retres1~0#1 := 0; 5894#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5855#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5856#L743 assume !(0 != activate_threads_~tmp~1#1); 5698#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5699#L311 assume 1 == ~t1_pc~0; 5830#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5831#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5623#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5602#L751 assume !(0 != activate_threads_~tmp___0~0#1); 5603#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6056#L330 assume 1 == ~t2_pc~0; 5859#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5759#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5760#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6003#L759 assume !(0 != activate_threads_~tmp___1~0#1); 6108#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5744#L349 assume !(1 == ~t3_pc~0); 5745#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5794#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5582#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5583#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6103#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6104#L368 assume 1 == ~t4_pc~0; 6109#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5823#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5729#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5730#L775 assume !(0 != activate_threads_~tmp___3~0#1); 5589#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5590#L387 assume !(1 == ~t5_pc~0); 5969#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5970#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5862#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5718#L783 assume !(0 != activate_threads_~tmp___4~0#1); 5719#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5811#L667 assume !(1 == ~M_E~0); 5886#L667-2 assume !(1 == ~T1_E~0); 6061#L672-1 assume !(1 == ~T2_E~0); 5844#L677-1 assume !(1 == ~T3_E~0); 5845#L682-1 assume !(1 == ~T4_E~0); 6037#L687-1 assume !(1 == ~T5_E~0); 6087#L692-1 assume !(1 == ~E_M~0); 6027#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6028#L702-1 assume !(1 == ~E_2~0); 6067#L707-1 assume !(1 == ~E_3~0); 5940#L712-1 assume !(1 == ~E_4~0); 5941#L717-1 assume !(1 == ~E_5~0); 6044#L722-1 assume { :end_inline_reset_delta_events } true; 5597#L928-2 [2023-11-21 22:04:57,634 INFO L750 eck$LassoCheckResult]: Loop: 5597#L928-2 assume !false; 5598#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5833#L574-1 assume !false; 5834#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6102#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5797#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6020#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5633#L499 assume !(0 != eval_~tmp~0#1); 5634#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5747#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5992#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5993#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5903#L604-3 assume !(0 == ~T2_E~0); 5904#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5976#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5604#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5605#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5987#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6034#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6045#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6046#L644-3 assume !(0 == ~E_4~0); 6106#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5913#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5914#L292-21 assume !(1 == ~m_pc~0); 5813#L292-23 is_master_triggered_~__retres1~0#1 := 0; 5680#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5681#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5781#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5897#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5898#L311-21 assume !(1 == ~t1_pc~0); 5825#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 5637#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5638#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5706#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5754#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5755#L330-21 assume !(1 == ~t2_pc~0); 6014#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 5984#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5892#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5893#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5690#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5691#L349-21 assume 1 == ~t3_pc~0; 5937#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6077#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6082#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6048#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6049#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5773#L368-21 assume 1 == ~t4_pc~0; 5654#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5655#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6081#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6071#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5580#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5581#L387-21 assume !(1 == ~t5_pc~0); 5642#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5968#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5978#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5979#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 5682#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5683#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5670#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5671#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5752#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5753#L682-3 assume !(1 == ~T4_E~0); 6080#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5792#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5793#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5867#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5868#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5994#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5676#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5677#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6019#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5612#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5965#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5906#L947 assume !(0 == start_simulation_~tmp~3#1); 5907#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5910#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5871#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5621#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 5622#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6058#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6059#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6008#L960 assume !(0 != start_simulation_~tmp___0~1#1); 5597#L928-2 [2023-11-21 22:04:57,634 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:57,635 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2023-11-21 22:04:57,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:57,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298757675] [2023-11-21 22:04:57,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:57,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:57,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:57,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:57,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:57,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298757675] [2023-11-21 22:04:57,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1298757675] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:57,718 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:57,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:04:57,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133349857] [2023-11-21 22:04:57,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:57,725 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:57,726 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:57,726 INFO L85 PathProgramCache]: Analyzing trace with hash -1923800974, now seen corresponding path program 2 times [2023-11-21 22:04:57,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:57,726 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506041756] [2023-11-21 22:04:57,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:57,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:57,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:57,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:57,793 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:57,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506041756] [2023-11-21 22:04:57,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [506041756] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:57,794 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:57,795 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:57,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395372630] [2023-11-21 22:04:57,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:57,796 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:57,796 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:57,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:04:57,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:04:57,797 INFO L87 Difference]: Start difference. First operand 552 states and 820 transitions. cyclomatic complexity: 269 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:57,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:57,865 INFO L93 Difference]: Finished difference Result 981 states and 1451 transitions. [2023-11-21 22:04:57,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 981 states and 1451 transitions. [2023-11-21 22:04:57,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2023-11-21 22:04:57,883 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 981 states to 981 states and 1451 transitions. [2023-11-21 22:04:57,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 981 [2023-11-21 22:04:57,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 981 [2023-11-21 22:04:57,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 981 states and 1451 transitions. [2023-11-21 22:04:57,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:57,887 INFO L218 hiAutomatonCegarLoop]: Abstraction has 981 states and 1451 transitions. [2023-11-21 22:04:57,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 981 states and 1451 transitions. [2023-11-21 22:04:57,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 981 to 981. [2023-11-21 22:04:57,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981 states, 981 states have (on average 1.4791029561671762) internal successors, (1451), 980 states have internal predecessors, (1451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:57,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981 states to 981 states and 1451 transitions. [2023-11-21 22:04:57,943 INFO L240 hiAutomatonCegarLoop]: Abstraction has 981 states and 1451 transitions. [2023-11-21 22:04:57,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:04:57,944 INFO L428 stractBuchiCegarLoop]: Abstraction has 981 states and 1451 transitions. [2023-11-21 22:04:57,944 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-21 22:04:57,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 981 states and 1451 transitions. [2023-11-21 22:04:57,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2023-11-21 22:04:57,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:57,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:57,952 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:57,952 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:57,952 INFO L748 eck$LassoCheckResult]: Stem: 7423#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7693#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 7501#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7502#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7670#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7473#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7474#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7664#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7469#L599 assume !(0 == ~M_E~0); 7470#L599-2 assume !(0 == ~T1_E~0); 7128#L604-1 assume !(0 == ~T2_E~0); 7115#L609-1 assume !(0 == ~T3_E~0); 7116#L614-1 assume !(0 == ~T4_E~0); 7284#L619-1 assume !(0 == ~T5_E~0); 7400#L624-1 assume !(0 == ~E_M~0); 7506#L629-1 assume !(0 == ~E_1~0); 7205#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7206#L639-1 assume !(0 == ~E_3~0); 7613#L644-1 assume !(0 == ~E_4~0); 7630#L649-1 assume !(0 == ~E_5~0); 7169#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7170#L292 assume !(1 == ~m_pc~0); 7297#L292-2 is_master_triggered_~__retres1~0#1 := 0; 7441#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7396#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7397#L743 assume !(0 != activate_threads_~tmp~1#1); 7238#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7239#L311 assume 1 == ~t1_pc~0; 7373#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7374#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7163#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7142#L751 assume !(0 != activate_threads_~tmp___0~0#1); 7143#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7614#L330 assume 1 == ~t2_pc~0; 7402#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7299#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7300#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7559#L759 assume !(0 != activate_threads_~tmp___1~0#1); 7691#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7285#L349 assume !(1 == ~t3_pc~0); 7286#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7333#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7117#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7118#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7684#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7685#L368 assume 1 == ~t4_pc~0; 7692#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7364#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7270#L775 assume !(0 != activate_threads_~tmp___3~0#1); 7129#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7130#L387 assume !(1 == ~t5_pc~0); 7525#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7526#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7405#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7255#L783 assume !(0 != activate_threads_~tmp___4~0#1); 7256#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7351#L667 assume !(1 == ~M_E~0); 7433#L667-2 assume !(1 == ~T1_E~0); 7620#L672-1 assume !(1 == ~T2_E~0); 7387#L677-1 assume !(1 == ~T3_E~0); 7388#L682-1 assume !(1 == ~T4_E~0); 7595#L687-1 assume !(1 == ~T5_E~0); 7659#L692-1 assume !(1 == ~E_M~0); 7583#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7584#L702-1 assume !(1 == ~E_2~0); 7629#L707-1 assume !(1 == ~E_3~0); 7490#L712-1 assume !(1 == ~E_4~0); 7491#L717-1 assume !(1 == ~E_5~0); 7602#L722-1 assume { :end_inline_reset_delta_events } true; 7137#L928-2 [2023-11-21 22:04:57,953 INFO L750 eck$LassoCheckResult]: Loop: 7137#L928-2 assume !false; 7138#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7376#L574-1 assume !false; 7377#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7683#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7338#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7770#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7768#L499 assume !(0 != eval_~tmp~0#1); 7767#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7656#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7546#L599-3 assume !(0 == ~M_E~0); 7547#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7451#L604-3 assume !(0 == ~T2_E~0); 7452#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7532#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7144#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7145#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7543#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7592#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7758#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7757#L644-3 assume !(0 == ~E_4~0); 7756#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7755#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7754#L292-21 assume !(1 == ~m_pc~0); 7752#L292-23 is_master_triggered_~__retres1~0#1 := 0; 7751#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7750#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7678#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7445#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7446#L311-21 assume 1 == ~t1_pc~0; 7747#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7746#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7745#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7744#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7743#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7742#L330-21 assume 1 == ~t2_pc~0; 7699#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7540#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7439#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7440#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7230#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7231#L349-21 assume !(1 == ~t3_pc~0); 7488#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 7643#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7650#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7607#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7608#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7689#L368-21 assume !(1 == ~t4_pc~0); 7729#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7728#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7682#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7636#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7122#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7123#L387-21 assume !(1 == ~t5_pc~0); 7182#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 7524#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7534#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7535#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 7222#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7223#L667-3 assume !(1 == ~M_E~0); 7444#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7969#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7968#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7967#L682-3 assume !(1 == ~T4_E~0); 7966#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7965#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7964#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7963#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7962#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7961#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7960#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7959#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7947#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7943#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7941#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7940#L947 assume !(0 == start_simulation_~tmp~3#1); 7938#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7934#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7931#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7930#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 7929#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7618#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7619#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7564#L960 assume !(0 != start_simulation_~tmp___0~1#1); 7137#L928-2 [2023-11-21 22:04:57,953 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:57,953 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2023-11-21 22:04:57,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:57,954 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439998109] [2023-11-21 22:04:57,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:57,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:57,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:57,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:57,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:57,997 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439998109] [2023-11-21 22:04:57,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [439998109] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:57,997 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:57,997 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:04:57,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424090989] [2023-11-21 22:04:57,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:57,998 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:57,998 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:57,998 INFO L85 PathProgramCache]: Analyzing trace with hash 1767686066, now seen corresponding path program 1 times [2023-11-21 22:04:57,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:57,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706730771] [2023-11-21 22:04:57,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:57,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:58,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:58,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:58,039 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:58,039 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706730771] [2023-11-21 22:04:58,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706730771] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:58,039 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:58,039 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:58,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456536078] [2023-11-21 22:04:58,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:58,040 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:58,040 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:58,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:04:58,040 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:04:58,041 INFO L87 Difference]: Start difference. First operand 981 states and 1451 transitions. cyclomatic complexity: 471 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:58,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:58,090 INFO L93 Difference]: Finished difference Result 981 states and 1429 transitions. [2023-11-21 22:04:58,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 981 states and 1429 transitions. [2023-11-21 22:04:58,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2023-11-21 22:04:58,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 981 states to 981 states and 1429 transitions. [2023-11-21 22:04:58,109 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 981 [2023-11-21 22:04:58,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 981 [2023-11-21 22:04:58,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 981 states and 1429 transitions. [2023-11-21 22:04:58,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:58,112 INFO L218 hiAutomatonCegarLoop]: Abstraction has 981 states and 1429 transitions. [2023-11-21 22:04:58,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 981 states and 1429 transitions. [2023-11-21 22:04:58,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 981 to 981. [2023-11-21 22:04:58,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981 states, 981 states have (on average 1.4566768603465852) internal successors, (1429), 980 states have internal predecessors, (1429), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:58,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981 states to 981 states and 1429 transitions. [2023-11-21 22:04:58,136 INFO L240 hiAutomatonCegarLoop]: Abstraction has 981 states and 1429 transitions. [2023-11-21 22:04:58,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:04:58,137 INFO L428 stractBuchiCegarLoop]: Abstraction has 981 states and 1429 transitions. [2023-11-21 22:04:58,137 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-21 22:04:58,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 981 states and 1429 transitions. [2023-11-21 22:04:58,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2023-11-21 22:04:58,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:58,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:58,145 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:58,146 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:58,146 INFO L748 eck$LassoCheckResult]: Stem: 9387#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9509#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9510#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9641#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 9457#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9458#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9617#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9433#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9434#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9612#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9429#L599 assume !(0 == ~M_E~0); 9430#L599-2 assume !(0 == ~T1_E~0); 9097#L604-1 assume !(0 == ~T2_E~0); 9084#L609-1 assume !(0 == ~T3_E~0); 9085#L614-1 assume !(0 == ~T4_E~0); 9252#L619-1 assume !(0 == ~T5_E~0); 9365#L624-1 assume !(0 == ~E_M~0); 9461#L629-1 assume !(0 == ~E_1~0); 9174#L634-1 assume !(0 == ~E_2~0); 9175#L639-1 assume !(0 == ~E_3~0); 9566#L644-1 assume !(0 == ~E_4~0); 9583#L649-1 assume !(0 == ~E_5~0); 9138#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9139#L292 assume !(1 == ~m_pc~0); 9265#L292-2 is_master_triggered_~__retres1~0#1 := 0; 9402#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9363#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9364#L743 assume !(0 != activate_threads_~tmp~1#1); 9207#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9208#L311 assume 1 == ~t1_pc~0; 9339#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9340#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9132#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9111#L751 assume !(0 != activate_threads_~tmp___0~0#1); 9112#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9569#L330 assume !(1 == ~t2_pc~0); 9368#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9268#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9269#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9514#L759 assume !(0 != activate_threads_~tmp___1~0#1); 9639#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9254#L349 assume !(1 == ~t3_pc~0); 9255#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9303#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9091#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9092#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9633#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9634#L368 assume 1 == ~t4_pc~0; 9640#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9332#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9238#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9239#L775 assume !(0 != activate_threads_~tmp___3~0#1); 9098#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9099#L387 assume !(1 == ~t5_pc~0); 9479#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9480#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9370#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9227#L783 assume !(0 != activate_threads_~tmp___4~0#1); 9228#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9320#L667 assume !(1 == ~M_E~0); 9394#L667-2 assume !(1 == ~T1_E~0); 9575#L672-1 assume !(1 == ~T2_E~0); 9352#L677-1 assume !(1 == ~T3_E~0); 9353#L682-1 assume !(1 == ~T4_E~0); 9549#L687-1 assume !(1 == ~T5_E~0); 9607#L692-1 assume !(1 == ~E_M~0); 9538#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9539#L702-1 assume !(1 == ~E_2~0); 9582#L707-1 assume !(1 == ~E_3~0); 9448#L712-1 assume !(1 == ~E_4~0); 9449#L717-1 assume !(1 == ~E_5~0); 9556#L722-1 assume { :end_inline_reset_delta_events } true; 9106#L928-2 [2023-11-21 22:04:58,146 INFO L750 eck$LassoCheckResult]: Loop: 9106#L928-2 assume !false; 9107#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9718#L574-1 assume !false; 9717#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9713#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9615#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9531#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9142#L499 assume !(0 != eval_~tmp~0#1); 9144#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9253#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9707#L599-3 assume !(0 == ~M_E~0); 9706#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9705#L604-3 assume !(0 == ~T2_E~0); 9704#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9703#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9702#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9701#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9700#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9602#L634-3 assume !(0 == ~E_2~0); 9557#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9558#L644-3 assume !(0 == ~E_4~0); 9636#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9653#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9696#L292-21 assume !(1 == ~m_pc~0); 9694#L292-23 is_master_triggered_~__retres1~0#1 := 0; 9693#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9692#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9626#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9406#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9407#L311-21 assume 1 == ~t1_pc~0; 9689#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9688#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9687#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9686#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9685#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9683#L330-21 assume !(1 == ~t2_pc~0); 9618#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9494#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9400#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9401#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9199#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9200#L349-21 assume 1 == ~t3_pc~0; 9445#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9593#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9598#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9560#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9561#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9638#L368-21 assume !(1 == ~t4_pc~0); 9670#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 9669#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9631#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9587#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9089#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9090#L387-21 assume !(1 == ~t5_pc~0); 9152#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 9478#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9488#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9489#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 9191#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9192#L667-3 assume !(1 == ~M_E~0); 9405#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9841#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9839#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9837#L682-3 assume !(1 == ~T4_E~0); 9835#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9834#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9833#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9832#L702-3 assume !(1 == ~E_2~0); 9831#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9829#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9827#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9825#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9816#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9812#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9810#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9809#L947 assume !(0 == start_simulation_~tmp~3#1); 9807#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9782#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9775#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9771#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 9749#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9742#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9621#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9519#L960 assume !(0 != start_simulation_~tmp___0~1#1); 9106#L928-2 [2023-11-21 22:04:58,147 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:58,147 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2023-11-21 22:04:58,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:58,147 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100314441] [2023-11-21 22:04:58,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:58,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:58,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:58,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:58,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:58,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100314441] [2023-11-21 22:04:58,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100314441] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:58,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:58,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:04:58,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246466157] [2023-11-21 22:04:58,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:58,189 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:58,189 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:58,189 INFO L85 PathProgramCache]: Analyzing trace with hash -982956238, now seen corresponding path program 1 times [2023-11-21 22:04:58,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:58,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770164589] [2023-11-21 22:04:58,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:58,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:58,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:58,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:58,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:58,229 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770164589] [2023-11-21 22:04:58,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770164589] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:58,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:58,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:58,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [573311380] [2023-11-21 22:04:58,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:58,230 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:58,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:58,230 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:04:58,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:04:58,231 INFO L87 Difference]: Start difference. First operand 981 states and 1429 transitions. cyclomatic complexity: 449 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:58,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:58,308 INFO L93 Difference]: Finished difference Result 1779 states and 2571 transitions. [2023-11-21 22:04:58,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1779 states and 2571 transitions. [2023-11-21 22:04:58,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1697 [2023-11-21 22:04:58,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1779 states to 1779 states and 2571 transitions. [2023-11-21 22:04:58,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1779 [2023-11-21 22:04:58,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1779 [2023-11-21 22:04:58,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1779 states and 2571 transitions. [2023-11-21 22:04:58,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:58,346 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1779 states and 2571 transitions. [2023-11-21 22:04:58,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1779 states and 2571 transitions. [2023-11-21 22:04:58,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1779 to 1775. [2023-11-21 22:04:58,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1775 states, 1775 states have (on average 1.4461971830985916) internal successors, (2567), 1774 states have internal predecessors, (2567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:58,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1775 states to 1775 states and 2567 transitions. [2023-11-21 22:04:58,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1775 states and 2567 transitions. [2023-11-21 22:04:58,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:04:58,438 INFO L428 stractBuchiCegarLoop]: Abstraction has 1775 states and 2567 transitions. [2023-11-21 22:04:58,438 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-21 22:04:58,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1775 states and 2567 transitions. [2023-11-21 22:04:58,452 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1693 [2023-11-21 22:04:58,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:58,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:58,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:58,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:58,455 INFO L748 eck$LassoCheckResult]: Stem: 12160#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12289#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12290#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12438#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 12235#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12236#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12417#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12208#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12209#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12411#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12204#L599 assume !(0 == ~M_E~0); 12205#L599-2 assume !(0 == ~T1_E~0); 11862#L604-1 assume !(0 == ~T2_E~0); 11851#L609-1 assume !(0 == ~T3_E~0); 11852#L614-1 assume !(0 == ~T4_E~0); 12019#L619-1 assume !(0 == ~T5_E~0); 12137#L624-1 assume !(0 == ~E_M~0); 12240#L629-1 assume !(0 == ~E_1~0); 11941#L634-1 assume !(0 == ~E_2~0); 11942#L639-1 assume !(0 == ~E_3~0); 12358#L644-1 assume !(0 == ~E_4~0); 12378#L649-1 assume !(0 == ~E_5~0); 11906#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11907#L292 assume !(1 == ~m_pc~0); 12033#L292-2 is_master_triggered_~__retres1~0#1 := 0; 12176#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12133#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12134#L743 assume !(0 != activate_threads_~tmp~1#1); 11975#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11976#L311 assume !(1 == ~t1_pc~0); 12357#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12247#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11900#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11879#L751 assume !(0 != activate_threads_~tmp___0~0#1); 11880#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12359#L330 assume !(1 == ~t2_pc~0); 12140#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12035#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12036#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12295#L759 assume !(0 != activate_threads_~tmp___1~0#1); 12436#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12020#L349 assume !(1 == ~t3_pc~0); 12021#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12069#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11853#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11854#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12431#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12432#L368 assume 1 == ~t4_pc~0; 12437#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12101#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12005#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12006#L775 assume !(0 != activate_threads_~tmp___3~0#1); 11865#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11866#L387 assume !(1 == ~t5_pc~0); 12260#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12261#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12142#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11991#L783 assume !(0 != activate_threads_~tmp___4~0#1); 11992#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12086#L667 assume !(1 == ~M_E~0); 12168#L667-2 assume !(1 == ~T1_E~0); 12365#L672-1 assume !(1 == ~T2_E~0); 12123#L677-1 assume !(1 == ~T3_E~0); 12124#L682-1 assume !(1 == ~T4_E~0); 12339#L687-1 assume !(1 == ~T5_E~0); 12406#L692-1 assume !(1 == ~E_M~0); 12326#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12327#L702-1 assume !(1 == ~E_2~0); 12377#L707-1 assume !(1 == ~E_3~0); 12226#L712-1 assume !(1 == ~E_4~0); 12227#L717-1 assume !(1 == ~E_5~0); 12346#L722-1 assume { :end_inline_reset_delta_events } true; 12347#L928-2 [2023-11-21 22:04:58,455 INFO L750 eck$LassoCheckResult]: Loop: 12347#L928-2 assume !false; 12847#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12845#L574-1 assume !false; 12844#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12840#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12416#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12313#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11910#L499 assume !(0 != eval_~tmp~0#1); 11912#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12834#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12831#L599-3 assume !(0 == ~M_E~0); 12832#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13168#L604-3 assume !(0 == ~T2_E~0); 13167#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13166#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13165#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13164#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13163#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13162#L634-3 assume !(0 == ~E_2~0); 13161#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13160#L644-3 assume !(0 == ~E_4~0); 13159#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13158#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13157#L292-21 assume !(1 == ~m_pc~0); 13155#L292-23 is_master_triggered_~__retres1~0#1 := 0; 13154#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13153#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13152#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12732#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12403#L311-21 assume !(1 == ~t1_pc~0); 12404#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 13222#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13221#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13220#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13219#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13217#L330-21 assume !(1 == ~t2_pc~0); 13216#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 13215#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13214#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13213#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13212#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13211#L349-21 assume 1 == ~t3_pc~0; 13209#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13208#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13207#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13206#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13205#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13204#L368-21 assume !(1 == ~t4_pc~0); 13202#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 13201#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13200#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13199#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13198#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13197#L387-21 assume 1 == ~t5_pc~0; 13195#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13194#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13193#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13192#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 13191#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13190#L667-3 assume !(1 == ~M_E~0); 13074#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13189#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13188#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13187#L682-3 assume !(1 == ~T4_E~0); 13186#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13185#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13184#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13183#L702-3 assume !(1 == ~E_2~0); 13182#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13181#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13180#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13179#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13175#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13172#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13171#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 12190#L947 assume !(0 == start_simulation_~tmp~3#1); 12191#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12462#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13010#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12876#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 12875#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12873#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12863#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 12856#L960 assume !(0 != start_simulation_~tmp___0~1#1); 12347#L928-2 [2023-11-21 22:04:58,455 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:58,456 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2023-11-21 22:04:58,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:58,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79461825] [2023-11-21 22:04:58,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:58,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:58,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:58,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:58,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:58,527 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [79461825] [2023-11-21 22:04:58,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [79461825] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:58,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:58,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:04:58,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680891469] [2023-11-21 22:04:58,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:58,529 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:58,529 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:58,529 INFO L85 PathProgramCache]: Analyzing trace with hash -319613902, now seen corresponding path program 1 times [2023-11-21 22:04:58,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:58,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [883335205] [2023-11-21 22:04:58,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:58,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:58,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:58,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:58,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:58,577 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [883335205] [2023-11-21 22:04:58,578 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [883335205] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:58,578 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:58,578 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:58,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [516541260] [2023-11-21 22:04:58,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:58,579 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:58,579 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:58,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:04:58,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:04:58,580 INFO L87 Difference]: Start difference. First operand 1775 states and 2567 transitions. cyclomatic complexity: 794 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:58,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:58,853 INFO L93 Difference]: Finished difference Result 3854 states and 5508 transitions. [2023-11-21 22:04:58,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3854 states and 5508 transitions. [2023-11-21 22:04:58,888 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3722 [2023-11-21 22:04:58,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3854 states to 3854 states and 5508 transitions. [2023-11-21 22:04:58,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3854 [2023-11-21 22:04:58,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3854 [2023-11-21 22:04:58,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3854 states and 5508 transitions. [2023-11-21 22:04:58,931 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:58,931 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3854 states and 5508 transitions. [2023-11-21 22:04:58,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3854 states and 5508 transitions. [2023-11-21 22:04:58,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3854 to 1862. [2023-11-21 22:04:58,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1862 states, 1862 states have (on average 1.4253490870032224) internal successors, (2654), 1861 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:58,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1862 states to 1862 states and 2654 transitions. [2023-11-21 22:04:58,992 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1862 states and 2654 transitions. [2023-11-21 22:04:58,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-21 22:04:58,992 INFO L428 stractBuchiCegarLoop]: Abstraction has 1862 states and 2654 transitions. [2023-11-21 22:04:58,993 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-21 22:04:58,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1862 states and 2654 transitions. [2023-11-21 22:04:59,003 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1777 [2023-11-21 22:04:59,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:59,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:59,005 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:59,005 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:59,005 INFO L748 eck$LassoCheckResult]: Stem: 17815#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 17816#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 17956#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17957#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18138#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 17897#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17898#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18106#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17867#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17868#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18099#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17861#L599 assume !(0 == ~M_E~0); 17862#L599-2 assume !(0 == ~T1_E~0); 17506#L604-1 assume !(0 == ~T2_E~0); 17493#L609-1 assume !(0 == ~T3_E~0); 17494#L614-1 assume !(0 == ~T4_E~0); 17664#L619-1 assume !(0 == ~T5_E~0); 17791#L624-1 assume !(0 == ~E_M~0); 17902#L629-1 assume !(0 == ~E_1~0); 17581#L634-1 assume !(0 == ~E_2~0); 17582#L639-1 assume !(0 == ~E_3~0); 18038#L644-1 assume !(0 == ~E_4~0); 18059#L649-1 assume !(0 == ~E_5~0); 17547#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17548#L292 assume !(1 == ~m_pc~0); 17678#L292-2 is_master_triggered_~__retres1~0#1 := 0; 17833#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17789#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17790#L743 assume !(0 != activate_threads_~tmp~1#1); 17615#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17616#L311 assume !(1 == ~t1_pc~0); 18036#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17909#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17541#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17520#L751 assume !(0 != activate_threads_~tmp___0~0#1); 17521#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18039#L330 assume !(1 == ~t2_pc~0); 17794#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17682#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17683#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17962#L759 assume !(0 != activate_threads_~tmp___1~0#1); 18134#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17665#L349 assume !(1 == ~t3_pc~0); 17666#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17997#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17998#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18202#L767 assume !(0 != activate_threads_~tmp___2~0#1); 18129#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18130#L368 assume 1 == ~t4_pc~0; 18137#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17755#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17651#L775 assume !(0 != activate_threads_~tmp___3~0#1); 17507#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17508#L387 assume !(1 == ~t5_pc~0); 17923#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17924#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17796#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17637#L783 assume !(0 != activate_threads_~tmp___4~0#1); 17638#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17738#L667 assume !(1 == ~M_E~0); 17824#L667-2 assume !(1 == ~T1_E~0); 18048#L672-1 assume !(1 == ~T2_E~0); 17777#L677-1 assume !(1 == ~T3_E~0); 17778#L682-1 assume !(1 == ~T4_E~0); 18014#L687-1 assume !(1 == ~T5_E~0); 18093#L692-1 assume !(1 == ~E_M~0); 17995#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17996#L702-1 assume !(1 == ~E_2~0); 18057#L707-1 assume !(1 == ~E_3~0); 17888#L712-1 assume !(1 == ~E_4~0); 17889#L717-1 assume !(1 == ~E_5~0); 18023#L722-1 assume { :end_inline_reset_delta_events } true; 18024#L928-2 [2023-11-21 22:04:59,005 INFO L750 eck$LassoCheckResult]: Loop: 18024#L928-2 assume !false; 17893#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17766#L574-1 assume !false; 17767#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18128#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 17723#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 17983#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17551#L499 assume !(0 != eval_~tmp~0#1); 17552#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18404#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18402#L599-3 assume !(0 == ~M_E~0); 18396#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18397#L604-3 assume !(0 == ~T2_E~0); 18374#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18375#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18354#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18355#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18332#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18333#L634-3 assume !(0 == ~E_2~0); 18314#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18315#L644-3 assume !(0 == ~E_4~0); 18297#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18298#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18276#L292-21 assume !(1 == ~m_pc~0); 18277#L292-23 is_master_triggered_~__retres1~0#1 := 0; 18719#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18718#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18717#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18716#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18090#L311-21 assume !(1 == ~t1_pc~0); 18091#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 18869#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18868#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18867#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18866#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18864#L330-21 assume !(1 == ~t2_pc~0); 18863#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 18862#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18861#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18860#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18859#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18858#L349-21 assume 1 == ~t3_pc~0; 18856#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18854#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18852#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18850#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18796#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18595#L368-21 assume !(1 == ~t4_pc~0); 18592#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 18590#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18587#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18585#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18583#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18581#L387-21 assume 1 == ~t5_pc~0; 18578#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18549#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18541#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18533#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 18525#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18523#L667-3 assume !(1 == ~M_E~0); 18520#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18519#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18518#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18516#L682-3 assume !(1 == ~T4_E~0); 18513#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18511#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18509#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18507#L702-3 assume !(1 == ~E_2~0); 18505#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18503#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18501#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18499#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18494#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18490#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18488#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 18486#L947 assume !(0 == start_simulation_~tmp~3#1); 18484#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18480#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18476#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18473#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 18468#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18444#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18434#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 18427#L960 assume !(0 != start_simulation_~tmp___0~1#1); 18024#L928-2 [2023-11-21 22:04:59,006 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:59,006 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2023-11-21 22:04:59,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:59,006 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941859111] [2023-11-21 22:04:59,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:59,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:59,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:59,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:59,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:59,050 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941859111] [2023-11-21 22:04:59,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [941859111] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:59,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:59,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:04:59,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498809145] [2023-11-21 22:04:59,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:59,051 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:59,051 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:59,051 INFO L85 PathProgramCache]: Analyzing trace with hash -319613902, now seen corresponding path program 2 times [2023-11-21 22:04:59,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:59,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [216967070] [2023-11-21 22:04:59,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:59,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:59,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:59,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:59,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:59,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [216967070] [2023-11-21 22:04:59,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [216967070] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:59,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:59,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:59,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [843273360] [2023-11-21 22:04:59,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:59,091 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:59,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:59,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:04:59,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:04:59,091 INFO L87 Difference]: Start difference. First operand 1862 states and 2654 transitions. cyclomatic complexity: 794 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:59,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:59,202 INFO L93 Difference]: Finished difference Result 3428 states and 4858 transitions. [2023-11-21 22:04:59,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3428 states and 4858 transitions. [2023-11-21 22:04:59,229 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3332 [2023-11-21 22:04:59,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3428 states to 3428 states and 4858 transitions. [2023-11-21 22:04:59,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3428 [2023-11-21 22:04:59,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3428 [2023-11-21 22:04:59,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3428 states and 4858 transitions. [2023-11-21 22:04:59,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:59,268 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3428 states and 4858 transitions. [2023-11-21 22:04:59,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3428 states and 4858 transitions. [2023-11-21 22:04:59,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3428 to 3420. [2023-11-21 22:04:59,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3420 states, 3420 states have (on average 1.4181286549707601) internal successors, (4850), 3419 states have internal predecessors, (4850), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:59,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3420 states to 3420 states and 4850 transitions. [2023-11-21 22:04:59,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3420 states and 4850 transitions. [2023-11-21 22:04:59,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:04:59,350 INFO L428 stractBuchiCegarLoop]: Abstraction has 3420 states and 4850 transitions. [2023-11-21 22:04:59,350 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-21 22:04:59,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3420 states and 4850 transitions. [2023-11-21 22:04:59,368 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3324 [2023-11-21 22:04:59,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:59,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:59,370 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:59,370 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:59,371 INFO L748 eck$LassoCheckResult]: Stem: 23096#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 23097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 23228#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23229#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23360#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 23171#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23172#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23342#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23145#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23146#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23336#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23141#L599 assume !(0 == ~M_E~0); 23142#L599-2 assume !(0 == ~T1_E~0); 22801#L604-1 assume !(0 == ~T2_E~0); 22790#L609-1 assume !(0 == ~T3_E~0); 22791#L614-1 assume !(0 == ~T4_E~0); 22957#L619-1 assume !(0 == ~T5_E~0); 23073#L624-1 assume !(0 == ~E_M~0); 23176#L629-1 assume !(0 == ~E_1~0); 22878#L634-1 assume !(0 == ~E_2~0); 22879#L639-1 assume !(0 == ~E_3~0); 23291#L644-1 assume !(0 == ~E_4~0); 23308#L649-1 assume !(0 == ~E_5~0); 22844#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22845#L292 assume !(1 == ~m_pc~0); 22971#L292-2 is_master_triggered_~__retres1~0#1 := 0; 23112#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23069#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23070#L743 assume !(0 != activate_threads_~tmp~1#1); 22911#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22912#L311 assume !(1 == ~t1_pc~0); 23290#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23185#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22838#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22817#L751 assume !(0 != activate_threads_~tmp___0~0#1); 22818#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23293#L330 assume !(1 == ~t2_pc~0); 23076#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22973#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22974#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23233#L759 assume !(0 != activate_threads_~tmp___1~0#1); 23359#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22958#L349 assume !(1 == ~t3_pc~0); 22959#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23389#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23411#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23401#L767 assume !(0 != activate_threads_~tmp___2~0#1); 23354#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23355#L368 assume !(1 == ~t4_pc~0); 23038#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23039#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22942#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22943#L775 assume !(0 != activate_threads_~tmp___3~0#1); 22804#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22805#L387 assume !(1 == ~t5_pc~0); 23198#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 23199#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23079#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22928#L783 assume !(0 != activate_threads_~tmp___4~0#1); 22929#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23027#L667 assume !(1 == ~M_E~0); 23104#L667-2 assume !(1 == ~T1_E~0); 23299#L672-1 assume !(1 == ~T2_E~0); 23060#L677-1 assume !(1 == ~T3_E~0); 23061#L682-1 assume !(1 == ~T4_E~0); 23271#L687-1 assume !(1 == ~T5_E~0); 23330#L692-1 assume !(1 == ~E_M~0); 23257#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 23258#L702-1 assume !(1 == ~E_2~0); 23307#L707-1 assume !(1 == ~E_3~0); 23162#L712-1 assume !(1 == ~E_4~0); 23163#L717-1 assume !(1 == ~E_5~0); 23278#L722-1 assume { :end_inline_reset_delta_events } true; 23279#L928-2 [2023-11-21 22:04:59,371 INFO L750 eck$LassoCheckResult]: Loop: 23279#L928-2 assume !false; 24917#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24915#L574-1 assume !false; 24912#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 24901#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 24897#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 24895#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 24893#L499 assume !(0 != eval_~tmp~0#1); 22961#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22962#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23219#L599-3 assume !(0 == ~M_E~0); 23220#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26015#L604-3 assume !(0 == ~T2_E~0); 26014#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26013#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26012#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26011#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26010#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26009#L634-3 assume !(0 == ~E_2~0); 26008#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26006#L644-3 assume !(0 == ~E_4~0); 26003#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26001#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25999#L292-21 assume !(1 == ~m_pc~0); 25996#L292-23 is_master_triggered_~__retres1~0#1 := 0; 25994#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25992#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25990#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25988#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25986#L311-21 assume !(1 == ~t1_pc~0); 25984#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 25982#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22919#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22920#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22969#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22970#L330-21 assume !(1 == ~t2_pc~0); 23244#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 23213#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23110#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23111#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22903#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22904#L349-21 assume 1 == ~t3_pc~0; 23159#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23405#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23367#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23368#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23285#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22989#L368-21 assume !(1 == ~t4_pc~0); 22990#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 23312#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23325#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23314#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22794#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22795#L387-21 assume !(1 == ~t5_pc~0); 22857#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 23197#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23207#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23208#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 22896#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22897#L667-3 assume !(1 == ~M_E~0); 23115#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24997#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24995#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24992#L682-3 assume !(1 == ~T4_E~0); 24990#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24988#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24986#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24984#L702-3 assume !(1 == ~E_2~0); 24982#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24979#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24977#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24975#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 24964#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 24960#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 24958#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 24956#L947 assume !(0 == start_simulation_~tmp~3#1); 24952#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 24939#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 24934#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 24933#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 24932#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24929#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24925#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 24924#L960 assume !(0 != start_simulation_~tmp___0~1#1); 23279#L928-2 [2023-11-21 22:04:59,371 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:59,371 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2023-11-21 22:04:59,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:59,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155088665] [2023-11-21 22:04:59,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:59,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:59,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:59,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:59,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:59,431 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1155088665] [2023-11-21 22:04:59,431 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1155088665] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:59,432 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:59,432 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:59,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749264105] [2023-11-21 22:04:59,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:59,432 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:59,433 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:59,433 INFO L85 PathProgramCache]: Analyzing trace with hash -2091084877, now seen corresponding path program 1 times [2023-11-21 22:04:59,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:59,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134099388] [2023-11-21 22:04:59,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:59,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:59,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:59,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:59,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:59,472 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134099388] [2023-11-21 22:04:59,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134099388] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:59,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:59,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:59,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2009502925] [2023-11-21 22:04:59,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:59,473 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:59,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:59,473 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 22:04:59,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 22:04:59,473 INFO L87 Difference]: Start difference. First operand 3420 states and 4850 transitions. cyclomatic complexity: 1434 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:59,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:04:59,612 INFO L93 Difference]: Finished difference Result 5429 states and 7639 transitions. [2023-11-21 22:04:59,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5429 states and 7639 transitions. [2023-11-21 22:04:59,650 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5244 [2023-11-21 22:04:59,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5429 states to 5429 states and 7639 transitions. [2023-11-21 22:04:59,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5429 [2023-11-21 22:04:59,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5429 [2023-11-21 22:04:59,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5429 states and 7639 transitions. [2023-11-21 22:04:59,704 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:04:59,704 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5429 states and 7639 transitions. [2023-11-21 22:04:59,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5429 states and 7639 transitions. [2023-11-21 22:04:59,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5429 to 3932. [2023-11-21 22:04:59,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3932 states, 3932 states have (on average 1.4109867751780265) internal successors, (5548), 3931 states have internal predecessors, (5548), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:04:59,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3932 states to 3932 states and 5548 transitions. [2023-11-21 22:04:59,859 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3932 states and 5548 transitions. [2023-11-21 22:04:59,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 22:04:59,861 INFO L428 stractBuchiCegarLoop]: Abstraction has 3932 states and 5548 transitions. [2023-11-21 22:04:59,861 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-21 22:04:59,861 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3932 states and 5548 transitions. [2023-11-21 22:04:59,881 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3780 [2023-11-21 22:04:59,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:04:59,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:04:59,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:59,883 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:04:59,883 INFO L748 eck$LassoCheckResult]: Stem: 31960#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 31961#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 32097#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32098#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32260#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 32037#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32038#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32232#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32010#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32011#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32228#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32006#L599 assume !(0 == ~M_E~0); 32007#L599-2 assume !(0 == ~T1_E~0); 31660#L604-1 assume !(0 == ~T2_E~0); 31649#L609-1 assume !(0 == ~T3_E~0); 31650#L614-1 assume !(0 == ~T4_E~0); 31813#L619-1 assume !(0 == ~T5_E~0); 31935#L624-1 assume !(0 == ~E_M~0); 32042#L629-1 assume 0 == ~E_1~0;~E_1~0 := 1; 32290#L634-1 assume !(0 == ~E_2~0); 32165#L639-1 assume !(0 == ~E_3~0); 32166#L644-1 assume !(0 == ~E_4~0); 32185#L649-1 assume !(0 == ~E_5~0); 32186#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31826#L292 assume !(1 == ~m_pc~0); 31827#L292-2 is_master_triggered_~__retres1~0#1 := 0; 32091#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32092#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32275#L743 assume !(0 != activate_threads_~tmp~1#1); 32276#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32163#L311 assume !(1 == ~t1_pc~0); 32164#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32050#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32051#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31676#L751 assume !(0 != activate_threads_~tmp___0~0#1); 31677#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32167#L330 assume !(1 == ~t2_pc~0); 31938#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31829#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31830#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32254#L759 assume !(0 != activate_threads_~tmp___1~0#1); 32255#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31814#L349 assume !(1 == ~t3_pc~0); 31815#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32360#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32358#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32297#L767 assume !(0 != activate_threads_~tmp___2~0#1); 32249#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32250#L368 assume !(1 == ~t4_pc~0); 31900#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31901#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32208#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32323#L775 assume !(0 != activate_threads_~tmp___3~0#1); 32322#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32321#L387 assume !(1 == ~t5_pc~0); 32319#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32302#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31940#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31941#L783 assume !(0 != activate_threads_~tmp___4~0#1); 32317#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32316#L667 assume !(1 == ~M_E~0); 32315#L667-2 assume !(1 == ~T1_E~0); 32314#L672-1 assume !(1 == ~T2_E~0); 32313#L677-1 assume !(1 == ~T3_E~0); 32312#L682-1 assume !(1 == ~T4_E~0); 32311#L687-1 assume !(1 == ~T5_E~0); 32310#L692-1 assume !(1 == ~E_M~0); 32309#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 32132#L702-1 assume !(1 == ~E_2~0); 32184#L707-1 assume !(1 == ~E_3~0); 32028#L712-1 assume !(1 == ~E_4~0); 32029#L717-1 assume !(1 == ~E_5~0); 32152#L722-1 assume { :end_inline_reset_delta_events } true; 32153#L928-2 [2023-11-21 22:04:59,883 INFO L750 eck$LassoCheckResult]: Loop: 32153#L928-2 assume !false; 32984#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32981#L574-1 assume !false; 32979#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 32973#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 32969#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 32967#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 32964#L499 assume !(0 != eval_~tmp~0#1); 32962#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32960#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32959#L599-3 assume !(0 == ~M_E~0); 32957#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32955#L604-3 assume !(0 == ~T2_E~0); 32953#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32951#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32928#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32927#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32563#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32560#L634-3 assume !(0 == ~E_2~0); 32558#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32556#L644-3 assume !(0 == ~E_4~0); 32554#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32552#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32550#L292-21 assume !(1 == ~m_pc~0); 32547#L292-23 is_master_triggered_~__retres1~0#1 := 0; 32544#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32542#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32540#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32538#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32536#L311-21 assume !(1 == ~t1_pc~0); 32534#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 32532#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32530#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32528#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32526#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32523#L330-21 assume !(1 == ~t2_pc~0); 32520#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 32518#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32516#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32514#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32512#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32510#L349-21 assume 1 == ~t3_pc~0; 32507#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32503#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32499#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32495#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32492#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32490#L368-21 assume !(1 == ~t4_pc~0); 32488#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 32486#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32484#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32482#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32480#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32478#L387-21 assume 1 == ~t5_pc~0; 32475#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32472#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32470#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32468#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 32466#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32464#L667-3 assume !(1 == ~M_E~0); 32461#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32460#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32459#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32458#L682-3 assume !(1 == ~T4_E~0); 32457#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32456#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32454#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32452#L702-3 assume !(1 == ~E_2~0); 32450#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32448#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32445#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32443#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 32434#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 32418#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 32413#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 32377#L947 assume !(0 == start_simulation_~tmp~3#1); 32379#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 33023#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 33020#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 33016#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 33014#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33012#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33002#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 32995#L960 assume !(0 != start_simulation_~tmp___0~1#1); 32153#L928-2 [2023-11-21 22:04:59,884 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:59,884 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2023-11-21 22:04:59,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:59,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382913385] [2023-11-21 22:04:59,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:59,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:59,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:59,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:59,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:59,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1382913385] [2023-11-21 22:04:59,946 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1382913385] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:59,946 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:59,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:59,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333167214] [2023-11-21 22:04:59,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:59,947 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:04:59,948 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:04:59,948 INFO L85 PathProgramCache]: Analyzing trace with hash -319613902, now seen corresponding path program 3 times [2023-11-21 22:04:59,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:04:59,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294313511] [2023-11-21 22:04:59,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:04:59,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:04:59,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:04:59,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:04:59,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:04:59,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294313511] [2023-11-21 22:04:59,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294313511] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:04:59,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:04:59,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:04:59,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783182426] [2023-11-21 22:04:59,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:04:59,996 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:04:59,996 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:04:59,997 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 22:04:59,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 22:04:59,997 INFO L87 Difference]: Start difference. First operand 3932 states and 5548 transitions. cyclomatic complexity: 1620 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:00,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:00,099 INFO L93 Difference]: Finished difference Result 4766 states and 6689 transitions. [2023-11-21 22:05:00,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4766 states and 6689 transitions. [2023-11-21 22:05:00,127 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4642 [2023-11-21 22:05:00,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4766 states to 4766 states and 6689 transitions. [2023-11-21 22:05:00,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4766 [2023-11-21 22:05:00,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4766 [2023-11-21 22:05:00,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4766 states and 6689 transitions. [2023-11-21 22:05:00,168 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:05:00,169 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4766 states and 6689 transitions. [2023-11-21 22:05:00,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4766 states and 6689 transitions. [2023-11-21 22:05:00,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4766 to 3420. [2023-11-21 22:05:00,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3420 states, 3420 states have (on average 1.4035087719298245) internal successors, (4800), 3419 states have internal predecessors, (4800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:00,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3420 states to 3420 states and 4800 transitions. [2023-11-21 22:05:00,254 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3420 states and 4800 transitions. [2023-11-21 22:05:00,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 22:05:00,255 INFO L428 stractBuchiCegarLoop]: Abstraction has 3420 states and 4800 transitions. [2023-11-21 22:05:00,255 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-21 22:05:00,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3420 states and 4800 transitions. [2023-11-21 22:05:00,271 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3324 [2023-11-21 22:05:00,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:00,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:00,272 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:00,273 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:00,273 INFO L748 eck$LassoCheckResult]: Stem: 40657#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 40658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 40792#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40793#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40942#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 40733#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40734#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40914#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40706#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40707#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40908#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40702#L599 assume !(0 == ~M_E~0); 40703#L599-2 assume !(0 == ~T1_E~0); 40368#L604-1 assume !(0 == ~T2_E~0); 40357#L609-1 assume !(0 == ~T3_E~0); 40358#L614-1 assume !(0 == ~T4_E~0); 40520#L619-1 assume !(0 == ~T5_E~0); 40635#L624-1 assume !(0 == ~E_M~0); 40737#L629-1 assume !(0 == ~E_1~0); 40445#L634-1 assume !(0 == ~E_2~0); 40446#L639-1 assume !(0 == ~E_3~0); 40860#L644-1 assume !(0 == ~E_4~0); 40877#L649-1 assume !(0 == ~E_5~0); 40411#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40412#L292 assume !(1 == ~m_pc~0); 40533#L292-2 is_master_triggered_~__retres1~0#1 := 0; 40673#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40631#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40632#L743 assume !(0 != activate_threads_~tmp~1#1); 40477#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40478#L311 assume !(1 == ~t1_pc~0); 40859#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40745#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40405#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40384#L751 assume !(0 != activate_threads_~tmp___0~0#1); 40385#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40862#L330 assume !(1 == ~t2_pc~0); 40638#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40535#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40536#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40797#L759 assume !(0 != activate_threads_~tmp___1~0#1); 40940#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40521#L349 assume !(1 == ~t3_pc~0); 40522#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40967#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40986#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40978#L767 assume !(0 != activate_threads_~tmp___2~0#1); 40934#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40935#L368 assume !(1 == ~t4_pc~0); 40600#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40601#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40507#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40508#L775 assume !(0 != activate_threads_~tmp___3~0#1); 40371#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40372#L387 assume !(1 == ~t5_pc~0); 40761#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40762#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40494#L783 assume !(0 != activate_threads_~tmp___4~0#1); 40495#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40589#L667 assume !(1 == ~M_E~0); 40665#L667-2 assume !(1 == ~T1_E~0); 40868#L672-1 assume !(1 == ~T2_E~0); 40621#L677-1 assume !(1 == ~T3_E~0); 40622#L682-1 assume !(1 == ~T4_E~0); 40840#L687-1 assume !(1 == ~T5_E~0); 40904#L692-1 assume !(1 == ~E_M~0); 40826#L697-1 assume !(1 == ~E_1~0); 40827#L702-1 assume !(1 == ~E_2~0); 40876#L707-1 assume !(1 == ~E_3~0); 40724#L712-1 assume !(1 == ~E_4~0); 40725#L717-1 assume !(1 == ~E_5~0); 40847#L722-1 assume { :end_inline_reset_delta_events } true; 40848#L928-2 [2023-11-21 22:05:00,274 INFO L750 eck$LassoCheckResult]: Loop: 40848#L928-2 assume !false; 41646#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41644#L574-1 assume !false; 41643#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 41639#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 41636#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 41635#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 41633#L499 assume !(0 != eval_~tmp~0#1); 41632#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41631#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41630#L599-3 assume !(0 == ~M_E~0); 41629#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41628#L604-3 assume !(0 == ~T2_E~0); 41627#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41626#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41625#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41624#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41623#L629-3 assume !(0 == ~E_1~0); 41622#L634-3 assume !(0 == ~E_2~0); 41621#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41620#L644-3 assume !(0 == ~E_4~0); 41619#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41618#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41617#L292-21 assume 1 == ~m_pc~0; 41616#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41614#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41613#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 41612#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41611#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41610#L311-21 assume !(1 == ~t1_pc~0); 41609#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 41608#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41607#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41606#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41605#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41603#L330-21 assume !(1 == ~t2_pc~0); 41602#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 41601#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41600#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41599#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41598#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41597#L349-21 assume 1 == ~t3_pc~0; 41595#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41593#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41591#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41589#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41588#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41587#L368-21 assume !(1 == ~t4_pc~0); 41586#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 41585#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41584#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41583#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41582#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41581#L387-21 assume 1 == ~t5_pc~0; 41579#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41578#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41577#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41576#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 41575#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41217#L667-3 assume !(1 == ~M_E~0); 41214#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41207#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41205#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41203#L682-3 assume !(1 == ~T4_E~0); 41200#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41198#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41195#L697-3 assume !(1 == ~E_1~0); 41193#L702-3 assume !(1 == ~E_2~0); 41191#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41188#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41186#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41184#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 41173#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 41168#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 41089#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 41021#L947 assume !(0 == start_simulation_~tmp~3#1); 41023#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 41752#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 41745#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 41732#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 41680#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41670#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41661#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 41655#L960 assume !(0 != start_simulation_~tmp___0~1#1); 40848#L928-2 [2023-11-21 22:05:00,274 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:00,274 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2023-11-21 22:05:00,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:00,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103287304] [2023-11-21 22:05:00,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:00,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:00,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:00,287 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:00,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:00,333 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:00,333 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:00,334 INFO L85 PathProgramCache]: Analyzing trace with hash -263477199, now seen corresponding path program 1 times [2023-11-21 22:05:00,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:00,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667580976] [2023-11-21 22:05:00,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:00,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:00,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:00,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:00,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:00,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667580976] [2023-11-21 22:05:00,432 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667580976] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:00,432 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:00,432 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:05:00,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869427404] [2023-11-21 22:05:00,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:00,433 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:05:00,433 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:00,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:05:00,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:05:00,434 INFO L87 Difference]: Start difference. First operand 3420 states and 4800 transitions. cyclomatic complexity: 1384 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:00,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:00,478 INFO L93 Difference]: Finished difference Result 3932 states and 5517 transitions. [2023-11-21 22:05:00,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3932 states and 5517 transitions. [2023-11-21 22:05:00,501 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3780 [2023-11-21 22:05:00,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3932 states to 3932 states and 5517 transitions. [2023-11-21 22:05:00,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3932 [2023-11-21 22:05:00,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3932 [2023-11-21 22:05:00,526 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3932 states and 5517 transitions. [2023-11-21 22:05:00,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:05:00,532 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3932 states and 5517 transitions. [2023-11-21 22:05:00,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3932 states and 5517 transitions. [2023-11-21 22:05:00,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3932 to 3932. [2023-11-21 22:05:00,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3932 states, 3932 states have (on average 1.4031027466937944) internal successors, (5517), 3931 states have internal predecessors, (5517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:00,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3932 states to 3932 states and 5517 transitions. [2023-11-21 22:05:00,617 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3932 states and 5517 transitions. [2023-11-21 22:05:00,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:05:00,618 INFO L428 stractBuchiCegarLoop]: Abstraction has 3932 states and 5517 transitions. [2023-11-21 22:05:00,618 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-21 22:05:00,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3932 states and 5517 transitions. [2023-11-21 22:05:00,635 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3780 [2023-11-21 22:05:00,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:00,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:00,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:00,637 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:00,638 INFO L748 eck$LassoCheckResult]: Stem: 48019#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 48020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 48153#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48154#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48299#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 48095#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48096#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48281#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48068#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48069#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48275#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48064#L599 assume !(0 == ~M_E~0); 48065#L599-2 assume !(0 == ~T1_E~0); 47726#L604-1 assume !(0 == ~T2_E~0); 47715#L609-1 assume !(0 == ~T3_E~0); 47716#L614-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47878#L619-1 assume !(0 == ~T5_E~0); 47997#L624-1 assume !(0 == ~E_M~0); 48408#L629-1 assume !(0 == ~E_1~0); 47804#L634-1 assume !(0 == ~E_2~0); 47805#L639-1 assume !(0 == ~E_3~0); 48269#L644-1 assume !(0 == ~E_4~0); 48239#L649-1 assume !(0 == ~E_5~0); 47770#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47771#L292 assume !(1 == ~m_pc~0); 47893#L292-2 is_master_triggered_~__retres1~0#1 := 0; 48034#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48148#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48311#L743 assume !(0 != activate_threads_~tmp~1#1); 47836#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47837#L311 assume !(1 == ~t1_pc~0); 48221#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48108#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47763#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 47764#L751 assume !(0 != activate_threads_~tmp___0~0#1); 48384#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48379#L330 assume !(1 == ~t2_pc~0); 48177#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47895#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47896#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48376#L759 assume !(0 != activate_threads_~tmp___1~0#1); 48375#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48374#L349 assume !(1 == ~t3_pc~0); 48372#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48370#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48368#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48363#L767 assume !(0 != activate_threads_~tmp___2~0#1); 48362#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48338#L368 assume !(1 == ~t4_pc~0); 48339#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 48360#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47865#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47866#L775 assume !(0 != activate_threads_~tmp___3~0#1); 47729#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47730#L387 assume !(1 == ~t5_pc~0); 48120#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48121#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48353#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47852#L783 assume !(0 != activate_threads_~tmp___4~0#1); 47853#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47949#L667 assume !(1 == ~M_E~0); 48027#L667-2 assume !(1 == ~T1_E~0); 48231#L672-1 assume !(1 == ~T2_E~0); 47983#L677-1 assume !(1 == ~T3_E~0); 47984#L682-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48202#L687-1 assume !(1 == ~T5_E~0); 48270#L692-1 assume !(1 == ~E_M~0); 48188#L697-1 assume !(1 == ~E_1~0); 48189#L702-1 assume !(1 == ~E_2~0); 48238#L707-1 assume !(1 == ~E_3~0); 48086#L712-1 assume !(1 == ~E_4~0); 48087#L717-1 assume !(1 == ~E_5~0); 48210#L722-1 assume { :end_inline_reset_delta_events } true; 48211#L928-2 [2023-11-21 22:05:00,638 INFO L750 eck$LassoCheckResult]: Loop: 48211#L928-2 assume !false; 50658#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50642#L574-1 assume !false; 50597#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 49758#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 49754#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 49752#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49750#L499 assume !(0 != eval_~tmp~0#1); 47883#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47884#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48143#L599-3 assume !(0 == ~M_E~0); 48144#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48044#L604-3 assume !(0 == ~T2_E~0); 48045#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48127#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47744#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47745#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48140#L629-3 assume !(0 == ~E_1~0); 48199#L634-3 assume !(0 == ~E_2~0); 48212#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48213#L644-3 assume !(0 == ~E_4~0); 48295#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48054#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48055#L292-21 assume !(1 == ~m_pc~0); 47954#L292-23 is_master_triggered_~__retres1~0#1 := 0; 47817#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47818#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 47920#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48037#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48038#L311-21 assume !(1 == ~t1_pc~0); 47966#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 47778#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47779#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 47844#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47891#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47892#L330-21 assume !(1 == ~t2_pc~0); 48171#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 48282#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51529#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51528#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51527#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51526#L349-21 assume !(1 == ~t3_pc~0); 51524#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 51522#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51520#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 51519#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 51517#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51516#L368-21 assume !(1 == ~t4_pc~0); 48242#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 48243#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48262#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48248#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47719#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47720#L387-21 assume !(1 == ~t5_pc~0); 47783#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 48119#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48130#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48131#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 47821#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47822#L667-3 assume !(1 == ~M_E~0); 47809#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47810#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48227#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48346#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48261#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47933#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47934#L697-3 assume !(1 == ~E_1~0); 48008#L702-3 assume !(1 == ~E_2~0); 48009#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48149#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48187#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51205#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 48296#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 47752#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 48116#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 48047#L947 assume !(0 == start_simulation_~tmp~3#1); 48048#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 50716#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 50708#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 50702#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 50694#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50684#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50677#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 50669#L960 assume !(0 != start_simulation_~tmp___0~1#1); 48211#L928-2 [2023-11-21 22:05:00,638 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:00,639 INFO L85 PathProgramCache]: Analyzing trace with hash -113006587, now seen corresponding path program 1 times [2023-11-21 22:05:00,639 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:00,639 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246189639] [2023-11-21 22:05:00,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:00,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:00,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:00,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:00,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:00,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246189639] [2023-11-21 22:05:00,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246189639] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:00,687 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:00,687 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:05:00,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [659632820] [2023-11-21 22:05:00,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:00,688 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:05:00,689 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:00,689 INFO L85 PathProgramCache]: Analyzing trace with hash -1375954700, now seen corresponding path program 1 times [2023-11-21 22:05:00,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:00,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546519594] [2023-11-21 22:05:00,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:00,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:00,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:00,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:00,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:00,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546519594] [2023-11-21 22:05:00,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546519594] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:00,746 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:00,746 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:05:00,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315885790] [2023-11-21 22:05:00,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:00,747 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:05:00,747 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:00,748 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 22:05:00,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 22:05:00,748 INFO L87 Difference]: Start difference. First operand 3932 states and 5517 transitions. cyclomatic complexity: 1589 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:00,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:00,874 INFO L93 Difference]: Finished difference Result 4958 states and 6933 transitions. [2023-11-21 22:05:00,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4958 states and 6933 transitions. [2023-11-21 22:05:00,907 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4846 [2023-11-21 22:05:00,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4958 states to 4958 states and 6933 transitions. [2023-11-21 22:05:00,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4958 [2023-11-21 22:05:00,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4958 [2023-11-21 22:05:00,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4958 states and 6933 transitions. [2023-11-21 22:05:00,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:05:00,949 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4958 states and 6933 transitions. [2023-11-21 22:05:00,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4958 states and 6933 transitions. [2023-11-21 22:05:01,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4958 to 3420. [2023-11-21 22:05:01,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3420 states, 3420 states have (on average 1.4008771929824562) internal successors, (4791), 3419 states have internal predecessors, (4791), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:01,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3420 states to 3420 states and 4791 transitions. [2023-11-21 22:05:01,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3420 states and 4791 transitions. [2023-11-21 22:05:01,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 22:05:01,063 INFO L428 stractBuchiCegarLoop]: Abstraction has 3420 states and 4791 transitions. [2023-11-21 22:05:01,063 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-21 22:05:01,064 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3420 states and 4791 transitions. [2023-11-21 22:05:01,084 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3324 [2023-11-21 22:05:01,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:01,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:01,086 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:01,086 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:01,086 INFO L748 eck$LassoCheckResult]: Stem: 56920#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 56921#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 57052#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 57053#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57196#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 56997#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56998#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57172#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56971#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56972#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57166#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56967#L599 assume !(0 == ~M_E~0); 56968#L599-2 assume !(0 == ~T1_E~0); 56628#L604-1 assume !(0 == ~T2_E~0); 56617#L609-1 assume !(0 == ~T3_E~0); 56618#L614-1 assume !(0 == ~T4_E~0); 56781#L619-1 assume !(0 == ~T5_E~0); 56897#L624-1 assume !(0 == ~E_M~0); 57003#L629-1 assume !(0 == ~E_1~0); 56707#L634-1 assume !(0 == ~E_2~0); 56708#L639-1 assume !(0 == ~E_3~0); 57118#L644-1 assume !(0 == ~E_4~0); 57136#L649-1 assume !(0 == ~E_5~0); 56671#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56672#L292 assume !(1 == ~m_pc~0); 56794#L292-2 is_master_triggered_~__retres1~0#1 := 0; 56936#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56893#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56894#L743 assume !(0 != activate_threads_~tmp~1#1); 56739#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56740#L311 assume !(1 == ~t1_pc~0); 57117#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 57010#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56665#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56644#L751 assume !(0 != activate_threads_~tmp___0~0#1); 56645#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57119#L330 assume !(1 == ~t2_pc~0); 56900#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56796#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56797#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57058#L759 assume !(0 != activate_threads_~tmp___1~0#1); 57193#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56782#L349 assume !(1 == ~t3_pc~0); 56783#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 57087#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56619#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56620#L767 assume !(0 != activate_threads_~tmp___2~0#1); 57187#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57188#L368 assume !(1 == ~t4_pc~0); 56862#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56863#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56768#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56769#L775 assume !(0 != activate_threads_~tmp___3~0#1); 56631#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56632#L387 assume !(1 == ~t5_pc~0); 57022#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 57023#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56902#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 56755#L783 assume !(0 != activate_threads_~tmp___4~0#1); 56756#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56849#L667 assume !(1 == ~M_E~0); 56928#L667-2 assume !(1 == ~T1_E~0); 57125#L672-1 assume !(1 == ~T2_E~0); 56883#L677-1 assume !(1 == ~T3_E~0); 56884#L682-1 assume !(1 == ~T4_E~0); 57100#L687-1 assume !(1 == ~T5_E~0); 57162#L692-1 assume !(1 == ~E_M~0); 57085#L697-1 assume !(1 == ~E_1~0); 57086#L702-1 assume !(1 == ~E_2~0); 57135#L707-1 assume !(1 == ~E_3~0); 56989#L712-1 assume !(1 == ~E_4~0); 56990#L717-1 assume !(1 == ~E_5~0); 57107#L722-1 assume { :end_inline_reset_delta_events } true; 57108#L928-2 [2023-11-21 22:05:01,087 INFO L750 eck$LassoCheckResult]: Loop: 57108#L928-2 assume !false; 57856#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57854#L574-1 assume !false; 57853#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 57849#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 57846#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 57845#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 57843#L499 assume !(0 != eval_~tmp~0#1); 57842#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57841#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57840#L599-3 assume !(0 == ~M_E~0); 57839#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 57838#L604-3 assume !(0 == ~T2_E~0); 57837#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57836#L614-3 assume !(0 == ~T4_E~0); 57835#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57834#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57833#L629-3 assume !(0 == ~E_1~0); 57832#L634-3 assume !(0 == ~E_2~0); 57831#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57830#L644-3 assume !(0 == ~E_4~0); 57829#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57828#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57827#L292-21 assume !(1 == ~m_pc~0); 57825#L292-23 is_master_triggered_~__retres1~0#1 := 0; 57824#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57823#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 57822#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57821#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57820#L311-21 assume !(1 == ~t1_pc~0); 57819#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 57818#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57817#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57816#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57815#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57813#L330-21 assume !(1 == ~t2_pc~0); 57812#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 57811#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57810#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57809#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57808#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57807#L349-21 assume 1 == ~t3_pc~0; 57805#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57803#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57801#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57799#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57798#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57797#L368-21 assume !(1 == ~t4_pc~0); 57796#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 57795#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57794#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57793#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57792#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57791#L387-21 assume 1 == ~t5_pc~0; 57789#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 57788#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57787#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 57786#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 57785#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57429#L667-3 assume !(1 == ~M_E~0); 57425#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57423#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57421#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57419#L682-3 assume !(1 == ~T4_E~0); 57417#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57405#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57400#L697-3 assume !(1 == ~E_1~0); 57394#L702-3 assume !(1 == ~E_2~0); 57387#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57386#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57369#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57363#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 57350#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 57337#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 57332#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 57326#L947 assume !(0 == start_simulation_~tmp~3#1); 57327#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 57906#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 57898#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 57892#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 57888#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57880#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57871#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 57865#L960 assume !(0 != start_simulation_~tmp___0~1#1); 57108#L928-2 [2023-11-21 22:05:01,087 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:01,088 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2023-11-21 22:05:01,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:01,088 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429566218] [2023-11-21 22:05:01,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:01,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:01,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:01,103 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:01,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:01,147 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:01,147 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:01,148 INFO L85 PathProgramCache]: Analyzing trace with hash -1621454544, now seen corresponding path program 1 times [2023-11-21 22:05:01,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:01,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345472121] [2023-11-21 22:05:01,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:01,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:01,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:01,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:01,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:01,217 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345472121] [2023-11-21 22:05:01,217 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345472121] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:01,217 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:01,217 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:05:01,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [109919103] [2023-11-21 22:05:01,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:01,218 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:05:01,218 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:01,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:05:01,219 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:05:01,219 INFO L87 Difference]: Start difference. First operand 3420 states and 4791 transitions. cyclomatic complexity: 1375 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:01,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:01,381 INFO L93 Difference]: Finished difference Result 6136 states and 8483 transitions. [2023-11-21 22:05:01,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6136 states and 8483 transitions. [2023-11-21 22:05:01,414 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6024 [2023-11-21 22:05:01,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6136 states to 6136 states and 8483 transitions. [2023-11-21 22:05:01,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6136 [2023-11-21 22:05:01,445 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6136 [2023-11-21 22:05:01,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6136 states and 8483 transitions. [2023-11-21 22:05:01,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:05:01,451 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6136 states and 8483 transitions. [2023-11-21 22:05:01,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6136 states and 8483 transitions. [2023-11-21 22:05:01,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6136 to 3444. [2023-11-21 22:05:01,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3444 states, 3444 states have (on average 1.3980836236933798) internal successors, (4815), 3443 states have internal predecessors, (4815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:01,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3444 states to 3444 states and 4815 transitions. [2023-11-21 22:05:01,583 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3444 states and 4815 transitions. [2023-11-21 22:05:01,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-21 22:05:01,584 INFO L428 stractBuchiCegarLoop]: Abstraction has 3444 states and 4815 transitions. [2023-11-21 22:05:01,584 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-21 22:05:01,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3444 states and 4815 transitions. [2023-11-21 22:05:01,598 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3348 [2023-11-21 22:05:01,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:01,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:01,600 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:01,600 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:01,601 INFO L748 eck$LassoCheckResult]: Stem: 66491#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 66492#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 66627#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66628#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66784#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 66567#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66568#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66761#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66542#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66543#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66754#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66536#L599 assume !(0 == ~M_E~0); 66537#L599-2 assume !(0 == ~T1_E~0); 66203#L604-1 assume !(0 == ~T2_E~0); 66190#L609-1 assume !(0 == ~T3_E~0); 66191#L614-1 assume !(0 == ~T4_E~0); 66353#L619-1 assume !(0 == ~T5_E~0); 66470#L624-1 assume !(0 == ~E_M~0); 66571#L629-1 assume !(0 == ~E_1~0); 66279#L634-1 assume !(0 == ~E_2~0); 66280#L639-1 assume !(0 == ~E_3~0); 66695#L644-1 assume !(0 == ~E_4~0); 66719#L649-1 assume !(0 == ~E_5~0); 66245#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66246#L292 assume !(1 == ~m_pc~0); 66367#L292-2 is_master_triggered_~__retres1~0#1 := 0; 66510#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66466#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 66467#L743 assume !(0 != activate_threads_~tmp~1#1); 66311#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66312#L311 assume !(1 == ~t1_pc~0); 66694#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66578#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66239#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 66218#L751 assume !(0 != activate_threads_~tmp___0~0#1); 66219#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66696#L330 assume !(1 == ~t2_pc~0); 66473#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 66369#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66370#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66632#L759 assume !(0 != activate_threads_~tmp___1~0#1); 66781#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66354#L349 assume !(1 == ~t3_pc~0); 66355#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 66662#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66663#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66818#L767 assume !(0 != activate_threads_~tmp___2~0#1); 66774#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66775#L368 assume !(1 == ~t4_pc~0); 66435#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 66436#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66340#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66341#L775 assume !(0 != activate_threads_~tmp___3~0#1); 66204#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66205#L387 assume !(1 == ~t5_pc~0); 66595#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 66596#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66475#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 66330#L783 assume !(0 != activate_threads_~tmp___4~0#1); 66331#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66425#L667 assume !(1 == ~M_E~0); 66502#L667-2 assume !(1 == ~T1_E~0); 66707#L672-1 assume !(1 == ~T2_E~0); 66457#L677-1 assume !(1 == ~T3_E~0); 66458#L682-1 assume !(1 == ~T4_E~0); 66675#L687-1 assume !(1 == ~T5_E~0); 66751#L692-1 assume !(1 == ~E_M~0); 66660#L697-1 assume !(1 == ~E_1~0); 66661#L702-1 assume !(1 == ~E_2~0); 66718#L707-1 assume !(1 == ~E_3~0); 66558#L712-1 assume !(1 == ~E_4~0); 66559#L717-1 assume !(1 == ~E_5~0); 66682#L722-1 assume { :end_inline_reset_delta_events } true; 66683#L928-2 [2023-11-21 22:05:01,601 INFO L750 eck$LassoCheckResult]: Loop: 66683#L928-2 assume !false; 67870#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67134#L574-1 assume !false; 67128#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 67122#L452 assume !(0 == ~m_st~0); 67116#L456 assume !(0 == ~t1_st~0); 67110#L460 assume !(0 == ~t2_st~0); 67104#L464 assume !(0 == ~t3_st~0); 67098#L468 assume !(0 == ~t4_st~0); 67091#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 67080#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 67074#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 67071#L499 assume !(0 != eval_~tmp~0#1); 67068#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67066#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67064#L599-3 assume !(0 == ~M_E~0); 67034#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67035#L604-3 assume !(0 == ~T2_E~0); 67022#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67023#L614-3 assume !(0 == ~T4_E~0); 68007#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66613#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66614#L629-3 assume !(0 == ~E_1~0); 66672#L634-3 assume !(0 == ~E_2~0); 66684#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66685#L644-3 assume !(0 == ~E_4~0); 66777#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66529#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66530#L292-21 assume !(1 == ~m_pc~0); 66657#L292-23 is_master_triggered_~__retres1~0#1 := 0; 67999#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67998#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67997#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67996#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67995#L311-21 assume !(1 == ~t1_pc~0); 67994#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 67993#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67992#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 67991#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 67990#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67988#L330-21 assume !(1 == ~t2_pc~0); 67987#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 66610#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66507#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66508#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66303#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66304#L349-21 assume !(1 == ~t3_pc~0); 66555#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 69187#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69186#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66689#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 66690#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66386#L368-21 assume !(1 == ~t4_pc~0); 66387#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 69060#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69059#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 69058#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69057#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69056#L387-21 assume !(1 == ~t5_pc~0); 69055#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 69053#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69052#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 69051#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 69050#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69049#L667-3 assume !(1 == ~M_E~0); 67960#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69048#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69047#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69046#L682-3 assume !(1 == ~T4_E~0); 69045#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69027#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69026#L697-3 assume !(1 == ~E_1~0); 69023#L702-3 assume !(1 == ~E_2~0); 69022#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69020#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69019#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69018#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 68616#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 68140#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 67924#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 67920#L947 assume !(0 == start_simulation_~tmp~3#1); 67916#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 67912#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 67907#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 67902#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 67896#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 67892#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 67886#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 67881#L960 assume !(0 != start_simulation_~tmp___0~1#1); 66683#L928-2 [2023-11-21 22:05:01,603 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:01,604 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2023-11-21 22:05:01,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:01,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308551944] [2023-11-21 22:05:01,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:01,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:01,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:01,618 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:01,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:01,643 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:01,644 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:01,644 INFO L85 PathProgramCache]: Analyzing trace with hash 846096703, now seen corresponding path program 1 times [2023-11-21 22:05:01,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:01,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525165063] [2023-11-21 22:05:01,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:01,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:01,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:01,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:01,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:01,754 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525165063] [2023-11-21 22:05:01,755 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1525165063] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:01,755 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:01,755 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:05:01,755 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844893296] [2023-11-21 22:05:01,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:01,756 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:05:01,756 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:01,756 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:05:01,756 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:05:01,757 INFO L87 Difference]: Start difference. First operand 3444 states and 4815 transitions. cyclomatic complexity: 1375 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:02,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:02,014 INFO L93 Difference]: Finished difference Result 8722 states and 11918 transitions. [2023-11-21 22:05:02,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8722 states and 11918 transitions. [2023-11-21 22:05:02,062 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8520 [2023-11-21 22:05:02,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8722 states to 8722 states and 11918 transitions. [2023-11-21 22:05:02,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8722 [2023-11-21 22:05:02,106 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8722 [2023-11-21 22:05:02,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8722 states and 11918 transitions. [2023-11-21 22:05:02,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:05:02,116 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8722 states and 11918 transitions. [2023-11-21 22:05:02,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8722 states and 11918 transitions. [2023-11-21 22:05:02,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8722 to 3603. [2023-11-21 22:05:02,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3603 states, 3603 states have (on average 1.3805162364696086) internal successors, (4974), 3602 states have internal predecessors, (4974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:02,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3603 states to 3603 states and 4974 transitions. [2023-11-21 22:05:02,326 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3603 states and 4974 transitions. [2023-11-21 22:05:02,326 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-21 22:05:02,328 INFO L428 stractBuchiCegarLoop]: Abstraction has 3603 states and 4974 transitions. [2023-11-21 22:05:02,328 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-21 22:05:02,328 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3603 states and 4974 transitions. [2023-11-21 22:05:02,343 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3504 [2023-11-21 22:05:02,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:02,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:02,345 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:02,346 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:02,346 INFO L748 eck$LassoCheckResult]: Stem: 78674#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 78675#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 78815#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 78816#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78989#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 78754#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78755#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78960#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78725#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78726#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78951#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 78721#L599 assume !(0 == ~M_E~0); 78722#L599-2 assume !(0 == ~T1_E~0); 78379#L604-1 assume !(0 == ~T2_E~0); 78368#L609-1 assume !(0 == ~T3_E~0); 78369#L614-1 assume !(0 == ~T4_E~0); 78529#L619-1 assume !(0 == ~T5_E~0); 78652#L624-1 assume !(0 == ~E_M~0); 78759#L629-1 assume !(0 == ~E_1~0); 78455#L634-1 assume !(0 == ~E_2~0); 78456#L639-1 assume !(0 == ~E_3~0); 78887#L644-1 assume !(0 == ~E_4~0); 78905#L649-1 assume !(0 == ~E_5~0); 78422#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78423#L292 assume !(1 == ~m_pc~0); 78543#L292-2 is_master_triggered_~__retres1~0#1 := 0; 78691#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78810#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 78998#L743 assume !(0 != activate_threads_~tmp~1#1); 78487#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78488#L311 assume !(1 == ~t1_pc~0); 78886#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 78767#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 78395#L751 assume !(0 != activate_threads_~tmp___0~0#1); 78396#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78888#L330 assume !(1 == ~t2_pc~0); 78655#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 78545#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78546#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 78820#L759 assume !(0 != activate_threads_~tmp___1~0#1); 78988#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78530#L349 assume !(1 == ~t3_pc~0); 78531#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 78853#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78370#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 78371#L767 assume !(0 != activate_threads_~tmp___2~0#1); 78982#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78983#L368 assume !(1 == ~t4_pc~0); 78617#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 78618#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78516#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 78517#L775 assume !(0 != activate_threads_~tmp___3~0#1); 78382#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78383#L387 assume !(1 == ~t5_pc~0); 78780#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 78781#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78657#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 78503#L783 assume !(0 != activate_threads_~tmp___4~0#1); 78504#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78600#L667 assume !(1 == ~M_E~0); 78682#L667-2 assume !(1 == ~T1_E~0); 78895#L672-1 assume !(1 == ~T2_E~0); 78638#L677-1 assume !(1 == ~T3_E~0); 78639#L682-1 assume !(1 == ~T4_E~0); 78865#L687-1 assume !(1 == ~T5_E~0); 78947#L692-1 assume !(1 == ~E_M~0); 78851#L697-1 assume !(1 == ~E_1~0); 78852#L702-1 assume !(1 == ~E_2~0); 78904#L707-1 assume !(1 == ~E_3~0); 78745#L712-1 assume !(1 == ~E_4~0); 78746#L717-1 assume !(1 == ~E_5~0); 78872#L722-1 assume { :end_inline_reset_delta_events } true; 78873#L928-2 [2023-11-21 22:05:02,346 INFO L750 eck$LassoCheckResult]: Loop: 78873#L928-2 assume !false; 81339#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81337#L574-1 assume !false; 81336#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 81331#L452 assume !(0 == ~m_st~0); 81332#L456 assume !(0 == ~t1_st~0); 81334#L460 assume !(0 == ~t2_st~0); 81329#L464 assume !(0 == ~t3_st~0); 81330#L468 assume !(0 == ~t4_st~0); 81333#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 81335#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 80731#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 80732#L499 assume !(0 != eval_~tmp~0#1); 81516#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81515#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81514#L599-3 assume !(0 == ~M_E~0); 81513#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 81512#L604-3 assume !(0 == ~T2_E~0); 81511#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 81510#L614-3 assume !(0 == ~T4_E~0); 81509#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81508#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 81507#L629-3 assume !(0 == ~E_1~0); 81506#L634-3 assume !(0 == ~E_2~0); 81505#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81504#L644-3 assume !(0 == ~E_4~0); 81503#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81502#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81501#L292-21 assume 1 == ~m_pc~0; 81499#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 81497#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81495#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81493#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81491#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81481#L311-21 assume !(1 == ~t1_pc~0); 81478#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 81474#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81470#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81467#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81462#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81456#L330-21 assume !(1 == ~t2_pc~0); 81450#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 81449#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81448#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81447#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81437#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81433#L349-21 assume 1 == ~t3_pc~0; 81431#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81430#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81429#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81424#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81422#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81420#L368-21 assume !(1 == ~t4_pc~0); 81418#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 81416#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81414#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81412#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81409#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81407#L387-21 assume !(1 == ~t5_pc~0); 81405#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 81403#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81402#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81399#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 81398#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81396#L667-3 assume !(1 == ~M_E~0); 81393#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81391#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81389#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81387#L682-3 assume !(1 == ~T4_E~0); 78929#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78584#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78585#L697-3 assume !(1 == ~E_1~0); 78662#L702-3 assume !(1 == ~E_2~0); 78663#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78811#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78847#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81372#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 78986#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 78405#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 78775#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 78776#L947 assume !(0 == start_simulation_~tmp~3#1); 81361#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 81357#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 81354#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 81353#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 81352#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81350#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81346#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 81344#L960 assume !(0 != start_simulation_~tmp___0~1#1); 78873#L928-2 [2023-11-21 22:05:02,347 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:02,347 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2023-11-21 22:05:02,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:02,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425726823] [2023-11-21 22:05:02,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:02,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:02,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:02,365 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:02,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:02,392 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:02,393 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:02,393 INFO L85 PathProgramCache]: Analyzing trace with hash -235598597, now seen corresponding path program 1 times [2023-11-21 22:05:02,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:02,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889874150] [2023-11-21 22:05:02,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:02,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:02,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:02,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:02,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:02,503 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889874150] [2023-11-21 22:05:02,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889874150] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:02,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:02,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:05:02,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256851264] [2023-11-21 22:05:02,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:02,504 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:05:02,504 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:02,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:05:02,504 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:05:02,505 INFO L87 Difference]: Start difference. First operand 3603 states and 4974 transitions. cyclomatic complexity: 1375 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:02,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:02,662 INFO L93 Difference]: Finished difference Result 4455 states and 6091 transitions. [2023-11-21 22:05:02,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4455 states and 6091 transitions. [2023-11-21 22:05:02,684 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4352 [2023-11-21 22:05:02,701 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4455 states to 4455 states and 6091 transitions. [2023-11-21 22:05:02,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4455 [2023-11-21 22:05:02,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4455 [2023-11-21 22:05:02,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4455 states and 6091 transitions. [2023-11-21 22:05:02,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:05:02,711 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4455 states and 6091 transitions. [2023-11-21 22:05:02,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4455 states and 6091 transitions. [2023-11-21 22:05:02,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4455 to 3615. [2023-11-21 22:05:02,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3615 states, 3615 states have (on average 1.3656984785615491) internal successors, (4937), 3614 states have internal predecessors, (4937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:02,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3615 states to 3615 states and 4937 transitions. [2023-11-21 22:05:02,799 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3615 states and 4937 transitions. [2023-11-21 22:05:02,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-21 22:05:02,800 INFO L428 stractBuchiCegarLoop]: Abstraction has 3615 states and 4937 transitions. [2023-11-21 22:05:02,800 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-21 22:05:02,800 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3615 states and 4937 transitions. [2023-11-21 22:05:02,812 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3516 [2023-11-21 22:05:02,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:02,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:02,814 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:02,814 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:02,815 INFO L748 eck$LassoCheckResult]: Stem: 86764#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 86765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 86918#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86919#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87162#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 86850#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86851#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87113#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86817#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86818#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87103#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86813#L599 assume !(0 == ~M_E~0); 86814#L599-2 assume !(0 == ~T1_E~0); 86449#L604-1 assume !(0 == ~T2_E~0); 86438#L609-1 assume !(0 == ~T3_E~0); 86439#L614-1 assume !(0 == ~T4_E~0); 86601#L619-1 assume !(0 == ~T5_E~0); 86735#L624-1 assume !(0 == ~E_M~0); 86856#L629-1 assume !(0 == ~E_1~0); 86526#L634-1 assume !(0 == ~E_2~0); 86527#L639-1 assume !(0 == ~E_3~0); 87000#L644-1 assume !(0 == ~E_4~0); 87026#L649-1 assume !(0 == ~E_5~0); 86492#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86493#L292 assume !(1 == ~m_pc~0); 86615#L292-2 is_master_triggered_~__retres1~0#1 := 0; 86783#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87262#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 87182#L743 assume !(0 != activate_threads_~tmp~1#1); 86558#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86559#L311 assume !(1 == ~t1_pc~0); 86999#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86864#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86486#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86465#L751 assume !(0 != activate_threads_~tmp___0~0#1); 86466#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87001#L330 assume !(1 == ~t2_pc~0); 86739#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86617#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86618#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86923#L759 assume !(0 != activate_threads_~tmp___1~0#1); 87157#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86602#L349 assume !(1 == ~t3_pc~0); 86603#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 87209#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87261#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 87238#L767 assume !(0 != activate_threads_~tmp___2~0#1); 87146#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87147#L368 assume !(1 == ~t4_pc~0); 86695#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 86696#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86588#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 86589#L775 assume !(0 != activate_threads_~tmp___3~0#1); 86452#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86453#L387 assume !(1 == ~t5_pc~0); 86880#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86881#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86742#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86575#L783 assume !(0 != activate_threads_~tmp___4~0#1); 86576#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86677#L667 assume !(1 == ~M_E~0); 86775#L667-2 assume !(1 == ~T1_E~0); 87007#L672-1 assume !(1 == ~T2_E~0); 86719#L677-1 assume !(1 == ~T3_E~0); 86720#L682-1 assume !(1 == ~T4_E~0); 86975#L687-1 assume !(1 == ~T5_E~0); 87095#L692-1 assume !(1 == ~E_M~0); 86961#L697-1 assume !(1 == ~E_1~0); 86962#L702-1 assume !(1 == ~E_2~0); 87025#L707-1 assume !(1 == ~E_3~0); 86839#L712-1 assume !(1 == ~E_4~0); 86840#L717-1 assume !(1 == ~E_5~0); 86985#L722-1 assume { :end_inline_reset_delta_events } true; 86986#L928-2 [2023-11-21 22:05:02,815 INFO L750 eck$LassoCheckResult]: Loop: 86986#L928-2 assume !false; 88194#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88192#L574-1 assume !false; 88191#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 88190#L452 assume !(0 == ~m_st~0); 88189#L456 assume !(0 == ~t1_st~0); 88188#L460 assume !(0 == ~t2_st~0); 88187#L464 assume !(0 == ~t3_st~0); 88186#L468 assume !(0 == ~t4_st~0); 88184#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 88182#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 88180#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 88177#L499 assume !(0 != eval_~tmp~0#1); 88178#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88628#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 88627#L599-3 assume !(0 == ~M_E~0); 88626#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 88625#L604-3 assume !(0 == ~T2_E~0); 88624#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88623#L614-3 assume !(0 == ~T4_E~0); 88622#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88621#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 88620#L629-3 assume !(0 == ~E_1~0); 88619#L634-3 assume !(0 == ~E_2~0); 88618#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88617#L644-3 assume !(0 == ~E_4~0); 88616#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88615#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88614#L292-21 assume !(1 == ~m_pc~0); 88609#L292-23 is_master_triggered_~__retres1~0#1 := 0; 88607#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88605#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 88603#L743-21 assume !(0 != activate_threads_~tmp~1#1); 88599#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88597#L311-21 assume !(1 == ~t1_pc~0); 88595#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 88593#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88591#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88589#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 88587#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88582#L330-21 assume !(1 == ~t2_pc~0); 88580#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 88578#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88576#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88574#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88572#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88568#L349-21 assume !(1 == ~t3_pc~0); 88564#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 88562#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88560#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88557#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 88554#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88552#L368-21 assume !(1 == ~t4_pc~0); 88550#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 88548#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88546#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88544#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88542#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88540#L387-21 assume !(1 == ~t5_pc~0); 88537#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 88534#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88532#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88530#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 88528#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88527#L667-3 assume !(1 == ~M_E~0); 88522#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88520#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88518#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88514#L682-3 assume !(1 == ~T4_E~0); 88512#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 88510#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 88508#L697-3 assume !(1 == ~E_1~0); 88505#L702-3 assume !(1 == ~E_2~0); 88503#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88501#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88499#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88497#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 88480#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 88476#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 88474#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 88472#L947 assume !(0 == start_simulation_~tmp~3#1); 88468#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 88459#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 88455#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 88453#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 88451#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88448#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88232#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 88202#L960 assume !(0 != start_simulation_~tmp___0~1#1); 86986#L928-2 [2023-11-21 22:05:02,816 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:02,816 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2023-11-21 22:05:02,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:02,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73858735] [2023-11-21 22:05:02,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:02,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:02,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:02,829 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:02,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:02,849 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:02,850 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:02,850 INFO L85 PathProgramCache]: Analyzing trace with hash 78427843, now seen corresponding path program 1 times [2023-11-21 22:05:02,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:02,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463284338] [2023-11-21 22:05:02,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:02,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:02,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:02,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:02,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:02,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463284338] [2023-11-21 22:05:02,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1463284338] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:02,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:02,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:05:02,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1298923747] [2023-11-21 22:05:02,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:02,952 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:05:02,952 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:02,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:05:02,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:05:02,953 INFO L87 Difference]: Start difference. First operand 3615 states and 4937 transitions. cyclomatic complexity: 1326 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:03,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:03,024 INFO L93 Difference]: Finished difference Result 6683 states and 8997 transitions. [2023-11-21 22:05:03,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6683 states and 8997 transitions. [2023-11-21 22:05:03,054 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6568 [2023-11-21 22:05:03,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6683 states to 6683 states and 8997 transitions. [2023-11-21 22:05:03,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6683 [2023-11-21 22:05:03,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6683 [2023-11-21 22:05:03,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6683 states and 8997 transitions. [2023-11-21 22:05:03,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:05:03,094 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6683 states and 8997 transitions. [2023-11-21 22:05:03,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6683 states and 8997 transitions. [2023-11-21 22:05:03,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6683 to 6359. [2023-11-21 22:05:03,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6359 states, 6359 states have (on average 1.3494260103789903) internal successors, (8581), 6358 states have internal predecessors, (8581), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:03,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6359 states to 6359 states and 8581 transitions. [2023-11-21 22:05:03,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6359 states and 8581 transitions. [2023-11-21 22:05:03,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:05:03,204 INFO L428 stractBuchiCegarLoop]: Abstraction has 6359 states and 8581 transitions. [2023-11-21 22:05:03,204 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-21 22:05:03,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6359 states and 8581 transitions. [2023-11-21 22:05:03,224 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6244 [2023-11-21 22:05:03,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:03,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:03,226 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:03,226 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:03,227 INFO L748 eck$LassoCheckResult]: Stem: 97052#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 97053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 97201#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97202#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 97376#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 97138#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97139#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97342#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97107#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97108#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97332#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 97103#L599 assume !(0 == ~M_E~0); 97104#L599-2 assume !(0 == ~T1_E~0); 96753#L604-1 assume !(0 == ~T2_E~0); 96742#L609-1 assume !(0 == ~T3_E~0); 96743#L614-1 assume !(0 == ~T4_E~0); 96907#L619-1 assume !(0 == ~T5_E~0); 97030#L624-1 assume !(0 == ~E_M~0); 97142#L629-1 assume !(0 == ~E_1~0); 96831#L634-1 assume !(0 == ~E_2~0); 96832#L639-1 assume !(0 == ~E_3~0); 97271#L644-1 assume !(0 == ~E_4~0); 97291#L649-1 assume !(0 == ~E_5~0); 96796#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96797#L292 assume !(1 == ~m_pc~0); 96921#L292-2 is_master_triggered_~__retres1~0#1 := 0; 97070#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97195#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 97393#L743 assume !(0 != activate_threads_~tmp~1#1); 96863#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96864#L311 assume !(1 == ~t1_pc~0); 97270#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97150#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96790#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 96769#L751 assume !(0 != activate_threads_~tmp___0~0#1); 96770#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97274#L330 assume !(1 == ~t2_pc~0); 97034#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96923#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96924#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 97206#L759 assume !(0 != activate_threads_~tmp___1~0#1); 97372#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96908#L349 assume !(1 == ~t3_pc~0); 96909#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97405#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97435#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 97422#L767 assume !(0 != activate_threads_~tmp___2~0#1); 97363#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97364#L368 assume !(1 == ~t4_pc~0); 96993#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 96994#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96893#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96894#L775 assume !(0 != activate_threads_~tmp___3~0#1); 96756#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96757#L387 assume !(1 == ~t5_pc~0); 97166#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 97167#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97036#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 96880#L783 assume !(0 != activate_threads_~tmp___4~0#1); 96881#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96977#L667 assume !(1 == ~M_E~0); 97062#L667-2 assume !(1 == ~T1_E~0); 97280#L672-1 assume !(1 == ~T2_E~0); 97016#L677-1 assume !(1 == ~T3_E~0); 97017#L682-1 assume !(1 == ~T4_E~0); 97249#L687-1 assume !(1 == ~T5_E~0); 97328#L692-1 assume !(1 == ~E_M~0); 97236#L697-1 assume !(1 == ~E_1~0); 97237#L702-1 assume !(1 == ~E_2~0); 97290#L707-1 assume !(1 == ~E_3~0); 97125#L712-1 assume !(1 == ~E_4~0); 97126#L717-1 assume !(1 == ~E_5~0); 97256#L722-1 assume { :end_inline_reset_delta_events } true; 97257#L928-2 [2023-11-21 22:05:03,227 INFO L750 eck$LassoCheckResult]: Loop: 97257#L928-2 assume !false; 99567#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99560#L574-1 assume !false; 99555#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 99553#L452 assume !(0 == ~m_st~0); 99554#L456 assume !(0 == ~t1_st~0); 100780#L460 assume !(0 == ~t2_st~0); 100777#L464 assume !(0 == ~t3_st~0); 100775#L468 assume !(0 == ~t4_st~0); 100772#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 100770#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 100768#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 100766#L499 assume !(0 != eval_~tmp~0#1); 100764#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 100762#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100760#L599-3 assume !(0 == ~M_E~0); 100759#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 100757#L604-3 assume !(0 == ~T2_E~0); 100755#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100753#L614-3 assume !(0 == ~T4_E~0); 100751#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 100749#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 100735#L629-3 assume !(0 == ~E_1~0); 100730#L634-3 assume !(0 == ~E_2~0); 100725#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100720#L644-3 assume !(0 == ~E_4~0); 100714#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 100710#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100676#L292-21 assume 1 == ~m_pc~0; 100674#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 100673#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100671#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 100669#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 100668#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100667#L311-21 assume !(1 == ~t1_pc~0); 100666#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 100665#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100663#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 100662#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 100661#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100656#L330-21 assume !(1 == ~t2_pc~0); 100654#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 100652#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100650#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100648#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100646#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100644#L349-21 assume 1 == ~t3_pc~0; 100641#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 100639#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100637#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100633#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100631#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100629#L368-21 assume !(1 == ~t4_pc~0); 100627#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 100625#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100623#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100621#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 100619#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100617#L387-21 assume 1 == ~t5_pc~0; 100613#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 100611#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100609#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100606#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 100604#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100602#L667-3 assume !(1 == ~M_E~0); 100534#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100599#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100597#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100595#L682-3 assume !(1 == ~T4_E~0); 100593#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 100592#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 100589#L697-3 assume !(1 == ~E_1~0); 100587#L702-3 assume !(1 == ~E_2~0); 100585#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 100583#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 100581#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 100579#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 100574#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 100572#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 100479#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 99601#L947 assume !(0 == start_simulation_~tmp~3#1); 99598#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 99595#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 99592#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 99589#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 99585#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 99584#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 99582#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 99578#L960 assume !(0 != start_simulation_~tmp___0~1#1); 97257#L928-2 [2023-11-21 22:05:03,227 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:03,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 6 times [2023-11-21 22:05:03,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:03,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857122679] [2023-11-21 22:05:03,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:03,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:03,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:03,239 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:03,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:03,269 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:03,270 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:03,270 INFO L85 PathProgramCache]: Analyzing trace with hash -492713732, now seen corresponding path program 1 times [2023-11-21 22:05:03,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:03,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60620154] [2023-11-21 22:05:03,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:03,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:03,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:03,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:03,331 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:03,331 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60620154] [2023-11-21 22:05:03,332 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [60620154] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:03,332 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:03,332 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:05:03,332 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115768062] [2023-11-21 22:05:03,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:03,333 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:05:03,334 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:03,334 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:05:03,334 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:05:03,334 INFO L87 Difference]: Start difference. First operand 6359 states and 8581 transitions. cyclomatic complexity: 2226 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:03,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:03,652 INFO L93 Difference]: Finished difference Result 12364 states and 16499 transitions. [2023-11-21 22:05:03,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12364 states and 16499 transitions. [2023-11-21 22:05:03,720 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12200 [2023-11-21 22:05:03,773 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12364 states to 12364 states and 16499 transitions. [2023-11-21 22:05:03,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12364 [2023-11-21 22:05:03,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12364 [2023-11-21 22:05:03,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12364 states and 16499 transitions. [2023-11-21 22:05:03,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:05:03,807 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12364 states and 16499 transitions. [2023-11-21 22:05:03,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12364 states and 16499 transitions. [2023-11-21 22:05:03,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12364 to 6650. [2023-11-21 22:05:03,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6650 states, 6650 states have (on average 1.3341353383458647) internal successors, (8872), 6649 states have internal predecessors, (8872), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:03,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6650 states to 6650 states and 8872 transitions. [2023-11-21 22:05:03,981 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8872 transitions. [2023-11-21 22:05:03,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-21 22:05:03,982 INFO L428 stractBuchiCegarLoop]: Abstraction has 6650 states and 8872 transitions. [2023-11-21 22:05:03,982 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-21 22:05:03,982 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6650 states and 8872 transitions. [2023-11-21 22:05:04,008 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6532 [2023-11-21 22:05:04,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:04,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:04,010 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:04,010 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:04,011 INFO L748 eck$LassoCheckResult]: Stem: 115784#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 115785#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 115930#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115931#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 116100#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 115863#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115864#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 116070#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115836#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115837#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116062#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115832#L599 assume !(0 == ~M_E~0); 115833#L599-2 assume !(0 == ~T1_E~0); 115488#L604-1 assume !(0 == ~T2_E~0); 115477#L609-1 assume !(0 == ~T3_E~0); 115478#L614-1 assume !(0 == ~T4_E~0); 115640#L619-1 assume !(0 == ~T5_E~0); 115759#L624-1 assume !(0 == ~E_M~0); 115867#L629-1 assume !(0 == ~E_1~0); 115565#L634-1 assume !(0 == ~E_2~0); 115566#L639-1 assume !(0 == ~E_3~0); 115998#L644-1 assume !(0 == ~E_4~0); 116018#L649-1 assume !(0 == ~E_5~0); 115531#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115532#L292 assume !(1 == ~m_pc~0); 115654#L292-2 is_master_triggered_~__retres1~0#1 := 0; 115803#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115755#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 115756#L743 assume !(0 != activate_threads_~tmp~1#1); 115597#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115598#L311 assume !(1 == ~t1_pc~0); 115997#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115874#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115525#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115504#L751 assume !(0 != activate_threads_~tmp___0~0#1); 115505#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116001#L330 assume !(1 == ~t2_pc~0); 115762#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 115656#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115657#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 115935#L759 assume !(0 != activate_threads_~tmp___1~0#1); 116096#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115641#L349 assume !(1 == ~t3_pc~0); 115642#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 115966#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115479#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 115480#L767 assume !(0 != activate_threads_~tmp___2~0#1); 116088#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116089#L368 assume !(1 == ~t4_pc~0); 115721#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 115722#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 115626#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 115627#L775 assume !(0 != activate_threads_~tmp___3~0#1); 115491#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 115492#L387 assume !(1 == ~t5_pc~0); 115892#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 115893#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115764#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 115765#L783 assume !(0 != activate_threads_~tmp___4~0#1); 115614#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115709#L667 assume !(1 == ~M_E~0); 115795#L667-2 assume !(1 == ~T1_E~0); 116008#L672-1 assume !(1 == ~T2_E~0); 115744#L677-1 assume !(1 == ~T3_E~0); 115745#L682-1 assume !(1 == ~T4_E~0); 115979#L687-1 assume !(1 == ~T5_E~0); 116057#L692-1 assume !(1 == ~E_M~0); 115964#L697-1 assume !(1 == ~E_1~0); 115965#L702-1 assume !(1 == ~E_2~0); 116017#L707-1 assume !(1 == ~E_3~0); 115854#L712-1 assume !(1 == ~E_4~0); 115855#L717-1 assume !(1 == ~E_5~0); 115986#L722-1 assume { :end_inline_reset_delta_events } true; 115987#L928-2 [2023-11-21 22:05:04,011 INFO L750 eck$LassoCheckResult]: Loop: 115987#L928-2 assume !false; 118052#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118049#L574-1 assume !false; 118047#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 118044#L452 assume !(0 == ~m_st~0); 118045#L456 assume !(0 == ~t1_st~0); 118903#L460 assume !(0 == ~t2_st~0); 118902#L464 assume !(0 == ~t3_st~0); 118901#L468 assume !(0 == ~t4_st~0); 118898#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 118896#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 118894#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 118889#L499 assume !(0 != eval_~tmp~0#1); 118887#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 118885#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 118883#L599-3 assume !(0 == ~M_E~0); 118881#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 118879#L604-3 assume !(0 == ~T2_E~0); 118877#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 118871#L614-3 assume !(0 == ~T4_E~0); 118851#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 118831#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 118521#L629-3 assume !(0 == ~E_1~0); 118519#L634-3 assume !(0 == ~E_2~0); 118518#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 118517#L644-3 assume !(0 == ~E_4~0); 118513#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 118511#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118509#L292-21 assume 1 == ~m_pc~0; 118402#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 118398#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118396#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 118393#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 118391#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118386#L311-21 assume !(1 == ~t1_pc~0); 118384#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 118382#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118380#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 118378#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 118376#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118372#L330-21 assume !(1 == ~t2_pc~0); 118369#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 118367#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118365#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118363#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 118361#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118359#L349-21 assume !(1 == ~t3_pc~0); 118353#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 118351#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118349#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118347#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 118343#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118341#L368-21 assume !(1 == ~t4_pc~0); 118339#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 118337#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118335#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 118333#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 118331#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118329#L387-21 assume 1 == ~t5_pc~0; 118325#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 118321#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118317#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 118230#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 118226#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118224#L667-3 assume !(1 == ~M_E~0); 118075#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 118219#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 118217#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 118214#L682-3 assume !(1 == ~T4_E~0); 118213#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 118212#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 118209#L697-3 assume !(1 == ~E_1~0); 118205#L702-3 assume !(1 == ~E_2~0); 118204#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 118203#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 118200#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 118198#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 118195#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 118192#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 118190#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 118187#L947 assume !(0 == start_simulation_~tmp~3#1); 118188#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 118422#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 118420#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 118419#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 118418#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 118416#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 118415#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 118414#L960 assume !(0 != start_simulation_~tmp___0~1#1); 115987#L928-2 [2023-11-21 22:05:04,013 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:04,013 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 7 times [2023-11-21 22:05:04,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:04,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914450521] [2023-11-21 22:05:04,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:04,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:04,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:04,030 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:04,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:04,055 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:04,055 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:04,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1932188669, now seen corresponding path program 1 times [2023-11-21 22:05:04,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:04,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871138690] [2023-11-21 22:05:04,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:04,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:04,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:04,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:04,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:04,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [871138690] [2023-11-21 22:05:04,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [871138690] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:04,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:04,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:05:04,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538759458] [2023-11-21 22:05:04,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:04,163 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:05:04,163 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:04,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:05:04,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:05:04,164 INFO L87 Difference]: Start difference. First operand 6650 states and 8872 transitions. cyclomatic complexity: 2226 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:04,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:04,338 INFO L93 Difference]: Finished difference Result 8434 states and 11117 transitions. [2023-11-21 22:05:04,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8434 states and 11117 transitions. [2023-11-21 22:05:04,378 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8308 [2023-11-21 22:05:04,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8434 states to 8434 states and 11117 transitions. [2023-11-21 22:05:04,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8434 [2023-11-21 22:05:04,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8434 [2023-11-21 22:05:04,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8434 states and 11117 transitions. [2023-11-21 22:05:04,432 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:05:04,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8434 states and 11117 transitions. [2023-11-21 22:05:04,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8434 states and 11117 transitions. [2023-11-21 22:05:04,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8434 to 6674. [2023-11-21 22:05:04,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6674 states, 6674 states have (on average 1.3195984417141144) internal successors, (8807), 6673 states have internal predecessors, (8807), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:04,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6674 states to 6674 states and 8807 transitions. [2023-11-21 22:05:04,637 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6674 states and 8807 transitions. [2023-11-21 22:05:04,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-21 22:05:04,638 INFO L428 stractBuchiCegarLoop]: Abstraction has 6674 states and 8807 transitions. [2023-11-21 22:05:04,638 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-21 22:05:04,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6674 states and 8807 transitions. [2023-11-21 22:05:04,659 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6556 [2023-11-21 22:05:04,659 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:04,659 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:04,661 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:04,661 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:04,661 INFO L748 eck$LassoCheckResult]: Stem: 130900#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 130901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 131059#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131060#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131297#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 130988#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130989#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131249#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 130958#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 130959#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131242#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 130954#L599 assume !(0 == ~M_E~0); 130955#L599-2 assume !(0 == ~T1_E~0); 130584#L604-1 assume !(0 == ~T2_E~0); 130573#L609-1 assume !(0 == ~T3_E~0); 130574#L614-1 assume !(0 == ~T4_E~0); 130739#L619-1 assume !(0 == ~T5_E~0); 130871#L624-1 assume !(0 == ~E_M~0); 130995#L629-1 assume !(0 == ~E_1~0); 130663#L634-1 assume !(0 == ~E_2~0); 130664#L639-1 assume !(0 == ~E_3~0); 131142#L644-1 assume !(0 == ~E_4~0); 131171#L649-1 assume !(0 == ~E_5~0); 130628#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 130629#L292 assume !(1 == ~m_pc~0); 130753#L292-2 is_master_triggered_~__retres1~0#1 := 0; 130919#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131048#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 131319#L743 assume !(0 != activate_threads_~tmp~1#1); 130695#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130696#L311 assume !(1 == ~t1_pc~0); 131141#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131003#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130622#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 130601#L751 assume !(0 != activate_threads_~tmp___0~0#1); 130602#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131145#L330 assume !(1 == ~t2_pc~0); 130874#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 130755#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130756#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 131065#L759 assume !(0 != activate_threads_~tmp___1~0#1); 131290#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130740#L349 assume !(1 == ~t3_pc~0); 130741#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 131343#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131386#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 131363#L767 assume !(0 != activate_threads_~tmp___2~0#1); 131279#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131280#L368 assume !(1 == ~t4_pc~0); 130831#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 130832#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 130726#L775 assume !(0 != activate_threads_~tmp___3~0#1); 130587#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130588#L387 assume !(1 == ~t5_pc~0); 131016#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 131017#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130877#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 130878#L783 assume !(0 != activate_threads_~tmp___4~0#1); 130713#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130811#L667 assume !(1 == ~M_E~0); 130910#L667-2 assume !(1 == ~T1_E~0); 131151#L672-1 assume !(1 == ~T2_E~0); 130855#L677-1 assume !(1 == ~T3_E~0); 130856#L682-1 assume !(1 == ~T4_E~0); 131120#L687-1 assume !(1 == ~T5_E~0); 131236#L692-1 assume !(1 == ~E_M~0); 131104#L697-1 assume !(1 == ~E_1~0); 131105#L702-1 assume !(1 == ~E_2~0); 131170#L707-1 assume !(1 == ~E_3~0); 130979#L712-1 assume !(1 == ~E_4~0); 130980#L717-1 assume !(1 == ~E_5~0); 131127#L722-1 assume { :end_inline_reset_delta_events } true; 131128#L928-2 [2023-11-21 22:05:04,662 INFO L750 eck$LassoCheckResult]: Loop: 131128#L928-2 assume !false; 131572#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 131775#L574-1 assume !false; 131776#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 131771#L452 assume !(0 == ~m_st~0); 131772#L456 assume !(0 == ~t1_st~0); 132464#L460 assume !(0 == ~t2_st~0); 132462#L464 assume !(0 == ~t3_st~0); 132460#L468 assume !(0 == ~t4_st~0); 132457#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 132454#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 132452#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 132450#L499 assume !(0 != eval_~tmp~0#1); 132448#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 132446#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132444#L599-3 assume !(0 == ~M_E~0); 132442#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 132440#L604-3 assume !(0 == ~T2_E~0); 132438#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132436#L614-3 assume !(0 == ~T4_E~0); 132434#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 132432#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 132430#L629-3 assume !(0 == ~E_1~0); 132428#L634-3 assume !(0 == ~E_2~0); 132426#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 132424#L644-3 assume !(0 == ~E_4~0); 132422#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 132420#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132418#L292-21 assume 1 == ~m_pc~0; 132415#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 132412#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132410#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 132407#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 132404#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132402#L311-21 assume !(1 == ~t1_pc~0); 132400#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 132398#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132396#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 132394#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 132392#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132389#L330-21 assume !(1 == ~t2_pc~0); 132386#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 132384#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132382#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 132380#L759-21 assume !(0 != activate_threads_~tmp___1~0#1); 132378#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132376#L349-21 assume !(1 == ~t3_pc~0); 132374#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 132370#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132366#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 132362#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 132358#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132356#L368-21 assume !(1 == ~t4_pc~0); 132354#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 132352#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132350#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 132348#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132346#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132344#L387-21 assume 1 == ~t5_pc~0; 132342#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132338#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132334#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 132330#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 132326#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132324#L667-3 assume !(1 == ~M_E~0); 132321#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 132320#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 132319#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 132318#L682-3 assume !(1 == ~T4_E~0); 132316#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 132315#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 132314#L697-3 assume !(1 == ~E_1~0); 132313#L702-3 assume !(1 == ~E_2~0); 132071#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 132068#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 132066#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 132064#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 132061#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 132059#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 132057#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 132054#L947 assume !(0 == start_simulation_~tmp~3#1); 132050#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 132051#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 132043#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 132041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 132038#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 132039#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 132032#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 132030#L960 assume !(0 != start_simulation_~tmp___0~1#1); 131128#L928-2 [2023-11-21 22:05:04,662 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:04,662 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 8 times [2023-11-21 22:05:04,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:04,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043654812] [2023-11-21 22:05:04,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:04,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:04,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:04,674 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:04,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:04,694 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:04,695 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:04,695 INFO L85 PathProgramCache]: Analyzing trace with hash -1469292289, now seen corresponding path program 1 times [2023-11-21 22:05:04,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:04,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [649440977] [2023-11-21 22:05:04,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:04,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:04,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:04,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:04,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:04,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [649440977] [2023-11-21 22:05:04,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [649440977] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:04,811 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:04,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:05:04,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76744383] [2023-11-21 22:05:04,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:04,812 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:05:04,812 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:04,812 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:05:04,812 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:05:04,813 INFO L87 Difference]: Start difference. First operand 6674 states and 8807 transitions. cyclomatic complexity: 2137 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:05,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:05,037 INFO L93 Difference]: Finished difference Result 10628 states and 13870 transitions. [2023-11-21 22:05:05,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10628 states and 13870 transitions. [2023-11-21 22:05:05,085 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10502 [2023-11-21 22:05:05,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10628 states to 10628 states and 13870 transitions. [2023-11-21 22:05:05,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10628 [2023-11-21 22:05:05,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10628 [2023-11-21 22:05:05,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10628 states and 13870 transitions. [2023-11-21 22:05:05,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:05:05,147 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10628 states and 13870 transitions. [2023-11-21 22:05:05,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10628 states and 13870 transitions. [2023-11-21 22:05:05,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10628 to 6830. [2023-11-21 22:05:05,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6830 states, 6830 states have (on average 1.305710102489019) internal successors, (8918), 6829 states have internal predecessors, (8918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:05,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6830 states to 6830 states and 8918 transitions. [2023-11-21 22:05:05,274 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6830 states and 8918 transitions. [2023-11-21 22:05:05,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-21 22:05:05,275 INFO L428 stractBuchiCegarLoop]: Abstraction has 6830 states and 8918 transitions. [2023-11-21 22:05:05,275 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-21 22:05:05,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6830 states and 8918 transitions. [2023-11-21 22:05:05,295 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6712 [2023-11-21 22:05:05,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:05,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:05,298 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:05,298 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:05,299 INFO L748 eck$LassoCheckResult]: Stem: 148194#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 148195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 148340#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 148341#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 148531#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 148273#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 148274#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 148487#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 148245#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 148246#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 148480#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 148241#L599 assume !(0 == ~M_E~0); 148242#L599-2 assume !(0 == ~T1_E~0); 147898#L604-1 assume !(0 == ~T2_E~0); 147887#L609-1 assume !(0 == ~T3_E~0); 147888#L614-1 assume !(0 == ~T4_E~0); 148049#L619-1 assume !(0 == ~T5_E~0); 148170#L624-1 assume !(0 == ~E_M~0); 148278#L629-1 assume !(0 == ~E_1~0); 147973#L634-1 assume !(0 == ~E_2~0); 147974#L639-1 assume !(0 == ~E_3~0); 148407#L644-1 assume !(0 == ~E_4~0); 148429#L649-1 assume !(0 == ~E_5~0); 147941#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 147942#L292 assume !(1 == ~m_pc~0); 148063#L292-2 is_master_triggered_~__retres1~0#1 := 0; 148209#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148332#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 148543#L743 assume !(0 != activate_threads_~tmp~1#1); 148005#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148006#L311 assume !(1 == ~t1_pc~0); 148406#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 148285#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 147935#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 147914#L751 assume !(0 != activate_threads_~tmp___0~0#1); 147915#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 148410#L330 assume !(1 == ~t2_pc~0); 148173#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 148065#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 148066#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 148346#L759 assume !(0 != activate_threads_~tmp___1~0#1); 148527#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148050#L349 assume !(1 == ~t3_pc~0); 148051#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 148374#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148375#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 148572#L767 assume !(0 != activate_threads_~tmp___2~0#1); 148515#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 148516#L368 assume !(1 == ~t4_pc~0); 148135#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 148136#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 148036#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 148037#L775 assume !(0 != activate_threads_~tmp___3~0#1); 147901#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 147902#L387 assume !(1 == ~t5_pc~0); 148301#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 148302#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 148175#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 148176#L783 assume !(0 != activate_threads_~tmp___4~0#1); 148023#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148121#L667 assume !(1 == ~M_E~0); 148202#L667-2 assume !(1 == ~T1_E~0); 148416#L672-1 assume !(1 == ~T2_E~0); 148157#L677-1 assume !(1 == ~T3_E~0); 148158#L682-1 assume !(1 == ~T4_E~0); 148389#L687-1 assume !(1 == ~T5_E~0); 148475#L692-1 assume !(1 == ~E_M~0); 148372#L697-1 assume !(1 == ~E_1~0); 148373#L702-1 assume !(1 == ~E_2~0); 148428#L707-1 assume !(1 == ~E_3~0); 148263#L712-1 assume !(1 == ~E_4~0); 148264#L717-1 assume !(1 == ~E_5~0); 148396#L722-1 assume { :end_inline_reset_delta_events } true; 148397#L928-2 [2023-11-21 22:05:05,299 INFO L750 eck$LassoCheckResult]: Loop: 148397#L928-2 assume !false; 149546#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 149542#L574-1 assume !false; 149539#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 149535#L452 assume !(0 == ~m_st~0); 149536#L456 assume !(0 == ~t1_st~0); 150176#L460 assume !(0 == ~t2_st~0); 150173#L464 assume !(0 == ~t3_st~0); 150174#L468 assume !(0 == ~t4_st~0); 150175#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 150170#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 150165#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 150160#L499 assume !(0 != eval_~tmp~0#1); 150156#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 150152#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 150148#L599-3 assume !(0 == ~M_E~0); 150145#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 150050#L604-3 assume !(0 == ~T2_E~0); 150046#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 150044#L614-3 assume !(0 == ~T4_E~0); 150042#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 150040#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 150037#L629-3 assume !(0 == ~E_1~0); 150034#L634-3 assume !(0 == ~E_2~0); 150032#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 150030#L644-3 assume !(0 == ~E_4~0); 150028#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 150026#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150024#L292-21 assume 1 == ~m_pc~0; 150021#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 150019#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 150011#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 150001#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 149989#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 149977#L311-21 assume !(1 == ~t1_pc~0); 149971#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 149867#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 149865#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 149862#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 149861#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 149859#L330-21 assume !(1 == ~t2_pc~0); 149857#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 149853#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 149851#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 149849#L759-21 assume !(0 != activate_threads_~tmp___1~0#1); 149847#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149842#L349-21 assume !(1 == ~t3_pc~0); 149840#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 149933#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149931#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 149831#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 149828#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 149825#L368-21 assume !(1 == ~t4_pc~0); 149823#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 149821#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 149819#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 149817#L775-21 assume !(0 != activate_threads_~tmp___3~0#1); 149815#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 149811#L387-21 assume 1 == ~t5_pc~0; 149809#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 149810#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 149833#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 149749#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 149740#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 149719#L667-3 assume !(1 == ~M_E~0); 149714#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 149712#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 149710#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 149708#L682-3 assume !(1 == ~T4_E~0); 149706#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 149704#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 149702#L697-3 assume !(1 == ~E_1~0); 149699#L702-3 assume !(1 == ~E_2~0); 149697#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 149680#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 149679#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 149678#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 149676#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 149674#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 149598#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 149595#L947 assume !(0 == start_simulation_~tmp~3#1); 149592#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 149590#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 149589#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 149585#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 149583#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 149581#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 149570#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 149562#L960 assume !(0 != start_simulation_~tmp___0~1#1); 148397#L928-2 [2023-11-21 22:05:05,300 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:05,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 9 times [2023-11-21 22:05:05,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:05,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078611052] [2023-11-21 22:05:05,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:05,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:05,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:05,311 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:05,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:05,330 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:05,331 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:05,331 INFO L85 PathProgramCache]: Analyzing trace with hash -1541678847, now seen corresponding path program 1 times [2023-11-21 22:05:05,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:05,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109063665] [2023-11-21 22:05:05,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:05,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:05,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:05,345 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:05,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:05,373 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:05,374 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:05,374 INFO L85 PathProgramCache]: Analyzing trace with hash 356636989, now seen corresponding path program 1 times [2023-11-21 22:05:05,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:05,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782080930] [2023-11-21 22:05:05,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:05,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:05,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:05,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:05,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:05,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782080930] [2023-11-21 22:05:05,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1782080930] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:05,436 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:05,437 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:05:05,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685857882] [2023-11-21 22:05:05,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:07,247 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:05:07,248 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:05:07,248 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:05:07,248 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:05:07,248 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-21 22:05:07,248 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:07,248 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:05:07,249 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:05:07,249 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-1.c_Iteration22_Loop [2023-11-21 22:05:07,249 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:05:07,249 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:05:07,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,291 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,293 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,296 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,302 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,305 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,308 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,311 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,317 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,320 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,322 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,325 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,328 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,331 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,334 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,341 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,344 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,347 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,354 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,356 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,361 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,366 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,369 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,372 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,374 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,377 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,380 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,384 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,387 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,393 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,395 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,401 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,404 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,407 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,412 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,415 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,423 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,429 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,432 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,434 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,437 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,439 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,442 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,447 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,452 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,455 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,458 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,462 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,467 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,470 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,475 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,480 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,482 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,485 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,487 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,490 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,493 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,495 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,502 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,506 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,508 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,515 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,518 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,520 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,526 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,528 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,530 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,533 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,536 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:07,539 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,100 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:05:08,101 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-21 22:05:08,103 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:08,104 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:08,108 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:08,122 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:05:08,122 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:05:08,135 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-21 22:05:08,151 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-21 22:05:08,152 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-21 22:05:08,171 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:08,172 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:08,172 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:08,175 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:08,185 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-21 22:05:08,186 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:05:08,186 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:05:08,209 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-21 22:05:08,210 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-21 22:05:08,230 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:08,232 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:08,233 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:08,234 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:08,240 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-21 22:05:08,248 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:05:08,248 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:05:08,270 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-21 22:05:08,270 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-21 22:05:08,294 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:08,294 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:08,294 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:08,296 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:08,303 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:05:08,303 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:05:08,316 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-21 22:05:08,326 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-21 22:05:08,326 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-21 22:05:08,345 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2023-11-21 22:05:08,346 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:08,346 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:08,347 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:08,348 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-21 22:05:08,350 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-21 22:05:08,350 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:05:08,388 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:08,389 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:08,389 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:08,394 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:08,405 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-21 22:05:08,405 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-21 22:05:08,418 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-21 22:05:08,429 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-21 22:05:08,452 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:08,453 INFO L210 LassoAnalysis]: Preferences: [2023-11-21 22:05:08,453 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-21 22:05:08,453 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-21 22:05:08,453 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-21 22:05:08,453 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-21 22:05:08,453 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:08,453 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-21 22:05:08,453 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-21 22:05:08,453 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-1.c_Iteration22_Loop [2023-11-21 22:05:08,454 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-21 22:05:08,454 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-21 22:05:08,458 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,463 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,466 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,468 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,471 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,485 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,487 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,492 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,495 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,513 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,516 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,518 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,521 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,524 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,527 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,533 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,535 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,537 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,539 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,542 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,548 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,553 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,555 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,560 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,562 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,566 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,568 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,575 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,577 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,580 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,582 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,587 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,590 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,593 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,603 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,605 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,607 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,609 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,611 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,613 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,616 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,621 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,624 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,629 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,631 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,636 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,638 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,645 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,648 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,651 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,653 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,667 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,682 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,688 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,690 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,699 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:08,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-21 22:05:09,315 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-21 22:05:09,328 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-21 22:05:09,330 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:09,330 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:09,331 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:09,346 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:05:09,358 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:05:09,358 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:05:09,359 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:05:09,359 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:05:09,359 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:05:09,361 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:05:09,362 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:05:09,364 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-21 22:05:09,384 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:05:09,407 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:09,407 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:09,407 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:09,408 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:09,415 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:05:09,427 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:05:09,427 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:05:09,428 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:05:09,428 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-21 22:05:09,428 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:05:09,429 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-21 22:05:09,429 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:05:09,431 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-21 22:05:09,448 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:05:09,470 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:09,470 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:09,470 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:09,471 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:09,474 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:05:09,486 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:05:09,486 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:05:09,486 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:05:09,486 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:05:09,486 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:05:09,487 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:05:09,487 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:05:09,489 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-21 22:05:09,504 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:05:09,526 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:09,526 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:09,527 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:09,528 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:09,531 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:05:09,543 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:05:09,543 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:05:09,543 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:05:09,543 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:05:09,543 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:05:09,544 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:05:09,544 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:05:09,546 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-21 22:05:09,550 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-21 22:05:09,570 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:09,571 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:09,571 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:09,572 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:09,577 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-21 22:05:09,589 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-21 22:05:09,589 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-21 22:05:09,589 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-21 22:05:09,589 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-21 22:05:09,589 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-21 22:05:09,590 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-21 22:05:09,591 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-21 22:05:09,592 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-21 22:05:09,608 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-21 22:05:09,611 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-21 22:05:09,611 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-21 22:05:09,613 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:05:09,613 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:05:09,649 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:05:09,655 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-21 22:05:09,656 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-21 22:05:09,656 INFO L513 LassoAnalysis]: Proved termination. [2023-11-21 22:05:09,656 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-21 22:05:09,656 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2023-11-21 22:05:09,680 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:09,682 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-21 22:05:09,724 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:09,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:09,778 INFO L262 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-21 22:05:09,781 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:05:09,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:09,930 INFO L262 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-21 22:05:09,933 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-21 22:05:10,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:10,156 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-21 22:05:10,157 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 6830 states and 8918 transitions. cyclomatic complexity: 2092 Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:10,403 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 6830 states and 8918 transitions. cyclomatic complexity: 2092. Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 18720 states and 24649 transitions. Complement of second has 5 states. [2023-11-21 22:05:10,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-21 22:05:10,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:10,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 717 transitions. [2023-11-21 22:05:10,408 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 717 transitions. Stem has 73 letters. Loop has 89 letters. [2023-11-21 22:05:10,417 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:05:10,417 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 717 transitions. Stem has 162 letters. Loop has 89 letters. [2023-11-21 22:05:10,418 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:05:10,418 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 717 transitions. Stem has 73 letters. Loop has 178 letters. [2023-11-21 22:05:10,420 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-21 22:05:10,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18720 states and 24649 transitions. [2023-11-21 22:05:10,519 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12568 [2023-11-21 22:05:10,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18720 states to 18704 states and 24633 transitions. [2023-11-21 22:05:10,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12735 [2023-11-21 22:05:10,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12776 [2023-11-21 22:05:10,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18704 states and 24633 transitions. [2023-11-21 22:05:10,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:05:10,609 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18704 states and 24633 transitions. [2023-11-21 22:05:10,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18704 states and 24633 transitions. [2023-11-21 22:05:10,821 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-21 22:05:10,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18704 to 18647. [2023-11-21 22:05:10,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18647 states, 18647 states have (on average 1.3158148763876227) internal successors, (24536), 18646 states have internal predecessors, (24536), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:11,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18647 states to 18647 states and 24536 transitions. [2023-11-21 22:05:11,046 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18647 states and 24536 transitions. [2023-11-21 22:05:11,046 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:11,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:05:11,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:05:11,047 INFO L87 Difference]: Start difference. First operand 18647 states and 24536 transitions. Second operand has 3 states, 3 states have (on average 54.0) internal successors, (162), 3 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:11,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:11,209 INFO L93 Difference]: Finished difference Result 19727 states and 25760 transitions. [2023-11-21 22:05:11,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19727 states and 25760 transitions. [2023-11-21 22:05:11,319 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13288 [2023-11-21 22:05:11,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19727 states to 19727 states and 25760 transitions. [2023-11-21 22:05:11,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13439 [2023-11-21 22:05:11,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13439 [2023-11-21 22:05:11,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19727 states and 25760 transitions. [2023-11-21 22:05:11,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:05:11,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19727 states and 25760 transitions. [2023-11-21 22:05:11,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19727 states and 25760 transitions. [2023-11-21 22:05:11,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19727 to 18647. [2023-11-21 22:05:11,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18647 states, 18647 states have (on average 1.3106665951627607) internal successors, (24440), 18646 states have internal predecessors, (24440), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:11,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18647 states to 18647 states and 24440 transitions. [2023-11-21 22:05:11,700 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18647 states and 24440 transitions. [2023-11-21 22:05:11,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:05:11,701 INFO L428 stractBuchiCegarLoop]: Abstraction has 18647 states and 24440 transitions. [2023-11-21 22:05:11,701 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-21 22:05:11,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18647 states and 24440 transitions. [2023-11-21 22:05:11,769 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12568 [2023-11-21 22:05:11,769 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:11,769 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:11,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:11,772 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:11,773 INFO L748 eck$LassoCheckResult]: Stem: 212891#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 212892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 213156#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 213157#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 213473#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 213040#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 213041#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 213406#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 212986#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 212987#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 213396#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 212980#L599 assume !(0 == ~M_E~0); 212981#L599-2 assume !(0 == ~T1_E~0); 212347#L604-1 assume !(0 == ~T2_E~0); 212325#L609-1 assume !(0 == ~T3_E~0); 212326#L614-1 assume !(0 == ~T4_E~0); 212623#L619-1 assume !(0 == ~T5_E~0); 212845#L624-1 assume !(0 == ~E_M~0); 213048#L629-1 assume !(0 == ~E_1~0); 212487#L634-1 assume !(0 == ~E_2~0); 212488#L639-1 assume !(0 == ~E_3~0); 213283#L644-1 assume !(0 == ~E_4~0); 213321#L649-1 assume !(0 == ~E_5~0); 212424#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 212425#L292 assume !(1 == ~m_pc~0); 212647#L292-2 is_master_triggered_~__retres1~0#1 := 0; 212917#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 213571#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 213493#L743 assume !(0 != activate_threads_~tmp~1#1); 212546#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 212547#L311 assume !(1 == ~t1_pc~0); 213281#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 213060#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 212413#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 212373#L751 assume !(0 != activate_threads_~tmp___0~0#1); 212374#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213288#L330 assume !(1 == ~t2_pc~0); 212850#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 212652#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 212653#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 213165#L759 assume !(0 != activate_threads_~tmp___1~0#1); 213466#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 212628#L349 assume !(1 == ~t3_pc~0); 212629#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 213220#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 212337#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 212338#L767 assume !(0 != activate_threads_~tmp___2~0#1); 213451#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 213452#L368 assume !(1 == ~t4_pc~0); 212784#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 212785#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 212599#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 212600#L775 assume !(0 != activate_threads_~tmp___3~0#1); 212348#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 212349#L387 assume !(1 == ~t5_pc~0); 213090#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 213091#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 213572#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 213570#L783 assume !(0 != activate_threads_~tmp___4~0#1); 212582#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 212760#L667 assume !(1 == ~M_E~0); 212904#L667-2 assume !(1 == ~T1_E~0); 213302#L672-1 assume !(1 == ~T2_E~0); 212821#L677-1 assume !(1 == ~T3_E~0); 212822#L682-1 assume !(1 == ~T4_E~0); 213244#L687-1 assume !(1 == ~T5_E~0); 213384#L692-1 assume !(1 == ~E_M~0); 213218#L697-1 assume !(1 == ~E_1~0); 213219#L702-1 assume !(1 == ~E_2~0); 213318#L707-1 assume !(1 == ~E_3~0); 213020#L712-1 assume !(1 == ~E_4~0); 213021#L717-1 assume !(1 == ~E_5~0); 213259#L722-1 assume { :end_inline_reset_delta_events } true; 213260#L928-2 assume !false; 213698#L929 [2023-11-21 22:05:11,780 INFO L750 eck$LassoCheckResult]: Loop: 213698#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 224163#L574-1 assume !false; 224161#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 224160#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 224159#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 224155#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 224153#L499 assume 0 != eval_~tmp~0#1; 224151#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 224149#L507 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 224150#L68 assume 0 == ~m_pc~0; 229954#L93-1 assume !false; 229951#L80 havoc master_#t~nondet4#1;~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 229949#L292-3 assume 1 == ~m_pc~0; 229947#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 229948#L303-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 229941#is_master_triggered_returnLabel#2 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 229939#L743-3 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 229914#L743-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 229887#L311-3 assume !(1 == ~t1_pc~0); 229886#L311-5 is_transmit1_triggered_~__retres1~1#1 := 0; 229885#L322-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 229884#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 229883#L751-3 assume !(0 != activate_threads_~tmp___0~0#1); 229881#L751-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 229879#L330-3 assume !(1 == ~t2_pc~0); 229877#L330-5 is_transmit2_triggered_~__retres1~2#1 := 0; 229876#L341-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 229875#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 229874#L759-3 assume !(0 != activate_threads_~tmp___1~0#1); 229872#L759-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 228058#L349-3 assume !(1 == ~t3_pc~0); 228054#L349-5 is_transmit3_triggered_~__retres1~3#1 := 0; 228052#L360-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 228051#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 228049#L767-3 assume !(0 != activate_threads_~tmp___2~0#1); 228046#L767-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 228044#L368-3 assume !(1 == ~t4_pc~0); 228042#L368-5 is_transmit4_triggered_~__retres1~4#1 := 0; 228007#L379-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 228006#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 228005#L775-3 assume !(0 != activate_threads_~tmp___3~0#1); 224834#L775-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224833#L387-3 assume !(1 == ~t5_pc~0); 224832#L387-5 is_transmit5_triggered_~__retres1~5#1 := 0; 221794#L398-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221763#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221761#L783-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 221758#L783-5 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 220748#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 220746#master_returnLabel#1 havoc master_#t~nondet4#1;assume { :end_inline_master } true; 220743#L507-2 havoc eval_~tmp_ndt_1~0#1; 220555#L504-1 assume !(0 == ~t1_st~0); 220556#L518-1 assume !(0 == ~t2_st~0); 221077#L532-1 assume !(0 == ~t3_st~0); 221073#L546-1 assume !(0 == ~t4_st~0); 221074#L560-1 assume !(0 == ~t5_st~0); 221773#L574-1 assume !false; 221771#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 221770#L452 assume !(0 == ~m_st~0); 221767#L456 assume !(0 == ~t1_st~0); 221768#L460 assume !(0 == ~t2_st~0); 221764#L464 assume !(0 == ~t3_st~0); 221765#L468 assume !(0 == ~t4_st~0); 221766#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 221769#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 230186#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 230185#L499 assume !(0 != eval_~tmp~0#1); 230006#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 229820#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 229819#L599-3 assume !(0 == ~M_E~0); 229818#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 229816#L604-3 assume !(0 == ~T2_E~0); 229815#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 229814#L614-3 assume !(0 == ~T4_E~0); 229812#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 229810#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 229809#L629-3 assume !(0 == ~E_1~0); 229808#L634-3 assume !(0 == ~E_2~0); 229807#L639-3 assume !(0 == ~E_3~0); 229806#L644-3 assume !(0 == ~E_4~0); 229805#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 229804#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 229802#L292-21 assume 1 == ~m_pc~0; 229800#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 229799#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 229798#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 229796#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 229795#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 229794#L311-21 assume !(1 == ~t1_pc~0); 229793#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 229792#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 229791#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 229789#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 229788#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 229786#L330-21 assume !(1 == ~t2_pc~0); 229782#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 229780#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 229778#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 229776#L759-21 assume !(0 != activate_threads_~tmp___1~0#1); 229772#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 229770#L349-21 assume !(1 == ~t3_pc~0); 229767#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 229764#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 229762#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 229760#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 229757#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 229755#L368-21 assume !(1 == ~t4_pc~0); 229753#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 229750#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 229748#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 229746#L775-21 assume !(0 != activate_threads_~tmp___3~0#1); 229744#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 229742#L387-21 assume 1 == ~t5_pc~0; 229739#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 229735#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 229733#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 229731#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 229728#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 229725#L667-3 assume !(1 == ~M_E~0); 222776#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 229722#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 229720#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 229718#L682-3 assume !(1 == ~T4_E~0); 229716#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 229278#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 229277#L697-3 assume !(1 == ~E_1~0); 229276#L702-3 assume !(1 == ~E_2~0); 229274#L707-3 assume !(1 == ~E_3~0); 223963#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 223960#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 223958#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 223956#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 223953#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 223951#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 223948#L947 assume !(0 == start_simulation_~tmp~3#1); 223949#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 224186#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 224183#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 224181#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 224177#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 224175#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 224173#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 224172#L960 assume !(0 != start_simulation_~tmp___0~1#1); 224169#L928-2 assume !false; 213698#L929 [2023-11-21 22:05:11,781 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:11,781 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 1 times [2023-11-21 22:05:11,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:11,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854795218] [2023-11-21 22:05:11,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:11,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:11,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:11,796 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:11,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:11,827 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:11,827 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:11,828 INFO L85 PathProgramCache]: Analyzing trace with hash 926434570, now seen corresponding path program 1 times [2023-11-21 22:05:11,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:11,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11912485] [2023-11-21 22:05:11,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:11,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:11,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:12,036 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:12,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:12,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11912485] [2023-11-21 22:05:12,037 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11912485] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:12,037 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:12,037 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:05:12,037 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [42703813] [2023-11-21 22:05:12,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:12,038 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:05:12,038 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:12,039 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:05:12,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:05:12,039 INFO L87 Difference]: Start difference. First operand 18647 states and 24440 transitions. cyclomatic complexity: 5805 Second operand has 3 states, 3 states have (on average 48.0) internal successors, (144), 3 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:12,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:12,240 INFO L93 Difference]: Finished difference Result 22482 states and 29144 transitions. [2023-11-21 22:05:12,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22482 states and 29144 transitions. [2023-11-21 22:05:12,374 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15160 [2023-11-21 22:05:12,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22482 states to 22482 states and 29144 transitions. [2023-11-21 22:05:12,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15340 [2023-11-21 22:05:12,482 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15340 [2023-11-21 22:05:12,483 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22482 states and 29144 transitions. [2023-11-21 22:05:12,483 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:05:12,483 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22482 states and 29144 transitions. [2023-11-21 22:05:12,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22482 states and 29144 transitions. [2023-11-21 22:05:12,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22482 to 21306. [2023-11-21 22:05:12,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21306 states, 21306 states have (on average 1.3014174410964048) internal successors, (27728), 21305 states have internal predecessors, (27728), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:12,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21306 states to 21306 states and 27728 transitions. [2023-11-21 22:05:12,849 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21306 states and 27728 transitions. [2023-11-21 22:05:12,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:05:12,850 INFO L428 stractBuchiCegarLoop]: Abstraction has 21306 states and 27728 transitions. [2023-11-21 22:05:12,850 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-21 22:05:12,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21306 states and 27728 transitions. [2023-11-21 22:05:12,938 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14376 [2023-11-21 22:05:12,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:12,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:12,940 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:12,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:12,941 INFO L748 eck$LassoCheckResult]: Stem: 254022#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 254023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 254294#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 254295#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 254631#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 254172#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 254173#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 254562#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 254121#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 254122#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 254546#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 254115#L599 assume !(0 == ~M_E~0); 254116#L599-2 assume !(0 == ~T1_E~0); 253478#L604-1 assume !(0 == ~T2_E~0); 253460#L609-1 assume !(0 == ~T3_E~0); 253461#L614-1 assume !(0 == ~T4_E~0); 253760#L619-1 assume !(0 == ~T5_E~0); 253980#L624-1 assume !(0 == ~E_M~0); 254181#L629-1 assume !(0 == ~E_1~0); 253623#L634-1 assume !(0 == ~E_2~0); 253624#L639-1 assume !(0 == ~E_3~0); 254415#L644-1 assume !(0 == ~E_4~0); 254456#L649-1 assume !(0 == ~E_5~0); 253559#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 253560#L292 assume !(1 == ~m_pc~0); 253784#L292-2 is_master_triggered_~__retres1~0#1 := 0; 254054#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 253974#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 253975#L743 assume !(0 != activate_threads_~tmp~1#1); 253682#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 253683#L311 assume !(1 == ~t1_pc~0); 254414#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 254194#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 253548#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 253508#L751 assume !(0 != activate_threads_~tmp___0~0#1); 253509#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 254416#L330 assume !(1 == ~t2_pc~0); 253984#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 253785#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 253786#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 254302#L759 assume !(0 != activate_threads_~tmp___1~0#1); 254627#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 253761#L349 assume !(1 == ~t3_pc~0); 253762#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 254350#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 253462#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 253463#L767 assume !(0 != activate_threads_~tmp___2~0#1); 254610#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 254611#L368 assume !(1 == ~t4_pc~0); 253917#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 253918#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 253735#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 253736#L775 assume !(0 != activate_threads_~tmp___3~0#1); 253483#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 253484#L387 assume !(1 == ~t5_pc~0); 254222#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 254223#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 254744#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 254743#L783 assume !(0 != activate_threads_~tmp___4~0#1); 253712#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253891#L667 assume !(1 == ~M_E~0); 254039#L667-2 assume !(1 == ~T1_E~0); 254432#L672-1 assume !(1 == ~T2_E~0); 253958#L677-1 assume !(1 == ~T3_E~0); 253959#L682-1 assume !(1 == ~T4_E~0); 254372#L687-1 assume !(1 == ~T5_E~0); 254539#L692-1 assume !(1 == ~E_M~0); 254348#L697-1 assume !(1 == ~E_1~0); 254349#L702-1 assume !(1 == ~E_2~0); 254455#L707-1 assume !(1 == ~E_3~0); 254157#L712-1 assume !(1 == ~E_4~0); 254158#L717-1 assume !(1 == ~E_5~0); 254387#L722-1 assume { :end_inline_reset_delta_events } true; 254388#L928-2 assume !false; 255098#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 254714#L574-1 [2023-11-21 22:05:12,941 INFO L750 eck$LassoCheckResult]: Loop: 254714#L574-1 assume !false; 274200#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 270991#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 270988#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 270984#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 270981#L499 assume 0 != eval_~tmp~0#1; 270978#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 270973#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 270971#L507-2 havoc eval_~tmp_ndt_1~0#1; 270969#L504-1 assume !(0 == ~t1_st~0); 270970#L518-1 assume !(0 == ~t2_st~0); 273232#L532-1 assume !(0 == ~t3_st~0); 273229#L546-1 assume !(0 == ~t4_st~0); 254713#L560-1 assume !(0 == ~t5_st~0); 254714#L574-1 [2023-11-21 22:05:12,941 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:12,941 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 1 times [2023-11-21 22:05:12,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:12,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278097210] [2023-11-21 22:05:12,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:12,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:12,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:12,960 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:12,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:12,986 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:12,987 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:12,987 INFO L85 PathProgramCache]: Analyzing trace with hash -2088174432, now seen corresponding path program 1 times [2023-11-21 22:05:12,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:12,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383833413] [2023-11-21 22:05:12,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:12,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:12,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:12,992 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:12,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:12,997 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:12,998 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:12,998 INFO L85 PathProgramCache]: Analyzing trace with hash 672119718, now seen corresponding path program 1 times [2023-11-21 22:05:12,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:13,000 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814570842] [2023-11-21 22:05:13,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:13,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:13,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:13,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:13,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:13,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814570842] [2023-11-21 22:05:13,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814570842] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:13,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:13,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:05:13,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906901749] [2023-11-21 22:05:13,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:13,124 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:13,124 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:05:13,125 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:05:13,125 INFO L87 Difference]: Start difference. First operand 21306 states and 27728 transitions. cyclomatic complexity: 6446 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:13,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:13,315 INFO L93 Difference]: Finished difference Result 36732 states and 47292 transitions. [2023-11-21 22:05:13,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36732 states and 47292 transitions. [2023-11-21 22:05:13,689 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 24124 [2023-11-21 22:05:13,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36732 states to 36732 states and 47292 transitions. [2023-11-21 22:05:13,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25206 [2023-11-21 22:05:13,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25206 [2023-11-21 22:05:13,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36732 states and 47292 transitions. [2023-11-21 22:05:13,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:05:13,982 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36732 states and 47292 transitions. [2023-11-21 22:05:14,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36732 states and 47292 transitions. [2023-11-21 22:05:14,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36732 to 36732. [2023-11-21 22:05:14,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36732 states, 36732 states have (on average 1.2874877491016008) internal successors, (47292), 36731 states have internal predecessors, (47292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:14,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36732 states to 36732 states and 47292 transitions. [2023-11-21 22:05:14,490 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36732 states and 47292 transitions. [2023-11-21 22:05:14,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:05:14,491 INFO L428 stractBuchiCegarLoop]: Abstraction has 36732 states and 47292 transitions. [2023-11-21 22:05:14,491 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-21 22:05:14,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36732 states and 47292 transitions. [2023-11-21 22:05:14,588 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 24124 [2023-11-21 22:05:14,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:14,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:14,589 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:14,589 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:14,589 INFO L748 eck$LassoCheckResult]: Stem: 312058#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 312059#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 312312#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 312313#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 312624#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 312197#L414-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 312198#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 321962#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 321961#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 321960#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 321959#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 321958#L599 assume !(0 == ~M_E~0); 321957#L599-2 assume !(0 == ~T1_E~0); 321956#L604-1 assume !(0 == ~T2_E~0); 321955#L609-1 assume !(0 == ~T3_E~0); 321954#L614-1 assume !(0 == ~T4_E~0); 321953#L619-1 assume !(0 == ~T5_E~0); 321952#L624-1 assume !(0 == ~E_M~0); 321951#L629-1 assume !(0 == ~E_1~0); 321950#L634-1 assume !(0 == ~E_2~0); 321949#L639-1 assume !(0 == ~E_3~0); 321948#L644-1 assume !(0 == ~E_4~0); 321947#L649-1 assume !(0 == ~E_5~0); 321946#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 321945#L292 assume !(1 == ~m_pc~0); 321944#L292-2 is_master_triggered_~__retres1~0#1 := 0; 321943#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 321942#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 321941#L743 assume !(0 != activate_threads_~tmp~1#1); 321940#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 321939#L311 assume !(1 == ~t1_pc~0); 321938#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 321937#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 321936#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 321935#L751 assume !(0 != activate_threads_~tmp___0~0#1); 321934#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 321933#L330 assume !(1 == ~t2_pc~0); 321931#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 321930#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 321929#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 321928#L759 assume !(0 != activate_threads_~tmp___1~0#1); 321927#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 321926#L349 assume !(1 == ~t3_pc~0); 321925#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 321963#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 311508#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 311509#L767 assume !(0 != activate_threads_~tmp___2~0#1); 312606#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 312607#L368 assume !(1 == ~t4_pc~0); 321917#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 321915#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 311780#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 311781#L775 assume !(0 != activate_threads_~tmp___3~0#1); 311529#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 311530#L387 assume !(1 == ~t5_pc~0); 321903#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 321902#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 321901#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 312722#L783 assume !(0 != activate_threads_~tmp___4~0#1); 311756#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 312074#L667 assume !(1 == ~M_E~0); 312075#L667-2 assume !(1 == ~T1_E~0); 312461#L672-1 assume !(1 == ~T2_E~0); 312462#L677-1 assume !(1 == ~T3_E~0); 312396#L682-1 assume !(1 == ~T4_E~0); 312397#L687-1 assume !(1 == ~T5_E~0); 312631#L692-1 assume !(1 == ~E_M~0); 312632#L697-1 assume !(1 == ~E_1~0); 312695#L702-1 assume !(1 == ~E_2~0); 312696#L707-1 assume !(1 == ~E_3~0); 315814#L712-1 assume !(1 == ~E_4~0); 315812#L717-1 assume !(1 == ~E_5~0); 315810#L722-1 assume { :end_inline_reset_delta_events } true; 315807#L928-2 assume !false; 315808#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 326358#L574-1 [2023-11-21 22:05:14,590 INFO L750 eck$LassoCheckResult]: Loop: 326358#L574-1 assume !false; 326354#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 326349#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 326347#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 326345#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 326343#L499 assume 0 != eval_~tmp~0#1; 326341#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 326338#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 326339#L507-2 havoc eval_~tmp_ndt_1~0#1; 327943#L504-1 assume !(0 == ~t1_st~0); 327749#L518-1 assume !(0 == ~t2_st~0); 327746#L532-1 assume !(0 == ~t3_st~0); 327737#L546-1 assume !(0 == ~t4_st~0); 326363#L560-1 assume !(0 == ~t5_st~0); 326358#L574-1 [2023-11-21 22:05:14,590 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:14,590 INFO L85 PathProgramCache]: Analyzing trace with hash 1586209477, now seen corresponding path program 1 times [2023-11-21 22:05:14,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:14,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439089361] [2023-11-21 22:05:14,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:14,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:14,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:14,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:14,617 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:14,617 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439089361] [2023-11-21 22:05:14,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1439089361] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:14,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:14,618 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:05:14,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734394782] [2023-11-21 22:05:14,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:14,618 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:05:14,619 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:14,619 INFO L85 PathProgramCache]: Analyzing trace with hash -2088174432, now seen corresponding path program 2 times [2023-11-21 22:05:14,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:14,619 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873449437] [2023-11-21 22:05:14,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:14,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:14,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:14,625 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:14,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:14,629 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:14,701 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:14,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:05:14,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:05:14,702 INFO L87 Difference]: Start difference. First operand 36732 states and 47292 transitions. cyclomatic complexity: 10602 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:15,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:15,018 INFO L93 Difference]: Finished difference Result 23261 states and 29866 transitions. [2023-11-21 22:05:15,018 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23261 states and 29866 transitions. [2023-11-21 22:05:15,143 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15790 [2023-11-21 22:05:15,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23261 states to 23261 states and 29866 transitions. [2023-11-21 22:05:15,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15974 [2023-11-21 22:05:15,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15974 [2023-11-21 22:05:15,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23261 states and 29866 transitions. [2023-11-21 22:05:15,248 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:05:15,249 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23261 states and 29866 transitions. [2023-11-21 22:05:15,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23261 states and 29866 transitions. [2023-11-21 22:05:15,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23261 to 23261. [2023-11-21 22:05:15,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23261 states, 23261 states have (on average 1.283951678775633) internal successors, (29866), 23260 states have internal predecessors, (29866), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:15,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23261 states to 23261 states and 29866 transitions. [2023-11-21 22:05:15,707 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23261 states and 29866 transitions. [2023-11-21 22:05:15,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:05:15,708 INFO L428 stractBuchiCegarLoop]: Abstraction has 23261 states and 29866 transitions. [2023-11-21 22:05:15,708 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-21 22:05:15,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23261 states and 29866 transitions. [2023-11-21 22:05:15,779 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15790 [2023-11-21 22:05:15,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:15,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:15,780 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:15,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:15,781 INFO L748 eck$LassoCheckResult]: Stem: 372056#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 372057#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 372311#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 372312#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 372626#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 372195#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 372196#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 372562#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 372150#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 372151#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 372552#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 372144#L599 assume !(0 == ~M_E~0); 372145#L599-2 assume !(0 == ~T1_E~0); 371527#L604-1 assume !(0 == ~T2_E~0); 371505#L609-1 assume !(0 == ~T3_E~0); 371506#L614-1 assume !(0 == ~T4_E~0); 371804#L619-1 assume !(0 == ~T5_E~0); 372012#L624-1 assume !(0 == ~E_M~0); 372204#L629-1 assume !(0 == ~E_1~0); 371668#L634-1 assume !(0 == ~E_2~0); 371669#L639-1 assume !(0 == ~E_3~0); 372432#L644-1 assume !(0 == ~E_4~0); 372466#L649-1 assume !(0 == ~E_5~0); 371603#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371604#L292 assume !(1 == ~m_pc~0); 371828#L292-2 is_master_triggered_~__retres1~0#1 := 0; 372083#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 372010#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 372011#L743 assume !(0 != activate_threads_~tmp~1#1); 371727#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 371728#L311 assume !(1 == ~t1_pc~0); 372431#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 372217#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 371592#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 371552#L751 assume !(0 != activate_threads_~tmp___0~0#1); 371553#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 372437#L330 assume !(1 == ~t2_pc~0); 372016#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 371832#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 371833#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 372320#L759 assume !(0 != activate_threads_~tmp___1~0#1); 372620#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 371809#L349 assume !(1 == ~t3_pc~0); 371810#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 372673#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 371517#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 371518#L767 assume !(0 != activate_threads_~tmp___2~0#1); 372600#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372601#L368 assume !(1 == ~t4_pc~0); 371953#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 371954#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 371779#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 371780#L775 assume !(0 != activate_threads_~tmp___3~0#1); 371528#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 371529#L387 assume !(1 == ~t5_pc~0); 372244#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 372245#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 372712#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 372711#L783 assume !(0 != activate_threads_~tmp___4~0#1); 371761#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 371933#L667 assume !(1 == ~M_E~0); 372070#L667-2 assume !(1 == ~T1_E~0); 372453#L672-1 assume !(1 == ~T2_E~0); 371988#L677-1 assume !(1 == ~T3_E~0); 371989#L682-1 assume !(1 == ~T4_E~0); 372394#L687-1 assume !(1 == ~T5_E~0); 372540#L692-1 assume !(1 == ~E_M~0); 372371#L697-1 assume !(1 == ~E_1~0); 372372#L702-1 assume !(1 == ~E_2~0); 372465#L707-1 assume !(1 == ~E_3~0); 372182#L712-1 assume !(1 == ~E_4~0); 372183#L717-1 assume !(1 == ~E_5~0); 372407#L722-1 assume { :end_inline_reset_delta_events } true; 372408#L928-2 assume !false; 376895#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 387835#L574-1 [2023-11-21 22:05:15,781 INFO L750 eck$LassoCheckResult]: Loop: 387835#L574-1 assume !false; 387832#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 387830#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 387828#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 387827#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 387824#L499 assume 0 != eval_~tmp~0#1; 387820#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 387814#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 387815#L507-2 havoc eval_~tmp_ndt_1~0#1; 387857#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 387854#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 387853#L521-2 havoc eval_~tmp_ndt_2~0#1; 387849#L518-1 assume !(0 == ~t2_st~0); 387846#L532-1 assume !(0 == ~t3_st~0); 387841#L546-1 assume !(0 == ~t4_st~0); 387838#L560-1 assume !(0 == ~t5_st~0); 387835#L574-1 [2023-11-21 22:05:15,782 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:15,782 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 2 times [2023-11-21 22:05:15,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:15,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949545200] [2023-11-21 22:05:15,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:15,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:15,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:15,796 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:15,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:15,964 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:15,978 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:15,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1426982192, now seen corresponding path program 1 times [2023-11-21 22:05:15,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:15,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151860194] [2023-11-21 22:05:15,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:15,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:15,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:15,982 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:15,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:15,986 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:15,986 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:15,986 INFO L85 PathProgramCache]: Analyzing trace with hash 1220874326, now seen corresponding path program 1 times [2023-11-21 22:05:15,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:15,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1125652462] [2023-11-21 22:05:15,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:15,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:15,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:16,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:16,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:16,025 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1125652462] [2023-11-21 22:05:16,026 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1125652462] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:16,026 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:16,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:05:16,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481581721] [2023-11-21 22:05:16,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:16,100 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:16,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:05:16,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:05:16,101 INFO L87 Difference]: Start difference. First operand 23261 states and 29866 transitions. cyclomatic complexity: 6629 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:16,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:16,268 INFO L93 Difference]: Finished difference Result 41587 states and 52969 transitions. [2023-11-21 22:05:16,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41587 states and 52969 transitions. [2023-11-21 22:05:16,591 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27902 [2023-11-21 22:05:16,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41587 states to 41587 states and 52969 transitions. [2023-11-21 22:05:16,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28186 [2023-11-21 22:05:16,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28186 [2023-11-21 22:05:16,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41587 states and 52969 transitions. [2023-11-21 22:05:16,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:05:16,795 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41587 states and 52969 transitions. [2023-11-21 22:05:16,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41587 states and 52969 transitions. [2023-11-21 22:05:17,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41587 to 41587. [2023-11-21 22:05:17,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41587 states, 41587 states have (on average 1.2736912977613197) internal successors, (52969), 41586 states have internal predecessors, (52969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:17,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41587 states to 41587 states and 52969 transitions. [2023-11-21 22:05:17,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41587 states and 52969 transitions. [2023-11-21 22:05:17,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:05:17,542 INFO L428 stractBuchiCegarLoop]: Abstraction has 41587 states and 52969 transitions. [2023-11-21 22:05:17,542 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-21 22:05:17,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41587 states and 52969 transitions. [2023-11-21 22:05:17,687 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27902 [2023-11-21 22:05:17,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:17,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:17,689 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:17,689 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:17,689 INFO L748 eck$LassoCheckResult]: Stem: 436914#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 436915#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 437178#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 437179#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 437503#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 437066#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 437067#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 437439#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 437009#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 437010#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 437422#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 437003#L599 assume !(0 == ~M_E~0); 437004#L599-2 assume !(0 == ~T1_E~0); 436379#L604-1 assume !(0 == ~T2_E~0); 436361#L609-1 assume !(0 == ~T3_E~0); 436362#L614-1 assume !(0 == ~T4_E~0); 436659#L619-1 assume !(0 == ~T5_E~0); 436872#L624-1 assume !(0 == ~E_M~0); 437074#L629-1 assume !(0 == ~E_1~0); 436522#L634-1 assume !(0 == ~E_2~0); 436523#L639-1 assume !(0 == ~E_3~0); 437304#L644-1 assume !(0 == ~E_4~0); 437338#L649-1 assume !(0 == ~E_5~0); 436459#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 436460#L292 assume !(1 == ~m_pc~0); 436683#L292-2 is_master_triggered_~__retres1~0#1 := 0; 436945#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 436866#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 436867#L743 assume !(0 != activate_threads_~tmp~1#1); 436581#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 436582#L311 assume !(1 == ~t1_pc~0); 437303#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 437087#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 436448#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 436408#L751 assume !(0 != activate_threads_~tmp___0~0#1); 436409#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 437306#L330 assume !(1 == ~t2_pc~0); 436877#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 436684#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 436685#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 437186#L759 assume !(0 != activate_threads_~tmp___1~0#1); 437494#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 436660#L349 assume !(1 == ~t3_pc~0); 436661#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 437239#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 436363#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 436364#L767 assume !(0 != activate_threads_~tmp___2~0#1); 437478#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 437479#L368 assume !(1 == ~t4_pc~0); 436812#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 436813#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 436634#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 436635#L775 assume !(0 != activate_threads_~tmp___3~0#1); 436384#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 436385#L387 assume !(1 == ~t5_pc~0); 437112#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 437113#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 437602#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 437601#L783 assume !(0 != activate_threads_~tmp___4~0#1); 436610#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 436786#L667 assume !(1 == ~M_E~0); 436931#L667-2 assume !(1 == ~T1_E~0); 437319#L672-1 assume !(1 == ~T2_E~0); 436849#L677-1 assume !(1 == ~T3_E~0); 436850#L682-1 assume !(1 == ~T4_E~0); 437263#L687-1 assume !(1 == ~T5_E~0); 437415#L692-1 assume !(1 == ~E_M~0); 437237#L697-1 assume !(1 == ~E_1~0); 437238#L702-1 assume !(1 == ~E_2~0); 437337#L707-1 assume !(1 == ~E_3~0); 437047#L712-1 assume !(1 == ~E_4~0); 437048#L717-1 assume !(1 == ~E_5~0); 437277#L722-1 assume { :end_inline_reset_delta_events } true; 437278#L928-2 assume !false; 443678#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 469402#L574-1 [2023-11-21 22:05:17,690 INFO L750 eck$LassoCheckResult]: Loop: 469402#L574-1 assume !false; 469400#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 469399#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 469398#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 469397#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 469396#L499 assume 0 != eval_~tmp~0#1; 469393#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 469391#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 469390#L507-2 havoc eval_~tmp_ndt_1~0#1; 464640#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 462614#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 462615#L521-2 havoc eval_~tmp_ndt_2~0#1; 462378#L518-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 462369#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 462361#L535-2 havoc eval_~tmp_ndt_3~0#1; 462353#L532-1 assume !(0 == ~t3_st~0); 462347#L546-1 assume !(0 == ~t4_st~0); 462348#L560-1 assume !(0 == ~t5_st~0); 469402#L574-1 [2023-11-21 22:05:17,690 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:17,691 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 3 times [2023-11-21 22:05:17,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:17,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721152017] [2023-11-21 22:05:17,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:17,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:17,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:17,704 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:17,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:17,732 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:17,733 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:17,733 INFO L85 PathProgramCache]: Analyzing trace with hash 2075640608, now seen corresponding path program 1 times [2023-11-21 22:05:17,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:17,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99683401] [2023-11-21 22:05:17,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:17,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:17,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:17,738 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:17,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:17,744 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:17,745 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:17,745 INFO L85 PathProgramCache]: Analyzing trace with hash -249852122, now seen corresponding path program 1 times [2023-11-21 22:05:17,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:17,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718471056] [2023-11-21 22:05:17,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:17,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:17,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:17,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:17,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:17,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718471056] [2023-11-21 22:05:17,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1718471056] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:17,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:17,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:05:17,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334249041] [2023-11-21 22:05:17,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:18,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:18,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:05:18,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:05:18,071 INFO L87 Difference]: Start difference. First operand 41587 states and 52969 transitions. cyclomatic complexity: 11406 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:18,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:18,380 INFO L93 Difference]: Finished difference Result 76365 states and 96990 transitions. [2023-11-21 22:05:18,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76365 states and 96990 transitions. [2023-11-21 22:05:18,918 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51324 [2023-11-21 22:05:19,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76365 states to 76365 states and 96990 transitions. [2023-11-21 22:05:19,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51808 [2023-11-21 22:05:19,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51808 [2023-11-21 22:05:19,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76365 states and 96990 transitions. [2023-11-21 22:05:19,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:05:19,172 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76365 states and 96990 transitions. [2023-11-21 22:05:19,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76365 states and 96990 transitions. [2023-11-21 22:05:20,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76365 to 72933. [2023-11-21 22:05:20,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72933 states, 72933 states have (on average 1.273168524536218) internal successors, (92856), 72932 states have internal predecessors, (92856), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:20,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72933 states to 72933 states and 92856 transitions. [2023-11-21 22:05:20,560 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72933 states and 92856 transitions. [2023-11-21 22:05:20,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:05:20,582 INFO L428 stractBuchiCegarLoop]: Abstraction has 72933 states and 92856 transitions. [2023-11-21 22:05:20,582 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-21 22:05:20,583 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72933 states and 92856 transitions. [2023-11-21 22:05:20,784 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 49036 [2023-11-21 22:05:20,784 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:20,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:20,785 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:20,786 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:20,786 INFO L748 eck$LassoCheckResult]: Stem: 554880#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 554881#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 555140#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 555141#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 555482#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 555026#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 555027#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 555413#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 554980#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 554981#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 555406#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 554974#L599 assume !(0 == ~M_E~0); 554975#L599-2 assume !(0 == ~T1_E~0); 554343#L604-1 assume !(0 == ~T2_E~0); 554321#L609-1 assume !(0 == ~T3_E~0); 554322#L614-1 assume !(0 == ~T4_E~0); 554618#L619-1 assume !(0 == ~T5_E~0); 554837#L624-1 assume !(0 == ~E_M~0); 555033#L629-1 assume !(0 == ~E_1~0); 554482#L634-1 assume !(0 == ~E_2~0); 554483#L639-1 assume !(0 == ~E_3~0); 555279#L644-1 assume !(0 == ~E_4~0); 555314#L649-1 assume !(0 == ~E_5~0); 554417#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 554418#L292 assume !(1 == ~m_pc~0); 554642#L292-2 is_master_triggered_~__retres1~0#1 := 0; 554913#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 554835#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 554836#L743 assume !(0 != activate_threads_~tmp~1#1); 554541#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 554542#L311 assume !(1 == ~t1_pc~0); 555277#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 555045#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 554406#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 554368#L751 assume !(0 != activate_threads_~tmp___0~0#1); 554369#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 555284#L330 assume !(1 == ~t2_pc~0); 554843#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 554645#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 554646#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 555148#L759 assume !(0 != activate_threads_~tmp___1~0#1); 555478#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 554623#L349 assume !(1 == ~t3_pc~0); 554624#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 555549#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 554333#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 554334#L767 assume !(0 != activate_threads_~tmp___2~0#1); 555458#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 555459#L368 assume !(1 == ~t4_pc~0); 554778#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 554779#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 554594#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 554595#L775 assume !(0 != activate_threads_~tmp___3~0#1); 554344#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 554345#L387 assume !(1 == ~t5_pc~0); 555070#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 555071#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 555607#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 555606#L783 assume !(0 != activate_threads_~tmp___4~0#1); 554577#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 554753#L667 assume !(1 == ~M_E~0); 554895#L667-2 assume !(1 == ~T1_E~0); 555298#L672-1 assume !(1 == ~T2_E~0); 554814#L677-1 assume !(1 == ~T3_E~0); 554815#L682-1 assume !(1 == ~T4_E~0); 555233#L687-1 assume !(1 == ~T5_E~0); 555393#L692-1 assume !(1 == ~E_M~0); 555205#L697-1 assume !(1 == ~E_1~0); 555206#L702-1 assume !(1 == ~E_2~0); 555312#L707-1 assume !(1 == ~E_3~0); 555010#L712-1 assume !(1 == ~E_4~0); 555011#L717-1 assume !(1 == ~E_5~0); 555250#L722-1 assume { :end_inline_reset_delta_events } true; 555251#L928-2 assume !false; 566143#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 593152#L574-1 [2023-11-21 22:05:20,786 INFO L750 eck$LassoCheckResult]: Loop: 593152#L574-1 assume !false; 593142#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 593131#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 593123#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 593117#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 593109#L499 assume 0 != eval_~tmp~0#1; 593102#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 593092#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 593093#L507-2 havoc eval_~tmp_ndt_1~0#1; 594643#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 594638#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 594632#L521-2 havoc eval_~tmp_ndt_2~0#1; 593204#L518-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 593201#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 593199#L535-2 havoc eval_~tmp_ndt_3~0#1; 593198#L532-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 593148#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 593193#L549-2 havoc eval_~tmp_ndt_4~0#1; 593180#L546-1 assume !(0 == ~t4_st~0); 593159#L560-1 assume !(0 == ~t5_st~0); 593152#L574-1 [2023-11-21 22:05:20,787 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:20,787 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 4 times [2023-11-21 22:05:20,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:20,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592899712] [2023-11-21 22:05:20,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:20,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:20,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:20,801 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:20,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:20,824 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:20,825 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:20,825 INFO L85 PathProgramCache]: Analyzing trace with hash 1655561552, now seen corresponding path program 1 times [2023-11-21 22:05:20,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:20,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611074182] [2023-11-21 22:05:20,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:20,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:20,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:20,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:20,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:20,836 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:20,836 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:20,836 INFO L85 PathProgramCache]: Analyzing trace with hash 240041942, now seen corresponding path program 1 times [2023-11-21 22:05:20,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:20,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018924180] [2023-11-21 22:05:20,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:20,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:20,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:20,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:20,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:20,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018924180] [2023-11-21 22:05:20,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018924180] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:20,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:20,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:05:20,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827674743] [2023-11-21 22:05:20,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:20,974 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:20,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:05:20,975 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:05:20,975 INFO L87 Difference]: Start difference. First operand 72933 states and 92856 transitions. cyclomatic complexity: 19947 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:21,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:21,407 INFO L93 Difference]: Finished difference Result 93000 states and 118079 transitions. [2023-11-21 22:05:21,407 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93000 states and 118079 transitions. [2023-11-21 22:05:22,164 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62720 [2023-11-21 22:05:22,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93000 states to 93000 states and 118079 transitions. [2023-11-21 22:05:22,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63236 [2023-11-21 22:05:22,401 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63236 [2023-11-21 22:05:22,401 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93000 states and 118079 transitions. [2023-11-21 22:05:22,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:05:22,426 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93000 states and 118079 transitions. [2023-11-21 22:05:22,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93000 states and 118079 transitions. [2023-11-21 22:05:23,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93000 to 90816. [2023-11-21 22:05:23,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90816 states, 90816 states have (on average 1.2709985024665258) internal successors, (115427), 90815 states have internal predecessors, (115427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:23,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90816 states to 90816 states and 115427 transitions. [2023-11-21 22:05:23,644 INFO L240 hiAutomatonCegarLoop]: Abstraction has 90816 states and 115427 transitions. [2023-11-21 22:05:23,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:05:23,645 INFO L428 stractBuchiCegarLoop]: Abstraction has 90816 states and 115427 transitions. [2023-11-21 22:05:23,645 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-21 22:05:23,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90816 states and 115427 transitions. [2023-11-21 22:05:23,828 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61264 [2023-11-21 22:05:23,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:23,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:23,829 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:23,829 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:23,830 INFO L748 eck$LassoCheckResult]: Stem: 720816#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 720817#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 721079#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 721080#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 721445#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 720964#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 720965#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 721370#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 720921#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 720922#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 721357#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 720915#L599 assume !(0 == ~M_E~0); 720916#L599-2 assume !(0 == ~T1_E~0); 720284#L604-1 assume !(0 == ~T2_E~0); 720262#L609-1 assume !(0 == ~T3_E~0); 720263#L614-1 assume !(0 == ~T4_E~0); 720560#L619-1 assume !(0 == ~T5_E~0); 720774#L624-1 assume !(0 == ~E_M~0); 720971#L629-1 assume !(0 == ~E_1~0); 720424#L634-1 assume !(0 == ~E_2~0); 720425#L639-1 assume !(0 == ~E_3~0); 721217#L644-1 assume !(0 == ~E_4~0); 721259#L649-1 assume !(0 == ~E_5~0); 720358#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 720359#L292 assume !(1 == ~m_pc~0); 720584#L292-2 is_master_triggered_~__retres1~0#1 := 0; 720848#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 720772#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 720773#L743 assume !(0 != activate_threads_~tmp~1#1); 720484#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 720485#L311 assume !(1 == ~t1_pc~0); 721215#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 720984#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 720347#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 720309#L751 assume !(0 != activate_threads_~tmp___0~0#1); 720310#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 721222#L330 assume !(1 == ~t2_pc~0); 720778#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 720588#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 720589#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 721087#L759 assume !(0 != activate_threads_~tmp___1~0#1); 721439#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 720565#L349 assume !(1 == ~t3_pc~0); 720566#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 721490#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 720274#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 720275#L767 assume !(0 != activate_threads_~tmp___2~0#1); 721417#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 721418#L368 assume !(1 == ~t4_pc~0); 720716#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 720717#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 720536#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 720537#L775 assume !(0 != activate_threads_~tmp___3~0#1); 720285#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 720286#L387 assume !(1 == ~t5_pc~0); 721012#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 721013#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 721550#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 721549#L783 assume !(0 != activate_threads_~tmp___4~0#1); 720519#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 720692#L667 assume !(1 == ~M_E~0); 720831#L667-2 assume !(1 == ~T1_E~0); 721236#L672-1 assume !(1 == ~T2_E~0); 720751#L677-1 assume !(1 == ~T3_E~0); 720752#L682-1 assume !(1 == ~T4_E~0); 721171#L687-1 assume !(1 == ~T5_E~0); 721344#L692-1 assume !(1 == ~E_M~0); 721146#L697-1 assume !(1 == ~E_1~0); 721147#L702-1 assume !(1 == ~E_2~0); 721256#L707-1 assume !(1 == ~E_3~0); 720951#L712-1 assume !(1 == ~E_4~0); 720952#L717-1 assume !(1 == ~E_5~0); 721187#L722-1 assume { :end_inline_reset_delta_events } true; 721188#L928-2 assume !false; 745902#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 759878#L574-1 [2023-11-21 22:05:23,830 INFO L750 eck$LassoCheckResult]: Loop: 759878#L574-1 assume !false; 759879#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 759872#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 759873#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 759866#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 759867#L499 assume 0 != eval_~tmp~0#1; 759860#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 759861#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 759853#L507-2 havoc eval_~tmp_ndt_1~0#1; 759854#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 759845#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 759847#L521-2 havoc eval_~tmp_ndt_2~0#1; 759775#L518-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 759772#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 759773#L535-2 havoc eval_~tmp_ndt_3~0#1; 759903#L532-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 759904#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 760269#L549-2 havoc eval_~tmp_ndt_4~0#1; 759893#L546-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 759894#L563 assume !(0 != eval_~tmp_ndt_5~0#1); 759886#L563-2 havoc eval_~tmp_ndt_5~0#1; 759887#L560-1 assume !(0 == ~t5_st~0); 759878#L574-1 [2023-11-21 22:05:23,830 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:23,831 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 5 times [2023-11-21 22:05:23,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:23,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341132530] [2023-11-21 22:05:23,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:23,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:23,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:23,842 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:23,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:23,863 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:23,863 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:23,863 INFO L85 PathProgramCache]: Analyzing trace with hash 1851312544, now seen corresponding path program 1 times [2023-11-21 22:05:23,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:23,864 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405828363] [2023-11-21 22:05:23,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:23,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:23,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:23,868 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:23,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:23,872 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:23,873 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:23,873 INFO L85 PathProgramCache]: Analyzing trace with hash -1253367130, now seen corresponding path program 1 times [2023-11-21 22:05:23,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:23,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621589084] [2023-11-21 22:05:23,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:23,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:23,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:05:23,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:05:23,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:05:23,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621589084] [2023-11-21 22:05:23,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1621589084] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:05:23,914 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:05:23,915 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:05:23,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455373618] [2023-11-21 22:05:23,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:05:24,003 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:05:24,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:05:24,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:05:24,004 INFO L87 Difference]: Start difference. First operand 90816 states and 115427 transitions. cyclomatic complexity: 24635 Second operand has 3 states, 2 states have (on average 48.5) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:24,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:05:24,884 INFO L93 Difference]: Finished difference Result 156969 states and 198989 transitions. [2023-11-21 22:05:24,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156969 states and 198989 transitions. [2023-11-21 22:05:25,402 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 106144 [2023-11-21 22:05:26,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156969 states to 156969 states and 198989 transitions. [2023-11-21 22:05:26,336 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 107092 [2023-11-21 22:05:26,406 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 107092 [2023-11-21 22:05:26,406 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156969 states and 198989 transitions. [2023-11-21 22:05:26,407 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-21 22:05:26,407 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156969 states and 198989 transitions. [2023-11-21 22:05:26,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156969 states and 198989 transitions. [2023-11-21 22:05:28,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156969 to 152829. [2023-11-21 22:05:28,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 152829 states, 152829 states have (on average 1.2749478174953706) internal successors, (194849), 152828 states have internal predecessors, (194849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:05:28,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152829 states to 152829 states and 194849 transitions. [2023-11-21 22:05:28,525 INFO L240 hiAutomatonCegarLoop]: Abstraction has 152829 states and 194849 transitions. [2023-11-21 22:05:28,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:05:28,526 INFO L428 stractBuchiCegarLoop]: Abstraction has 152829 states and 194849 transitions. [2023-11-21 22:05:28,526 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-21 22:05:28,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 152829 states and 194849 transitions. [2023-11-21 22:05:29,603 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 103314 [2023-11-21 22:05:29,603 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:05:29,603 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:05:29,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:29,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:05:29,613 INFO L748 eck$LassoCheckResult]: Stem: 968603#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 968604#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 968877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 968878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 969261#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 968756#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 968757#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 969186#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 968703#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 968704#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 969168#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 968697#L599 assume !(0 == ~M_E~0); 968698#L599-2 assume !(0 == ~T1_E~0); 968073#L604-1 assume !(0 == ~T2_E~0); 968055#L609-1 assume !(0 == ~T3_E~0); 968056#L614-1 assume !(0 == ~T4_E~0); 968352#L619-1 assume !(0 == ~T5_E~0); 968560#L624-1 assume !(0 == ~E_M~0); 968765#L629-1 assume !(0 == ~E_1~0); 968216#L634-1 assume !(0 == ~E_2~0); 968217#L639-1 assume !(0 == ~E_3~0); 969014#L644-1 assume !(0 == ~E_4~0); 969053#L649-1 assume !(0 == ~E_5~0); 968151#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 968152#L292 assume !(1 == ~m_pc~0); 968376#L292-2 is_master_triggered_~__retres1~0#1 := 0; 968636#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 968554#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 968555#L743 assume !(0 != activate_threads_~tmp~1#1); 968275#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 968276#L311 assume !(1 == ~t1_pc~0); 969013#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 968777#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 968140#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 968102#L751 assume !(0 != activate_threads_~tmp___0~0#1); 968103#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 969018#L330 assume !(1 == ~t2_pc~0); 968565#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 968377#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 968378#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 968885#L759 assume !(0 != activate_threads_~tmp___1~0#1); 969252#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 968353#L349 assume !(1 == ~t3_pc~0); 968354#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 968950#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 968057#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 968058#L767 assume !(0 != activate_threads_~tmp___2~0#1); 969233#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 969234#L368 assume !(1 == ~t4_pc~0); 968499#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 968500#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 968327#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 968328#L775 assume !(0 != activate_threads_~tmp___3~0#1); 968078#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 968079#L387 assume !(1 == ~t5_pc~0); 968803#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 968804#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 969405#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 969404#L783 assume !(0 != activate_threads_~tmp___4~0#1); 968303#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 968475#L667 assume !(1 == ~M_E~0); 968621#L667-2 assume !(1 == ~T1_E~0); 969030#L672-1 assume !(1 == ~T2_E~0); 968538#L677-1 assume !(1 == ~T3_E~0); 968539#L682-1 assume !(1 == ~T4_E~0); 968972#L687-1 assume !(1 == ~T5_E~0); 969162#L692-1 assume !(1 == ~E_M~0); 968948#L697-1 assume !(1 == ~E_1~0); 968949#L702-1 assume !(1 == ~E_2~0); 969052#L707-1 assume !(1 == ~E_3~0); 968740#L712-1 assume !(1 == ~E_4~0); 968741#L717-1 assume !(1 == ~E_5~0); 968985#L722-1 assume { :end_inline_reset_delta_events } true; 968986#L928-2 assume !false; 987745#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1063331#L574-1 [2023-11-21 22:05:29,613 INFO L750 eck$LassoCheckResult]: Loop: 1063331#L574-1 assume !false; 1063329#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1063326#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1063324#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1063322#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1063320#L499 assume 0 != eval_~tmp~0#1; 1063318#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1063315#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 1063313#L507-2 havoc eval_~tmp_ndt_1~0#1; 1063311#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1062880#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 1062876#L521-2 havoc eval_~tmp_ndt_2~0#1; 1062874#L518-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1062477#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 1062872#L535-2 havoc eval_~tmp_ndt_3~0#1; 1063160#L532-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1063142#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 1063158#L549-2 havoc eval_~tmp_ndt_4~0#1; 1063347#L546-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1063344#L563 assume !(0 != eval_~tmp_ndt_5~0#1); 1063342#L563-2 havoc eval_~tmp_ndt_5~0#1; 1063340#L560-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1062171#L577 assume !(0 != eval_~tmp_ndt_6~0#1); 1063333#L577-2 havoc eval_~tmp_ndt_6~0#1; 1063331#L574-1 [2023-11-21 22:05:29,615 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:29,615 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 6 times [2023-11-21 22:05:29,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:29,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976673909] [2023-11-21 22:05:29,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:29,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:29,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:29,668 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:29,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:29,704 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:29,704 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:29,704 INFO L85 PathProgramCache]: Analyzing trace with hash 994770896, now seen corresponding path program 1 times [2023-11-21 22:05:29,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:29,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469295565] [2023-11-21 22:05:29,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:29,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:29,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:29,725 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:29,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:29,730 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:29,730 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:05:29,731 INFO L85 PathProgramCache]: Analyzing trace with hash -1895092394, now seen corresponding path program 1 times [2023-11-21 22:05:29,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:05:29,731 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800338878] [2023-11-21 22:05:29,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:05:29,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:05:29,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:29,768 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:29,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:29,827 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-21 22:05:31,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:31,620 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-21 22:05:31,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-21 22:05:31,882 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.11 10:05:31 BoogieIcfgContainer [2023-11-21 22:05:31,883 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-21 22:05:31,883 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-21 22:05:31,883 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-21 22:05:31,884 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-21 22:05:31,884 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:04:55" (3/4) ... [2023-11-21 22:05:31,886 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-21 22:05:32,029 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/witness.graphml [2023-11-21 22:05:32,030 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-21 22:05:32,031 INFO L158 Benchmark]: Toolchain (without parser) took 38529.35ms. Allocated memory was 132.1MB in the beginning and 11.5GB in the end (delta: 11.4GB). Free memory was 98.3MB in the beginning and 9.5GB in the end (delta: -9.4GB). Peak memory consumption was 2.0GB. Max. memory is 16.1GB. [2023-11-21 22:05:32,031 INFO L158 Benchmark]: CDTParser took 0.29ms. Allocated memory is still 132.1MB. Free memory is still 104.7MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-21 22:05:32,031 INFO L158 Benchmark]: CACSL2BoogieTranslator took 488.26ms. Allocated memory is still 132.1MB. Free memory was 98.3MB in the beginning and 81.8MB in the end (delta: 16.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-21 22:05:32,032 INFO L158 Benchmark]: Boogie Procedure Inliner took 77.54ms. Allocated memory is still 132.1MB. Free memory was 81.8MB in the beginning and 76.9MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-21 22:05:32,032 INFO L158 Benchmark]: Boogie Preprocessor took 126.14ms. Allocated memory is still 132.1MB. Free memory was 76.9MB in the beginning and 70.1MB in the end (delta: 6.8MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-21 22:05:32,033 INFO L158 Benchmark]: RCFGBuilder took 1587.66ms. Allocated memory was 132.1MB in the beginning and 182.5MB in the end (delta: 50.3MB). Free memory was 70.1MB in the beginning and 110.0MB in the end (delta: -39.9MB). Peak memory consumption was 30.9MB. Max. memory is 16.1GB. [2023-11-21 22:05:32,033 INFO L158 Benchmark]: BuchiAutomizer took 36097.26ms. Allocated memory was 182.5MB in the beginning and 11.5GB in the end (delta: 11.4GB). Free memory was 110.0MB in the beginning and 9.5GB in the end (delta: -9.4GB). Peak memory consumption was 2.0GB. Max. memory is 16.1GB. [2023-11-21 22:05:32,034 INFO L158 Benchmark]: Witness Printer took 146.80ms. Allocated memory is still 11.5GB. Free memory was 9.5GB in the beginning and 9.5GB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2023-11-21 22:05:32,037 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29ms. Allocated memory is still 132.1MB. Free memory is still 104.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 488.26ms. Allocated memory is still 132.1MB. Free memory was 98.3MB in the beginning and 81.8MB in the end (delta: 16.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 77.54ms. Allocated memory is still 132.1MB. Free memory was 81.8MB in the beginning and 76.9MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 126.14ms. Allocated memory is still 132.1MB. Free memory was 76.9MB in the beginning and 70.1MB in the end (delta: 6.8MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 1587.66ms. Allocated memory was 132.1MB in the beginning and 182.5MB in the end (delta: 50.3MB). Free memory was 70.1MB in the beginning and 110.0MB in the end (delta: -39.9MB). Peak memory consumption was 30.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 36097.26ms. Allocated memory was 182.5MB in the beginning and 11.5GB in the end (delta: 11.4GB). Free memory was 110.0MB in the beginning and 9.5GB in the end (delta: -9.4GB). Peak memory consumption was 2.0GB. Max. memory is 16.1GB. * Witness Printer took 146.80ms. Allocated memory is still 11.5GB. Free memory was 9.5GB in the beginning and 9.5GB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 30 terminating modules (29 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function ((-1 * E_3) + 1) and consists of 3 locations. 29 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 152829 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 35.8s and 30 iterations. TraceHistogramMax:2. Analysis of lassos took 11.2s. Construction of modules took 1.2s. Büchi inclusion checks took 20.3s. Highest rank in rank-based complementation 3. Minimization of det autom 21. Minimization of nondet autom 9. Automata minimization 9.5s AutomataMinimizationTime, 30 MinimizatonAttempts, 38701 StatesRemovedByMinimization, 19 NontrivialMinimizations. Non-live state removal took 6.1s Buchi closure took 0.3s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 24216 SdHoareTripleChecker+Valid, 1.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 24215 mSDsluCounter, 56140 SdHoareTripleChecker+Invalid, 1.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 28821 mSDsCounter, 422 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1312 IncrementalHoareTripleChecker+Invalid, 1734 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 422 mSolverCounterUnsat, 27319 mSDtfsCounter, 1312 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI9 SFLT0 conc5 concLT1 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital167 mio100 ax100 hnf100 lsp5 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 41ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 4 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.2s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 494]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L973] int __retres1 ; [L977] CALL init_model() [L884] m_i = 1 [L885] t1_i = 1 [L886] t2_i = 1 [L887] t3_i = 1 [L888] t4_i = 1 [L889] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L977] RET init_model() [L978] CALL start_simulation() [L914] int kernel_st ; [L915] int tmp ; [L916] int tmp___0 ; [L920] kernel_st = 0 [L921] FCALL update_channels() [L922] CALL init_threads() [L414] COND TRUE m_i == 1 [L415] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L419] COND TRUE t1_i == 1 [L420] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L424] COND TRUE t2_i == 1 [L425] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L429] COND TRUE t3_i == 1 [L430] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L434] COND TRUE t4_i == 1 [L435] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L439] COND TRUE t5_i == 1 [L440] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L922] RET init_threads() [L923] CALL fire_delta_events() [L599] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L604] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L609] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L614] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L619] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L624] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L629] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L634] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L639] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L644] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L649] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L654] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L923] RET fire_delta_events() [L924] CALL activate_threads() [L732] int tmp ; [L733] int tmp___0 ; [L734] int tmp___1 ; [L735] int tmp___2 ; [L736] int tmp___3 ; [L737] int tmp___4 ; [L741] CALL, EXPR is_master_triggered() [L289] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L292] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L302] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L741] RET, EXPR is_master_triggered() [L741] tmp = is_master_triggered() [L743] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L749] CALL, EXPR is_transmit1_triggered() [L308] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L311] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L321] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] RET, EXPR is_transmit1_triggered() [L749] tmp___0 = is_transmit1_triggered() [L751] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L757] CALL, EXPR is_transmit2_triggered() [L327] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L330] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L340] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] RET, EXPR is_transmit2_triggered() [L757] tmp___1 = is_transmit2_triggered() [L759] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L765] CALL, EXPR is_transmit3_triggered() [L346] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L349] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L359] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] RET, EXPR is_transmit3_triggered() [L765] tmp___2 = is_transmit3_triggered() [L767] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L773] CALL, EXPR is_transmit4_triggered() [L365] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L368] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L378] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] RET, EXPR is_transmit4_triggered() [L773] tmp___3 = is_transmit4_triggered() [L775] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L781] CALL, EXPR is_transmit5_triggered() [L384] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L387] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L397] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] RET, EXPR is_transmit5_triggered() [L781] tmp___4 = is_transmit5_triggered() [L783] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L924] RET activate_threads() [L925] CALL reset_delta_events() [L667] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L672] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L677] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L682] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L687] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L692] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L697] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L702] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L707] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L712] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L717] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L722] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L925] RET reset_delta_events() [L928] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L931] kernel_st = 1 [L932] CALL eval() [L490] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L494] COND TRUE 1 [L497] CALL, EXPR exists_runnable_thread() [L449] int __retres1 ; [L452] COND TRUE m_st == 0 [L453] __retres1 = 1 [L485] return (__retres1); [L497] RET, EXPR exists_runnable_thread() [L497] tmp = exists_runnable_thread() [L499] COND TRUE \read(tmp) [L504] COND TRUE m_st == 0 [L505] int tmp_ndt_1; [L506] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L507] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L504-L515] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L518] COND TRUE t1_st == 0 [L519] int tmp_ndt_2; [L520] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L521] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L518-L529] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L532] COND TRUE t2_st == 0 [L533] int tmp_ndt_3; [L534] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L535] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L532-L543] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L546] COND TRUE t3_st == 0 [L547] int tmp_ndt_4; [L548] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L549] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L546-L557] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L560] COND TRUE t4_st == 0 [L561] int tmp_ndt_5; [L562] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L563] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L560-L571] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L574] COND TRUE t5_st == 0 [L575] int tmp_ndt_6; [L576] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L577] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L574-L585] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 494]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L973] int __retres1 ; [L977] CALL init_model() [L884] m_i = 1 [L885] t1_i = 1 [L886] t2_i = 1 [L887] t3_i = 1 [L888] t4_i = 1 [L889] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L977] RET init_model() [L978] CALL start_simulation() [L914] int kernel_st ; [L915] int tmp ; [L916] int tmp___0 ; [L920] kernel_st = 0 [L921] FCALL update_channels() [L922] CALL init_threads() [L414] COND TRUE m_i == 1 [L415] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L419] COND TRUE t1_i == 1 [L420] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L424] COND TRUE t2_i == 1 [L425] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L429] COND TRUE t3_i == 1 [L430] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L434] COND TRUE t4_i == 1 [L435] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L439] COND TRUE t5_i == 1 [L440] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L922] RET init_threads() [L923] CALL fire_delta_events() [L599] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L604] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L609] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L614] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L619] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L624] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L629] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L634] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L639] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L644] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L649] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L654] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L923] RET fire_delta_events() [L924] CALL activate_threads() [L732] int tmp ; [L733] int tmp___0 ; [L734] int tmp___1 ; [L735] int tmp___2 ; [L736] int tmp___3 ; [L737] int tmp___4 ; [L741] CALL, EXPR is_master_triggered() [L289] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L292] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L302] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L741] RET, EXPR is_master_triggered() [L741] tmp = is_master_triggered() [L743] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L749] CALL, EXPR is_transmit1_triggered() [L308] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L311] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L321] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] RET, EXPR is_transmit1_triggered() [L749] tmp___0 = is_transmit1_triggered() [L751] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L757] CALL, EXPR is_transmit2_triggered() [L327] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L330] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L340] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] RET, EXPR is_transmit2_triggered() [L757] tmp___1 = is_transmit2_triggered() [L759] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L765] CALL, EXPR is_transmit3_triggered() [L346] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L349] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L359] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] RET, EXPR is_transmit3_triggered() [L765] tmp___2 = is_transmit3_triggered() [L767] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L773] CALL, EXPR is_transmit4_triggered() [L365] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L368] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L378] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] RET, EXPR is_transmit4_triggered() [L773] tmp___3 = is_transmit4_triggered() [L775] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L781] CALL, EXPR is_transmit5_triggered() [L384] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L387] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L397] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] RET, EXPR is_transmit5_triggered() [L781] tmp___4 = is_transmit5_triggered() [L783] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L924] RET activate_threads() [L925] CALL reset_delta_events() [L667] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L672] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L677] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L682] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L687] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L692] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L697] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L702] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L707] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L712] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L717] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L722] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L925] RET reset_delta_events() [L928] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L931] kernel_st = 1 [L932] CALL eval() [L490] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L494] COND TRUE 1 [L497] CALL, EXPR exists_runnable_thread() [L449] int __retres1 ; [L452] COND TRUE m_st == 0 [L453] __retres1 = 1 [L485] return (__retres1); [L497] RET, EXPR exists_runnable_thread() [L497] tmp = exists_runnable_thread() [L499] COND TRUE \read(tmp) [L504] COND TRUE m_st == 0 [L505] int tmp_ndt_1; [L506] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L507] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L504-L515] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L518] COND TRUE t1_st == 0 [L519] int tmp_ndt_2; [L520] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L521] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L518-L529] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L532] COND TRUE t2_st == 0 [L533] int tmp_ndt_3; [L534] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L535] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L532-L543] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L546] COND TRUE t3_st == 0 [L547] int tmp_ndt_4; [L548] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L549] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L546-L557] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L560] COND TRUE t4_st == 0 [L561] int tmp_ndt_5; [L562] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L563] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L560-L571] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L574] COND TRUE t5_st == 0 [L575] int tmp_ndt_6; [L576] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L577] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L574-L585] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-21 22:05:32,243 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_39c13438-7549-4c71-93fa-5447f7b6449a/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)