./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.11.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 527bcce2 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.11.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 79f20a4b12634e812af836a5fe92e9d987e7766e2c28337c49504608346f2347 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-527bcce [2023-11-21 21:03:24,084 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-21 21:03:24,160 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-21 21:03:24,166 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-21 21:03:24,167 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-21 21:03:24,196 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-21 21:03:24,197 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-21 21:03:24,197 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-21 21:03:24,198 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-21 21:03:24,199 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-21 21:03:24,200 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-21 21:03:24,200 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-21 21:03:24,201 INFO L153 SettingsManager]: * Use SBE=true [2023-11-21 21:03:24,201 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-21 21:03:24,202 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-21 21:03:24,202 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-21 21:03:24,203 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-21 21:03:24,203 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-21 21:03:24,204 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-21 21:03:24,204 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-21 21:03:24,205 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-21 21:03:24,205 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-21 21:03:24,206 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-21 21:03:24,206 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-21 21:03:24,207 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-21 21:03:24,207 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-21 21:03:24,208 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-21 21:03:24,208 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-21 21:03:24,208 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-21 21:03:24,209 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-21 21:03:24,209 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-21 21:03:24,210 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-21 21:03:24,210 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-21 21:03:24,210 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-21 21:03:24,211 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-21 21:03:24,211 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-21 21:03:24,211 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-21 21:03:24,212 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-21 21:03:24,212 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 79f20a4b12634e812af836a5fe92e9d987e7766e2c28337c49504608346f2347 [2023-11-21 21:03:24,445 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-21 21:03:24,483 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-21 21:03:24,486 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-21 21:03:24,488 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-21 21:03:24,488 INFO L274 PluginConnector]: CDTParser initialized [2023-11-21 21:03:24,490 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/../../sv-benchmarks/c/systemc/token_ring.11.cil-1.c [2023-11-21 21:03:27,594 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-21 21:03:27,826 INFO L384 CDTParser]: Found 1 translation units. [2023-11-21 21:03:27,826 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/sv-benchmarks/c/systemc/token_ring.11.cil-1.c [2023-11-21 21:03:27,845 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/data/2b781436e/0905de536d6447b1adc200685f0222b8/FLAG873601477 [2023-11-21 21:03:27,873 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/data/2b781436e/0905de536d6447b1adc200685f0222b8 [2023-11-21 21:03:27,877 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-21 21:03:27,879 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-21 21:03:27,881 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-21 21:03:27,881 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-21 21:03:27,893 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-21 21:03:27,894 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 09:03:27" (1/1) ... [2023-11-21 21:03:27,895 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@48141a86 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:27, skipping insertion in model container [2023-11-21 21:03:27,896 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 09:03:27" (1/1) ... [2023-11-21 21:03:27,956 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-21 21:03:28,260 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 21:03:28,276 INFO L202 MainTranslator]: Completed pre-run [2023-11-21 21:03:28,359 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 21:03:28,390 INFO L206 MainTranslator]: Completed translation [2023-11-21 21:03:28,390 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28 WrapperNode [2023-11-21 21:03:28,390 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-21 21:03:28,391 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-21 21:03:28,392 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-21 21:03:28,392 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-21 21:03:28,399 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,414 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,554 INFO L138 Inliner]: procedures = 50, calls = 66, calls flagged for inlining = 61, calls inlined = 241, statements flattened = 3684 [2023-11-21 21:03:28,555 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-21 21:03:28,555 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-21 21:03:28,556 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-21 21:03:28,556 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-21 21:03:28,567 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,568 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,592 INFO L184 PluginConnector]: Executing the observer HeapSplitter from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,653 INFO L187 HeapSplitter]: Split 2 memory accesses to 1 slices as follows [2] [2023-11-21 21:03:28,668 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,668 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,739 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,787 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,798 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,816 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,829 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-21 21:03:28,830 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-21 21:03:28,830 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-21 21:03:28,831 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-21 21:03:28,831 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (1/1) ... [2023-11-21 21:03:28,837 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 21:03:28,849 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 21:03:28,862 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 21:03:28,890 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a26f6beb-33bc-4f3f-8fed-8bc4929a107d/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-21 21:03:28,913 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-21 21:03:28,914 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-21 21:03:28,914 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-21 21:03:28,914 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-21 21:03:29,095 INFO L240 CfgBuilder]: Building ICFG [2023-11-21 21:03:29,097 INFO L266 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-21 21:03:31,424 INFO L281 CfgBuilder]: Performing block encoding [2023-11-21 21:03:31,463 INFO L303 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-21 21:03:31,464 INFO L308 CfgBuilder]: Removed 14 assume(true) statements. [2023-11-21 21:03:31,466 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 09:03:31 BoogieIcfgContainer [2023-11-21 21:03:31,466 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-21 21:03:31,467 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-21 21:03:31,467 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-21 21:03:31,471 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-21 21:03:31,472 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 21:03:31,472 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.11 09:03:27" (1/3) ... [2023-11-21 21:03:31,473 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2ae36de0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 09:03:31, skipping insertion in model container [2023-11-21 21:03:31,474 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 21:03:31,474 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 09:03:28" (2/3) ... [2023-11-21 21:03:31,474 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2ae36de0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 09:03:31, skipping insertion in model container [2023-11-21 21:03:31,474 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 21:03:31,474 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 09:03:31" (3/3) ... [2023-11-21 21:03:31,476 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-1.c [2023-11-21 21:03:31,569 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-21 21:03:31,569 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-21 21:03:31,569 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-21 21:03:31,570 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-21 21:03:31,571 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-21 21:03:31,571 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-21 21:03:31,571 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-21 21:03:31,571 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-21 21:03:31,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1593 states, 1592 states have (on average 1.4987437185929648) internal successors, (2386), 1592 states have internal predecessors, (2386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:31,688 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1438 [2023-11-21 21:03:31,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:31,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:31,706 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:31,706 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:31,706 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-21 21:03:31,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1593 states, 1592 states have (on average 1.4987437185929648) internal successors, (2386), 1592 states have internal predecessors, (2386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:31,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1438 [2023-11-21 21:03:31,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:31,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:31,761 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:31,762 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:31,773 INFO L748 eck$LassoCheckResult]: Stem: 114#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1514#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 539#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1511#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 661#L792true assume !(1 == ~m_i~0);~m_st~0 := 2; 1006#L792-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 48#L797-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1428#L802-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1314#L807-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 637#L812-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1140#L817-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 931#L822-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1074#L827-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1373#L832-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1219#L837-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1226#L842-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1007#L847-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 800#L1121true assume !(0 == ~M_E~0); 586#L1121-2true assume !(0 == ~T1_E~0); 182#L1126-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 274#L1131-1true assume !(0 == ~T3_E~0); 335#L1136-1true assume !(0 == ~T4_E~0); 484#L1141-1true assume !(0 == ~T5_E~0); 1266#L1146-1true assume !(0 == ~T6_E~0); 734#L1151-1true assume !(0 == ~T7_E~0); 371#L1156-1true assume !(0 == ~T8_E~0); 41#L1161-1true assume !(0 == ~T9_E~0); 866#L1166-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 145#L1171-1true assume !(0 == ~T11_E~0); 749#L1176-1true assume !(0 == ~E_M~0); 889#L1181-1true assume !(0 == ~E_1~0); 1345#L1186-1true assume !(0 == ~E_2~0); 948#L1191-1true assume !(0 == ~E_3~0); 161#L1196-1true assume !(0 == ~E_4~0); 1356#L1201-1true assume !(0 == ~E_5~0); 1435#L1206-1true assume 0 == ~E_6~0;~E_6~0 := 1; 1008#L1211-1true assume !(0 == ~E_7~0); 1160#L1216-1true assume !(0 == ~E_8~0); 235#L1221-1true assume !(0 == ~E_9~0); 1091#L1226-1true assume !(0 == ~E_10~0); 89#L1231-1true assume !(0 == ~E_11~0); 1238#L1236-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 750#L556true assume 1 == ~m_pc~0; 763#L557true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28#L567true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 461#is_master_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1141#L1391true assume !(0 != activate_threads_~tmp~1#1); 922#L1391-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1088#L575true assume !(1 == ~t1_pc~0); 7#L575-2true is_transmit1_triggered_~__retres1~1#1 := 0; 74#L586true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 802#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 242#L1399true assume !(0 != activate_threads_~tmp___0~0#1); 219#L1399-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 722#L594true assume 1 == ~t2_pc~0; 184#L595true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1540#L605true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 183#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36#L1407true assume !(0 != activate_threads_~tmp___1~0#1); 69#L1407-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1210#L613true assume !(1 == ~t3_pc~0); 1558#L613-2true is_transmit3_triggered_~__retres1~3#1 := 0; 309#L624true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 779#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 483#L1415true assume !(0 != activate_threads_~tmp___2~0#1); 1084#L1415-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 295#L632true assume 1 == ~t4_pc~0; 647#L633true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 801#L643true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1510#L1423true assume !(0 != activate_threads_~tmp___3~0#1); 754#L1423-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 533#L651true assume 1 == ~t5_pc~0; 972#L652true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 128#L662true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1281#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 459#L1431true assume !(0 != activate_threads_~tmp___4~0#1); 135#L1431-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1118#L670true assume !(1 == ~t6_pc~0); 979#L670-2true is_transmit6_triggered_~__retres1~6#1 := 0; 326#L681true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 178#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1316#L1439true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 511#L1439-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1339#L689true assume 1 == ~t7_pc~0; 1533#L690true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 596#L700true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1534#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1005#L1447true assume !(0 != activate_threads_~tmp___6~0#1); 443#L1447-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1193#L708true assume !(1 == ~t8_pc~0); 181#L708-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1137#L719true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1241#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1115#L1455true assume !(0 != activate_threads_~tmp___7~0#1); 212#L1455-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 281#L727true assume 1 == ~t9_pc~0; 1229#L728true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1426#L738true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 206#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1448#L1463true assume !(0 != activate_threads_~tmp___8~0#1); 1318#L1463-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 240#L746true assume !(1 == ~t10_pc~0); 710#L746-2true is_transmit10_triggered_~__retres1~10#1 := 0; 826#L757true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1057#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1130#L1471true assume !(0 != activate_threads_~tmp___9~0#1); 926#L1471-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 340#L765true assume 1 == ~t11_pc~0; 1380#L766true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1403#L776true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1159#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 977#L1479true assume !(0 != activate_threads_~tmp___10~0#1); 1170#L1479-2true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1111#L1249true assume !(1 == ~M_E~0); 651#L1249-2true assume !(1 == ~T1_E~0); 395#L1254-1true assume !(1 == ~T2_E~0); 34#L1259-1true assume !(1 == ~T3_E~0); 25#L1264-1true assume !(1 == ~T4_E~0); 1589#L1269-1true assume !(1 == ~T5_E~0); 1519#L1274-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1249#L1279-1true assume !(1 == ~T7_E~0); 122#L1284-1true assume !(1 == ~T8_E~0); 1381#L1289-1true assume !(1 == ~T9_E~0); 426#L1294-1true assume !(1 == ~T10_E~0); 433#L1299-1true assume !(1 == ~T11_E~0); 1444#L1304-1true assume !(1 == ~E_M~0); 1475#L1309-1true assume !(1 == ~E_1~0); 1451#L1314-1true assume 1 == ~E_2~0;~E_2~0 := 2; 99#L1319-1true assume !(1 == ~E_3~0); 849#L1324-1true assume !(1 == ~E_4~0); 158#L1329-1true assume !(1 == ~E_5~0); 1053#L1334-1true assume !(1 == ~E_6~0); 1409#L1339-1true assume !(1 == ~E_7~0); 1173#L1344-1true assume !(1 == ~E_8~0); 1539#L1349-1true assume !(1 == ~E_9~0); 522#L1354-1true assume 1 == ~E_10~0;~E_10~0 := 2; 853#L1359-1true assume !(1 == ~E_11~0); 1387#L1364-1true assume { :end_inline_reset_delta_events } true; 204#L1690-2true [2023-11-21 21:03:31,776 INFO L750 eck$LassoCheckResult]: Loop: 204#L1690-2true assume !false; 876#L1691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1384#L1096-1true assume !true; 422#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 260#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 324#L1121-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1532#L1121-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1327#L1126-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 457#L1131-3true assume !(0 == ~T3_E~0); 1543#L1136-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1524#L1141-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 756#L1146-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 180#L1151-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1166#L1156-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1395#L1161-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 587#L1166-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1260#L1171-3true assume !(0 == ~T11_E~0); 618#L1176-3true assume 0 == ~E_M~0;~E_M~0 := 1; 202#L1181-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1227#L1186-3true assume 0 == ~E_2~0;~E_2~0 := 1; 688#L1191-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1215#L1196-3true assume 0 == ~E_4~0;~E_4~0 := 1; 901#L1201-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1438#L1206-3true assume 0 == ~E_6~0;~E_6~0 := 1; 599#L1211-3true assume !(0 == ~E_7~0); 155#L1216-3true assume 0 == ~E_8~0;~E_8~0 := 1; 402#L1221-3true assume 0 == ~E_9~0;~E_9~0 := 1; 874#L1226-3true assume 0 == ~E_10~0;~E_10~0 := 1; 187#L1231-3true assume 0 == ~E_11~0;~E_11~0 := 1; 315#L1236-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1466#L556-39true assume !(1 == ~m_pc~0); 1107#L556-41true is_master_triggered_~__retres1~0#1 := 0; 666#L567-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 557#is_master_triggered_returnLabel#14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 344#L1391-39true assume !(0 != activate_threads_~tmp~1#1); 1308#L1391-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 628#L575-39true assume !(1 == ~t1_pc~0); 1437#L575-41true is_transmit1_triggered_~__retres1~1#1 := 0; 904#L586-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1396#is_transmit1_triggered_returnLabel#14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1493#L1399-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 610#L1399-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 806#L594-39true assume !(1 == ~t2_pc~0); 1197#L594-41true is_transmit2_triggered_~__retres1~2#1 := 0; 612#L605-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 381#is_transmit2_triggered_returnLabel#14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1119#L1407-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 275#L1407-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1080#L613-39true assume 1 == ~t3_pc~0; 1482#L614-13true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14#L624-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1568#is_transmit3_triggered_returnLabel#14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 814#L1415-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67#L1415-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1506#L632-39true assume 1 == ~t4_pc~0; 1028#L633-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 379#L643-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 491#is_transmit4_triggered_returnLabel#14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1087#L1423-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1024#L1423-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 192#L651-39true assume 1 == ~t5_pc~0; 1574#L652-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1002#L662-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 507#is_transmit5_triggered_returnLabel#14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1277#L1431-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1516#L1431-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1383#L670-39true assume 1 == ~t6_pc~0; 1491#L671-13true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37#L681-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1473#is_transmit6_triggered_returnLabel#14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 482#L1439-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 400#L1439-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 556#L689-39true assume !(1 == ~t7_pc~0); 486#L689-41true is_transmit7_triggered_~__retres1~7#1 := 0; 495#L700-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 795#is_transmit7_triggered_returnLabel#14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1481#L1447-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 129#L1447-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 738#L708-39true assume !(1 == ~t8_pc~0); 493#L708-41true is_transmit8_triggered_~__retres1~8#1 := 0; 435#L719-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 891#is_transmit8_triggered_returnLabel#14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1181#L1455-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 764#L1455-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 362#L727-39true assume 1 == ~t9_pc~0; 1517#L728-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 226#L738-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50#is_transmit9_triggered_returnLabel#14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1152#L1463-39true assume !(0 != activate_threads_~tmp___8~0#1); 809#L1463-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 962#L746-39true assume !(1 == ~t10_pc~0); 1076#L746-41true is_transmit10_triggered_~__retres1~10#1 := 0; 1290#L757-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1150#is_transmit10_triggered_returnLabel#14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 543#L1471-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 968#L1471-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1469#L765-39true assume 1 == ~t11_pc~0; 39#L766-13true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1199#L776-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 523#is_transmit11_triggered_returnLabel#14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 203#L1479-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 717#L1479-41true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 581#L1249-3true assume 1 == ~M_E~0;~M_E~0 := 2; 111#L1249-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1360#L1254-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1164#L1259-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 682#L1264-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 91#L1269-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1429#L1274-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1246#L1279-3true assume !(1 == ~T7_E~0); 349#L1284-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1293#L1289-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 343#L1294-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1470#L1299-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 519#L1304-3true assume 1 == ~E_M~0;~E_M~0 := 2; 868#L1309-3true assume 1 == ~E_1~0;~E_1~0 := 2; 294#L1314-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1547#L1319-3true assume !(1 == ~E_3~0); 913#L1324-3true assume 1 == ~E_4~0;~E_4~0 := 2; 140#L1329-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1425#L1334-3true assume 1 == ~E_6~0;~E_6~0 := 2; 467#L1339-3true assume 1 == ~E_7~0;~E_7~0 := 2; 674#L1344-3true assume 1 == ~E_8~0;~E_8~0 := 2; 633#L1349-3true assume 1 == ~E_9~0;~E_9~0 := 2; 278#L1354-3true assume 1 == ~E_10~0;~E_10~0 := 2; 646#L1359-3true assume !(1 == ~E_11~0); 1443#L1364-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 75#L860-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 606#L922-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 156#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 846#L1709true assume !(0 == start_simulation_~tmp~3#1); 1304#L1709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 939#L860-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1541#L922-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 109#L1664true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 619#L1671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1083#stop_simulation_returnLabel#1true start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1068#L1722true assume !(0 != start_simulation_~tmp___0~1#1); 204#L1690-2true [2023-11-21 21:03:31,784 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:31,784 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2023-11-21 21:03:31,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:31,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229402208] [2023-11-21 21:03:31,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:31,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:31,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:32,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:32,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:32,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229402208] [2023-11-21 21:03:32,195 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1229402208] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:32,195 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:32,195 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:32,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377938252] [2023-11-21 21:03:32,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:32,203 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:32,205 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:32,205 INFO L85 PathProgramCache]: Analyzing trace with hash -735606737, now seen corresponding path program 1 times [2023-11-21 21:03:32,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:32,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249807134] [2023-11-21 21:03:32,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:32,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:32,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:32,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:32,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:32,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249807134] [2023-11-21 21:03:32,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249807134] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:32,347 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:32,348 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 21:03:32,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782639268] [2023-11-21 21:03:32,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:32,349 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:32,350 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:32,408 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-21 21:03:32,410 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-21 21:03:32,416 INFO L87 Difference]: Start difference. First operand has 1593 states, 1592 states have (on average 1.4987437185929648) internal successors, (2386), 1592 states have internal predecessors, (2386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:32,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:32,500 INFO L93 Difference]: Finished difference Result 1589 states and 2352 transitions. [2023-11-21 21:03:32,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1589 states and 2352 transitions. [2023-11-21 21:03:32,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:32,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1589 states to 1583 states and 2346 transitions. [2023-11-21 21:03:32,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:32,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:32,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2346 transitions. [2023-11-21 21:03:32,556 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:32,556 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2346 transitions. [2023-11-21 21:03:32,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2346 transitions. [2023-11-21 21:03:32,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:32,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.4819962097283639) internal successors, (2346), 1582 states have internal predecessors, (2346), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:32,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2346 transitions. [2023-11-21 21:03:32,666 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2346 transitions. [2023-11-21 21:03:32,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-21 21:03:32,671 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2346 transitions. [2023-11-21 21:03:32,671 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-21 21:03:32,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2346 transitions. [2023-11-21 21:03:32,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:32,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:32,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:32,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:32,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:32,689 INFO L748 eck$LassoCheckResult]: Stem: 3428#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3429#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4155#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4156#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4296#L792 assume !(1 == ~m_i~0);~m_st~0 := 2; 4297#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3289#L797-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3290#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4731#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4264#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4265#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4534#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4535#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4634#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4704#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4705#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4584#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4432#L1121 assume !(0 == ~M_E~0); 4206#L1121-2 assume !(0 == ~T1_E~0); 3568#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3569#L1131-1 assume !(0 == ~T3_E~0); 3737#L1136-1 assume !(0 == ~T4_E~0); 3843#L1141-1 assume !(0 == ~T5_E~0); 4066#L1146-1 assume !(0 == ~T6_E~0); 4364#L1151-1 assume !(0 == ~T7_E~0); 3907#L1156-1 assume !(0 == ~T8_E~0); 3275#L1161-1 assume !(0 == ~T9_E~0); 3276#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3498#L1171-1 assume !(0 == ~T11_E~0); 3499#L1176-1 assume !(0 == ~E_M~0); 4377#L1181-1 assume !(0 == ~E_1~0); 4497#L1186-1 assume !(0 == ~E_2~0); 4547#L1191-1 assume !(0 == ~E_3~0); 3529#L1196-1 assume !(0 == ~E_4~0); 3530#L1201-1 assume !(0 == ~E_5~0); 4744#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 4585#L1211-1 assume !(0 == ~E_7~0); 4586#L1216-1 assume !(0 == ~E_8~0); 3667#L1221-1 assume !(0 == ~E_9~0); 3668#L1226-1 assume !(0 == ~E_10~0); 3375#L1231-1 assume !(0 == ~E_11~0); 3376#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4378#L556 assume 1 == ~m_pc~0; 4379#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3249#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3250#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4040#L1391 assume !(0 != activate_threads_~tmp~1#1); 4524#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4525#L575 assume !(1 == ~t1_pc~0); 3202#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3203#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3342#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3681#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 3636#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3637#L594 assume 1 == ~t2_pc~0; 3571#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3572#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3570#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3264#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 3265#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3331#L613 assume !(1 == ~t3_pc~0); 3446#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3445#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3796#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4064#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 4065#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3768#L632 assume 1 == ~t4_pc~0; 3769#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4283#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3281#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3282#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 4383#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4143#L651 assume 1 == ~t5_pc~0; 4144#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3460#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3461#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4037#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 3475#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3476#L670 assume !(1 == ~t6_pc~0); 4568#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3826#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3561#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3562#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4108#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4109#L689 assume 1 == ~t7_pc~0; 4740#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4224#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4583#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 4010#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4011#L708 assume !(1 == ~t8_pc~0); 3566#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3567#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4671#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4659#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 3623#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3624#L727 assume 1 == ~t9_pc~0; 3747#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3333#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3612#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3613#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 4732#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3677#L746 assume !(1 == ~t10_pc~0); 3678#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4338#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4451#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4620#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 4528#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3852#L765 assume 1 == ~t11_pc~0; 3853#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4056#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4678#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4566#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 4567#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4655#L1249 assume !(1 == ~M_E~0); 4287#L1249-2 assume !(1 == ~T1_E~0); 3942#L1254-1 assume !(1 == ~T2_E~0); 3260#L1259-1 assume !(1 == ~T3_E~0); 3242#L1264-1 assume !(1 == ~T4_E~0); 3243#L1269-1 assume !(1 == ~T5_E~0); 4770#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4712#L1279-1 assume !(1 == ~T7_E~0); 3447#L1284-1 assume !(1 == ~T8_E~0); 3448#L1289-1 assume !(1 == ~T9_E~0); 3990#L1294-1 assume !(1 == ~T10_E~0); 3991#L1299-1 assume !(1 == ~T11_E~0); 4000#L1304-1 assume !(1 == ~E_M~0); 4762#L1309-1 assume !(1 == ~E_1~0); 4764#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3396#L1319-1 assume !(1 == ~E_3~0); 3397#L1324-1 assume !(1 == ~E_4~0); 3522#L1329-1 assume !(1 == ~E_5~0); 3523#L1334-1 assume !(1 == ~E_6~0); 4615#L1339-1 assume !(1 == ~E_7~0); 4685#L1344-1 assume !(1 == ~E_8~0); 4686#L1349-1 assume !(1 == ~E_9~0); 4126#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4127#L1359-1 assume !(1 == ~E_11~0); 4475#L1364-1 assume { :end_inline_reset_delta_events } true; 3609#L1690-2 [2023-11-21 21:03:32,690 INFO L750 eck$LassoCheckResult]: Loop: 3609#L1690-2 assume !false; 3610#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3970#L1096-1 assume !false; 4749#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3351#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3352#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4381#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3850#L937 assume !(0 != eval_~tmp~0#1); 3851#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3712#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3713#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3823#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4734#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4033#L1131-3 assume !(0 == ~T3_E~0); 4034#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4771#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4384#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3564#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3565#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4681#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4207#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4208#L1171-3 assume !(0 == ~T11_E~0); 4245#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3605#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3606#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4322#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4323#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4506#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4507#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4227#L1211-3 assume !(0 == ~E_7~0); 3518#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3519#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3954#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3579#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3580#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3805#L556-39 assume 1 == ~m_pc~0; 4330#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4301#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4174#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3862#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 3863#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4255#L575-39 assume 1 == ~t1_pc~0; 4256#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4511#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4512#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4753#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4237#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4238#L594-39 assume !(1 == ~t2_pc~0); 4434#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 4240#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3922#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3923#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3738#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3739#L613-39 assume 1 == ~t3_pc~0; 4638#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3218#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3219#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4442#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3327#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3328#L632-39 assume 1 == ~t4_pc~0; 4601#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3919#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3920#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4081#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4599#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3588#L651-39 assume 1 == ~t5_pc~0; 3589#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3359#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4102#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4103#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4726#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4747#L670-39 assume !(1 == ~t6_pc~0); 4332#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 3266#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3267#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4063#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3950#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3951#L689-39 assume !(1 == ~t7_pc~0); 4070#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4071#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4087#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4425#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3462#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3463#L708-39 assume 1 == ~t8_pc~0; 3401#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3402#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4001#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4499#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4394#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3891#L727-39 assume !(1 == ~t9_pc~0); 3892#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 3651#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3293#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3294#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 4438#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4439#L746-39 assume 1 == ~t10_pc~0; 4412#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4413#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4677#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4161#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4162#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4557#L765-39 assume 1 == ~t11_pc~0; 3270#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3272#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4128#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3607#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3608#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4200#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3422#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3423#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4680#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4314#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3379#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3380#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4711#L1279-3 assume !(1 == ~T7_E~0); 3867#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3868#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3860#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3861#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4120#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4121#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3766#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3767#L1319-3 assume !(1 == ~E_3~0); 4521#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3485#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3486#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4047#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4048#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4262#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3744#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3745#L1359-3 assume !(1 == ~E_11~0); 4282#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3343#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3344#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3520#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3521#L1709 assume !(0 == start_simulation_~tmp~3#1); 3774#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4541#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3455#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3230#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 3231#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3420#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4246#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4630#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 3609#L1690-2 [2023-11-21 21:03:32,691 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:32,691 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2023-11-21 21:03:32,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:32,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865726164] [2023-11-21 21:03:32,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:32,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:32,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:32,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:32,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:32,796 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865726164] [2023-11-21 21:03:32,796 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [865726164] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:32,796 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:32,796 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:32,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639621253] [2023-11-21 21:03:32,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:32,797 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:32,819 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:32,819 INFO L85 PathProgramCache]: Analyzing trace with hash -1355425216, now seen corresponding path program 1 times [2023-11-21 21:03:32,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:32,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [701935537] [2023-11-21 21:03:32,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:32,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:32,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:33,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:33,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:33,006 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [701935537] [2023-11-21 21:03:33,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [701935537] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:33,006 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:33,006 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:33,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537994275] [2023-11-21 21:03:33,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:33,008 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:33,008 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:33,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:33,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:33,009 INFO L87 Difference]: Start difference. First operand 1583 states and 2346 transitions. cyclomatic complexity: 764 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:33,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:33,068 INFO L93 Difference]: Finished difference Result 1583 states and 2345 transitions. [2023-11-21 21:03:33,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2345 transitions. [2023-11-21 21:03:33,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:33,102 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1583 states and 2345 transitions. [2023-11-21 21:03:33,102 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:33,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:33,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2345 transitions. [2023-11-21 21:03:33,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:33,108 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2345 transitions. [2023-11-21 21:03:33,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2345 transitions. [2023-11-21 21:03:33,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:33,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.4813644977890081) internal successors, (2345), 1582 states have internal predecessors, (2345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:33,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2345 transitions. [2023-11-21 21:03:33,156 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2345 transitions. [2023-11-21 21:03:33,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:33,157 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2345 transitions. [2023-11-21 21:03:33,158 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-21 21:03:33,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2345 transitions. [2023-11-21 21:03:33,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:33,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:33,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:33,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:33,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:33,176 INFO L748 eck$LassoCheckResult]: Stem: 6601#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 6602#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7328#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7329#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7469#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 7470#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6462#L797-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6463#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7904#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7437#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7438#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7707#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7708#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7807#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7877#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7878#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7757#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7605#L1121 assume !(0 == ~M_E~0); 7379#L1121-2 assume !(0 == ~T1_E~0); 6741#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6742#L1131-1 assume !(0 == ~T3_E~0); 6910#L1136-1 assume !(0 == ~T4_E~0); 7016#L1141-1 assume !(0 == ~T5_E~0); 7239#L1146-1 assume !(0 == ~T6_E~0); 7537#L1151-1 assume !(0 == ~T7_E~0); 7080#L1156-1 assume !(0 == ~T8_E~0); 6448#L1161-1 assume !(0 == ~T9_E~0); 6449#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6671#L1171-1 assume !(0 == ~T11_E~0); 6672#L1176-1 assume !(0 == ~E_M~0); 7550#L1181-1 assume !(0 == ~E_1~0); 7670#L1186-1 assume !(0 == ~E_2~0); 7720#L1191-1 assume !(0 == ~E_3~0); 6702#L1196-1 assume !(0 == ~E_4~0); 6703#L1201-1 assume !(0 == ~E_5~0); 7917#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7758#L1211-1 assume !(0 == ~E_7~0); 7759#L1216-1 assume !(0 == ~E_8~0); 6840#L1221-1 assume !(0 == ~E_9~0); 6841#L1226-1 assume !(0 == ~E_10~0); 6548#L1231-1 assume !(0 == ~E_11~0); 6549#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7551#L556 assume 1 == ~m_pc~0; 7552#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6422#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6423#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7213#L1391 assume !(0 != activate_threads_~tmp~1#1); 7697#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7698#L575 assume !(1 == ~t1_pc~0); 6375#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6376#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6515#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6854#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 6809#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6810#L594 assume 1 == ~t2_pc~0; 6744#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6745#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6743#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6437#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 6438#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6504#L613 assume !(1 == ~t3_pc~0); 6619#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6618#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6969#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7237#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 7238#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6941#L632 assume 1 == ~t4_pc~0; 6942#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7456#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6454#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6455#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 7556#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7316#L651 assume 1 == ~t5_pc~0; 7317#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6633#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6634#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7210#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 6648#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6649#L670 assume !(1 == ~t6_pc~0); 7741#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6999#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6734#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6735#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7281#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7282#L689 assume 1 == ~t7_pc~0; 7913#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7397#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7398#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7756#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 7183#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7184#L708 assume !(1 == ~t8_pc~0); 6739#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6740#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7844#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7832#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 6796#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6797#L727 assume 1 == ~t9_pc~0; 6920#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6506#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6785#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6786#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 7905#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6850#L746 assume !(1 == ~t10_pc~0); 6851#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7511#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7624#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7793#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 7701#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7025#L765 assume 1 == ~t11_pc~0; 7026#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7229#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7851#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7739#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 7740#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7828#L1249 assume !(1 == ~M_E~0); 7460#L1249-2 assume !(1 == ~T1_E~0); 7115#L1254-1 assume !(1 == ~T2_E~0); 6433#L1259-1 assume !(1 == ~T3_E~0); 6415#L1264-1 assume !(1 == ~T4_E~0); 6416#L1269-1 assume !(1 == ~T5_E~0); 7943#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7885#L1279-1 assume !(1 == ~T7_E~0); 6620#L1284-1 assume !(1 == ~T8_E~0); 6621#L1289-1 assume !(1 == ~T9_E~0); 7163#L1294-1 assume !(1 == ~T10_E~0); 7164#L1299-1 assume !(1 == ~T11_E~0); 7173#L1304-1 assume !(1 == ~E_M~0); 7935#L1309-1 assume !(1 == ~E_1~0); 7937#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6569#L1319-1 assume !(1 == ~E_3~0); 6570#L1324-1 assume !(1 == ~E_4~0); 6695#L1329-1 assume !(1 == ~E_5~0); 6696#L1334-1 assume !(1 == ~E_6~0); 7788#L1339-1 assume !(1 == ~E_7~0); 7858#L1344-1 assume !(1 == ~E_8~0); 7859#L1349-1 assume !(1 == ~E_9~0); 7299#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7300#L1359-1 assume !(1 == ~E_11~0); 7648#L1364-1 assume { :end_inline_reset_delta_events } true; 6782#L1690-2 [2023-11-21 21:03:33,177 INFO L750 eck$LassoCheckResult]: Loop: 6782#L1690-2 assume !false; 6783#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7143#L1096-1 assume !false; 7922#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6524#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6525#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7554#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7023#L937 assume !(0 != eval_~tmp~0#1); 7024#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6885#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6886#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6996#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7907#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7206#L1131-3 assume !(0 == ~T3_E~0); 7207#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7944#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7557#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6737#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6738#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7854#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7380#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7381#L1171-3 assume !(0 == ~T11_E~0); 7418#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6778#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6779#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7495#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7496#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7679#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7680#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7400#L1211-3 assume !(0 == ~E_7~0); 6691#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6692#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7127#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6752#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 6753#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6978#L556-39 assume !(1 == ~m_pc~0); 7504#L556-41 is_master_triggered_~__retres1~0#1 := 0; 7474#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7347#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7035#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 7036#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7428#L575-39 assume 1 == ~t1_pc~0; 7429#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7684#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7685#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7926#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7410#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7411#L594-39 assume !(1 == ~t2_pc~0); 7607#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 7413#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7095#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7096#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6911#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6912#L613-39 assume 1 == ~t3_pc~0; 7811#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6391#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6392#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7615#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6500#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6501#L632-39 assume !(1 == ~t4_pc~0); 7649#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 7092#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7093#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7254#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7772#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6761#L651-39 assume !(1 == ~t5_pc~0); 6531#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 6532#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7275#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7276#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7899#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7920#L670-39 assume !(1 == ~t6_pc~0); 7505#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 6439#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6440#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7236#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7123#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7124#L689-39 assume 1 == ~t7_pc~0; 7346#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7244#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7260#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7598#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6635#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6636#L708-39 assume !(1 == ~t8_pc~0); 6576#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 6575#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7174#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7672#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7567#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7064#L727-39 assume !(1 == ~t9_pc~0); 7065#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 6824#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6466#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6467#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 7611#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7612#L746-39 assume 1 == ~t10_pc~0; 7585#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7586#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7850#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7334#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7335#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7730#L765-39 assume 1 == ~t11_pc~0; 6443#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6445#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7301#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6780#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 6781#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7373#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6595#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6596#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7853#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7487#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6552#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6553#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7884#L1279-3 assume !(1 == ~T7_E~0); 7040#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7041#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7033#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7034#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7293#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7294#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6939#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6940#L1319-3 assume !(1 == ~E_3~0); 7694#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6658#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6659#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7220#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7221#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7435#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6917#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6918#L1359-3 assume !(1 == ~E_11~0); 7455#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6516#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6517#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6693#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 6694#L1709 assume !(0 == start_simulation_~tmp~3#1); 6947#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7714#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6628#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6403#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 6404#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6593#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7419#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7803#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 6782#L1690-2 [2023-11-21 21:03:33,178 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:33,178 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2023-11-21 21:03:33,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:33,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005508915] [2023-11-21 21:03:33,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:33,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:33,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:33,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:33,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:33,331 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005508915] [2023-11-21 21:03:33,331 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005508915] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:33,331 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:33,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:33,332 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805580600] [2023-11-21 21:03:33,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:33,334 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:33,334 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:33,335 INFO L85 PathProgramCache]: Analyzing trace with hash -1288241405, now seen corresponding path program 1 times [2023-11-21 21:03:33,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:33,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276938400] [2023-11-21 21:03:33,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:33,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:33,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:33,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:33,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:33,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276938400] [2023-11-21 21:03:33,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276938400] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:33,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:33,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:33,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878292413] [2023-11-21 21:03:33,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:33,457 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:33,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:33,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:33,459 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:33,460 INFO L87 Difference]: Start difference. First operand 1583 states and 2345 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:33,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:33,502 INFO L93 Difference]: Finished difference Result 1583 states and 2344 transitions. [2023-11-21 21:03:33,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2344 transitions. [2023-11-21 21:03:33,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:33,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1583 states and 2344 transitions. [2023-11-21 21:03:33,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:33,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:33,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2344 transitions. [2023-11-21 21:03:33,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:33,534 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2344 transitions. [2023-11-21 21:03:33,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2344 transitions. [2023-11-21 21:03:33,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:33,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.4807327858496526) internal successors, (2344), 1582 states have internal predecessors, (2344), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:33,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2344 transitions. [2023-11-21 21:03:33,573 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2344 transitions. [2023-11-21 21:03:33,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:33,575 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2344 transitions. [2023-11-21 21:03:33,576 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-21 21:03:33,576 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2344 transitions. [2023-11-21 21:03:33,585 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:33,586 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:33,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:33,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:33,590 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:33,591 INFO L748 eck$LassoCheckResult]: Stem: 9774#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 9775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10504#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10505#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10642#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 10643#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9639#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9640#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 11077#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10610#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10611#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10880#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10881#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10980#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11050#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11051#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10930#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10778#L1121 assume !(0 == ~M_E~0); 10552#L1121-2 assume !(0 == ~T1_E~0); 9914#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9915#L1131-1 assume !(0 == ~T3_E~0); 10083#L1136-1 assume !(0 == ~T4_E~0); 10189#L1141-1 assume !(0 == ~T5_E~0); 10417#L1146-1 assume !(0 == ~T6_E~0); 10710#L1151-1 assume !(0 == ~T7_E~0); 10253#L1156-1 assume !(0 == ~T8_E~0); 9621#L1161-1 assume !(0 == ~T9_E~0); 9622#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9844#L1171-1 assume !(0 == ~T11_E~0); 9845#L1176-1 assume !(0 == ~E_M~0); 10723#L1181-1 assume !(0 == ~E_1~0); 10843#L1186-1 assume !(0 == ~E_2~0); 10893#L1191-1 assume !(0 == ~E_3~0); 9875#L1196-1 assume !(0 == ~E_4~0); 9876#L1201-1 assume !(0 == ~E_5~0); 11090#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10931#L1211-1 assume !(0 == ~E_7~0); 10932#L1216-1 assume !(0 == ~E_8~0); 10016#L1221-1 assume !(0 == ~E_9~0); 10017#L1226-1 assume !(0 == ~E_10~0); 9721#L1231-1 assume !(0 == ~E_11~0); 9722#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10725#L556 assume 1 == ~m_pc~0; 10726#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9595#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9596#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10386#L1391 assume !(0 != activate_threads_~tmp~1#1); 10871#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10872#L575 assume !(1 == ~t1_pc~0); 9548#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9549#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9688#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10029#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 9982#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9983#L594 assume 1 == ~t2_pc~0; 9917#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9918#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9916#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9612#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 9613#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9677#L613 assume !(1 == ~t3_pc~0); 9792#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9791#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10142#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10410#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 10411#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10114#L632 assume 1 == ~t4_pc~0; 10115#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10629#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9631#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9632#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 10729#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10489#L651 assume 1 == ~t5_pc~0; 10490#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9806#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9807#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10383#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 9821#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9822#L670 assume !(1 == ~t6_pc~0); 10915#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10177#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9908#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9909#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10456#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10457#L689 assume 1 == ~t7_pc~0; 11086#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10570#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10571#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10929#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 10356#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10357#L708 assume !(1 == ~t8_pc~0); 9912#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9913#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11018#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11005#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 9969#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9970#L727 assume 1 == ~t9_pc~0; 10093#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9679#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9958#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9959#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 11079#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10024#L746 assume !(1 == ~t10_pc~0); 10025#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10684#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10797#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10966#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 10874#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10201#L765 assume 1 == ~t11_pc~0; 10202#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10402#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11024#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10912#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 10913#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11001#L1249 assume !(1 == ~M_E~0); 10634#L1249-2 assume !(1 == ~T1_E~0); 10288#L1254-1 assume !(1 == ~T2_E~0); 9606#L1259-1 assume !(1 == ~T3_E~0); 9588#L1264-1 assume !(1 == ~T4_E~0); 9589#L1269-1 assume !(1 == ~T5_E~0); 11116#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11058#L1279-1 assume !(1 == ~T7_E~0); 9793#L1284-1 assume !(1 == ~T8_E~0); 9794#L1289-1 assume !(1 == ~T9_E~0); 10336#L1294-1 assume !(1 == ~T10_E~0); 10337#L1299-1 assume !(1 == ~T11_E~0); 10346#L1304-1 assume !(1 == ~E_M~0); 11108#L1309-1 assume !(1 == ~E_1~0); 11110#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9742#L1319-1 assume !(1 == ~E_3~0); 9743#L1324-1 assume !(1 == ~E_4~0); 9868#L1329-1 assume !(1 == ~E_5~0); 9869#L1334-1 assume !(1 == ~E_6~0); 10961#L1339-1 assume !(1 == ~E_7~0); 11031#L1344-1 assume !(1 == ~E_8~0); 11032#L1349-1 assume !(1 == ~E_9~0); 10473#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10474#L1359-1 assume !(1 == ~E_11~0); 10821#L1364-1 assume { :end_inline_reset_delta_events } true; 9956#L1690-2 [2023-11-21 21:03:33,592 INFO L750 eck$LassoCheckResult]: Loop: 9956#L1690-2 assume !false; 9957#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10316#L1096-1 assume !false; 11095#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9697#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9698#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10728#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10196#L937 assume !(0 != eval_~tmp~0#1); 10197#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10061#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10062#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10171#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11080#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10379#L1131-3 assume !(0 == ~T3_E~0); 10380#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11117#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10730#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9910#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9911#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11027#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10553#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10554#L1171-3 assume !(0 == ~T11_E~0); 10591#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9951#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9952#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10668#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10669#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10852#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10853#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10573#L1211-3 assume !(0 == ~E_7~0); 9864#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9865#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10300#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9925#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9926#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10151#L556-39 assume 1 == ~m_pc~0; 10676#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10647#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10520#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10208#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 10209#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10601#L575-39 assume 1 == ~t1_pc~0; 10602#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10857#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10858#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11099#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10583#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10584#L594-39 assume !(1 == ~t2_pc~0); 10780#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 10586#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10268#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10269#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10084#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10085#L613-39 assume 1 == ~t3_pc~0; 10984#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9564#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9565#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10788#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9673#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9674#L632-39 assume 1 == ~t4_pc~0; 10947#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10265#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10266#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10427#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10945#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9934#L651-39 assume !(1 == ~t5_pc~0); 9704#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 9705#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10448#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10449#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11072#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11093#L670-39 assume !(1 == ~t6_pc~0); 10678#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 9610#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9611#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10409#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10296#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10297#L689-39 assume 1 == ~t7_pc~0; 10519#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10416#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10433#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10771#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9808#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9809#L708-39 assume 1 == ~t8_pc~0; 9747#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9748#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10347#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10845#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10740#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10237#L727-39 assume !(1 == ~t9_pc~0); 10238#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 9997#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9637#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9638#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 10784#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10785#L746-39 assume 1 == ~t10_pc~0; 10758#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10759#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11023#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10507#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10508#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10903#L765-39 assume 1 == ~t11_pc~0; 9616#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9618#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10472#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9953#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9954#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10546#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9768#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9769#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11026#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10660#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9725#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9726#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11057#L1279-3 assume !(1 == ~T7_E~0); 10213#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10214#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10206#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10207#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10466#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10467#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10112#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10113#L1319-3 assume !(1 == ~E_3~0); 10867#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9828#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9829#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10393#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10394#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10608#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10090#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10091#L1359-3 assume !(1 == ~E_11~0); 10628#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9689#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9690#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9866#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 9867#L1709 assume !(0 == start_simulation_~tmp~3#1); 10120#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10887#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9801#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9576#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 9577#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9766#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10592#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 10976#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 9956#L1690-2 [2023-11-21 21:03:33,593 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:33,593 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2023-11-21 21:03:33,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:33,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697330631] [2023-11-21 21:03:33,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:33,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:33,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:33,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:33,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:33,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697330631] [2023-11-21 21:03:33,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697330631] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:33,697 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:33,698 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:33,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [903495703] [2023-11-21 21:03:33,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:33,699 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:33,699 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:33,700 INFO L85 PathProgramCache]: Analyzing trace with hash -134979392, now seen corresponding path program 1 times [2023-11-21 21:03:33,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:33,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116196210] [2023-11-21 21:03:33,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:33,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:33,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:33,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:33,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:33,801 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116196210] [2023-11-21 21:03:33,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116196210] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:33,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:33,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:33,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515866183] [2023-11-21 21:03:33,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:33,802 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:33,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:33,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:33,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:33,804 INFO L87 Difference]: Start difference. First operand 1583 states and 2344 transitions. cyclomatic complexity: 762 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:33,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:33,855 INFO L93 Difference]: Finished difference Result 1583 states and 2343 transitions. [2023-11-21 21:03:33,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2343 transitions. [2023-11-21 21:03:33,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:33,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1583 states and 2343 transitions. [2023-11-21 21:03:33,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:33,886 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:33,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2343 transitions. [2023-11-21 21:03:33,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:33,890 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2343 transitions. [2023-11-21 21:03:33,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2343 transitions. [2023-11-21 21:03:33,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:33,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.4801010739102969) internal successors, (2343), 1582 states have internal predecessors, (2343), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:33,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2343 transitions. [2023-11-21 21:03:33,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2343 transitions. [2023-11-21 21:03:33,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:33,938 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2343 transitions. [2023-11-21 21:03:33,938 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-21 21:03:33,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2343 transitions. [2023-11-21 21:03:33,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:33,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:33,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:33,951 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:33,956 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:33,956 INFO L748 eck$LassoCheckResult]: Stem: 12947#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 12948#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13674#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13675#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13815#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 13816#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12810#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12811#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14250#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13783#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13784#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14053#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14054#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14153#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14223#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14224#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14103#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13951#L1121 assume !(0 == ~M_E~0); 13725#L1121-2 assume !(0 == ~T1_E~0); 13087#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13088#L1131-1 assume !(0 == ~T3_E~0); 13256#L1136-1 assume !(0 == ~T4_E~0); 13362#L1141-1 assume !(0 == ~T5_E~0); 13587#L1146-1 assume !(0 == ~T6_E~0); 13883#L1151-1 assume !(0 == ~T7_E~0); 13426#L1156-1 assume !(0 == ~T8_E~0); 12794#L1161-1 assume !(0 == ~T9_E~0); 12795#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13017#L1171-1 assume !(0 == ~T11_E~0); 13018#L1176-1 assume !(0 == ~E_M~0); 13896#L1181-1 assume !(0 == ~E_1~0); 14016#L1186-1 assume !(0 == ~E_2~0); 14066#L1191-1 assume !(0 == ~E_3~0); 13048#L1196-1 assume !(0 == ~E_4~0); 13049#L1201-1 assume !(0 == ~E_5~0); 14263#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14104#L1211-1 assume !(0 == ~E_7~0); 14105#L1216-1 assume !(0 == ~E_8~0); 13186#L1221-1 assume !(0 == ~E_9~0); 13187#L1226-1 assume !(0 == ~E_10~0); 12894#L1231-1 assume !(0 == ~E_11~0); 12895#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13897#L556 assume 1 == ~m_pc~0; 13898#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12768#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12769#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13559#L1391 assume !(0 != activate_threads_~tmp~1#1); 14043#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14044#L575 assume !(1 == ~t1_pc~0); 12721#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12722#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13200#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 13155#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13156#L594 assume 1 == ~t2_pc~0; 13090#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13091#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13089#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12783#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 12784#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12850#L613 assume !(1 == ~t3_pc~0); 12965#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12964#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13315#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13583#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 13584#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13287#L632 assume 1 == ~t4_pc~0; 13288#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13802#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12800#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12801#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 13902#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13662#L651 assume 1 == ~t5_pc~0; 13663#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12979#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12980#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13556#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 12994#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12995#L670 assume !(1 == ~t6_pc~0); 14087#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13345#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13080#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13081#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13627#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13628#L689 assume 1 == ~t7_pc~0; 14259#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13743#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13744#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14102#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 13529#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13530#L708 assume !(1 == ~t8_pc~0); 13085#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13086#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14190#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14178#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 13142#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13143#L727 assume 1 == ~t9_pc~0; 13266#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12852#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13131#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13132#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 14251#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13196#L746 assume !(1 == ~t10_pc~0); 13197#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13857#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13970#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14139#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 14047#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13371#L765 assume 1 == ~t11_pc~0; 13372#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13575#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14197#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14085#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 14086#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14174#L1249 assume !(1 == ~M_E~0); 13806#L1249-2 assume !(1 == ~T1_E~0); 13461#L1254-1 assume !(1 == ~T2_E~0); 12779#L1259-1 assume !(1 == ~T3_E~0); 12761#L1264-1 assume !(1 == ~T4_E~0); 12762#L1269-1 assume !(1 == ~T5_E~0); 14289#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14231#L1279-1 assume !(1 == ~T7_E~0); 12966#L1284-1 assume !(1 == ~T8_E~0); 12967#L1289-1 assume !(1 == ~T9_E~0); 13509#L1294-1 assume !(1 == ~T10_E~0); 13510#L1299-1 assume !(1 == ~T11_E~0); 13519#L1304-1 assume !(1 == ~E_M~0); 14281#L1309-1 assume !(1 == ~E_1~0); 14283#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12915#L1319-1 assume !(1 == ~E_3~0); 12916#L1324-1 assume !(1 == ~E_4~0); 13041#L1329-1 assume !(1 == ~E_5~0); 13042#L1334-1 assume !(1 == ~E_6~0); 14134#L1339-1 assume !(1 == ~E_7~0); 14204#L1344-1 assume !(1 == ~E_8~0); 14205#L1349-1 assume !(1 == ~E_9~0); 13646#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13647#L1359-1 assume !(1 == ~E_11~0); 13994#L1364-1 assume { :end_inline_reset_delta_events } true; 13128#L1690-2 [2023-11-21 21:03:33,957 INFO L750 eck$LassoCheckResult]: Loop: 13128#L1690-2 assume !false; 13129#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13489#L1096-1 assume !false; 14268#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12870#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12871#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13900#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13369#L937 assume !(0 != eval_~tmp~0#1); 13370#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13231#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13232#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13344#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14253#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13552#L1131-3 assume !(0 == ~T3_E~0); 13553#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14290#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13903#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13083#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13084#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14200#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13726#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13727#L1171-3 assume !(0 == ~T11_E~0); 13765#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13124#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13125#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13841#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13842#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14025#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14026#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13746#L1211-3 assume !(0 == ~E_7~0); 13037#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13038#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13473#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13098#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13099#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13324#L556-39 assume 1 == ~m_pc~0; 13849#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13820#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13693#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13381#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 13382#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13774#L575-39 assume !(1 == ~t1_pc~0); 13776#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 14030#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14031#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14272#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13756#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13757#L594-39 assume !(1 == ~t2_pc~0); 13953#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 13759#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13441#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13442#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13257#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13258#L613-39 assume 1 == ~t3_pc~0; 14157#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12737#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12738#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13963#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12846#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12847#L632-39 assume 1 == ~t4_pc~0; 14120#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13438#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13439#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13600#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14118#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13107#L651-39 assume 1 == ~t5_pc~0; 13108#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12878#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13621#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13622#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14245#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14266#L670-39 assume !(1 == ~t6_pc~0); 13851#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 12785#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12786#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13582#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13469#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13470#L689-39 assume !(1 == ~t7_pc~0); 13585#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 13586#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13606#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13944#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12981#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12982#L708-39 assume 1 == ~t8_pc~0; 12920#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12921#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13520#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14018#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13913#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13409#L727-39 assume !(1 == ~t9_pc~0); 13410#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 13170#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12808#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12809#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 13956#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13957#L746-39 assume 1 == ~t10_pc~0; 13931#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13932#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14196#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13679#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13680#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14076#L765-39 assume 1 == ~t11_pc~0; 12789#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12791#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13645#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13126#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13127#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13719#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12940#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12941#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14199#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13833#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12898#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12899#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14230#L1279-3 assume !(1 == ~T7_E~0); 13386#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13387#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13377#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13378#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13639#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13640#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13281#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13282#L1319-3 assume !(1 == ~E_3~0); 14040#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12998#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12999#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13566#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13567#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13781#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13263#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13264#L1359-3 assume !(1 == ~E_11~0); 13801#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12862#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12863#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13039#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 13040#L1709 assume !(0 == start_simulation_~tmp~3#1); 13293#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 14060#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12974#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12749#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 12750#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12939#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13764#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14149#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 13128#L1690-2 [2023-11-21 21:03:33,958 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:33,958 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2023-11-21 21:03:33,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:33,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267462764] [2023-11-21 21:03:33,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:33,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:33,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:34,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:34,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:34,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267462764] [2023-11-21 21:03:34,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267462764] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:34,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:34,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:34,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260500870] [2023-11-21 21:03:34,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:34,023 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:34,024 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:34,024 INFO L85 PathProgramCache]: Analyzing trace with hash 959955137, now seen corresponding path program 1 times [2023-11-21 21:03:34,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:34,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107576836] [2023-11-21 21:03:34,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:34,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:34,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:34,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:34,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:34,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107576836] [2023-11-21 21:03:34,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2107576836] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:34,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:34,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:34,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82533997] [2023-11-21 21:03:34,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:34,104 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:34,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:34,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:34,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:34,105 INFO L87 Difference]: Start difference. First operand 1583 states and 2343 transitions. cyclomatic complexity: 761 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:34,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:34,146 INFO L93 Difference]: Finished difference Result 1583 states and 2342 transitions. [2023-11-21 21:03:34,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2342 transitions. [2023-11-21 21:03:34,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:34,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1583 states and 2342 transitions. [2023-11-21 21:03:34,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:34,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:34,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2342 transitions. [2023-11-21 21:03:34,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:34,179 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2342 transitions. [2023-11-21 21:03:34,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2342 transitions. [2023-11-21 21:03:34,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:34,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.4794693619709411) internal successors, (2342), 1582 states have internal predecessors, (2342), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:34,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2342 transitions. [2023-11-21 21:03:34,219 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2342 transitions. [2023-11-21 21:03:34,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:34,222 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2342 transitions. [2023-11-21 21:03:34,222 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-21 21:03:34,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2342 transitions. [2023-11-21 21:03:34,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:34,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:34,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:34,237 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:34,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:34,237 INFO L748 eck$LassoCheckResult]: Stem: 16120#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16121#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16847#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16848#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16988#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 16989#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15981#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15982#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17423#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16956#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16957#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17226#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17227#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17326#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17396#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17397#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17276#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17124#L1121 assume !(0 == ~M_E~0); 16898#L1121-2 assume !(0 == ~T1_E~0); 16260#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16261#L1131-1 assume !(0 == ~T3_E~0); 16429#L1136-1 assume !(0 == ~T4_E~0); 16535#L1141-1 assume !(0 == ~T5_E~0); 16758#L1146-1 assume !(0 == ~T6_E~0); 17056#L1151-1 assume !(0 == ~T7_E~0); 16599#L1156-1 assume !(0 == ~T8_E~0); 15967#L1161-1 assume !(0 == ~T9_E~0); 15968#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16190#L1171-1 assume !(0 == ~T11_E~0); 16191#L1176-1 assume !(0 == ~E_M~0); 17069#L1181-1 assume !(0 == ~E_1~0); 17189#L1186-1 assume !(0 == ~E_2~0); 17239#L1191-1 assume !(0 == ~E_3~0); 16221#L1196-1 assume !(0 == ~E_4~0); 16222#L1201-1 assume !(0 == ~E_5~0); 17436#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 17277#L1211-1 assume !(0 == ~E_7~0); 17278#L1216-1 assume !(0 == ~E_8~0); 16359#L1221-1 assume !(0 == ~E_9~0); 16360#L1226-1 assume !(0 == ~E_10~0); 16067#L1231-1 assume !(0 == ~E_11~0); 16068#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17070#L556 assume 1 == ~m_pc~0; 17071#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15941#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15942#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16732#L1391 assume !(0 != activate_threads_~tmp~1#1); 17216#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17217#L575 assume !(1 == ~t1_pc~0); 15894#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15895#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16034#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16373#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 16328#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16329#L594 assume 1 == ~t2_pc~0; 16263#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16264#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16262#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15956#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 15957#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16023#L613 assume !(1 == ~t3_pc~0); 16138#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16137#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16488#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16756#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 16757#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16460#L632 assume 1 == ~t4_pc~0; 16461#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16975#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15973#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15974#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 17075#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16835#L651 assume 1 == ~t5_pc~0; 16836#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16152#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16153#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16729#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 16167#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16168#L670 assume !(1 == ~t6_pc~0); 17260#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16518#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16253#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16254#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16800#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16801#L689 assume 1 == ~t7_pc~0; 17432#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16916#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16917#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17275#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 16702#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16703#L708 assume !(1 == ~t8_pc~0); 16258#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16259#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17363#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17351#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 16315#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16316#L727 assume 1 == ~t9_pc~0; 16439#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16025#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16304#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16305#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 17424#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16369#L746 assume !(1 == ~t10_pc~0); 16370#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17030#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17143#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17312#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 17220#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16544#L765 assume 1 == ~t11_pc~0; 16545#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16748#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17370#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17258#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 17259#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17347#L1249 assume !(1 == ~M_E~0); 16979#L1249-2 assume !(1 == ~T1_E~0); 16634#L1254-1 assume !(1 == ~T2_E~0); 15952#L1259-1 assume !(1 == ~T3_E~0); 15934#L1264-1 assume !(1 == ~T4_E~0); 15935#L1269-1 assume !(1 == ~T5_E~0); 17462#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17404#L1279-1 assume !(1 == ~T7_E~0); 16139#L1284-1 assume !(1 == ~T8_E~0); 16140#L1289-1 assume !(1 == ~T9_E~0); 16682#L1294-1 assume !(1 == ~T10_E~0); 16683#L1299-1 assume !(1 == ~T11_E~0); 16692#L1304-1 assume !(1 == ~E_M~0); 17454#L1309-1 assume !(1 == ~E_1~0); 17456#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16088#L1319-1 assume !(1 == ~E_3~0); 16089#L1324-1 assume !(1 == ~E_4~0); 16214#L1329-1 assume !(1 == ~E_5~0); 16215#L1334-1 assume !(1 == ~E_6~0); 17307#L1339-1 assume !(1 == ~E_7~0); 17377#L1344-1 assume !(1 == ~E_8~0); 17378#L1349-1 assume !(1 == ~E_9~0); 16818#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16819#L1359-1 assume !(1 == ~E_11~0); 17167#L1364-1 assume { :end_inline_reset_delta_events } true; 16301#L1690-2 [2023-11-21 21:03:34,238 INFO L750 eck$LassoCheckResult]: Loop: 16301#L1690-2 assume !false; 16302#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16662#L1096-1 assume !false; 17441#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16043#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16044#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 17073#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16542#L937 assume !(0 != eval_~tmp~0#1); 16543#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16404#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16405#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16515#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17426#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16725#L1131-3 assume !(0 == ~T3_E~0); 16726#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17463#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17076#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16256#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16257#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17373#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16899#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16900#L1171-3 assume !(0 == ~T11_E~0); 16937#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16297#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16298#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17014#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17015#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17198#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17199#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16919#L1211-3 assume !(0 == ~E_7~0); 16210#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16211#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16646#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16271#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16272#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16497#L556-39 assume 1 == ~m_pc~0; 17022#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16993#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16866#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16554#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 16555#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16947#L575-39 assume 1 == ~t1_pc~0; 16948#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17203#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17204#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17445#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16929#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16930#L594-39 assume !(1 == ~t2_pc~0); 17126#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 16932#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16614#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16615#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16430#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16431#L613-39 assume 1 == ~t3_pc~0; 17330#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15910#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15911#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17134#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16019#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16020#L632-39 assume !(1 == ~t4_pc~0); 17168#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 16611#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16612#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16773#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17291#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16280#L651-39 assume !(1 == ~t5_pc~0); 16050#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 16051#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16794#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16795#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17418#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17439#L670-39 assume !(1 == ~t6_pc~0); 17024#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 15958#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15959#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16755#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16642#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16643#L689-39 assume 1 == ~t7_pc~0; 16865#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16763#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16779#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17117#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16154#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16155#L708-39 assume 1 == ~t8_pc~0; 16093#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16094#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16693#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17191#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17086#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16583#L727-39 assume !(1 == ~t9_pc~0); 16584#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 16343#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15985#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15986#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 17130#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17131#L746-39 assume 1 == ~t10_pc~0; 17104#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17105#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17369#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16853#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16854#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17249#L765-39 assume 1 == ~t11_pc~0; 15962#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15964#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16820#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16299#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16300#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16892#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16114#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16115#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17372#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17006#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16071#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16072#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17403#L1279-3 assume !(1 == ~T7_E~0); 16559#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16560#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16552#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16553#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16812#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16813#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16458#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16459#L1319-3 assume !(1 == ~E_3~0); 17213#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16177#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16178#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16739#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16740#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16954#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16436#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16437#L1359-3 assume !(1 == ~E_11~0); 16974#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16035#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16036#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16212#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 16213#L1709 assume !(0 == start_simulation_~tmp~3#1); 16466#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 17233#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16147#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15922#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 15923#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16112#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16938#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 17322#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 16301#L1690-2 [2023-11-21 21:03:34,239 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:34,239 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2023-11-21 21:03:34,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:34,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748890626] [2023-11-21 21:03:34,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:34,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:34,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:34,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:34,331 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:34,331 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748890626] [2023-11-21 21:03:34,331 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1748890626] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:34,332 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:34,332 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:34,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955695723] [2023-11-21 21:03:34,337 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:34,338 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:34,338 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:34,338 INFO L85 PathProgramCache]: Analyzing trace with hash -1352166015, now seen corresponding path program 1 times [2023-11-21 21:03:34,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:34,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726719206] [2023-11-21 21:03:34,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:34,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:34,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:34,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:34,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:34,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726719206] [2023-11-21 21:03:34,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [726719206] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:34,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:34,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:34,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653070512] [2023-11-21 21:03:34,426 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:34,427 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:34,427 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:34,428 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:34,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:34,429 INFO L87 Difference]: Start difference. First operand 1583 states and 2342 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:34,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:34,468 INFO L93 Difference]: Finished difference Result 1583 states and 2341 transitions. [2023-11-21 21:03:34,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2341 transitions. [2023-11-21 21:03:34,478 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:34,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1583 states and 2341 transitions. [2023-11-21 21:03:34,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:34,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:34,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2341 transitions. [2023-11-21 21:03:34,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:34,496 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2341 transitions. [2023-11-21 21:03:34,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2341 transitions. [2023-11-21 21:03:34,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:34,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.4788376500315856) internal successors, (2341), 1582 states have internal predecessors, (2341), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:34,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2341 transitions. [2023-11-21 21:03:34,536 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2341 transitions. [2023-11-21 21:03:34,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:34,538 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2341 transitions. [2023-11-21 21:03:34,540 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-21 21:03:34,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2341 transitions. [2023-11-21 21:03:34,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:34,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:34,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:34,550 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:34,550 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:34,550 INFO L748 eck$LassoCheckResult]: Stem: 19293#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19294#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 20020#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20021#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20161#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 20162#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19154#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19155#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20596#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20129#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20130#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20399#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20400#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20499#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20569#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20570#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20449#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20297#L1121 assume !(0 == ~M_E~0); 20071#L1121-2 assume !(0 == ~T1_E~0); 19433#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19434#L1131-1 assume !(0 == ~T3_E~0); 19602#L1136-1 assume !(0 == ~T4_E~0); 19708#L1141-1 assume !(0 == ~T5_E~0); 19931#L1146-1 assume !(0 == ~T6_E~0); 20229#L1151-1 assume !(0 == ~T7_E~0); 19772#L1156-1 assume !(0 == ~T8_E~0); 19140#L1161-1 assume !(0 == ~T9_E~0); 19141#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19363#L1171-1 assume !(0 == ~T11_E~0); 19364#L1176-1 assume !(0 == ~E_M~0); 20242#L1181-1 assume !(0 == ~E_1~0); 20362#L1186-1 assume !(0 == ~E_2~0); 20412#L1191-1 assume !(0 == ~E_3~0); 19394#L1196-1 assume !(0 == ~E_4~0); 19395#L1201-1 assume !(0 == ~E_5~0); 20609#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 20450#L1211-1 assume !(0 == ~E_7~0); 20451#L1216-1 assume !(0 == ~E_8~0); 19532#L1221-1 assume !(0 == ~E_9~0); 19533#L1226-1 assume !(0 == ~E_10~0); 19240#L1231-1 assume !(0 == ~E_11~0); 19241#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20243#L556 assume 1 == ~m_pc~0; 20244#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19114#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19115#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19905#L1391 assume !(0 != activate_threads_~tmp~1#1); 20389#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20390#L575 assume !(1 == ~t1_pc~0); 19067#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19068#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19207#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19546#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 19501#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19502#L594 assume 1 == ~t2_pc~0; 19436#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19437#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19435#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19129#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 19130#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19196#L613 assume !(1 == ~t3_pc~0); 19311#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19310#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19661#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19929#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 19930#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19633#L632 assume 1 == ~t4_pc~0; 19634#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20148#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19146#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19147#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 20248#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20008#L651 assume 1 == ~t5_pc~0; 20009#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19325#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19326#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19902#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 19340#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19341#L670 assume !(1 == ~t6_pc~0); 20433#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19691#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19426#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19427#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19973#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19974#L689 assume 1 == ~t7_pc~0; 20605#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20089#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20090#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20448#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 19875#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19876#L708 assume !(1 == ~t8_pc~0); 19431#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19432#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20536#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20524#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 19488#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19489#L727 assume 1 == ~t9_pc~0; 19612#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19198#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19477#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19478#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 20597#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19542#L746 assume !(1 == ~t10_pc~0); 19543#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20203#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20316#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20485#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 20393#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19717#L765 assume 1 == ~t11_pc~0; 19718#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19921#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20543#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20431#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 20432#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20520#L1249 assume !(1 == ~M_E~0); 20152#L1249-2 assume !(1 == ~T1_E~0); 19807#L1254-1 assume !(1 == ~T2_E~0); 19125#L1259-1 assume !(1 == ~T3_E~0); 19107#L1264-1 assume !(1 == ~T4_E~0); 19108#L1269-1 assume !(1 == ~T5_E~0); 20635#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20577#L1279-1 assume !(1 == ~T7_E~0); 19312#L1284-1 assume !(1 == ~T8_E~0); 19313#L1289-1 assume !(1 == ~T9_E~0); 19855#L1294-1 assume !(1 == ~T10_E~0); 19856#L1299-1 assume !(1 == ~T11_E~0); 19865#L1304-1 assume !(1 == ~E_M~0); 20627#L1309-1 assume !(1 == ~E_1~0); 20629#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19261#L1319-1 assume !(1 == ~E_3~0); 19262#L1324-1 assume !(1 == ~E_4~0); 19387#L1329-1 assume !(1 == ~E_5~0); 19388#L1334-1 assume !(1 == ~E_6~0); 20480#L1339-1 assume !(1 == ~E_7~0); 20550#L1344-1 assume !(1 == ~E_8~0); 20551#L1349-1 assume !(1 == ~E_9~0); 19991#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19992#L1359-1 assume !(1 == ~E_11~0); 20340#L1364-1 assume { :end_inline_reset_delta_events } true; 19474#L1690-2 [2023-11-21 21:03:34,551 INFO L750 eck$LassoCheckResult]: Loop: 19474#L1690-2 assume !false; 19475#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19835#L1096-1 assume !false; 20614#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19216#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19217#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20246#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19715#L937 assume !(0 != eval_~tmp~0#1); 19716#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19577#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19578#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19688#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20599#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19898#L1131-3 assume !(0 == ~T3_E~0); 19899#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20636#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20249#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19429#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19430#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20546#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20072#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20073#L1171-3 assume !(0 == ~T11_E~0); 20110#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19470#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19471#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20187#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20188#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20371#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20372#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20092#L1211-3 assume !(0 == ~E_7~0); 19383#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19384#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19819#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19444#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19445#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19670#L556-39 assume 1 == ~m_pc~0; 20195#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20166#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20039#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19727#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 19728#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20120#L575-39 assume 1 == ~t1_pc~0; 20121#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20376#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20377#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20618#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20102#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20103#L594-39 assume !(1 == ~t2_pc~0); 20299#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 20105#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19787#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19788#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19603#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19604#L613-39 assume 1 == ~t3_pc~0; 20503#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19083#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19084#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20307#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19192#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19193#L632-39 assume 1 == ~t4_pc~0; 20466#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19784#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19785#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19946#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20464#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19453#L651-39 assume !(1 == ~t5_pc~0); 19223#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 19224#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19967#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19968#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20591#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20612#L670-39 assume !(1 == ~t6_pc~0); 20197#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 19131#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19132#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19928#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19815#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19816#L689-39 assume 1 == ~t7_pc~0; 20038#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19936#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19952#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20290#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19327#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19328#L708-39 assume 1 == ~t8_pc~0; 19266#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19267#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19866#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20364#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20259#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19756#L727-39 assume !(1 == ~t9_pc~0); 19757#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 19516#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19158#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19159#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 20303#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20304#L746-39 assume 1 == ~t10_pc~0; 20277#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20278#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20542#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20026#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20027#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20422#L765-39 assume !(1 == ~t11_pc~0); 19136#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 19137#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19993#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19472#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19473#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20065#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19287#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19288#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20545#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20179#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19244#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19245#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20576#L1279-3 assume !(1 == ~T7_E~0); 19732#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19733#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19725#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19726#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19985#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19986#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19631#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19632#L1319-3 assume !(1 == ~E_3~0); 20386#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19350#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19351#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19912#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19913#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20127#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19609#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19610#L1359-3 assume !(1 == ~E_11~0); 20147#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19208#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19209#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19385#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 19386#L1709 assume !(0 == start_simulation_~tmp~3#1); 19639#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 20406#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19320#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19095#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 19096#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19285#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20111#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 20495#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 19474#L1690-2 [2023-11-21 21:03:34,553 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:34,553 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2023-11-21 21:03:34,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:34,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014459850] [2023-11-21 21:03:34,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:34,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:34,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:34,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:34,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:34,611 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1014459850] [2023-11-21 21:03:34,611 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1014459850] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:34,611 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:34,611 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:34,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302787455] [2023-11-21 21:03:34,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:34,612 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:34,612 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:34,613 INFO L85 PathProgramCache]: Analyzing trace with hash 1763550913, now seen corresponding path program 1 times [2023-11-21 21:03:34,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:34,613 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798900178] [2023-11-21 21:03:34,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:34,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:34,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:34,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:34,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:34,685 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798900178] [2023-11-21 21:03:34,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [798900178] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:34,686 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:34,686 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:34,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648444397] [2023-11-21 21:03:34,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:34,687 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:34,687 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:34,687 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:34,687 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:34,688 INFO L87 Difference]: Start difference. First operand 1583 states and 2341 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:34,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:34,726 INFO L93 Difference]: Finished difference Result 1583 states and 2340 transitions. [2023-11-21 21:03:34,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2340 transitions. [2023-11-21 21:03:34,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:34,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1583 states and 2340 transitions. [2023-11-21 21:03:34,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:34,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:34,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2340 transitions. [2023-11-21 21:03:34,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:34,757 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2340 transitions. [2023-11-21 21:03:34,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2340 transitions. [2023-11-21 21:03:34,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:34,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.4782059380922299) internal successors, (2340), 1582 states have internal predecessors, (2340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:34,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2340 transitions. [2023-11-21 21:03:34,796 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2340 transitions. [2023-11-21 21:03:34,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:34,798 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2340 transitions. [2023-11-21 21:03:34,799 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-21 21:03:34,799 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2340 transitions. [2023-11-21 21:03:34,805 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:34,806 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:34,806 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:34,808 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:34,808 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:34,809 INFO L748 eck$LassoCheckResult]: Stem: 22466#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22467#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23193#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23194#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23334#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 23335#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22327#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22328#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23769#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23302#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23303#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23572#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23573#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23672#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23742#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 23743#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 23622#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23470#L1121 assume !(0 == ~M_E~0); 23244#L1121-2 assume !(0 == ~T1_E~0); 22606#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22607#L1131-1 assume !(0 == ~T3_E~0); 22775#L1136-1 assume !(0 == ~T4_E~0); 22881#L1141-1 assume !(0 == ~T5_E~0); 23104#L1146-1 assume !(0 == ~T6_E~0); 23402#L1151-1 assume !(0 == ~T7_E~0); 22945#L1156-1 assume !(0 == ~T8_E~0); 22313#L1161-1 assume !(0 == ~T9_E~0); 22314#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22536#L1171-1 assume !(0 == ~T11_E~0); 22537#L1176-1 assume !(0 == ~E_M~0); 23415#L1181-1 assume !(0 == ~E_1~0); 23535#L1186-1 assume !(0 == ~E_2~0); 23585#L1191-1 assume !(0 == ~E_3~0); 22567#L1196-1 assume !(0 == ~E_4~0); 22568#L1201-1 assume !(0 == ~E_5~0); 23782#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 23623#L1211-1 assume !(0 == ~E_7~0); 23624#L1216-1 assume !(0 == ~E_8~0); 22705#L1221-1 assume !(0 == ~E_9~0); 22706#L1226-1 assume !(0 == ~E_10~0); 22413#L1231-1 assume !(0 == ~E_11~0); 22414#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23416#L556 assume 1 == ~m_pc~0; 23417#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22287#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22288#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23078#L1391 assume !(0 != activate_threads_~tmp~1#1); 23562#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23563#L575 assume !(1 == ~t1_pc~0); 22240#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22241#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22380#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22719#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 22674#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22675#L594 assume 1 == ~t2_pc~0; 22609#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22610#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22608#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22302#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 22303#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22369#L613 assume !(1 == ~t3_pc~0); 22484#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22483#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22834#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23102#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 23103#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22806#L632 assume 1 == ~t4_pc~0; 22807#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23321#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22319#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22320#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 23421#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23181#L651 assume 1 == ~t5_pc~0; 23182#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22498#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22499#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23075#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 22513#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22514#L670 assume !(1 == ~t6_pc~0); 23606#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22864#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22599#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22600#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23146#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23147#L689 assume 1 == ~t7_pc~0; 23778#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23262#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23263#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23621#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 23048#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23049#L708 assume !(1 == ~t8_pc~0); 22604#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22605#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23709#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23697#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 22661#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22662#L727 assume 1 == ~t9_pc~0; 22785#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22371#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22650#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22651#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 23770#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22715#L746 assume !(1 == ~t10_pc~0); 22716#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23376#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23489#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23658#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 23566#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22890#L765 assume 1 == ~t11_pc~0; 22891#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23094#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23716#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23604#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 23605#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23693#L1249 assume !(1 == ~M_E~0); 23325#L1249-2 assume !(1 == ~T1_E~0); 22980#L1254-1 assume !(1 == ~T2_E~0); 22298#L1259-1 assume !(1 == ~T3_E~0); 22280#L1264-1 assume !(1 == ~T4_E~0); 22281#L1269-1 assume !(1 == ~T5_E~0); 23808#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23750#L1279-1 assume !(1 == ~T7_E~0); 22485#L1284-1 assume !(1 == ~T8_E~0); 22486#L1289-1 assume !(1 == ~T9_E~0); 23028#L1294-1 assume !(1 == ~T10_E~0); 23029#L1299-1 assume !(1 == ~T11_E~0); 23038#L1304-1 assume !(1 == ~E_M~0); 23800#L1309-1 assume !(1 == ~E_1~0); 23802#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22434#L1319-1 assume !(1 == ~E_3~0); 22435#L1324-1 assume !(1 == ~E_4~0); 22560#L1329-1 assume !(1 == ~E_5~0); 22561#L1334-1 assume !(1 == ~E_6~0); 23653#L1339-1 assume !(1 == ~E_7~0); 23723#L1344-1 assume !(1 == ~E_8~0); 23724#L1349-1 assume !(1 == ~E_9~0); 23164#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 23165#L1359-1 assume !(1 == ~E_11~0); 23513#L1364-1 assume { :end_inline_reset_delta_events } true; 22647#L1690-2 [2023-11-21 21:03:34,809 INFO L750 eck$LassoCheckResult]: Loop: 22647#L1690-2 assume !false; 22648#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23008#L1096-1 assume !false; 23787#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22389#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22390#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23419#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22888#L937 assume !(0 != eval_~tmp~0#1); 22889#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22750#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22751#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22861#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23772#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23071#L1131-3 assume !(0 == ~T3_E~0); 23072#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23809#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23422#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22602#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22603#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23719#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23245#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23246#L1171-3 assume !(0 == ~T11_E~0); 23283#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22643#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22644#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23360#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23361#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23544#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23545#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23265#L1211-3 assume !(0 == ~E_7~0); 22556#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22557#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22992#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22617#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22618#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22843#L556-39 assume 1 == ~m_pc~0; 23368#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23339#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23212#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22900#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 22901#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23293#L575-39 assume 1 == ~t1_pc~0; 23294#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23549#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23550#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23791#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23275#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23276#L594-39 assume !(1 == ~t2_pc~0); 23472#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 23278#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22960#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22961#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22776#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22777#L613-39 assume 1 == ~t3_pc~0; 23676#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22256#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22257#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23480#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22365#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22366#L632-39 assume 1 == ~t4_pc~0; 23639#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22957#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22958#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23119#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23637#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22626#L651-39 assume 1 == ~t5_pc~0; 22627#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22397#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23140#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23141#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23764#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23785#L670-39 assume !(1 == ~t6_pc~0); 23370#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 22304#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22305#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23101#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22988#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22989#L689-39 assume !(1 == ~t7_pc~0); 23108#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 23109#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23125#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23463#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22500#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22501#L708-39 assume 1 == ~t8_pc~0; 22439#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22440#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23039#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23537#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23432#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22929#L727-39 assume !(1 == ~t9_pc~0); 22930#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 22689#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22331#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22332#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 23476#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23477#L746-39 assume 1 == ~t10_pc~0; 23450#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23451#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23715#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23199#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23200#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23595#L765-39 assume 1 == ~t11_pc~0; 22308#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22310#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23166#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22645#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22646#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23238#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22460#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22461#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23718#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23352#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22417#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22418#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23749#L1279-3 assume !(1 == ~T7_E~0); 22905#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22906#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22898#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22899#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23158#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23159#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22804#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22805#L1319-3 assume !(1 == ~E_3~0); 23559#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22523#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22524#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23085#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23086#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23300#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22782#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22783#L1359-3 assume !(1 == ~E_11~0); 23320#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22381#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22382#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22558#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 22559#L1709 assume !(0 == start_simulation_~tmp~3#1); 22812#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23579#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22493#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22268#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 22269#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22458#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23284#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 23668#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 22647#L1690-2 [2023-11-21 21:03:34,810 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:34,811 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2023-11-21 21:03:34,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:34,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127987146] [2023-11-21 21:03:34,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:34,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:34,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:34,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:34,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:34,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [127987146] [2023-11-21 21:03:34,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [127987146] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:34,867 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:34,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:34,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2146211944] [2023-11-21 21:03:34,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:34,871 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:34,872 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:34,872 INFO L85 PathProgramCache]: Analyzing trace with hash -1355425216, now seen corresponding path program 2 times [2023-11-21 21:03:34,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:34,874 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402432653] [2023-11-21 21:03:34,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:34,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:34,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:34,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:34,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:34,996 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402432653] [2023-11-21 21:03:34,996 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402432653] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:34,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:34,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:35,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921038483] [2023-11-21 21:03:35,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:35,000 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:35,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:35,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:35,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:35,001 INFO L87 Difference]: Start difference. First operand 1583 states and 2340 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:35,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:35,043 INFO L93 Difference]: Finished difference Result 1583 states and 2339 transitions. [2023-11-21 21:03:35,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2339 transitions. [2023-11-21 21:03:35,054 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:35,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1583 states and 2339 transitions. [2023-11-21 21:03:35,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:35,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:35,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2339 transitions. [2023-11-21 21:03:35,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:35,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2339 transitions. [2023-11-21 21:03:35,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2339 transitions. [2023-11-21 21:03:35,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:35,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.4775742261528744) internal successors, (2339), 1582 states have internal predecessors, (2339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:35,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2339 transitions. [2023-11-21 21:03:35,111 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2339 transitions. [2023-11-21 21:03:35,112 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:35,114 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2339 transitions. [2023-11-21 21:03:35,114 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-21 21:03:35,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2339 transitions. [2023-11-21 21:03:35,121 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:35,122 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:35,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:35,124 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:35,125 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:35,125 INFO L748 eck$LassoCheckResult]: Stem: 25639#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25640#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26368#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26369#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26507#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 26508#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25504#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25505#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26942#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26475#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26476#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26745#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26746#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26845#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26915#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26916#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26795#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26643#L1121 assume !(0 == ~M_E~0); 26417#L1121-2 assume !(0 == ~T1_E~0); 25779#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25780#L1131-1 assume !(0 == ~T3_E~0); 25948#L1136-1 assume !(0 == ~T4_E~0); 26054#L1141-1 assume !(0 == ~T5_E~0); 26282#L1146-1 assume !(0 == ~T6_E~0); 26575#L1151-1 assume !(0 == ~T7_E~0); 26118#L1156-1 assume !(0 == ~T8_E~0); 25486#L1161-1 assume !(0 == ~T9_E~0); 25487#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25709#L1171-1 assume !(0 == ~T11_E~0); 25710#L1176-1 assume !(0 == ~E_M~0); 26588#L1181-1 assume !(0 == ~E_1~0); 26708#L1186-1 assume !(0 == ~E_2~0); 26758#L1191-1 assume !(0 == ~E_3~0); 25740#L1196-1 assume !(0 == ~E_4~0); 25741#L1201-1 assume !(0 == ~E_5~0); 26955#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 26796#L1211-1 assume !(0 == ~E_7~0); 26797#L1216-1 assume !(0 == ~E_8~0); 25878#L1221-1 assume !(0 == ~E_9~0); 25879#L1226-1 assume !(0 == ~E_10~0); 25586#L1231-1 assume !(0 == ~E_11~0); 25587#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26589#L556 assume 1 == ~m_pc~0; 26590#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25460#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25461#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26251#L1391 assume !(0 != activate_threads_~tmp~1#1); 26736#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26737#L575 assume !(1 == ~t1_pc~0); 25413#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25414#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25553#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25892#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 25847#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25848#L594 assume 1 == ~t2_pc~0; 25782#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25783#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25781#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25477#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 25478#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25542#L613 assume !(1 == ~t3_pc~0); 25657#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25656#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26007#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26275#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 26276#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25979#L632 assume 1 == ~t4_pc~0; 25980#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26494#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25494#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25495#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 26594#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26354#L651 assume 1 == ~t5_pc~0; 26355#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25671#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25672#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26248#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 25686#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25687#L670 assume !(1 == ~t6_pc~0); 26779#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26042#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25772#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25773#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26319#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26320#L689 assume 1 == ~t7_pc~0; 26951#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26435#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26436#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26794#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 26221#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26222#L708 assume !(1 == ~t8_pc~0); 25777#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25778#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26882#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26870#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 25834#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25835#L727 assume 1 == ~t9_pc~0; 25958#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25544#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25823#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25824#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 26943#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25889#L746 assume !(1 == ~t10_pc~0); 25890#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26549#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26662#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26831#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 26739#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26063#L765 assume 1 == ~t11_pc~0; 26064#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26267#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26889#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26777#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 26778#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26866#L1249 assume !(1 == ~M_E~0); 26499#L1249-2 assume !(1 == ~T1_E~0); 26153#L1254-1 assume !(1 == ~T2_E~0); 25471#L1259-1 assume !(1 == ~T3_E~0); 25453#L1264-1 assume !(1 == ~T4_E~0); 25454#L1269-1 assume !(1 == ~T5_E~0); 26981#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26923#L1279-1 assume !(1 == ~T7_E~0); 25658#L1284-1 assume !(1 == ~T8_E~0); 25659#L1289-1 assume !(1 == ~T9_E~0); 26201#L1294-1 assume !(1 == ~T10_E~0); 26202#L1299-1 assume !(1 == ~T11_E~0); 26211#L1304-1 assume !(1 == ~E_M~0); 26973#L1309-1 assume !(1 == ~E_1~0); 26975#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25607#L1319-1 assume !(1 == ~E_3~0); 25608#L1324-1 assume !(1 == ~E_4~0); 25733#L1329-1 assume !(1 == ~E_5~0); 25734#L1334-1 assume !(1 == ~E_6~0); 26826#L1339-1 assume !(1 == ~E_7~0); 26896#L1344-1 assume !(1 == ~E_8~0); 26897#L1349-1 assume !(1 == ~E_9~0); 26338#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26339#L1359-1 assume !(1 == ~E_11~0); 26686#L1364-1 assume { :end_inline_reset_delta_events } true; 25820#L1690-2 [2023-11-21 21:03:35,126 INFO L750 eck$LassoCheckResult]: Loop: 25820#L1690-2 assume !false; 25821#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26181#L1096-1 assume !false; 26960#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25562#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25563#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26592#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26061#L937 assume !(0 != eval_~tmp~0#1); 26062#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25923#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25924#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26036#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26945#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26244#L1131-3 assume !(0 == ~T3_E~0); 26245#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26982#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26595#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25775#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25776#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26892#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26418#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26419#L1171-3 assume !(0 == ~T11_E~0); 26457#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25816#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25817#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26533#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26534#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26717#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26718#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26438#L1211-3 assume !(0 == ~E_7~0); 25729#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25730#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26165#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25790#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25791#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26016#L556-39 assume 1 == ~m_pc~0; 26541#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26514#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26385#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26073#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 26074#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26466#L575-39 assume 1 == ~t1_pc~0; 26467#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26722#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26723#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26964#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26448#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26449#L594-39 assume !(1 == ~t2_pc~0); 26645#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 26450#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26133#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26134#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25949#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25950#L613-39 assume 1 == ~t3_pc~0; 26849#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25429#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25430#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26653#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25538#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25539#L632-39 assume 1 == ~t4_pc~0; 26812#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26130#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26131#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26292#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26810#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25798#L651-39 assume !(1 == ~t5_pc~0); 25569#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 25570#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26313#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26314#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26937#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26958#L670-39 assume !(1 == ~t6_pc~0); 26543#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 25475#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25476#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26274#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26161#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26162#L689-39 assume 1 == ~t7_pc~0; 26384#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26281#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26298#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26636#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25673#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25674#L708-39 assume 1 == ~t8_pc~0; 25612#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25613#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26212#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26710#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26605#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26102#L727-39 assume !(1 == ~t9_pc~0); 26103#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 25862#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25502#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25503#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 26649#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26650#L746-39 assume !(1 == ~t10_pc~0); 26625#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 26624#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26888#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26372#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26373#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26768#L765-39 assume 1 == ~t11_pc~0; 25481#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25483#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26337#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25818#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25819#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26411#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25633#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25634#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26891#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26525#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25590#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25591#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26922#L1279-3 assume !(1 == ~T7_E~0); 26078#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26079#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26069#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26070#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26331#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26332#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25973#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25974#L1319-3 assume !(1 == ~E_3~0); 26732#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25690#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25691#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26258#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26259#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26473#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25955#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25956#L1359-3 assume !(1 == ~E_11~0); 26493#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25554#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25555#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25731#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 25732#L1709 assume !(0 == start_simulation_~tmp~3#1); 25985#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26752#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25666#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25441#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 25442#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25631#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26456#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 26841#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 25820#L1690-2 [2023-11-21 21:03:35,126 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:35,127 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2023-11-21 21:03:35,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:35,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530797800] [2023-11-21 21:03:35,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:35,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:35,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:35,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:35,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:35,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [530797800] [2023-11-21 21:03:35,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [530797800] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:35,186 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:35,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:35,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935927362] [2023-11-21 21:03:35,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:35,187 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:35,187 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:35,187 INFO L85 PathProgramCache]: Analyzing trace with hash 1333223937, now seen corresponding path program 1 times [2023-11-21 21:03:35,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:35,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171130070] [2023-11-21 21:03:35,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:35,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:35,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:35,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:35,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:35,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171130070] [2023-11-21 21:03:35,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171130070] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:35,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:35,258 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:35,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074980721] [2023-11-21 21:03:35,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:35,258 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:35,259 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:35,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:35,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:35,259 INFO L87 Difference]: Start difference. First operand 1583 states and 2339 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:35,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:35,301 INFO L93 Difference]: Finished difference Result 1583 states and 2338 transitions. [2023-11-21 21:03:35,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2338 transitions. [2023-11-21 21:03:35,312 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:35,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1583 states and 2338 transitions. [2023-11-21 21:03:35,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:35,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:35,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2338 transitions. [2023-11-21 21:03:35,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:35,329 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2338 transitions. [2023-11-21 21:03:35,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2338 transitions. [2023-11-21 21:03:35,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:35,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.4769425142135186) internal successors, (2338), 1582 states have internal predecessors, (2338), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:35,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2338 transitions. [2023-11-21 21:03:35,367 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2338 transitions. [2023-11-21 21:03:35,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:35,369 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2338 transitions. [2023-11-21 21:03:35,370 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-21 21:03:35,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2338 transitions. [2023-11-21 21:03:35,376 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:35,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:35,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:35,379 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:35,379 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:35,380 INFO L748 eck$LassoCheckResult]: Stem: 28812#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 28813#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29539#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29540#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29680#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 29681#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28673#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28674#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30115#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29648#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29649#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29918#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29919#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30018#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30088#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30089#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29968#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29816#L1121 assume !(0 == ~M_E~0); 29590#L1121-2 assume !(0 == ~T1_E~0); 28952#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28953#L1131-1 assume !(0 == ~T3_E~0); 29121#L1136-1 assume !(0 == ~T4_E~0); 29227#L1141-1 assume !(0 == ~T5_E~0); 29450#L1146-1 assume !(0 == ~T6_E~0); 29748#L1151-1 assume !(0 == ~T7_E~0); 29291#L1156-1 assume !(0 == ~T8_E~0); 28659#L1161-1 assume !(0 == ~T9_E~0); 28660#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28882#L1171-1 assume !(0 == ~T11_E~0); 28883#L1176-1 assume !(0 == ~E_M~0); 29761#L1181-1 assume !(0 == ~E_1~0); 29881#L1186-1 assume !(0 == ~E_2~0); 29931#L1191-1 assume !(0 == ~E_3~0); 28913#L1196-1 assume !(0 == ~E_4~0); 28914#L1201-1 assume !(0 == ~E_5~0); 30128#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 29969#L1211-1 assume !(0 == ~E_7~0); 29970#L1216-1 assume !(0 == ~E_8~0); 29051#L1221-1 assume !(0 == ~E_9~0); 29052#L1226-1 assume !(0 == ~E_10~0); 28759#L1231-1 assume !(0 == ~E_11~0); 28760#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29762#L556 assume 1 == ~m_pc~0; 29763#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28633#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28634#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29424#L1391 assume !(0 != activate_threads_~tmp~1#1); 29908#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29909#L575 assume !(1 == ~t1_pc~0); 28586#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28587#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28726#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29065#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 29020#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29021#L594 assume 1 == ~t2_pc~0; 28955#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28956#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28954#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28648#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 28649#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28715#L613 assume !(1 == ~t3_pc~0); 28830#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28829#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29180#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29448#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 29449#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29152#L632 assume 1 == ~t4_pc~0; 29153#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29667#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28665#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28666#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 29767#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29527#L651 assume 1 == ~t5_pc~0; 29528#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28844#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28845#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29421#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 28859#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28860#L670 assume !(1 == ~t6_pc~0); 29952#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29210#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28945#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28946#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29492#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29493#L689 assume 1 == ~t7_pc~0; 30124#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29608#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29609#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29967#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 29394#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29395#L708 assume !(1 == ~t8_pc~0); 28950#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28951#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30055#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30043#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 29007#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29008#L727 assume 1 == ~t9_pc~0; 29131#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28717#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28996#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28997#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 30116#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29061#L746 assume !(1 == ~t10_pc~0); 29062#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29722#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29835#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30004#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 29912#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29236#L765 assume 1 == ~t11_pc~0; 29237#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29440#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30062#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29950#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 29951#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30039#L1249 assume !(1 == ~M_E~0); 29671#L1249-2 assume !(1 == ~T1_E~0); 29326#L1254-1 assume !(1 == ~T2_E~0); 28644#L1259-1 assume !(1 == ~T3_E~0); 28626#L1264-1 assume !(1 == ~T4_E~0); 28627#L1269-1 assume !(1 == ~T5_E~0); 30154#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30096#L1279-1 assume !(1 == ~T7_E~0); 28831#L1284-1 assume !(1 == ~T8_E~0); 28832#L1289-1 assume !(1 == ~T9_E~0); 29374#L1294-1 assume !(1 == ~T10_E~0); 29375#L1299-1 assume !(1 == ~T11_E~0); 29384#L1304-1 assume !(1 == ~E_M~0); 30146#L1309-1 assume !(1 == ~E_1~0); 30148#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28780#L1319-1 assume !(1 == ~E_3~0); 28781#L1324-1 assume !(1 == ~E_4~0); 28906#L1329-1 assume !(1 == ~E_5~0); 28907#L1334-1 assume !(1 == ~E_6~0); 29999#L1339-1 assume !(1 == ~E_7~0); 30069#L1344-1 assume !(1 == ~E_8~0); 30070#L1349-1 assume !(1 == ~E_9~0); 29510#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29511#L1359-1 assume !(1 == ~E_11~0); 29859#L1364-1 assume { :end_inline_reset_delta_events } true; 28993#L1690-2 [2023-11-21 21:03:35,380 INFO L750 eck$LassoCheckResult]: Loop: 28993#L1690-2 assume !false; 28994#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29354#L1096-1 assume !false; 30133#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28735#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28736#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29765#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29234#L937 assume !(0 != eval_~tmp~0#1); 29235#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29097#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29207#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30118#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29417#L1131-3 assume !(0 == ~T3_E~0); 29418#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30155#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29768#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28948#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28949#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30065#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29591#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29592#L1171-3 assume !(0 == ~T11_E~0); 29629#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28989#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28990#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29706#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29707#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29890#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29891#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29611#L1211-3 assume !(0 == ~E_7~0); 28902#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28903#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29338#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28963#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28964#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29189#L556-39 assume 1 == ~m_pc~0; 29714#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29685#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29558#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29246#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 29247#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29639#L575-39 assume 1 == ~t1_pc~0; 29640#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29895#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29896#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30137#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29621#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29622#L594-39 assume !(1 == ~t2_pc~0); 29818#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 29624#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29306#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29307#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29122#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29123#L613-39 assume 1 == ~t3_pc~0; 30022#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28602#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28603#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29826#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28711#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28712#L632-39 assume 1 == ~t4_pc~0; 29985#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29303#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29304#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29465#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29983#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28972#L651-39 assume !(1 == ~t5_pc~0); 28742#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 28743#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29486#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29487#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30110#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30131#L670-39 assume !(1 == ~t6_pc~0); 29716#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 28650#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28651#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29447#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29334#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29335#L689-39 assume 1 == ~t7_pc~0; 29557#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29455#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29471#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29809#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28846#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28847#L708-39 assume 1 == ~t8_pc~0; 28785#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28786#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29385#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29883#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29778#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29275#L727-39 assume !(1 == ~t9_pc~0); 29276#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 29035#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28677#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28678#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 29822#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29823#L746-39 assume 1 == ~t10_pc~0; 29796#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 29797#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30061#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29545#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29546#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29941#L765-39 assume 1 == ~t11_pc~0; 28654#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28656#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29512#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28991#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28992#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29584#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28806#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28807#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30064#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29698#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28763#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28764#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30095#L1279-3 assume !(1 == ~T7_E~0); 29251#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29252#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29244#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29245#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29504#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29505#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29150#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29151#L1319-3 assume !(1 == ~E_3~0); 29905#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28869#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28870#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29431#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29432#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29646#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29128#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29129#L1359-3 assume !(1 == ~E_11~0); 29666#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28727#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28728#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28904#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 28905#L1709 assume !(0 == start_simulation_~tmp~3#1); 29158#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29925#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28839#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28614#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 28615#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28804#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29630#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 30014#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 28993#L1690-2 [2023-11-21 21:03:35,381 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:35,381 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2023-11-21 21:03:35,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:35,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671129143] [2023-11-21 21:03:35,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:35,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:35,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:35,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:35,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:35,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671129143] [2023-11-21 21:03:35,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [671129143] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:35,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:35,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:35,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514683046] [2023-11-21 21:03:35,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:35,443 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:35,443 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:35,443 INFO L85 PathProgramCache]: Analyzing trace with hash -134979392, now seen corresponding path program 2 times [2023-11-21 21:03:35,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:35,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412891783] [2023-11-21 21:03:35,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:35,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:35,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:35,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:35,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:35,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412891783] [2023-11-21 21:03:35,518 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412891783] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:35,519 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:35,519 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:35,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [616415793] [2023-11-21 21:03:35,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:35,520 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:35,520 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:35,520 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:35,520 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:35,521 INFO L87 Difference]: Start difference. First operand 1583 states and 2338 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:35,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:35,568 INFO L93 Difference]: Finished difference Result 1583 states and 2337 transitions. [2023-11-21 21:03:35,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2337 transitions. [2023-11-21 21:03:35,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:35,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1583 states and 2337 transitions. [2023-11-21 21:03:35,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:35,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:35,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2337 transitions. [2023-11-21 21:03:35,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:35,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2337 transitions. [2023-11-21 21:03:35,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2337 transitions. [2023-11-21 21:03:35,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:35,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.476310802274163) internal successors, (2337), 1582 states have internal predecessors, (2337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:35,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2337 transitions. [2023-11-21 21:03:35,674 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2337 transitions. [2023-11-21 21:03:35,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:35,675 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2337 transitions. [2023-11-21 21:03:35,675 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-21 21:03:35,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2337 transitions. [2023-11-21 21:03:35,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:35,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:35,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:35,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:35,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:35,688 INFO L748 eck$LassoCheckResult]: Stem: 31985#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 31986#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32712#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32713#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32853#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 32854#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31846#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31847#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33288#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32821#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32822#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33091#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33092#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33191#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33261#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33262#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33141#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32989#L1121 assume !(0 == ~M_E~0); 32763#L1121-2 assume !(0 == ~T1_E~0); 32125#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32126#L1131-1 assume !(0 == ~T3_E~0); 32294#L1136-1 assume !(0 == ~T4_E~0); 32400#L1141-1 assume !(0 == ~T5_E~0); 32623#L1146-1 assume !(0 == ~T6_E~0); 32921#L1151-1 assume !(0 == ~T7_E~0); 32464#L1156-1 assume !(0 == ~T8_E~0); 31832#L1161-1 assume !(0 == ~T9_E~0); 31833#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32055#L1171-1 assume !(0 == ~T11_E~0); 32056#L1176-1 assume !(0 == ~E_M~0); 32934#L1181-1 assume !(0 == ~E_1~0); 33054#L1186-1 assume !(0 == ~E_2~0); 33104#L1191-1 assume !(0 == ~E_3~0); 32086#L1196-1 assume !(0 == ~E_4~0); 32087#L1201-1 assume !(0 == ~E_5~0); 33301#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 33142#L1211-1 assume !(0 == ~E_7~0); 33143#L1216-1 assume !(0 == ~E_8~0); 32224#L1221-1 assume !(0 == ~E_9~0); 32225#L1226-1 assume !(0 == ~E_10~0); 31932#L1231-1 assume !(0 == ~E_11~0); 31933#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32935#L556 assume 1 == ~m_pc~0; 32936#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31806#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31807#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32597#L1391 assume !(0 != activate_threads_~tmp~1#1); 33081#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33082#L575 assume !(1 == ~t1_pc~0); 31759#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31760#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31899#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32238#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 32193#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32194#L594 assume 1 == ~t2_pc~0; 32128#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32129#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32127#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31821#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 31822#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31888#L613 assume !(1 == ~t3_pc~0); 32003#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32002#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32353#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32621#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 32622#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32325#L632 assume 1 == ~t4_pc~0; 32326#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32840#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31838#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31839#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 32940#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32700#L651 assume 1 == ~t5_pc~0; 32701#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32017#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32018#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32594#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 32032#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32033#L670 assume !(1 == ~t6_pc~0); 33125#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 32383#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32118#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32119#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32665#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32666#L689 assume 1 == ~t7_pc~0; 33297#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32781#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32782#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33140#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 32567#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32568#L708 assume !(1 == ~t8_pc~0); 32123#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32124#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33228#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33216#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 32180#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32181#L727 assume 1 == ~t9_pc~0; 32304#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31890#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32169#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32170#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 33289#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32234#L746 assume !(1 == ~t10_pc~0); 32235#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32895#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33008#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33177#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 33085#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32409#L765 assume 1 == ~t11_pc~0; 32410#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32613#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33235#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33123#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 33124#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33212#L1249 assume !(1 == ~M_E~0); 32844#L1249-2 assume !(1 == ~T1_E~0); 32499#L1254-1 assume !(1 == ~T2_E~0); 31817#L1259-1 assume !(1 == ~T3_E~0); 31799#L1264-1 assume !(1 == ~T4_E~0); 31800#L1269-1 assume !(1 == ~T5_E~0); 33327#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33269#L1279-1 assume !(1 == ~T7_E~0); 32004#L1284-1 assume !(1 == ~T8_E~0); 32005#L1289-1 assume !(1 == ~T9_E~0); 32547#L1294-1 assume !(1 == ~T10_E~0); 32548#L1299-1 assume !(1 == ~T11_E~0); 32557#L1304-1 assume !(1 == ~E_M~0); 33319#L1309-1 assume !(1 == ~E_1~0); 33321#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 31953#L1319-1 assume !(1 == ~E_3~0); 31954#L1324-1 assume !(1 == ~E_4~0); 32079#L1329-1 assume !(1 == ~E_5~0); 32080#L1334-1 assume !(1 == ~E_6~0); 33172#L1339-1 assume !(1 == ~E_7~0); 33242#L1344-1 assume !(1 == ~E_8~0); 33243#L1349-1 assume !(1 == ~E_9~0); 32683#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32684#L1359-1 assume !(1 == ~E_11~0); 33032#L1364-1 assume { :end_inline_reset_delta_events } true; 32166#L1690-2 [2023-11-21 21:03:35,689 INFO L750 eck$LassoCheckResult]: Loop: 32166#L1690-2 assume !false; 32167#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32527#L1096-1 assume !false; 33306#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31908#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31909#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32938#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32407#L937 assume !(0 != eval_~tmp~0#1); 32408#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32269#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32270#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32380#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33291#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32590#L1131-3 assume !(0 == ~T3_E~0); 32591#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33328#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32941#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32121#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32122#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33238#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32764#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32765#L1171-3 assume !(0 == ~T11_E~0); 32802#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32162#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32163#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32879#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32880#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33063#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33064#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32784#L1211-3 assume !(0 == ~E_7~0); 32075#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32076#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32511#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32136#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32137#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32362#L556-39 assume 1 == ~m_pc~0; 32887#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32858#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32731#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32419#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 32420#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32812#L575-39 assume 1 == ~t1_pc~0; 32813#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33068#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33069#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33310#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32794#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32795#L594-39 assume 1 == ~t2_pc~0; 32992#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32797#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32479#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32480#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32295#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32296#L613-39 assume 1 == ~t3_pc~0; 33195#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31775#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31776#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32999#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31884#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31885#L632-39 assume 1 == ~t4_pc~0; 33158#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32476#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32477#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32638#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33156#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32145#L651-39 assume 1 == ~t5_pc~0; 32146#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31916#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32659#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32660#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33283#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33304#L670-39 assume !(1 == ~t6_pc~0); 32889#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 31823#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31824#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32620#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32507#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32508#L689-39 assume !(1 == ~t7_pc~0); 32627#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 32628#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32644#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32982#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32019#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32020#L708-39 assume 1 == ~t8_pc~0; 31958#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31959#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32558#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33056#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32951#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32448#L727-39 assume !(1 == ~t9_pc~0); 32449#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 32208#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31850#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31851#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 32995#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32996#L746-39 assume 1 == ~t10_pc~0; 32969#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32970#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33234#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32718#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32719#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33114#L765-39 assume 1 == ~t11_pc~0; 31827#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31829#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32685#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32164#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32165#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32757#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31979#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31980#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33237#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32871#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31936#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31937#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33268#L1279-3 assume !(1 == ~T7_E~0); 32424#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32425#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32417#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32418#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32677#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32678#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32323#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32324#L1319-3 assume !(1 == ~E_3~0); 33078#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32042#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32043#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32604#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32605#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32819#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32301#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32302#L1359-3 assume !(1 == ~E_11~0); 32839#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31900#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31901#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32077#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 32078#L1709 assume !(0 == start_simulation_~tmp~3#1); 32331#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33098#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32012#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31787#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 31788#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31977#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32803#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 33187#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 32166#L1690-2 [2023-11-21 21:03:35,689 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:35,690 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2023-11-21 21:03:35,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:35,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075307611] [2023-11-21 21:03:35,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:35,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:35,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:35,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:35,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:35,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075307611] [2023-11-21 21:03:35,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075307611] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:35,764 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:35,764 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:35,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114255141] [2023-11-21 21:03:35,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:35,765 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:35,765 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:35,765 INFO L85 PathProgramCache]: Analyzing trace with hash 505986815, now seen corresponding path program 1 times [2023-11-21 21:03:35,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:35,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462938994] [2023-11-21 21:03:35,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:35,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:35,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:35,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:35,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:35,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462938994] [2023-11-21 21:03:35,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1462938994] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:35,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:35,872 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:35,873 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1257203399] [2023-11-21 21:03:35,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:35,873 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:35,874 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:35,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:35,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:35,875 INFO L87 Difference]: Start difference. First operand 1583 states and 2337 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:35,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:35,920 INFO L93 Difference]: Finished difference Result 1583 states and 2336 transitions. [2023-11-21 21:03:35,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2336 transitions. [2023-11-21 21:03:35,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:35,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1583 states and 2336 transitions. [2023-11-21 21:03:35,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2023-11-21 21:03:35,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1583 [2023-11-21 21:03:35,944 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1583 states and 2336 transitions. [2023-11-21 21:03:35,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:35,946 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2336 transitions. [2023-11-21 21:03:35,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states and 2336 transitions. [2023-11-21 21:03:35,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1583. [2023-11-21 21:03:35,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1583 states, 1583 states have (on average 1.4756790903348074) internal successors, (2336), 1582 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:35,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1583 states to 1583 states and 2336 transitions. [2023-11-21 21:03:35,982 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1583 states and 2336 transitions. [2023-11-21 21:03:35,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:35,983 INFO L428 stractBuchiCegarLoop]: Abstraction has 1583 states and 2336 transitions. [2023-11-21 21:03:35,984 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-21 21:03:35,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1583 states and 2336 transitions. [2023-11-21 21:03:35,990 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1432 [2023-11-21 21:03:35,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:35,991 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:35,993 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:35,993 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:35,994 INFO L748 eck$LassoCheckResult]: Stem: 35158#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35159#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35885#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35886#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36026#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 36027#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35019#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35020#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36461#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35994#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35995#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36264#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36265#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36364#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36434#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36435#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36314#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36162#L1121 assume !(0 == ~M_E~0); 35936#L1121-2 assume !(0 == ~T1_E~0); 35298#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35299#L1131-1 assume !(0 == ~T3_E~0); 35467#L1136-1 assume !(0 == ~T4_E~0); 35573#L1141-1 assume !(0 == ~T5_E~0); 35796#L1146-1 assume !(0 == ~T6_E~0); 36094#L1151-1 assume !(0 == ~T7_E~0); 35637#L1156-1 assume !(0 == ~T8_E~0); 35005#L1161-1 assume !(0 == ~T9_E~0); 35006#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35228#L1171-1 assume !(0 == ~T11_E~0); 35229#L1176-1 assume !(0 == ~E_M~0); 36107#L1181-1 assume !(0 == ~E_1~0); 36227#L1186-1 assume !(0 == ~E_2~0); 36277#L1191-1 assume !(0 == ~E_3~0); 35259#L1196-1 assume !(0 == ~E_4~0); 35260#L1201-1 assume !(0 == ~E_5~0); 36474#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 36315#L1211-1 assume !(0 == ~E_7~0); 36316#L1216-1 assume !(0 == ~E_8~0); 35397#L1221-1 assume !(0 == ~E_9~0); 35398#L1226-1 assume !(0 == ~E_10~0); 35105#L1231-1 assume !(0 == ~E_11~0); 35106#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36108#L556 assume 1 == ~m_pc~0; 36109#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 34979#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34980#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35770#L1391 assume !(0 != activate_threads_~tmp~1#1); 36254#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36255#L575 assume !(1 == ~t1_pc~0); 34932#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34933#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35072#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35411#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 35366#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35367#L594 assume 1 == ~t2_pc~0; 35301#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35302#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35300#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34994#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 34995#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35061#L613 assume !(1 == ~t3_pc~0); 35176#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35175#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35526#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35794#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 35795#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35498#L632 assume 1 == ~t4_pc~0; 35499#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36013#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35011#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35012#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 36113#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35873#L651 assume 1 == ~t5_pc~0; 35874#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35190#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35191#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35767#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 35205#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35206#L670 assume !(1 == ~t6_pc~0); 36298#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35556#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35291#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35292#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35838#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35839#L689 assume 1 == ~t7_pc~0; 36470#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35954#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35955#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36313#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 35740#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35741#L708 assume !(1 == ~t8_pc~0); 35296#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35297#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36401#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36389#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 35353#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35354#L727 assume 1 == ~t9_pc~0; 35477#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35063#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35342#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35343#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 36462#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35407#L746 assume !(1 == ~t10_pc~0); 35408#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36068#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36181#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36350#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 36258#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35582#L765 assume 1 == ~t11_pc~0; 35583#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35786#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36408#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36296#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 36297#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36385#L1249 assume !(1 == ~M_E~0); 36017#L1249-2 assume !(1 == ~T1_E~0); 35672#L1254-1 assume !(1 == ~T2_E~0); 34990#L1259-1 assume !(1 == ~T3_E~0); 34972#L1264-1 assume !(1 == ~T4_E~0); 34973#L1269-1 assume !(1 == ~T5_E~0); 36500#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36442#L1279-1 assume !(1 == ~T7_E~0); 35177#L1284-1 assume !(1 == ~T8_E~0); 35178#L1289-1 assume !(1 == ~T9_E~0); 35720#L1294-1 assume !(1 == ~T10_E~0); 35721#L1299-1 assume !(1 == ~T11_E~0); 35730#L1304-1 assume !(1 == ~E_M~0); 36492#L1309-1 assume !(1 == ~E_1~0); 36494#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 35126#L1319-1 assume !(1 == ~E_3~0); 35127#L1324-1 assume !(1 == ~E_4~0); 35252#L1329-1 assume !(1 == ~E_5~0); 35253#L1334-1 assume !(1 == ~E_6~0); 36345#L1339-1 assume !(1 == ~E_7~0); 36415#L1344-1 assume !(1 == ~E_8~0); 36416#L1349-1 assume !(1 == ~E_9~0); 35856#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35857#L1359-1 assume !(1 == ~E_11~0); 36205#L1364-1 assume { :end_inline_reset_delta_events } true; 35339#L1690-2 [2023-11-21 21:03:35,994 INFO L750 eck$LassoCheckResult]: Loop: 35339#L1690-2 assume !false; 35340#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35700#L1096-1 assume !false; 36479#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35081#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35082#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36111#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35580#L937 assume !(0 != eval_~tmp~0#1); 35581#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35442#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35443#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35553#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36464#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35763#L1131-3 assume !(0 == ~T3_E~0); 35764#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36501#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36114#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35294#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35295#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36411#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35937#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35938#L1171-3 assume !(0 == ~T11_E~0); 35975#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35335#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35336#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36052#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36053#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36236#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36237#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35957#L1211-3 assume !(0 == ~E_7~0); 35248#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35249#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35684#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35309#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35310#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35535#L556-39 assume 1 == ~m_pc~0; 36060#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36031#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35904#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35592#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 35593#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35985#L575-39 assume 1 == ~t1_pc~0; 35986#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36241#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36242#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36483#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35967#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35968#L594-39 assume !(1 == ~t2_pc~0); 36164#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 35970#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35652#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35653#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35468#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35469#L613-39 assume 1 == ~t3_pc~0; 36368#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34948#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34949#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36172#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35057#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35058#L632-39 assume 1 == ~t4_pc~0; 36331#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35649#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35650#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35811#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36329#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35318#L651-39 assume !(1 == ~t5_pc~0); 35088#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 35089#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35832#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35833#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36456#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36477#L670-39 assume !(1 == ~t6_pc~0); 36062#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 34996#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34997#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35793#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35680#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35681#L689-39 assume !(1 == ~t7_pc~0); 35800#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 35801#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35817#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36155#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35192#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35193#L708-39 assume 1 == ~t8_pc~0; 35131#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35132#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35731#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36229#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36124#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35621#L727-39 assume !(1 == ~t9_pc~0); 35622#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 35381#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35023#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35024#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 36168#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36169#L746-39 assume !(1 == ~t10_pc~0); 36144#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 36143#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36407#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35891#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35892#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36287#L765-39 assume 1 == ~t11_pc~0; 35000#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35002#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35858#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35337#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35338#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35930#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35152#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35153#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36410#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36044#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35109#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35110#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36441#L1279-3 assume !(1 == ~T7_E~0); 35597#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35598#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35590#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35591#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35850#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35851#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35496#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35497#L1319-3 assume !(1 == ~E_3~0); 36251#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35215#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35216#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35777#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35778#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35992#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35474#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35475#L1359-3 assume !(1 == ~E_11~0); 36012#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35073#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35074#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35250#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 35251#L1709 assume !(0 == start_simulation_~tmp~3#1); 35504#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36271#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35185#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34960#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 34961#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35150#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35976#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 36360#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 35339#L1690-2 [2023-11-21 21:03:35,995 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:35,995 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2023-11-21 21:03:35,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:35,998 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303106893] [2023-11-21 21:03:35,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:35,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:36,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:36,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:36,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:36,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303106893] [2023-11-21 21:03:36,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [303106893] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:36,105 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:36,105 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:36,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1956707816] [2023-11-21 21:03:36,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:36,106 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:36,106 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:36,106 INFO L85 PathProgramCache]: Analyzing trace with hash -824249086, now seen corresponding path program 1 times [2023-11-21 21:03:36,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:36,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662934637] [2023-11-21 21:03:36,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:36,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:36,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:36,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:36,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:36,181 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662934637] [2023-11-21 21:03:36,181 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662934637] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:36,182 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:36,182 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:36,182 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938027925] [2023-11-21 21:03:36,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:36,183 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:36,183 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:36,183 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 21:03:36,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 21:03:36,184 INFO L87 Difference]: Start difference. First operand 1583 states and 2336 transitions. cyclomatic complexity: 754 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:36,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:36,388 INFO L93 Difference]: Finished difference Result 2929 states and 4307 transitions. [2023-11-21 21:03:36,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2929 states and 4307 transitions. [2023-11-21 21:03:36,403 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2754 [2023-11-21 21:03:36,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2929 states to 2929 states and 4307 transitions. [2023-11-21 21:03:36,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2929 [2023-11-21 21:03:36,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2929 [2023-11-21 21:03:36,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2929 states and 4307 transitions. [2023-11-21 21:03:36,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:36,431 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2929 states and 4307 transitions. [2023-11-21 21:03:36,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2929 states and 4307 transitions. [2023-11-21 21:03:36,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2929 to 2929. [2023-11-21 21:03:36,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2929 states, 2929 states have (on average 1.4704677364288152) internal successors, (4307), 2928 states have internal predecessors, (4307), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:36,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2929 states to 2929 states and 4307 transitions. [2023-11-21 21:03:36,561 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2929 states and 4307 transitions. [2023-11-21 21:03:36,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 21:03:36,562 INFO L428 stractBuchiCegarLoop]: Abstraction has 2929 states and 4307 transitions. [2023-11-21 21:03:36,562 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-21 21:03:36,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2929 states and 4307 transitions. [2023-11-21 21:03:36,575 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2754 [2023-11-21 21:03:36,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:36,575 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:36,578 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:36,578 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:36,579 INFO L748 eck$LassoCheckResult]: Stem: 39680#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 39681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40422#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40423#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40570#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 40571#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39545#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39546#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41071#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40536#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40537#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40840#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40841#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40952#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41035#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41036#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40896#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40723#L1121 assume !(0 == ~M_E~0); 40473#L1121-2 assume !(0 == ~T1_E~0); 39821#L1126-1 assume !(0 == ~T2_E~0); 39822#L1131-1 assume !(0 == ~T3_E~0); 39990#L1136-1 assume !(0 == ~T4_E~0); 40097#L1141-1 assume !(0 == ~T5_E~0); 40333#L1146-1 assume !(0 == ~T6_E~0); 40648#L1151-1 assume !(0 == ~T7_E~0); 40162#L1156-1 assume !(0 == ~T8_E~0); 39527#L1161-1 assume !(0 == ~T9_E~0); 39528#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39751#L1171-1 assume !(0 == ~T11_E~0); 39752#L1176-1 assume !(0 == ~E_M~0); 40663#L1181-1 assume !(0 == ~E_1~0); 40798#L1186-1 assume !(0 == ~E_2~0); 40853#L1191-1 assume !(0 == ~E_3~0); 39782#L1196-1 assume !(0 == ~E_4~0); 39783#L1201-1 assume !(0 == ~E_5~0); 41084#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 40897#L1211-1 assume !(0 == ~E_7~0); 40898#L1216-1 assume !(0 == ~E_8~0); 39923#L1221-1 assume !(0 == ~E_9~0); 39924#L1226-1 assume !(0 == ~E_10~0); 39627#L1231-1 assume !(0 == ~E_11~0); 39628#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40665#L556 assume 1 == ~m_pc~0; 40666#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39501#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39502#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40301#L1391 assume !(0 != activate_threads_~tmp~1#1); 40831#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40832#L575 assume !(1 == ~t1_pc~0); 39454#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39455#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39594#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39936#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 39889#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39890#L594 assume 1 == ~t2_pc~0; 39824#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39825#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39823#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39518#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 39519#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39583#L613 assume !(1 == ~t3_pc~0); 39698#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39697#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40049#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40326#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 40327#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40021#L632 assume 1 == ~t4_pc~0; 40022#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40555#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39537#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39538#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 40670#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40407#L651 assume 1 == ~t5_pc~0; 40408#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39713#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39714#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40298#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 39728#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39729#L670 assume !(1 == ~t6_pc~0); 40876#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40085#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39815#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39816#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40372#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40373#L689 assume 1 == ~t7_pc~0; 41080#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40492#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40493#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40895#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 40270#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40271#L708 assume !(1 == ~t8_pc~0); 39819#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39820#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40995#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40979#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 39876#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39877#L727 assume 1 == ~t9_pc~0; 40000#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39585#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39865#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39866#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 41073#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39931#L746 assume !(1 == ~t10_pc~0); 39932#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40617#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40742#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40937#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 40834#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40110#L765 assume 1 == ~t11_pc~0; 40111#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40318#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41001#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40873#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 40874#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40974#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 40562#L1249-2 assume !(1 == ~T1_E~0); 40197#L1254-1 assume !(1 == ~T2_E~0); 40198#L1259-1 assume !(1 == ~T3_E~0); 41318#L1264-1 assume !(1 == ~T4_E~0); 41316#L1269-1 assume !(1 == ~T5_E~0); 41315#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41048#L1279-1 assume !(1 == ~T7_E~0); 39699#L1284-1 assume !(1 == ~T8_E~0); 39700#L1289-1 assume !(1 == ~T9_E~0); 40250#L1294-1 assume !(1 == ~T10_E~0); 40251#L1299-1 assume !(1 == ~T11_E~0); 40260#L1304-1 assume !(1 == ~E_M~0); 41106#L1309-1 assume !(1 == ~E_1~0); 41108#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 39648#L1319-1 assume !(1 == ~E_3~0); 39649#L1324-1 assume !(1 == ~E_4~0); 39775#L1329-1 assume !(1 == ~E_5~0); 39776#L1334-1 assume !(1 == ~E_6~0); 40932#L1339-1 assume !(1 == ~E_7~0); 41008#L1344-1 assume !(1 == ~E_8~0); 41009#L1349-1 assume !(1 == ~E_9~0); 40389#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 40390#L1359-1 assume !(1 == ~E_11~0); 40769#L1364-1 assume { :end_inline_reset_delta_events } true; 40948#L1690-2 [2023-11-21 21:03:36,579 INFO L750 eck$LassoCheckResult]: Loop: 40948#L1690-2 assume !false; 40787#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40228#L1096-1 assume !false; 41089#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41114#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40668#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40669#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40104#L937 assume !(0 != eval_~tmp~0#1); 40106#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39968#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39969#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41123#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41074#L1126-3 assume !(0 == ~T2_E~0); 40294#L1131-3 assume !(0 == ~T3_E~0); 40295#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41118#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40671#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39817#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39818#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41004#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40474#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40475#L1171-3 assume !(0 == ~T11_E~0); 40513#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39858#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39859#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40599#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40600#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40808#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40809#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40495#L1211-3 assume !(0 == ~E_7~0); 39771#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39772#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40210#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39832#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39833#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40058#L556-39 assume 1 == ~m_pc~0; 40609#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40575#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40441#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40117#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 40118#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40526#L575-39 assume !(1 == ~t1_pc~0); 40528#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 40813#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40814#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41094#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40505#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40506#L594-39 assume !(1 == ~t2_pc~0); 40725#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 40508#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40177#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40178#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39991#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39992#L613-39 assume 1 == ~t3_pc~0; 40956#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39470#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39471#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40733#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39579#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39580#L632-39 assume 1 == ~t4_pc~0; 40914#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40174#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40175#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40343#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40912#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39841#L651-39 assume 1 == ~t5_pc~0; 39842#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39611#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40364#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40365#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41063#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41087#L670-39 assume 1 == ~t6_pc~0; 41088#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39516#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39517#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40325#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40206#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40207#L689-39 assume 1 == ~t7_pc~0; 40440#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40332#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40349#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40716#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39715#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39716#L708-39 assume 1 == ~t8_pc~0; 39653#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39654#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40261#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40800#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40681#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40146#L727-39 assume !(1 == ~t9_pc~0); 40147#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 39904#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39543#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39544#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 40729#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40730#L746-39 assume 1 == ~t10_pc~0; 40701#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40702#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41000#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40425#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40426#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40864#L765-39 assume 1 == ~t11_pc~0; 39522#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39524#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40388#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39860#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39861#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40467#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39674#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39675#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41003#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40590#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39631#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39632#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41046#L1279-3 assume !(1 == ~T7_E~0); 40122#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40123#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40115#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40116#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40382#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40383#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40019#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40020#L1319-3 assume !(1 == ~E_3~0); 40823#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39735#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39736#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40308#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40309#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40533#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39997#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39998#L1359-3 assume !(1 == ~E_11~0); 40554#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 39595#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39596#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39773#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 39774#L1709 assume !(0 == start_simulation_~tmp~3#1); 40027#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40847#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39708#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39482#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 39483#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39672#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40514#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 40947#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 40948#L1690-2 [2023-11-21 21:03:36,580 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:36,580 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2023-11-21 21:03:36,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:36,581 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409144419] [2023-11-21 21:03:36,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:36,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:36,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:36,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:36,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:36,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409144419] [2023-11-21 21:03:36,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409144419] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:36,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:36,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:36,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091460616] [2023-11-21 21:03:36,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:36,683 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:36,683 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:36,683 INFO L85 PathProgramCache]: Analyzing trace with hash 1274259517, now seen corresponding path program 1 times [2023-11-21 21:03:36,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:36,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081283581] [2023-11-21 21:03:36,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:36,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:36,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:36,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:36,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:36,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081283581] [2023-11-21 21:03:36,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2081283581] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:36,747 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:36,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:36,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918869768] [2023-11-21 21:03:36,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:36,748 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:36,748 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:36,749 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 21:03:36,749 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 21:03:36,750 INFO L87 Difference]: Start difference. First operand 2929 states and 4307 transitions. cyclomatic complexity: 1380 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:36,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:36,892 INFO L93 Difference]: Finished difference Result 5609 states and 8226 transitions. [2023-11-21 21:03:36,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5609 states and 8226 transitions. [2023-11-21 21:03:36,922 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5398 [2023-11-21 21:03:36,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5609 states to 5609 states and 8226 transitions. [2023-11-21 21:03:36,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5609 [2023-11-21 21:03:36,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5609 [2023-11-21 21:03:36,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5609 states and 8226 transitions. [2023-11-21 21:03:36,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:36,980 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5609 states and 8226 transitions. [2023-11-21 21:03:36,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5609 states and 8226 transitions. [2023-11-21 21:03:37,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5609 to 5609. [2023-11-21 21:03:37,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5609 states, 5609 states have (on average 1.4665715813870566) internal successors, (8226), 5608 states have internal predecessors, (8226), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:37,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5609 states to 5609 states and 8226 transitions. [2023-11-21 21:03:37,119 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5609 states and 8226 transitions. [2023-11-21 21:03:37,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 21:03:37,121 INFO L428 stractBuchiCegarLoop]: Abstraction has 5609 states and 8226 transitions. [2023-11-21 21:03:37,121 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-21 21:03:37,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5609 states and 8226 transitions. [2023-11-21 21:03:37,144 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5398 [2023-11-21 21:03:37,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:37,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:37,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:37,148 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:37,148 INFO L748 eck$LassoCheckResult]: Stem: 48229#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 48230#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 48960#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48961#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49105#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 49106#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48090#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48091#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49561#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49072#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49073#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49348#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49349#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49454#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49527#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49528#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49402#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49243#L1121 assume !(0 == ~M_E~0); 49014#L1121-2 assume !(0 == ~T1_E~0); 48370#L1126-1 assume !(0 == ~T2_E~0); 48371#L1131-1 assume !(0 == ~T3_E~0); 48540#L1136-1 assume !(0 == ~T4_E~0); 48646#L1141-1 assume !(0 == ~T5_E~0); 48871#L1146-1 assume !(0 == ~T6_E~0); 49175#L1151-1 assume !(0 == ~T7_E~0); 48711#L1156-1 assume !(0 == ~T8_E~0); 48076#L1161-1 assume !(0 == ~T9_E~0); 48077#L1166-1 assume !(0 == ~T10_E~0); 48300#L1171-1 assume !(0 == ~T11_E~0); 48301#L1176-1 assume !(0 == ~E_M~0); 49188#L1181-1 assume !(0 == ~E_1~0); 49310#L1186-1 assume !(0 == ~E_2~0); 49362#L1191-1 assume !(0 == ~E_3~0); 48331#L1196-1 assume !(0 == ~E_4~0); 48332#L1201-1 assume !(0 == ~E_5~0); 49575#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 49403#L1211-1 assume !(0 == ~E_7~0); 49404#L1216-1 assume !(0 == ~E_8~0); 48470#L1221-1 assume !(0 == ~E_9~0); 48471#L1226-1 assume !(0 == ~E_10~0); 48176#L1231-1 assume !(0 == ~E_11~0); 48177#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49189#L556 assume 1 == ~m_pc~0; 49190#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48049#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48050#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48845#L1391 assume !(0 != activate_threads_~tmp~1#1); 49337#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49338#L575 assume !(1 == ~t1_pc~0); 48002#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48003#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48484#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 48438#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48439#L594 assume 1 == ~t2_pc~0; 48373#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48374#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48372#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48065#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 48066#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48132#L613 assume !(1 == ~t3_pc~0); 48247#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48246#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48599#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48869#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 48870#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48571#L632 assume 1 == ~t4_pc~0; 48572#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49091#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48082#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48083#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 49194#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48948#L651 assume 1 == ~t5_pc~0; 48949#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48262#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48263#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48842#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 48277#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48278#L670 assume !(1 == ~t6_pc~0); 49385#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48629#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48363#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48364#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48913#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48914#L689 assume 1 == ~t7_pc~0; 49571#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49032#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49033#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49401#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 48815#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48816#L708 assume !(1 == ~t8_pc~0); 48368#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48369#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49494#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49480#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 48425#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48426#L727 assume 1 == ~t9_pc~0; 48550#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48134#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48414#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48415#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 49562#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48480#L746 assume !(1 == ~t10_pc~0); 48481#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49148#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49262#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49439#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 49341#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48655#L765 assume 1 == ~t11_pc~0; 48656#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48861#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49501#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49383#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 49384#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49475#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 49476#L1249-2 assume !(1 == ~T1_E~0); 48746#L1254-1 assume !(1 == ~T2_E~0); 48060#L1259-1 assume !(1 == ~T3_E~0); 48061#L1264-1 assume !(1 == ~T4_E~0); 49612#L1269-1 assume !(1 == ~T5_E~0); 49613#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49535#L1279-1 assume !(1 == ~T7_E~0); 49536#L1284-1 assume !(1 == ~T8_E~0); 49579#L1289-1 assume !(1 == ~T9_E~0); 49580#L1294-1 assume !(1 == ~T10_E~0); 50362#L1299-1 assume !(1 == ~T11_E~0); 50357#L1304-1 assume !(1 == ~E_M~0); 50353#L1309-1 assume !(1 == ~E_1~0); 49837#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 49811#L1319-1 assume !(1 == ~E_3~0); 49788#L1324-1 assume !(1 == ~E_4~0); 49755#L1329-1 assume !(1 == ~E_5~0); 49719#L1334-1 assume !(1 == ~E_6~0); 49698#L1339-1 assume !(1 == ~E_7~0); 49696#L1344-1 assume !(1 == ~E_8~0); 49695#L1349-1 assume !(1 == ~E_9~0); 49674#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 49662#L1359-1 assume !(1 == ~E_11~0); 49653#L1364-1 assume { :end_inline_reset_delta_events } true; 49645#L1690-2 [2023-11-21 21:03:37,149 INFO L750 eck$LassoCheckResult]: Loop: 49645#L1690-2 assume !false; 49639#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49635#L1096-1 assume !false; 49634#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49624#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49621#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49620#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49618#L937 assume !(0 != eval_~tmp~0#1); 49617#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49616#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49614#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49615#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53559#L1126-3 assume !(0 == ~T2_E~0); 53558#L1131-3 assume !(0 == ~T3_E~0); 53557#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53556#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53555#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53554#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53553#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53552#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53551#L1166-3 assume !(0 == ~T10_E~0); 53550#L1171-3 assume !(0 == ~T11_E~0); 53549#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53548#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53547#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53546#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53545#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53544#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53543#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53542#L1211-3 assume !(0 == ~E_7~0); 53541#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53540#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53539#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53538#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 53537#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53536#L556-39 assume 1 == ~m_pc~0; 53534#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53533#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53532#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53531#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 53530#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53529#L575-39 assume 1 == ~t1_pc~0; 53527#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53526#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53525#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53524#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53523#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53522#L594-39 assume 1 == ~t2_pc~0; 53520#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53519#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53518#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53517#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53516#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53515#L613-39 assume 1 == ~t3_pc~0; 53513#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53512#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53511#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53510#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53509#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53508#L632-39 assume !(1 == ~t4_pc~0); 53506#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 53505#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53504#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53503#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53502#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53501#L651-39 assume 1 == ~t5_pc~0; 53499#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53498#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53497#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53496#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53495#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53494#L670-39 assume !(1 == ~t6_pc~0); 53492#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 53491#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53490#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53489#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53488#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53487#L689-39 assume !(1 == ~t7_pc~0); 48875#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 48876#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48892#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49236#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48264#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48265#L708-39 assume 1 == ~t8_pc~0; 48202#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48203#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48806#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49312#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49205#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48695#L727-39 assume !(1 == ~t9_pc~0); 48696#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 48453#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48454#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50839#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 50831#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49370#L746-39 assume 1 == ~t10_pc~0; 49223#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49224#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50806#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50798#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50791#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50785#L765-39 assume !(1 == ~t11_pc~0); 50777#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 50770#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50764#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50756#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50749#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50743#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49008#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50732#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50726#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50719#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50713#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50708#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50703#L1279-3 assume !(1 == ~T7_E~0); 50698#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49556#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49557#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50685#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50683#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50681#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50679#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50677#L1319-3 assume !(1 == ~E_3~0); 50674#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50672#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50670#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50668#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50666#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50664#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50661#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50522#L1359-3 assume !(1 == ~E_11~0); 50520#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49858#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49825#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49801#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49799#L1709 assume !(0 == start_simulation_~tmp~3#1); 48577#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49738#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49734#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49712#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 49691#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49673#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49661#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 49652#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 49645#L1690-2 [2023-11-21 21:03:37,150 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:37,150 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2023-11-21 21:03:37,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:37,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440059432] [2023-11-21 21:03:37,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:37,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:37,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:37,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:37,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:37,284 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440059432] [2023-11-21 21:03:37,284 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440059432] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:37,285 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:37,285 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:37,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583336694] [2023-11-21 21:03:37,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:37,286 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:37,288 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:37,288 INFO L85 PathProgramCache]: Analyzing trace with hash -1871779523, now seen corresponding path program 1 times [2023-11-21 21:03:37,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:37,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [893892166] [2023-11-21 21:03:37,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:37,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:37,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:37,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:37,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:37,361 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [893892166] [2023-11-21 21:03:37,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [893892166] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:37,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:37,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:37,362 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734945008] [2023-11-21 21:03:37,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:37,362 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:37,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:37,363 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 21:03:37,363 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 21:03:37,364 INFO L87 Difference]: Start difference. First operand 5609 states and 8226 transitions. cyclomatic complexity: 2621 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:37,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:37,605 INFO L93 Difference]: Finished difference Result 10589 states and 15497 transitions. [2023-11-21 21:03:37,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10589 states and 15497 transitions. [2023-11-21 21:03:37,660 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10342 [2023-11-21 21:03:37,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10589 states to 10589 states and 15497 transitions. [2023-11-21 21:03:37,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10589 [2023-11-21 21:03:37,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10589 [2023-11-21 21:03:37,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10589 states and 15497 transitions. [2023-11-21 21:03:37,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:37,722 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10589 states and 15497 transitions. [2023-11-21 21:03:37,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10589 states and 15497 transitions. [2023-11-21 21:03:37,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10589 to 10585. [2023-11-21 21:03:37,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10585 states, 10585 states have (on average 1.463675011809164) internal successors, (15493), 10584 states have internal predecessors, (15493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:37,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10585 states to 10585 states and 15493 transitions. [2023-11-21 21:03:37,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10585 states and 15493 transitions. [2023-11-21 21:03:37,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 21:03:37,916 INFO L428 stractBuchiCegarLoop]: Abstraction has 10585 states and 15493 transitions. [2023-11-21 21:03:37,916 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-21 21:03:37,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10585 states and 15493 transitions. [2023-11-21 21:03:37,954 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10342 [2023-11-21 21:03:37,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:37,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:37,958 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:37,958 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:37,959 INFO L748 eck$LassoCheckResult]: Stem: 64437#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 64438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 65172#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65173#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65320#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 65321#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64298#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64299#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65785#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65288#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65289#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65571#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65572#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65676#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 65754#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 65755#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 65623#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65463#L1121 assume !(0 == ~M_E~0); 65227#L1121-2 assume !(0 == ~T1_E~0); 64577#L1126-1 assume !(0 == ~T2_E~0); 64578#L1131-1 assume !(0 == ~T3_E~0); 64747#L1136-1 assume !(0 == ~T4_E~0); 64853#L1141-1 assume !(0 == ~T5_E~0); 65082#L1146-1 assume !(0 == ~T6_E~0); 65393#L1151-1 assume !(0 == ~T7_E~0); 64917#L1156-1 assume !(0 == ~T8_E~0); 64284#L1161-1 assume !(0 == ~T9_E~0); 64285#L1166-1 assume !(0 == ~T10_E~0); 64507#L1171-1 assume !(0 == ~T11_E~0); 64508#L1176-1 assume !(0 == ~E_M~0); 65406#L1181-1 assume !(0 == ~E_1~0); 65533#L1186-1 assume !(0 == ~E_2~0); 65584#L1191-1 assume !(0 == ~E_3~0); 64538#L1196-1 assume !(0 == ~E_4~0); 64539#L1201-1 assume !(0 == ~E_5~0); 65801#L1206-1 assume !(0 == ~E_6~0); 65624#L1211-1 assume !(0 == ~E_7~0); 65625#L1216-1 assume !(0 == ~E_8~0); 64676#L1221-1 assume !(0 == ~E_9~0); 64677#L1226-1 assume !(0 == ~E_10~0); 64384#L1231-1 assume !(0 == ~E_11~0); 64385#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65407#L556 assume 1 == ~m_pc~0; 65408#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 64257#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64258#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65054#L1391 assume !(0 != activate_threads_~tmp~1#1); 65561#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65562#L575 assume !(1 == ~t1_pc~0); 64210#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64211#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64351#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64690#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 64645#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64646#L594 assume 1 == ~t2_pc~0; 64580#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64581#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64579#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64273#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 64274#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64340#L613 assume !(1 == ~t3_pc~0); 64455#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64454#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64806#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65080#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 65081#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64778#L632 assume 1 == ~t4_pc~0; 64779#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65307#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64290#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64291#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 65412#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65160#L651 assume 1 == ~t5_pc~0; 65161#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64469#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64470#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65051#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 64484#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64485#L670 assume !(1 == ~t6_pc~0); 65606#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64836#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64570#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64571#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65125#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65126#L689 assume 1 == ~t7_pc~0; 65796#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65245#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65246#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65622#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 65024#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65025#L708 assume !(1 == ~t8_pc~0); 64575#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64576#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65716#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65703#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 64632#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64633#L727 assume 1 == ~t9_pc~0; 64757#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64342#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64621#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64622#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 65786#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64686#L746 assume !(1 == ~t10_pc~0); 64687#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 65366#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65483#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65661#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 65565#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64862#L765 assume 1 == ~t11_pc~0; 64863#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65071#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65725#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65604#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 65605#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65698#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 65311#L1249-2 assume !(1 == ~T1_E~0); 64954#L1254-1 assume !(1 == ~T2_E~0); 64955#L1259-1 assume !(1 == ~T3_E~0); 66240#L1264-1 assume !(1 == ~T4_E~0); 66238#L1269-1 assume !(1 == ~T5_E~0); 66235#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66187#L1279-1 assume !(1 == ~T7_E~0); 66185#L1284-1 assume !(1 == ~T8_E~0); 66144#L1289-1 assume !(1 == ~T9_E~0); 66142#L1294-1 assume !(1 == ~T10_E~0); 66140#L1299-1 assume !(1 == ~T11_E~0); 66090#L1304-1 assume !(1 == ~E_M~0); 66088#L1309-1 assume !(1 == ~E_1~0); 66042#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 66040#L1319-1 assume !(1 == ~E_3~0); 66038#L1324-1 assume !(1 == ~E_4~0); 66010#L1329-1 assume !(1 == ~E_5~0); 66006#L1334-1 assume !(1 == ~E_6~0); 65958#L1339-1 assume !(1 == ~E_7~0); 65954#L1344-1 assume !(1 == ~E_8~0); 65950#L1349-1 assume !(1 == ~E_9~0); 65913#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65897#L1359-1 assume !(1 == ~E_11~0); 65888#L1364-1 assume { :end_inline_reset_delta_events } true; 65880#L1690-2 [2023-11-21 21:03:37,959 INFO L750 eck$LassoCheckResult]: Loop: 65880#L1690-2 assume !false; 65874#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65870#L1096-1 assume !false; 65869#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65859#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65856#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65855#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65853#L937 assume !(0 != eval_~tmp~0#1); 65852#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65851#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65850#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65845#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65790#L1126-3 assume !(0 == ~T2_E~0); 65047#L1131-3 assume !(0 == ~T3_E~0); 65048#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65843#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65413#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64573#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64574#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 65729#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 65228#L1166-3 assume !(0 == ~T10_E~0); 65229#L1171-3 assume !(0 == ~T11_E~0); 65268#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 64614#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64615#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65349#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65350#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 65543#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65544#L1206-3 assume !(0 == ~E_6~0); 65249#L1211-3 assume !(0 == ~E_7~0); 64527#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64528#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 64967#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 64588#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 64589#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64815#L556-39 assume 1 == ~m_pc~0; 65357#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 65325#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65192#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64872#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 64873#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65278#L575-39 assume !(1 == ~t1_pc~0); 65280#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 65548#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65549#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65815#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65260#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65261#L594-39 assume !(1 == ~t2_pc~0); 65465#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 65263#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64932#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64933#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64748#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64749#L613-39 assume !(1 == ~t3_pc~0); 65681#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 64226#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64227#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65473#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65474#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66870#L632-39 assume !(1 == ~t4_pc~0); 66867#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 66865#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66863#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66861#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66858#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66856#L651-39 assume 1 == ~t5_pc~0; 66787#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66785#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66783#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66781#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 66778#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66776#L670-39 assume 1 == ~t6_pc~0; 66703#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66699#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66696#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66694#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66692#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66691#L689-39 assume !(1 == ~t7_pc~0); 66627#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 66623#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66621#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66619#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66618#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66556#L708-39 assume !(1 == ~t8_pc~0); 66553#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 66551#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66549#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66547#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66545#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66542#L727-39 assume !(1 == ~t9_pc~0); 66539#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 66536#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66494#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66492#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 66490#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66424#L746-39 assume 1 == ~t10_pc~0; 66421#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 66418#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66416#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66414#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66412#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66410#L765-39 assume !(1 == ~t11_pc~0); 66407#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 66404#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66402#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66400#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66398#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66396#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 65221#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66346#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66342#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66340#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66279#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66276#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66211#L1279-3 assume !(1 == ~T7_E~0); 66209#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66205#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 66203#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 66199#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 66198#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66161#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66159#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66157#L1319-3 assume !(1 == ~E_3~0); 66154#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66152#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66123#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 66119#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66117#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 66115#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 66114#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 66113#L1359-3 assume !(1 == ~E_11~0); 66110#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 66063#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 66015#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65967#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65965#L1709 assume !(0 == start_simulation_~tmp~3#1); 64784#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65931#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65927#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 65924#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65909#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65896#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 65887#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 65880#L1690-2 [2023-11-21 21:03:37,960 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:37,960 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2023-11-21 21:03:37,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:37,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707537185] [2023-11-21 21:03:37,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:37,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:37,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:38,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:38,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:38,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [707537185] [2023-11-21 21:03:38,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [707537185] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:38,082 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:38,082 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 21:03:38,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795617325] [2023-11-21 21:03:38,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:38,083 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:38,083 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:38,083 INFO L85 PathProgramCache]: Analyzing trace with hash 280209726, now seen corresponding path program 1 times [2023-11-21 21:03:38,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:38,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158647526] [2023-11-21 21:03:38,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:38,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:38,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:38,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:38,145 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:38,145 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158647526] [2023-11-21 21:03:38,145 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [158647526] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:38,145 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:38,145 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:38,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017125953] [2023-11-21 21:03:38,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:38,146 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:38,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:38,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:38,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:38,147 INFO L87 Difference]: Start difference. First operand 10585 states and 15493 transitions. cyclomatic complexity: 4916 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:38,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:38,352 INFO L93 Difference]: Finished difference Result 20769 states and 30174 transitions. [2023-11-21 21:03:38,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20769 states and 30174 transitions. [2023-11-21 21:03:38,448 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20511 [2023-11-21 21:03:38,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20769 states to 20769 states and 30174 transitions. [2023-11-21 21:03:38,525 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20769 [2023-11-21 21:03:38,546 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20769 [2023-11-21 21:03:38,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20769 states and 30174 transitions. [2023-11-21 21:03:38,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:38,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20769 states and 30174 transitions. [2023-11-21 21:03:38,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20769 states and 30174 transitions. [2023-11-21 21:03:39,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20769 to 20105. [2023-11-21 21:03:39,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20105 states, 20105 states have (on average 1.4542651081820444) internal successors, (29238), 20104 states have internal predecessors, (29238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:39,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20105 states to 20105 states and 29238 transitions. [2023-11-21 21:03:39,260 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20105 states and 29238 transitions. [2023-11-21 21:03:39,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:39,261 INFO L428 stractBuchiCegarLoop]: Abstraction has 20105 states and 29238 transitions. [2023-11-21 21:03:39,261 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-21 21:03:39,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20105 states and 29238 transitions. [2023-11-21 21:03:39,345 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19847 [2023-11-21 21:03:39,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:39,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:39,349 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:39,349 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:39,350 INFO L748 eck$LassoCheckResult]: Stem: 95798#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 95799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 96548#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96549#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96716#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 96717#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95658#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95659#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97299#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96681#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96682#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96999#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 97000#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97134#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97242#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97243#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97071#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96875#L1121 assume !(0 == ~M_E~0); 96610#L1121-2 assume !(0 == ~T1_E~0); 95937#L1126-1 assume !(0 == ~T2_E~0); 95938#L1131-1 assume !(0 == ~T3_E~0); 96111#L1136-1 assume !(0 == ~T4_E~0); 96220#L1141-1 assume !(0 == ~T5_E~0); 96455#L1146-1 assume !(0 == ~T6_E~0); 96795#L1151-1 assume !(0 == ~T7_E~0); 96286#L1156-1 assume !(0 == ~T8_E~0); 95644#L1161-1 assume !(0 == ~T9_E~0); 95645#L1166-1 assume !(0 == ~T10_E~0); 95866#L1171-1 assume !(0 == ~T11_E~0); 95867#L1176-1 assume !(0 == ~E_M~0); 96810#L1181-1 assume !(0 == ~E_1~0); 96954#L1186-1 assume !(0 == ~E_2~0); 97017#L1191-1 assume !(0 == ~E_3~0); 95898#L1196-1 assume !(0 == ~E_4~0); 95899#L1201-1 assume !(0 == ~E_5~0); 97335#L1206-1 assume !(0 == ~E_6~0); 97072#L1211-1 assume !(0 == ~E_7~0); 97073#L1216-1 assume !(0 == ~E_8~0); 96039#L1221-1 assume !(0 == ~E_9~0); 96040#L1226-1 assume !(0 == ~E_10~0); 95744#L1231-1 assume !(0 == ~E_11~0); 95745#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96811#L556 assume !(1 == ~m_pc~0); 96812#L556-2 is_master_triggered_~__retres1~0#1 := 0; 95617#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95618#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96426#L1391 assume !(0 != activate_threads_~tmp~1#1); 96988#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96989#L575 assume !(1 == ~t1_pc~0); 95571#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95572#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95711#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96053#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 96006#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96007#L594 assume 1 == ~t2_pc~0; 95940#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95941#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95939#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95633#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 95634#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95700#L613 assume !(1 == ~t3_pc~0); 95816#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95815#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96172#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96453#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 96454#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96144#L632 assume 1 == ~t4_pc~0; 96145#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 96700#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95651#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 96817#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96535#L651 assume 1 == ~t5_pc~0; 96536#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95830#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95831#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96423#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 95844#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95845#L670 assume !(1 == ~t6_pc~0); 97047#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 96202#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95930#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 95931#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96499#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96500#L689 assume 1 == ~t7_pc~0; 97323#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 96629#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96630#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97070#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 96396#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96397#L708 assume !(1 == ~t8_pc~0); 95935#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95936#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 97189#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97172#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 95993#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95994#L727 assume 1 == ~t9_pc~0; 96122#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 95702#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95982#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95983#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 97300#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 96049#L746 assume !(1 == ~t10_pc~0); 96050#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 96769#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96897#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97116#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 96992#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 96229#L765 assume 1 == ~t11_pc~0; 96230#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 96443#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 97201#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 97044#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 97045#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97166#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 97167#L1249-2 assume !(1 == ~T1_E~0); 96322#L1254-1 assume !(1 == ~T2_E~0); 96323#L1259-1 assume !(1 == ~T3_E~0); 98687#L1264-1 assume !(1 == ~T4_E~0); 98683#L1269-1 assume !(1 == ~T5_E~0); 98678#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98674#L1279-1 assume !(1 == ~T7_E~0); 98668#L1284-1 assume !(1 == ~T8_E~0); 98664#L1289-1 assume !(1 == ~T9_E~0); 98659#L1294-1 assume !(1 == ~T10_E~0); 98652#L1299-1 assume !(1 == ~T11_E~0); 98647#L1304-1 assume !(1 == ~E_M~0); 98646#L1309-1 assume !(1 == ~E_1~0); 98644#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 98633#L1319-1 assume !(1 == ~E_3~0); 98625#L1324-1 assume !(1 == ~E_4~0); 98617#L1329-1 assume !(1 == ~E_5~0); 98610#L1334-1 assume !(1 == ~E_6~0); 98604#L1339-1 assume !(1 == ~E_7~0); 98575#L1344-1 assume !(1 == ~E_8~0); 98559#L1349-1 assume !(1 == ~E_9~0); 98542#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 98530#L1359-1 assume !(1 == ~E_11~0); 98521#L1364-1 assume { :end_inline_reset_delta_events } true; 98513#L1690-2 [2023-11-21 21:03:39,351 INFO L750 eck$LassoCheckResult]: Loop: 98513#L1690-2 assume !false; 98507#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 98503#L1096-1 assume !false; 98502#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 98492#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 98489#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 98488#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 98486#L937 assume !(0 != eval_~tmp~0#1); 98485#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98484#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 98481#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 98482#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 100254#L1126-3 assume !(0 == ~T2_E~0); 100252#L1131-3 assume !(0 == ~T3_E~0); 100250#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 100248#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 100245#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 100243#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 100241#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 100239#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 100084#L1166-3 assume !(0 == ~T10_E~0); 100080#L1171-3 assume !(0 == ~T11_E~0); 100076#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 100072#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 100042#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 100028#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100018#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 100009#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 100001#L1206-3 assume !(0 == ~E_6~0); 99996#L1211-3 assume !(0 == ~E_7~0); 99991#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 99989#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 99987#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 99986#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 99973#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99971#L556-39 assume !(1 == ~m_pc~0); 99870#L556-41 is_master_triggered_~__retres1~0#1 := 0; 99868#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99866#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 99864#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 99862#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99860#L575-39 assume 1 == ~t1_pc~0; 99857#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 99855#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99853#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 99851#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99849#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99848#L594-39 assume 1 == ~t2_pc~0; 99785#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 99751#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99709#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 99596#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99593#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99591#L613-39 assume !(1 == ~t3_pc~0); 99589#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 99515#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99513#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 99510#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 99508#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99506#L632-39 assume 1 == ~t4_pc~0; 99449#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99446#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99443#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 99441#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 99439#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99437#L651-39 assume !(1 == ~t5_pc~0); 99435#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 99432#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99429#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 99427#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 99425#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 99423#L670-39 assume !(1 == ~t6_pc~0); 99417#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 99415#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99413#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 99411#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 99409#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99407#L689-39 assume 1 == ~t7_pc~0; 99369#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 99367#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 99365#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 99362#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 99360#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 99323#L708-39 assume 1 == ~t8_pc~0; 99321#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 99296#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99288#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99280#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 99274#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 99248#L727-39 assume 1 == ~t9_pc~0; 99205#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 99202#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 99200#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99198#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 99196#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 99187#L746-39 assume 1 == ~t10_pc~0; 99181#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 99176#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 99171#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 99140#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 99137#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 99135#L765-39 assume !(1 == ~t11_pc~0); 99131#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 99115#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99109#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 99103#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 99063#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99060#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 98399#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 99032#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98394#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99017#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 99010#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 99004#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98997#L1279-3 assume !(1 == ~T7_E~0); 98991#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 98985#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 98979#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 98970#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 98966#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98961#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 98957#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 98953#L1319-3 assume !(1 == ~E_3~0); 98949#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98944#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98940#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 98934#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 98932#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 98931#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 98930#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 98929#L1359-3 assume !(1 == ~E_11~0); 98928#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 98925#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 98915#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 98914#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 98913#L1709 assume !(0 == start_simulation_~tmp~3#1); 96150#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 98579#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 98576#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 98560#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 98543#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98541#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98529#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 98520#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 98513#L1690-2 [2023-11-21 21:03:39,352 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:39,352 INFO L85 PathProgramCache]: Analyzing trace with hash -1258502475, now seen corresponding path program 1 times [2023-11-21 21:03:39,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:39,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637404271] [2023-11-21 21:03:39,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:39,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:39,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:39,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:39,451 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:39,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637404271] [2023-11-21 21:03:39,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637404271] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:39,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:39,452 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 21:03:39,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1554550584] [2023-11-21 21:03:39,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:39,453 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:39,453 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:39,454 INFO L85 PathProgramCache]: Analyzing trace with hash -784116485, now seen corresponding path program 1 times [2023-11-21 21:03:39,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:39,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440312998] [2023-11-21 21:03:39,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:39,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:39,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:39,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:39,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:39,539 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440312998] [2023-11-21 21:03:39,539 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [440312998] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:39,539 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:39,539 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:39,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066716776] [2023-11-21 21:03:39,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:39,540 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:39,541 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:39,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:39,541 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:39,542 INFO L87 Difference]: Start difference. First operand 20105 states and 29238 transitions. cyclomatic complexity: 9149 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:39,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:39,936 INFO L93 Difference]: Finished difference Result 38405 states and 55572 transitions. [2023-11-21 21:03:39,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38405 states and 55572 transitions. [2023-11-21 21:03:40,236 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 38100 [2023-11-21 21:03:40,502 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38405 states to 38405 states and 55572 transitions. [2023-11-21 21:03:40,503 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38405 [2023-11-21 21:03:40,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38405 [2023-11-21 21:03:40,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38405 states and 55572 transitions. [2023-11-21 21:03:40,585 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:40,585 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38405 states and 55572 transitions. [2023-11-21 21:03:40,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38405 states and 55572 transitions. [2023-11-21 21:03:41,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38405 to 38373. [2023-11-21 21:03:41,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38373 states, 38373 states have (on average 1.447371849998697) internal successors, (55540), 38372 states have internal predecessors, (55540), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:41,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38373 states to 38373 states and 55540 transitions. [2023-11-21 21:03:41,449 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38373 states and 55540 transitions. [2023-11-21 21:03:41,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:41,450 INFO L428 stractBuchiCegarLoop]: Abstraction has 38373 states and 55540 transitions. [2023-11-21 21:03:41,450 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-21 21:03:41,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38373 states and 55540 transitions. [2023-11-21 21:03:41,662 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 38068 [2023-11-21 21:03:41,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:41,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:41,665 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:41,665 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:41,666 INFO L748 eck$LassoCheckResult]: Stem: 154313#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 154314#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 155055#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155056#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 155207#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 155208#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154179#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154180#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 155727#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 155173#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 155174#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 155481#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 155482#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 155598#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 155686#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 155687#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 155540#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 155361#L1121 assume !(0 == ~M_E~0); 155105#L1121-2 assume !(0 == ~T1_E~0); 154449#L1126-1 assume !(0 == ~T2_E~0); 154450#L1131-1 assume !(0 == ~T3_E~0); 154619#L1136-1 assume !(0 == ~T4_E~0); 154728#L1141-1 assume !(0 == ~T5_E~0); 154968#L1146-1 assume !(0 == ~T6_E~0); 155293#L1151-1 assume !(0 == ~T7_E~0); 154793#L1156-1 assume !(0 == ~T8_E~0); 154161#L1161-1 assume !(0 == ~T9_E~0); 154162#L1166-1 assume !(0 == ~T10_E~0); 154379#L1171-1 assume !(0 == ~T11_E~0); 154380#L1176-1 assume !(0 == ~E_M~0); 155305#L1181-1 assume !(0 == ~E_1~0); 155440#L1186-1 assume !(0 == ~E_2~0); 155501#L1191-1 assume !(0 == ~E_3~0); 154410#L1196-1 assume !(0 == ~E_4~0); 154411#L1201-1 assume !(0 == ~E_5~0); 155743#L1206-1 assume !(0 == ~E_6~0); 155541#L1211-1 assume !(0 == ~E_7~0); 155542#L1216-1 assume !(0 == ~E_8~0); 154549#L1221-1 assume !(0 == ~E_9~0); 154550#L1226-1 assume !(0 == ~E_10~0); 154261#L1231-1 assume !(0 == ~E_11~0); 154262#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155308#L556 assume !(1 == ~m_pc~0); 155309#L556-2 is_master_triggered_~__retres1~0#1 := 0; 154134#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154135#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 154935#L1391 assume !(0 != activate_threads_~tmp~1#1); 155471#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155472#L575 assume !(1 == ~t1_pc~0); 154088#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 154089#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 154228#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 154562#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 154515#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 154516#L594 assume !(1 == ~t2_pc~0); 155278#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 155375#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154451#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154152#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 154153#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 154217#L613 assume !(1 == ~t3_pc~0); 154330#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154329#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154679#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 154961#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 154962#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154651#L632 assume 1 == ~t4_pc~0; 154652#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 155193#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 154171#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154172#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 155310#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 155041#L651 assume 1 == ~t5_pc~0; 155042#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 154344#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154345#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 154932#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 154358#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154359#L670 assume !(1 == ~t6_pc~0); 155523#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 154715#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154443#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 154444#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 155005#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 155006#L689 assume 1 == ~t7_pc~0; 155738#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 155125#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 155126#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 155539#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 154905#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 154906#L708 assume !(1 == ~t8_pc~0); 154447#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 154448#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 155644#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 155630#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 154502#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 154503#L727 assume 1 == ~t9_pc~0; 154629#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 154219#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 154491#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 154492#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 155731#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 154557#L746 assume !(1 == ~t10_pc~0); 154558#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 155257#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 155385#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 155583#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 155475#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 154741#L765 assume 1 == ~t11_pc~0; 154742#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 154951#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 155655#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 155520#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 155521#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155625#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 155626#L1249-2 assume !(1 == ~T1_E~0); 154830#L1254-1 assume !(1 == ~T2_E~0); 154831#L1259-1 assume !(1 == ~T3_E~0); 181787#L1264-1 assume !(1 == ~T4_E~0); 181785#L1269-1 assume !(1 == ~T5_E~0); 181783#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 181781#L1279-1 assume !(1 == ~T7_E~0); 181778#L1284-1 assume !(1 == ~T8_E~0); 181776#L1289-1 assume !(1 == ~T9_E~0); 181774#L1294-1 assume !(1 == ~T10_E~0); 181772#L1299-1 assume !(1 == ~T11_E~0); 181770#L1304-1 assume !(1 == ~E_M~0); 181768#L1309-1 assume !(1 == ~E_1~0); 181765#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 181763#L1319-1 assume !(1 == ~E_3~0); 181761#L1324-1 assume !(1 == ~E_4~0); 181759#L1329-1 assume !(1 == ~E_5~0); 181757#L1334-1 assume !(1 == ~E_6~0); 181753#L1339-1 assume !(1 == ~E_7~0); 181750#L1344-1 assume !(1 == ~E_8~0); 181748#L1349-1 assume !(1 == ~E_9~0); 181746#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 181744#L1359-1 assume !(1 == ~E_11~0); 181742#L1364-1 assume { :end_inline_reset_delta_events } true; 181739#L1690-2 [2023-11-21 21:03:41,666 INFO L750 eck$LassoCheckResult]: Loop: 181739#L1690-2 assume !false; 181736#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 181731#L1096-1 assume !false; 181729#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 181683#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 181677#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 181670#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 181666#L937 assume !(0 != eval_~tmp~0#1); 154875#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 154594#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 154595#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 154709#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 155732#L1126-3 assume !(0 == ~T2_E~0); 154928#L1131-3 assume !(0 == ~T3_E~0); 154929#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 155791#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 155311#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 154445#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 154446#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 155658#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 155106#L1166-3 assume !(0 == ~T10_E~0); 155107#L1171-3 assume !(0 == ~T11_E~0); 155150#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 154484#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 154485#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 155237#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 155238#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 155452#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 155453#L1206-3 assume !(0 == ~E_6~0); 155129#L1211-3 assume !(0 == ~E_7~0); 154399#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 154400#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 154843#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 154457#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 154458#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 154689#L556-39 assume !(1 == ~m_pc~0); 155624#L556-41 is_master_triggered_~__retres1~0#1 := 0; 155212#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155073#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 154748#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 154749#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155162#L575-39 assume 1 == ~t1_pc~0; 155163#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 155457#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155458#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 155759#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 155140#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155141#L594-39 assume !(1 == ~t2_pc~0); 155367#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 155143#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154808#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154809#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 154620#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 154621#L613-39 assume 1 == ~t3_pc~0; 155602#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 154103#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154104#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 155376#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 154213#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154214#L632-39 assume 1 == ~t4_pc~0; 155562#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 154805#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 154806#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154978#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 155557#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154463#L651-39 assume 1 == ~t5_pc~0; 154464#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 154241#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 191438#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 155714#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 155715#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 155751#L670-39 assume !(1 == ~t6_pc~0); 155250#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 154150#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154151#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 154960#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 154839#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154840#L689-39 assume !(1 == ~t7_pc~0); 154963#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 154964#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 154984#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 155353#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 154346#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 154347#L708-39 assume !(1 == ~t8_pc~0); 154289#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 154288#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 154895#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 155442#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 155321#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 155322#L727-39 assume 1 == ~t9_pc~0; 181952#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 181950#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 181948#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 181946#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 181944#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 181942#L746-39 assume 1 == ~t10_pc~0; 181938#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 181936#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 181934#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 181932#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 181930#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 181928#L765-39 assume !(1 == ~t11_pc~0); 181924#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 181922#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 181920#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 181918#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 181916#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 181914#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 173096#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 181909#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 173091#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 181907#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 181905#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 181903#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 181901#L1279-3 assume !(1 == ~T7_E~0); 181899#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 181897#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 181893#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 181889#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 181887#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 181885#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 181883#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 181881#L1319-3 assume !(1 == ~E_3~0); 181879#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 181877#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 181876#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 181873#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 181872#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 181871#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 181870#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 181869#L1359-3 assume !(1 == ~E_11~0); 181868#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 181863#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 181852#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 181850#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 181818#L1709 assume !(0 == start_simulation_~tmp~3#1); 181817#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 181807#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 181804#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 181802#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 181800#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 181798#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 181796#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 181741#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 181739#L1690-2 [2023-11-21 21:03:41,667 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:41,667 INFO L85 PathProgramCache]: Analyzing trace with hash 1819278198, now seen corresponding path program 1 times [2023-11-21 21:03:41,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:41,667 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483831001] [2023-11-21 21:03:41,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:41,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:41,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:41,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:41,739 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:41,739 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483831001] [2023-11-21 21:03:41,739 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483831001] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:41,739 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:41,739 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 21:03:41,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942534220] [2023-11-21 21:03:41,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:41,740 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:41,740 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:41,741 INFO L85 PathProgramCache]: Analyzing trace with hash -1676594820, now seen corresponding path program 1 times [2023-11-21 21:03:41,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:41,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618495873] [2023-11-21 21:03:41,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:41,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:41,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:41,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:41,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:41,801 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1618495873] [2023-11-21 21:03:41,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1618495873] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:41,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:41,802 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:41,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007487261] [2023-11-21 21:03:41,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:41,802 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:41,802 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:41,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:41,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:41,803 INFO L87 Difference]: Start difference. First operand 38373 states and 55540 transitions. cyclomatic complexity: 17199 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:42,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:42,484 INFO L93 Difference]: Finished difference Result 73412 states and 105781 transitions. [2023-11-21 21:03:42,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73412 states and 105781 transitions. [2023-11-21 21:03:42,911 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 72980 [2023-11-21 21:03:43,272 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73412 states to 73412 states and 105781 transitions. [2023-11-21 21:03:43,272 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73412 [2023-11-21 21:03:43,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73412 [2023-11-21 21:03:43,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73412 states and 105781 transitions. [2023-11-21 21:03:43,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:43,445 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73412 states and 105781 transitions. [2023-11-21 21:03:43,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73412 states and 105781 transitions. [2023-11-21 21:03:44,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73412 to 73348. [2023-11-21 21:03:44,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73348 states, 73348 states have (on average 1.441307193106833) internal successors, (105717), 73347 states have internal predecessors, (105717), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:44,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73348 states to 73348 states and 105717 transitions. [2023-11-21 21:03:44,946 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73348 states and 105717 transitions. [2023-11-21 21:03:44,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:44,947 INFO L428 stractBuchiCegarLoop]: Abstraction has 73348 states and 105717 transitions. [2023-11-21 21:03:44,947 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-21 21:03:44,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73348 states and 105717 transitions. [2023-11-21 21:03:45,110 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 72916 [2023-11-21 21:03:45,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:45,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:45,113 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:45,113 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:45,114 INFO L748 eck$LassoCheckResult]: Stem: 266102#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 266103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 266836#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 266837#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 266993#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 266994#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 265968#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 265969#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 267561#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 266958#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 266959#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 267291#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 267292#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 267410#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 267509#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 267510#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 267352#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 267160#L1121 assume !(0 == ~M_E~0); 266891#L1121-2 assume !(0 == ~T1_E~0); 266239#L1126-1 assume !(0 == ~T2_E~0); 266240#L1131-1 assume !(0 == ~T3_E~0); 266406#L1136-1 assume !(0 == ~T4_E~0); 266512#L1141-1 assume !(0 == ~T5_E~0); 266744#L1146-1 assume !(0 == ~T6_E~0); 267080#L1151-1 assume !(0 == ~T7_E~0); 266578#L1156-1 assume !(0 == ~T8_E~0); 265952#L1161-1 assume !(0 == ~T9_E~0); 265953#L1166-1 assume !(0 == ~T10_E~0); 266168#L1171-1 assume !(0 == ~T11_E~0); 266169#L1176-1 assume !(0 == ~E_M~0); 267100#L1181-1 assume !(0 == ~E_1~0); 267248#L1186-1 assume !(0 == ~E_2~0); 267308#L1191-1 assume !(0 == ~E_3~0); 266200#L1196-1 assume !(0 == ~E_4~0); 266201#L1201-1 assume !(0 == ~E_5~0); 267589#L1206-1 assume !(0 == ~E_6~0); 267353#L1211-1 assume !(0 == ~E_7~0); 267354#L1216-1 assume !(0 == ~E_8~0); 266336#L1221-1 assume !(0 == ~E_9~0); 266337#L1226-1 assume !(0 == ~E_10~0); 266050#L1231-1 assume !(0 == ~E_11~0); 266051#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 267101#L556 assume !(1 == ~m_pc~0); 267102#L556-2 is_master_triggered_~__retres1~0#1 := 0; 265926#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 265927#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 266719#L1391 assume !(0 != activate_threads_~tmp~1#1); 267281#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 267282#L575 assume !(1 == ~t1_pc~0); 265880#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 265881#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 266018#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 266350#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 266305#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 266306#L594 assume !(1 == ~t2_pc~0); 267062#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 267176#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 266241#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 265941#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 265942#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 266008#L613 assume !(1 == ~t3_pc~0); 266119#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 266118#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 266465#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 266742#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 266743#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 266439#L632 assume !(1 == ~t4_pc~0); 266440#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 267161#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 265958#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 265959#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 267105#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 266825#L651 assume 1 == ~t5_pc~0; 266826#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 266132#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 266133#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 266716#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 266146#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 266147#L670 assume !(1 == ~t6_pc~0); 267332#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 266495#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 266232#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 266233#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 266788#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 266789#L689 assume 1 == ~t7_pc~0; 267579#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 266909#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 266910#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 267351#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 266689#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 266690#L708 assume !(1 == ~t8_pc~0); 266237#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 266238#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 267458#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 267443#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 266292#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 266293#L727 assume 1 == ~t9_pc~0; 266418#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 266010#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 266281#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 266282#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 267563#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 266346#L746 assume !(1 == ~t10_pc~0); 266347#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 267047#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 267186#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 267394#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 267285#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 266522#L765 assume 1 == ~t11_pc~0; 266523#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 266735#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 267474#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 267330#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 267331#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 267438#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 267439#L1249-2 assume !(1 == ~T1_E~0); 266616#L1254-1 assume !(1 == ~T2_E~0); 266617#L1259-1 assume !(1 == ~T3_E~0); 326505#L1264-1 assume !(1 == ~T4_E~0); 326504#L1269-1 assume !(1 == ~T5_E~0); 326501#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 267529#L1279-1 assume !(1 == ~T7_E~0); 266120#L1284-1 assume !(1 == ~T8_E~0); 266121#L1289-1 assume !(1 == ~T9_E~0); 266668#L1294-1 assume !(1 == ~T10_E~0); 266669#L1299-1 assume !(1 == ~T11_E~0); 266678#L1304-1 assume !(1 == ~E_M~0); 267633#L1309-1 assume !(1 == ~E_1~0); 267638#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 266071#L1319-1 assume !(1 == ~E_3~0); 266072#L1324-1 assume !(1 == ~E_4~0); 266193#L1329-1 assume !(1 == ~E_5~0); 266194#L1334-1 assume !(1 == ~E_6~0); 267389#L1339-1 assume !(1 == ~E_7~0); 267483#L1344-1 assume !(1 == ~E_8~0); 267484#L1349-1 assume !(1 == ~E_9~0); 266808#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 266809#L1359-1 assume !(1 == ~E_11~0); 267217#L1364-1 assume { :end_inline_reset_delta_events } true; 266278#L1690-2 [2023-11-21 21:03:45,114 INFO L750 eck$LassoCheckResult]: Loop: 266278#L1690-2 assume !false; 266279#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 266645#L1096-1 assume !false; 267602#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 266027#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 266028#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 267103#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 266519#L937 assume !(0 != eval_~tmp~0#1); 266521#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 337734#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 337733#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 337732#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 337730#L1126-3 assume !(0 == ~T2_E~0); 337727#L1131-3 assume !(0 == ~T3_E~0); 337725#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 337724#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 267107#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 266235#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 266236#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 337718#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 337717#L1166-3 assume !(0 == ~T10_E~0); 337713#L1171-3 assume !(0 == ~T11_E~0); 337712#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 337708#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 267515#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 267025#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 267026#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 337581#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 337580#L1206-3 assume !(0 == ~E_6~0); 337579#L1211-3 assume !(0 == ~E_7~0); 337578#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 337577#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 337576#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 337575#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 337574#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 267648#L556-39 assume !(1 == ~m_pc~0); 267434#L556-41 is_master_triggered_~__retres1~0#1 := 0; 266998#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 266856#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 266532#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 266533#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 266949#L575-39 assume 1 == ~t1_pc~0; 266950#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 267265#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 267266#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 267612#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 266926#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 266927#L594-39 assume !(1 == ~t2_pc~0); 267168#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 337638#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 337636#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 337634#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 337630#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 337627#L613-39 assume 1 == ~t3_pc~0; 337623#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 337621#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 337619#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 337616#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 337614#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 337611#L632-39 assume !(1 == ~t4_pc~0); 337609#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 335450#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 335449#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 335448#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 335447#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 335446#L651-39 assume !(1 == ~t5_pc~0); 335445#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 335443#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 335442#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 335441#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 335440#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 335439#L670-39 assume !(1 == ~t6_pc~0); 335437#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 335436#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 335435#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 335433#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 335431#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 335429#L689-39 assume !(1 == ~t7_pc~0); 335427#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 335424#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 335422#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 335420#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 335419#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 335417#L708-39 assume 1 == ~t8_pc~0; 335415#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 335412#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 335410#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 335408#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 335407#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 335406#L727-39 assume !(1 == ~t9_pc~0); 335405#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 335403#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 335402#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 334775#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 267170#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 267171#L746-39 assume !(1 == ~t10_pc~0); 267140#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 267139#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 267467#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 266841#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 266842#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 267321#L765-39 assume !(1 == ~t11_pc~0); 265948#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 265949#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 266807#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 266276#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 266277#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 266883#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 266884#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 336016#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 326683#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 336015#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 336014#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 336012#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 336010#L1279-3 assume !(1 == ~T7_E~0); 336008#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 336006#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 336001#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 314940#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 335999#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 335998#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 266433#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 266434#L1319-3 assume !(1 == ~E_3~0); 267276#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 266150#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 266151#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 266726#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 266727#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 266956#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 266414#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 266415#L1359-3 assume !(1 == ~E_11~0); 266976#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 266019#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 266020#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 266191#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 266192#L1709 assume !(0 == start_simulation_~tmp~3#1); 266444#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 267301#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 266128#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 265907#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 265908#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 266094#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 266937#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 267405#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 266278#L1690-2 [2023-11-21 21:03:45,115 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:45,115 INFO L85 PathProgramCache]: Analyzing trace with hash -343701065, now seen corresponding path program 1 times [2023-11-21 21:03:45,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:45,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63751016] [2023-11-21 21:03:45,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:45,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:45,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:45,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:45,179 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:45,179 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63751016] [2023-11-21 21:03:45,179 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63751016] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:45,179 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:45,179 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 21:03:45,180 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [513265858] [2023-11-21 21:03:45,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:45,180 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:45,180 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:45,181 INFO L85 PathProgramCache]: Analyzing trace with hash -204298817, now seen corresponding path program 1 times [2023-11-21 21:03:45,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:45,181 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284452434] [2023-11-21 21:03:45,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:45,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:45,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:45,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:45,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:45,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1284452434] [2023-11-21 21:03:45,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1284452434] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:45,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:45,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:45,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421128724] [2023-11-21 21:03:45,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:45,240 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:45,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:45,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 21:03:45,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 21:03:45,241 INFO L87 Difference]: Start difference. First operand 73348 states and 105717 transitions. cyclomatic complexity: 32433 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:46,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:46,200 INFO L93 Difference]: Finished difference Result 143007 states and 205102 transitions. [2023-11-21 21:03:46,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 143007 states and 205102 transitions. [2023-11-21 21:03:47,177 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 142256 [2023-11-21 21:03:48,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 143007 states to 143007 states and 205102 transitions. [2023-11-21 21:03:48,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 143007 [2023-11-21 21:03:48,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 143007 [2023-11-21 21:03:48,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 143007 states and 205102 transitions. [2023-11-21 21:03:48,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:48,282 INFO L218 hiAutomatonCegarLoop]: Abstraction has 143007 states and 205102 transitions. [2023-11-21 21:03:48,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143007 states and 205102 transitions. [2023-11-21 21:03:49,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143007 to 142879. [2023-11-21 21:03:49,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 142879 states, 142879 states have (on average 1.4345985064285165) internal successors, (204974), 142878 states have internal predecessors, (204974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:50,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142879 states to 142879 states and 204974 transitions. [2023-11-21 21:03:50,040 INFO L240 hiAutomatonCegarLoop]: Abstraction has 142879 states and 204974 transitions. [2023-11-21 21:03:50,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 21:03:50,041 INFO L428 stractBuchiCegarLoop]: Abstraction has 142879 states and 204974 transitions. [2023-11-21 21:03:50,041 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-21 21:03:50,041 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 142879 states and 204974 transitions. [2023-11-21 21:03:51,059 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 142128 [2023-11-21 21:03:51,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:51,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:51,062 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:51,062 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:51,063 INFO L748 eck$LassoCheckResult]: Stem: 482469#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 482470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 483215#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 483216#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 483374#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 483375#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 482328#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 482329#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 483935#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 483341#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 483342#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 483656#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 483657#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 483782#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 483877#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 483878#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 483721#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 483529#L1121 assume !(0 == ~M_E~0); 483276#L1121-2 assume !(0 == ~T1_E~0); 482608#L1126-1 assume !(0 == ~T2_E~0); 482609#L1131-1 assume !(0 == ~T3_E~0); 482776#L1136-1 assume !(0 == ~T4_E~0); 482884#L1141-1 assume !(0 == ~T5_E~0); 483120#L1146-1 assume !(0 == ~T6_E~0); 483457#L1151-1 assume !(0 == ~T7_E~0); 482948#L1156-1 assume !(0 == ~T8_E~0); 482314#L1161-1 assume !(0 == ~T9_E~0); 482315#L1166-1 assume !(0 == ~T10_E~0); 482537#L1171-1 assume !(0 == ~T11_E~0); 482538#L1176-1 assume !(0 == ~E_M~0); 483471#L1181-1 assume !(0 == ~E_1~0); 483613#L1186-1 assume !(0 == ~E_2~0); 483670#L1191-1 assume !(0 == ~E_3~0); 482569#L1196-1 assume !(0 == ~E_4~0); 482570#L1201-1 assume !(0 == ~E_5~0); 483955#L1206-1 assume !(0 == ~E_6~0); 483722#L1211-1 assume !(0 == ~E_7~0); 483723#L1216-1 assume !(0 == ~E_8~0); 482706#L1221-1 assume !(0 == ~E_9~0); 482707#L1226-1 assume !(0 == ~E_10~0); 482415#L1231-1 assume !(0 == ~E_11~0); 482416#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 483472#L556 assume !(1 == ~m_pc~0); 483473#L556-2 is_master_triggered_~__retres1~0#1 := 0; 482288#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 482289#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 483089#L1391 assume !(0 != activate_threads_~tmp~1#1); 483646#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 483647#L575 assume !(1 == ~t1_pc~0); 482242#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 482243#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 482382#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 482720#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 482674#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 482675#L594 assume !(1 == ~t2_pc~0); 483443#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 483544#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 482610#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 482303#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 482304#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 482371#L613 assume !(1 == ~t3_pc~0); 482487#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 482486#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 482836#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 483118#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 483119#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 482810#L632 assume !(1 == ~t4_pc~0); 482811#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 483530#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 482320#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 482321#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 483477#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 483204#L651 assume !(1 == ~t5_pc~0); 483205#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 482501#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 482502#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 483086#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 482515#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 482516#L670 assume !(1 == ~t6_pc~0); 483699#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 482866#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 482601#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 482602#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 483168#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 483169#L689 assume 1 == ~t7_pc~0; 483947#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 483295#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 483296#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 483720#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 483057#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 483058#L708 assume !(1 == ~t8_pc~0); 482606#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 482607#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 483834#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 483816#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 482661#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 482662#L727 assume 1 == ~t9_pc~0; 482787#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 482373#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 482650#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 482651#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 483936#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 482716#L746 assume !(1 == ~t10_pc~0); 482717#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 483426#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 483558#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 483765#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 483650#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 482893#L765 assume 1 == ~t11_pc~0; 482894#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 483109#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 483843#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 483697#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 483698#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 483810#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 483811#L1249-2 assume !(1 == ~T1_E~0); 487380#L1254-1 assume !(1 == ~T2_E~0); 487378#L1259-1 assume !(1 == ~T3_E~0); 487376#L1264-1 assume !(1 == ~T4_E~0); 487374#L1269-1 assume !(1 == ~T5_E~0); 487372#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 487370#L1279-1 assume !(1 == ~T7_E~0); 487368#L1284-1 assume !(1 == ~T8_E~0); 487366#L1289-1 assume !(1 == ~T9_E~0); 487362#L1294-1 assume !(1 == ~T10_E~0); 486420#L1299-1 assume !(1 == ~T11_E~0); 486418#L1304-1 assume !(1 == ~E_M~0); 486417#L1309-1 assume !(1 == ~E_1~0); 486416#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 486415#L1319-1 assume !(1 == ~E_3~0); 486412#L1324-1 assume !(1 == ~E_4~0); 486408#L1329-1 assume !(1 == ~E_5~0); 486404#L1334-1 assume !(1 == ~E_6~0); 486398#L1339-1 assume !(1 == ~E_7~0); 486394#L1344-1 assume !(1 == ~E_8~0); 486390#L1349-1 assume !(1 == ~E_9~0); 486386#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 486382#L1359-1 assume !(1 == ~E_11~0); 486378#L1364-1 assume { :end_inline_reset_delta_events } true; 486373#L1690-2 [2023-11-21 21:03:51,063 INFO L750 eck$LassoCheckResult]: Loop: 486373#L1690-2 assume !false; 486372#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 486368#L1096-1 assume !false; 486367#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 486171#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 486167#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 486165#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 486162#L937 assume !(0 != eval_~tmp~0#1); 486163#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 515993#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 515991#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 515989#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 515987#L1126-3 assume !(0 == ~T2_E~0); 515985#L1131-3 assume !(0 == ~T3_E~0); 515982#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 515980#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 515978#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 515976#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 515974#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 515972#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 515970#L1166-3 assume !(0 == ~T10_E~0); 515968#L1171-3 assume !(0 == ~T11_E~0); 515966#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 515964#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 515962#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 515960#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 515938#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 515930#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 515922#L1206-3 assume !(0 == ~E_6~0); 515913#L1211-3 assume !(0 == ~E_7~0); 515905#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 515897#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 515887#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 515880#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 515873#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 515866#L556-39 assume !(1 == ~m_pc~0); 515858#L556-41 is_master_triggered_~__retres1~0#1 := 0; 515850#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 515840#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 515834#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 515828#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 515822#L575-39 assume 1 == ~t1_pc~0; 515815#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 515808#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 515798#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 515791#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 515786#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 515782#L594-39 assume !(1 == ~t2_pc~0); 515780#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 515517#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 515514#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 515512#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 515510#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 515508#L613-39 assume !(1 == ~t3_pc~0); 515506#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 515503#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 515500#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 515498#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 515496#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 515494#L632-39 assume !(1 == ~t4_pc~0); 515492#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 515490#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 515489#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 515486#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 515484#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 515482#L651-39 assume !(1 == ~t5_pc~0); 515480#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 515478#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 515476#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 515473#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 515471#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 515469#L670-39 assume 1 == ~t6_pc~0; 515443#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 515434#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 515427#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 515426#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 515414#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 515413#L689-39 assume !(1 == ~t7_pc~0); 515410#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 515407#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 515405#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 515402#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 515400#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 515376#L708-39 assume 1 == ~t8_pc~0; 515365#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 515353#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 515345#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 515339#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 515335#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 515333#L727-39 assume !(1 == ~t9_pc~0); 515331#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 515328#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 515326#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 515324#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 515322#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 515320#L746-39 assume !(1 == ~t10_pc~0); 515318#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 515315#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 515313#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 515311#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 515307#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 515303#L765-39 assume 1 == ~t11_pc~0; 515299#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 515295#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 515293#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 515291#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 515288#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 515284#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 492684#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 492679#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 492675#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 492673#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 492671#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 492669#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 492665#L1279-3 assume !(1 == ~T7_E~0); 492663#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 492661#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 492659#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 492655#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 492653#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 492651#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 492649#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 492648#L1319-3 assume !(1 == ~E_3~0); 492644#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 492642#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 492640#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 492636#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 492634#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 492632#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 492630#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 492629#L1359-3 assume !(1 == ~E_11~0); 489257#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 488104#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 488094#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 488093#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 488090#L1709 assume !(0 == start_simulation_~tmp~3#1); 488088#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 486856#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 486852#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 486849#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 486847#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 486845#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 486843#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 486377#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 486373#L1690-2 [2023-11-21 21:03:51,064 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:51,064 INFO L85 PathProgramCache]: Analyzing trace with hash 1793793208, now seen corresponding path program 1 times [2023-11-21 21:03:51,065 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:51,065 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [325309219] [2023-11-21 21:03:51,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:51,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:51,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:51,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:51,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:51,152 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [325309219] [2023-11-21 21:03:51,152 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [325309219] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:51,152 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:51,152 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 21:03:51,152 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869153999] [2023-11-21 21:03:51,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:51,154 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:51,154 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:51,154 INFO L85 PathProgramCache]: Analyzing trace with hash -1100697218, now seen corresponding path program 1 times [2023-11-21 21:03:51,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:51,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901398943] [2023-11-21 21:03:51,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:51,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:51,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:51,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:51,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:51,222 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901398943] [2023-11-21 21:03:51,225 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [901398943] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:51,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:51,226 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:51,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534997022] [2023-11-21 21:03:51,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:51,228 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:51,228 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:51,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 21:03:51,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 21:03:51,229 INFO L87 Difference]: Start difference. First operand 142879 states and 204974 transitions. cyclomatic complexity: 62223 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:53,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:03:53,117 INFO L93 Difference]: Finished difference Result 331647 states and 472521 transitions. [2023-11-21 21:03:53,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 331647 states and 472521 transitions. [2023-11-21 21:03:54,918 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 330192 [2023-11-21 21:03:55,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 331647 states to 331647 states and 472521 transitions. [2023-11-21 21:03:55,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 331647 [2023-11-21 21:03:55,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 331647 [2023-11-21 21:03:55,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 331647 states and 472521 transitions. [2023-11-21 21:03:56,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:03:56,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 331647 states and 472521 transitions. [2023-11-21 21:03:56,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331647 states and 472521 transitions. [2023-11-21 21:03:58,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331647 to 147058. [2023-11-21 21:03:58,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147058 states, 147058 states have (on average 1.4222483645908417) internal successors, (209153), 147057 states have internal predecessors, (209153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:03:58,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147058 states to 147058 states and 209153 transitions. [2023-11-21 21:03:58,654 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147058 states and 209153 transitions. [2023-11-21 21:03:58,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-21 21:03:58,655 INFO L428 stractBuchiCegarLoop]: Abstraction has 147058 states and 209153 transitions. [2023-11-21 21:03:58,655 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-21 21:03:58,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147058 states and 209153 transitions. [2023-11-21 21:03:58,998 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 146304 [2023-11-21 21:03:58,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 21:03:58,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 21:03:59,001 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:59,001 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 21:03:59,001 INFO L748 eck$LassoCheckResult]: Stem: 957006#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 957007#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 957737#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 957738#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 957885#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 957886#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 956868#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 956869#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 958418#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 957851#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 957852#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 958170#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 958171#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 958291#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 958379#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 958380#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 958230#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 958044#L1121 assume !(0 == ~M_E~0); 957791#L1121-2 assume !(0 == ~T1_E~0); 957146#L1126-1 assume !(0 == ~T2_E~0); 957147#L1131-1 assume !(0 == ~T3_E~0); 957311#L1136-1 assume !(0 == ~T4_E~0); 957419#L1141-1 assume !(0 == ~T5_E~0); 957648#L1146-1 assume !(0 == ~T6_E~0); 957971#L1151-1 assume !(0 == ~T7_E~0); 957482#L1156-1 assume !(0 == ~T8_E~0); 956854#L1161-1 assume !(0 == ~T9_E~0); 956855#L1166-1 assume !(0 == ~T10_E~0); 957076#L1171-1 assume !(0 == ~T11_E~0); 957077#L1176-1 assume !(0 == ~E_M~0); 957984#L1181-1 assume !(0 == ~E_1~0); 958127#L1186-1 assume !(0 == ~E_2~0); 958183#L1191-1 assume !(0 == ~E_3~0); 957107#L1196-1 assume !(0 == ~E_4~0); 957108#L1201-1 assume !(0 == ~E_5~0); 958445#L1206-1 assume !(0 == ~E_6~0); 958231#L1211-1 assume !(0 == ~E_7~0); 958232#L1216-1 assume !(0 == ~E_8~0); 957241#L1221-1 assume !(0 == ~E_9~0); 957242#L1226-1 assume !(0 == ~E_10~0); 956953#L1231-1 assume !(0 == ~E_11~0); 956954#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 957985#L556 assume !(1 == ~m_pc~0); 957986#L556-2 is_master_triggered_~__retres1~0#1 := 0; 956828#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 956829#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 957619#L1391 assume !(0 != activate_threads_~tmp~1#1); 958160#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 958161#L575 assume !(1 == ~t1_pc~0); 956781#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 956782#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 956920#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 957255#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 957210#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 957211#L594 assume !(1 == ~t2_pc~0); 957957#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 958056#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 957148#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 956843#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 956844#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 956910#L613 assume !(1 == ~t3_pc~0); 957024#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 957023#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 957369#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 957646#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 957647#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 957344#L632 assume !(1 == ~t4_pc~0); 957345#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 958045#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 956860#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 956861#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 957989#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 957726#L651 assume !(1 == ~t5_pc~0); 957727#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 957038#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 957039#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 957616#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 957053#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 957054#L670 assume !(1 == ~t6_pc~0); 958209#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 957399#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 957400#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 958419#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 957690#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 957691#L689 assume 1 == ~t7_pc~0; 958433#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 957809#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 957810#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 958229#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 957589#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 957590#L708 assume !(1 == ~t8_pc~0); 957144#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 957145#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 958336#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 958321#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 957197#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 957198#L727 assume 1 == ~t9_pc~0; 957321#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 956912#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 957186#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 957187#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 958420#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 957251#L746 assume !(1 == ~t10_pc~0); 957252#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 957942#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 958071#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 958274#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 958164#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 957428#L765 assume 1 == ~t11_pc~0; 957429#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 957638#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 958350#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 958207#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 958208#L1479-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 958316#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 958317#L1249-2 assume !(1 == ~T1_E~0); 957519#L1254-1 assume !(1 == ~T2_E~0); 956839#L1259-1 assume !(1 == ~T3_E~0); 956821#L1264-1 assume !(1 == ~T4_E~0); 956822#L1269-1 assume !(1 == ~T5_E~0); 958519#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 958388#L1279-1 assume !(1 == ~T7_E~0); 957025#L1284-1 assume !(1 == ~T8_E~0); 957026#L1289-1 assume !(1 == ~T9_E~0); 957568#L1294-1 assume !(1 == ~T10_E~0); 957569#L1299-1 assume !(1 == ~T11_E~0); 979938#L1304-1 assume !(1 == ~E_M~0); 958501#L1309-1 assume !(1 == ~E_1~0); 958493#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 956974#L1319-1 assume !(1 == ~E_3~0); 956975#L1324-1 assume !(1 == ~E_4~0); 957100#L1329-1 assume !(1 == ~E_5~0); 957101#L1334-1 assume !(1 == ~E_6~0); 958269#L1339-1 assume !(1 == ~E_7~0); 984070#L1344-1 assume !(1 == ~E_8~0); 984060#L1349-1 assume !(1 == ~E_9~0); 984054#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 984046#L1359-1 assume !(1 == ~E_11~0); 983984#L1364-1 assume { :end_inline_reset_delta_events } true; 983979#L1690-2 [2023-11-21 21:03:59,002 INFO L750 eck$LassoCheckResult]: Loop: 983979#L1690-2 assume !false; 983978#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 983974#L1096-1 assume !false; 983972#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 983961#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 983957#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 983911#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 983906#L937 assume !(0 != eval_~tmp~0#1); 983907#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 987161#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 987160#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 987159#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 987158#L1126-3 assume !(0 == ~T2_E~0); 987157#L1131-3 assume !(0 == ~T3_E~0); 987156#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 987155#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 987154#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 987153#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 987152#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 987151#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 987150#L1166-3 assume !(0 == ~T10_E~0); 987149#L1171-3 assume !(0 == ~T11_E~0); 987148#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 987147#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 987146#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 987145#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 987144#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 987143#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 987142#L1206-3 assume !(0 == ~E_6~0); 987141#L1211-3 assume !(0 == ~E_7~0); 987140#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 987139#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 987138#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 987137#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 987136#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 987135#L556-39 assume !(1 == ~m_pc~0); 987134#L556-41 is_master_triggered_~__retres1~0#1 := 0; 987133#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 987132#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 987131#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 987130#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 987129#L575-39 assume !(1 == ~t1_pc~0); 987128#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 987126#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 987125#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 987124#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 987123#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 987122#L594-39 assume !(1 == ~t2_pc~0); 987121#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 987120#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 987119#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 987118#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 987117#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 987116#L613-39 assume !(1 == ~t3_pc~0); 987115#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 987113#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 987112#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 987111#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 987110#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 987109#L632-39 assume !(1 == ~t4_pc~0); 987108#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 987107#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 987106#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 987105#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 987104#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 987103#L651-39 assume !(1 == ~t5_pc~0); 987102#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 987101#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 987100#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 987099#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 987098#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 987097#L670-39 assume !(1 == ~t6_pc~0); 987096#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 987094#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 987092#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 987090#L1439-39 assume !(0 != activate_threads_~tmp___5~0#1); 984280#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 984278#L689-39 assume !(1 == ~t7_pc~0); 984276#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 984272#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 984270#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 984268#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 984266#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 984264#L708-39 assume 1 == ~t8_pc~0; 984262#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 984258#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 984256#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 984254#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 984252#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 984250#L727-39 assume !(1 == ~t9_pc~0); 984248#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 984244#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 984242#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 984240#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 984238#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 984236#L746-39 assume !(1 == ~t10_pc~0); 984234#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 984230#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 984228#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 984226#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 984224#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 984222#L765-39 assume 1 == ~t11_pc~0; 984220#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 984216#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 984214#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 984212#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 984210#L1479-41 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 984209#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 959063#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 984208#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 984205#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 984204#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 984203#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 984202#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 984201#L1279-3 assume !(1 == ~T7_E~0); 984200#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 984199#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 984198#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 984196#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 984195#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 984194#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 984193#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 984192#L1319-3 assume !(1 == ~E_3~0); 984191#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 984190#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 984189#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 977569#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 984188#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 984187#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 984186#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 984185#L1359-3 assume !(1 == ~E_11~0); 984184#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 984137#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 984125#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 984122#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 984119#L1709 assume !(0 == start_simulation_~tmp~3#1); 984116#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 984074#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 984071#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 984069#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 984059#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 984053#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 984045#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 983983#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 983979#L1690-2 [2023-11-21 21:03:59,003 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:59,003 INFO L85 PathProgramCache]: Analyzing trace with hash -1240256838, now seen corresponding path program 1 times [2023-11-21 21:03:59,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:59,003 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138145266] [2023-11-21 21:03:59,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:59,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:59,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:59,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:59,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:59,797 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138145266] [2023-11-21 21:03:59,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1138145266] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:59,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:59,798 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:59,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805845934] [2023-11-21 21:03:59,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:59,798 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 21:03:59,799 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 21:03:59,799 INFO L85 PathProgramCache]: Analyzing trace with hash -1440922302, now seen corresponding path program 1 times [2023-11-21 21:03:59,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 21:03:59,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445256052] [2023-11-21 21:03:59,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 21:03:59,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 21:03:59,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 21:03:59,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 21:03:59,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 21:03:59,910 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445256052] [2023-11-21 21:03:59,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445256052] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 21:03:59,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 21:03:59,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 21:03:59,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [322746199] [2023-11-21 21:03:59,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 21:03:59,912 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 21:03:59,912 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 21:03:59,912 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 21:03:59,912 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 21:03:59,913 INFO L87 Difference]: Start difference. First operand 147058 states and 209153 transitions. cyclomatic complexity: 62223 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:04:02,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 21:04:02,187 INFO L93 Difference]: Finished difference Result 407712 states and 575595 transitions. [2023-11-21 21:04:02,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 407712 states and 575595 transitions. [2023-11-21 21:04:04,815 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 404912 [2023-11-21 21:04:05,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 407712 states to 407712 states and 575595 transitions. [2023-11-21 21:04:05,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 407712 [2023-11-21 21:04:05,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 407712 [2023-11-21 21:04:05,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 407712 states and 575595 transitions. [2023-11-21 21:04:06,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 21:04:06,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 407712 states and 575595 transitions. [2023-11-21 21:04:06,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407712 states and 575595 transitions. [2023-11-21 21:04:10,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407712 to 402336. [2023-11-21 21:04:10,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 402336 states, 402336 states have (on average 1.412816650759564) internal successors, (568427), 402335 states have internal predecessors, (568427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 21:04:12,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 402336 states to 402336 states and 568427 transitions. [2023-11-21 21:04:12,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 402336 states and 568427 transitions. [2023-11-21 21:04:12,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 21:04:12,089 INFO L428 stractBuchiCegarLoop]: Abstraction has 402336 states and 568427 transitions. [2023-11-21 21:04:12,090 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-21 21:04:12,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 402336 states and 568427 transitions.