./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 527bcce2 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-527bcce [2023-11-21 22:09:31,304 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-21 22:09:31,428 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-21 22:09:31,436 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-21 22:09:31,437 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-21 22:09:31,479 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-21 22:09:31,480 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-21 22:09:31,481 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-21 22:09:31,482 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-21 22:09:31,487 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-21 22:09:31,489 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-21 22:09:31,490 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-21 22:09:31,490 INFO L153 SettingsManager]: * Use SBE=true [2023-11-21 22:09:31,493 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-21 22:09:31,494 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-21 22:09:31,494 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-21 22:09:31,495 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-21 22:09:31,495 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-21 22:09:31,496 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-21 22:09:31,497 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-21 22:09:31,497 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-21 22:09:31,498 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-21 22:09:31,498 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-21 22:09:31,499 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-21 22:09:31,500 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-21 22:09:31,500 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-21 22:09:31,501 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-21 22:09:31,501 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-21 22:09:31,502 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-21 22:09:31,502 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-21 22:09:31,504 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-21 22:09:31,504 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-21 22:09:31,504 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-21 22:09:31,505 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-21 22:09:31,505 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-21 22:09:31,506 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-21 22:09:31,506 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-21 22:09:31,507 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-21 22:09:31,507 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 [2023-11-21 22:09:31,857 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-21 22:09:31,890 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-21 22:09:31,895 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-21 22:09:31,896 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-21 22:09:31,897 INFO L274 PluginConnector]: CDTParser initialized [2023-11-21 22:09:31,898 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/../../sv-benchmarks/c/systemc/token_ring.15.cil.c [2023-11-21 22:09:35,087 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-21 22:09:35,427 INFO L384 CDTParser]: Found 1 translation units. [2023-11-21 22:09:35,428 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/sv-benchmarks/c/systemc/token_ring.15.cil.c [2023-11-21 22:09:35,460 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/data/cb5b6f4d3/9c859063bec14df0ae4191fc86f51216/FLAG62f83e78c [2023-11-21 22:09:35,476 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/data/cb5b6f4d3/9c859063bec14df0ae4191fc86f51216 [2023-11-21 22:09:35,479 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-21 22:09:35,481 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-21 22:09:35,482 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-21 22:09:35,482 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-21 22:09:35,487 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-21 22:09:35,488 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 10:09:35" (1/1) ... [2023-11-21 22:09:35,489 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@a10a629 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:35, skipping insertion in model container [2023-11-21 22:09:35,490 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 10:09:35" (1/1) ... [2023-11-21 22:09:35,550 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-21 22:09:35,889 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 22:09:35,910 INFO L202 MainTranslator]: Completed pre-run [2023-11-21 22:09:36,060 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-21 22:09:36,095 INFO L206 MainTranslator]: Completed translation [2023-11-21 22:09:36,095 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36 WrapperNode [2023-11-21 22:09:36,096 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-21 22:09:36,097 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-21 22:09:36,097 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-21 22:09:36,097 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-21 22:09:36,106 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,135 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,285 INFO L138 Inliner]: procedures = 54, calls = 72, calls flagged for inlining = 67, calls inlined = 305, statements flattened = 4694 [2023-11-21 22:09:36,286 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-21 22:09:36,286 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-21 22:09:36,287 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-21 22:09:36,287 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-21 22:09:36,372 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,372 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,382 INFO L184 PluginConnector]: Executing the observer HeapSplitter from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,480 INFO L187 HeapSplitter]: Split 2 memory accesses to 1 slices as follows [2] [2023-11-21 22:09:36,480 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,481 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,545 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,592 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,604 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,619 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,634 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-21 22:09:36,635 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-21 22:09:36,636 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-21 22:09:36,636 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-21 22:09:36,637 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (1/1) ... [2023-11-21 22:09:36,642 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-21 22:09:36,659 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/z3 [2023-11-21 22:09:36,671 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-21 22:09:36,695 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a77cb90e-ac76-4013-81c7-1637a7b2a5c4/bin/uautomizer-verify-bycVGegfSx/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-21 22:09:36,717 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-21 22:09:36,717 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-21 22:09:36,717 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-21 22:09:36,717 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-21 22:09:36,850 INFO L240 CfgBuilder]: Building ICFG [2023-11-21 22:09:36,852 INFO L266 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-21 22:09:39,584 INFO L281 CfgBuilder]: Performing block encoding [2023-11-21 22:09:39,646 INFO L303 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-21 22:09:39,647 INFO L308 CfgBuilder]: Removed 16 assume(true) statements. [2023-11-21 22:09:39,650 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:09:39 BoogieIcfgContainer [2023-11-21 22:09:39,650 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-21 22:09:39,652 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-21 22:09:39,652 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-21 22:09:39,656 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-21 22:09:39,657 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:09:39,657 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.11 10:09:35" (1/3) ... [2023-11-21 22:09:39,659 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@62030f08 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 10:09:39, skipping insertion in model container [2023-11-21 22:09:39,659 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:09:39,661 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 10:09:36" (2/3) ... [2023-11-21 22:09:39,663 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@62030f08 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 10:09:39, skipping insertion in model container [2023-11-21 22:09:39,664 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-21 22:09:39,664 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 10:09:39" (3/3) ... [2023-11-21 22:09:39,665 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.15.cil.c [2023-11-21 22:09:39,771 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-21 22:09:39,771 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-21 22:09:39,771 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-21 22:09:39,772 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-21 22:09:39,772 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-21 22:09:39,772 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-21 22:09:39,772 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-21 22:09:39,772 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-21 22:09:39,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2045 states, 2044 states have (on average 1.4921722113502935) internal successors, (3050), 2044 states have internal predecessors, (3050), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:39,897 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1866 [2023-11-21 22:09:39,897 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:39,897 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:39,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:39,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:39,921 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-21 22:09:39,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2045 states, 2044 states have (on average 1.4921722113502935) internal successors, (3050), 2044 states have internal predecessors, (3050), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:39,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1866 [2023-11-21 22:09:39,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:39,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:39,993 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:39,993 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:40,005 INFO L748 eck$LassoCheckResult]: Stem: 147#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1965#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 743#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1962#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1844#L909true assume !(1 == ~m_i~0);~m_st~0 := 2; 1951#L909-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 423#L914-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 454#L919-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1239#L924-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1113#L929-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1869#L934-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1274#L939-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1680#L944-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 313#L949-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1334#L954-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1973#L959-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 643#L964-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1184#L969-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 1777#L974-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1923#L1286true assume 0 == ~M_E~0;~M_E~0 := 1; 1458#L1286-2true assume !(0 == ~T1_E~0); 262#L1291-1true assume !(0 == ~T2_E~0); 1859#L1296-1true assume !(0 == ~T3_E~0); 709#L1301-1true assume !(0 == ~T4_E~0); 1228#L1306-1true assume !(0 == ~T5_E~0); 1196#L1311-1true assume !(0 == ~T6_E~0); 238#L1316-1true assume !(0 == ~T7_E~0); 1689#L1321-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 725#L1326-1true assume !(0 == ~T9_E~0); 140#L1331-1true assume !(0 == ~T10_E~0); 5#L1336-1true assume !(0 == ~T11_E~0); 1079#L1341-1true assume !(0 == ~T12_E~0); 28#L1346-1true assume !(0 == ~T13_E~0); 1501#L1351-1true assume !(0 == ~E_M~0); 204#L1356-1true assume !(0 == ~E_1~0); 1981#L1361-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1655#L1366-1true assume !(0 == ~E_3~0); 230#L1371-1true assume !(0 == ~E_4~0); 1465#L1376-1true assume !(0 == ~E_5~0); 770#L1381-1true assume !(0 == ~E_6~0); 1747#L1386-1true assume !(0 == ~E_7~0); 1890#L1391-1true assume !(0 == ~E_8~0); 1811#L1396-1true assume !(0 == ~E_9~0); 671#L1401-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1286#L1406-1true assume !(0 == ~E_11~0); 917#L1411-1true assume !(0 == ~E_12~0); 1715#L1416-1true assume !(0 == ~E_13~0); 613#L1421-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 512#L635true assume !(1 == ~m_pc~0); 38#L635-2true is_master_triggered_~__retres1~0#1 := 0; 199#L646true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 615#is_master_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1316#L1598true assume !(0 != activate_threads_~tmp~1#1); 120#L1598-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 584#L654true assume 1 == ~t1_pc~0; 522#L655true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1738#L665true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1042#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 583#L1606true assume !(0 != activate_threads_~tmp___0~0#1); 840#L1606-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 142#L673true assume 1 == ~t2_pc~0; 1800#L674true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 886#L684true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1896#L1614true assume !(0 != activate_threads_~tmp___1~0#1); 1997#L1614-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 633#L692true assume !(1 == ~t3_pc~0); 513#L692-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1794#L703true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1021#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 405#L1622true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1722#L1622-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 155#L711true assume 1 == ~t4_pc~0; 436#L712true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1328#L722true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16#L1630true assume !(0 != activate_threads_~tmp___3~0#1); 1845#L1630-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1843#L730true assume !(1 == ~t5_pc~0); 1979#L730-2true is_transmit5_triggered_~__retres1~5#1 := 0; 102#L741true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1675#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 159#L1638true assume !(0 != activate_threads_~tmp___4~0#1); 350#L1638-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 884#L749true assume 1 == ~t6_pc~0; 217#L750true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 426#L760true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 239#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1461#L1646true assume !(0 != activate_threads_~tmp___5~0#1); 475#L1646-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7#L768true assume !(1 == ~t7_pc~0); 1668#L768-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1395#L779true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1983#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1372#L1654true assume !(0 != activate_threads_~tmp___6~0#1); 809#L1654-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 240#L787true assume 1 == ~t8_pc~0; 1130#L788true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1698#L798true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1598#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1912#L1662true assume !(0 != activate_threads_~tmp___7~0#1); 27#L1662-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1197#L806true assume 1 == ~t9_pc~0; 1141#L807true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44#L817true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 276#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 160#L1670true assume !(0 != activate_threads_~tmp___8~0#1); 1599#L1670-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1122#L825true assume !(1 == ~t10_pc~0); 1388#L825-2true is_transmit10_triggered_~__retres1~10#1 := 0; 761#L836true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1365#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 200#L1678true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2033#L1678-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 555#L844true assume 1 == ~t11_pc~0; 362#L845true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1267#L855true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1504#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1179#L1686true assume !(0 != activate_threads_~tmp___10~0#1); 1110#L1686-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1410#L863true assume !(1 == ~t12_pc~0); 1474#L863-2true is_transmit12_triggered_~__retres1~12#1 := 0; 194#L874true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1232#L1694true assume !(0 != activate_threads_~tmp___11~0#1); 1624#L1694-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 641#L882true assume 1 == ~t13_pc~0; 916#L883true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1864#L893true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1423#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1186#L1702true assume !(0 != activate_threads_~tmp___12~0#1); 860#L1702-2true havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1583#L1434true assume !(1 == ~M_E~0); 1950#L1434-2true assume !(1 == ~T1_E~0); 1862#L1439-1true assume !(1 == ~T2_E~0); 151#L1444-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 921#L1449-1true assume !(1 == ~T4_E~0); 402#L1454-1true assume !(1 == ~T5_E~0); 1496#L1459-1true assume !(1 == ~T6_E~0); 810#L1464-1true assume !(1 == ~T7_E~0); 868#L1469-1true assume !(1 == ~T8_E~0); 1734#L1474-1true assume !(1 == ~T9_E~0); 614#L1479-1true assume !(1 == ~T10_E~0); 815#L1484-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1253#L1489-1true assume !(1 == ~T12_E~0); 530#L1494-1true assume !(1 == ~T13_E~0); 1850#L1499-1true assume !(1 == ~E_M~0); 657#L1504-1true assume !(1 == ~E_1~0); 1547#L1509-1true assume !(1 == ~E_2~0); 1252#L1514-1true assume !(1 == ~E_3~0); 896#L1519-1true assume !(1 == ~E_4~0); 1966#L1524-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1700#L1529-1true assume !(1 == ~E_6~0); 1781#L1534-1true assume !(1 == ~E_7~0); 52#L1539-1true assume !(1 == ~E_8~0); 274#L1544-1true assume !(1 == ~E_9~0); 1615#L1549-1true assume !(1 == ~E_10~0); 1641#L1554-1true assume !(1 == ~E_11~0); 1612#L1559-1true assume !(1 == ~E_12~0); 1317#L1564-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1681#L1569-1true assume { :end_inline_reset_delta_events } true; 1991#L1935-2true [2023-11-21 22:09:40,009 INFO L750 eck$LassoCheckResult]: Loop: 1991#L1935-2true assume !false; 56#L1936true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9#L1261-1true assume !true; 560#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 358#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1361#L1286-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1495#L1286-5true assume !(0 == ~T1_E~0); 977#L1291-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1873#L1296-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1786#L1301-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1640#L1306-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 592#L1311-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 166#L1316-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 222#L1321-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 686#L1326-3true assume !(0 == ~T9_E~0); 1603#L1331-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 899#L1336-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1533#L1341-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 398#L1346-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 388#L1351-3true assume 0 == ~E_M~0;~E_M~0 := 1; 356#L1356-3true assume 0 == ~E_1~0;~E_1~0 := 1; 751#L1361-3true assume 0 == ~E_2~0;~E_2~0 := 1; 784#L1366-3true assume !(0 == ~E_3~0); 22#L1371-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1283#L1376-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1573#L1381-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1082#L1386-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1705#L1391-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1338#L1396-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1987#L1401-3true assume 0 == ~E_10~0;~E_10~0 := 1; 198#L1406-3true assume !(0 == ~E_11~0); 121#L1411-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1785#L1416-3true assume 0 == ~E_13~0;~E_13~0 := 1; 483#L1421-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65#L635-45true assume 1 == ~m_pc~0; 507#L636-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 861#L646-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 946#is_master_triggered_returnLabel#16true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1109#L1598-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 210#L1598-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 741#L654-45true assume 1 == ~t1_pc~0; 1761#L655-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1051#L665-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1870#is_transmit1_triggered_returnLabel#16true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58#L1606-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1459#L1606-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 517#L673-45true assume !(1 == ~t2_pc~0); 1355#L673-47true is_transmit2_triggered_~__retres1~2#1 := 0; 758#L684-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 941#is_transmit2_triggered_returnLabel#16true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1509#L1614-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1183#L1614-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 292#L692-45true assume 1 == ~t3_pc~0; 1769#L693-15true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1212#L703-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2000#is_transmit3_triggered_returnLabel#16true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 317#L1622-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 510#L1622-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2030#L711-45true assume !(1 == ~t4_pc~0); 639#L711-47true is_transmit4_triggered_~__retres1~4#1 := 0; 1982#L722-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1288#is_transmit4_triggered_returnLabel#16true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1704#L1630-45true assume !(0 != activate_threads_~tmp___3~0#1); 793#L1630-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224#L730-45true assume 1 == ~t5_pc~0; 143#L731-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2046#L741-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1996#is_transmit5_triggered_returnLabel#16true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 904#L1638-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1004#L1638-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132#L749-45true assume 1 == ~t6_pc~0; 1124#L750-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1216#L760-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 669#is_transmit6_triggered_returnLabel#16true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1424#L1646-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1025#L1646-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 304#L768-45true assume !(1 == ~t7_pc~0); 449#L768-47true is_transmit7_triggered_~__retres1~7#1 := 0; 1185#L779-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 742#is_transmit7_triggered_returnLabel#16true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1855#L1654-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1006#L1654-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1909#L787-45true assume 1 == ~t8_pc~0; 1218#L788-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 385#L798-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1736#is_transmit8_triggered_returnLabel#16true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 656#L1662-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 903#L1662-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1779#L806-45true assume 1 == ~t9_pc~0; 1623#L807-15true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 532#L817-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1075#is_transmit9_triggered_returnLabel#16true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 433#L1670-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 371#L1670-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1832#L825-45true assume 1 == ~t10_pc~0; 806#L826-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1851#L836-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1189#is_transmit10_triggered_returnLabel#16true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 937#L1678-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1026#L1678-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 170#L844-45true assume !(1 == ~t11_pc~0); 1548#L844-47true is_transmit11_triggered_~__retres1~11#1 := 0; 484#L855-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 187#is_transmit11_triggered_returnLabel#16true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 789#L1686-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1343#L1686-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 189#L863-45true assume 1 == ~t12_pc~0; 1140#L864-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4#L874-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1120#is_transmit12_triggered_returnLabel#16true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 260#L1694-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 797#L1694-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1118#L882-45true assume !(1 == ~t13_pc~0); 464#L882-47true is_transmit13_triggered_~__retres1~13#1 := 0; 12#L893-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1057#is_transmit13_triggered_returnLabel#16true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1327#L1702-45true assume !(0 != activate_threads_~tmp___12~0#1); 1380#L1702-47true havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 872#L1434-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1084#L1434-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1049#L1439-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 149#L1444-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 231#L1449-3true assume !(1 == ~T4_E~0); 1639#L1454-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 865#L1459-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 2026#L1464-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1416#L1469-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1285#L1474-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1645#L1479-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1426#L1484-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 595#L1489-3true assume !(1 == ~T12_E~0); 1178#L1494-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1806#L1499-3true assume 1 == ~E_M~0;~E_M~0 := 2; 820#L1504-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1304#L1509-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1370#L1514-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1903#L1519-3true assume 1 == ~E_4~0;~E_4~0 := 2; 533#L1524-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1481#L1529-3true assume !(1 == ~E_6~0); 1699#L1534-3true assume 1 == ~E_7~0;~E_7~0 := 2; 760#L1539-3true assume 1 == ~E_8~0;~E_8~0 := 2; 381#L1544-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1435#L1549-3true assume 1 == ~E_10~0;~E_10~0 := 2; 726#L1554-3true assume 1 == ~E_11~0;~E_11~0 := 2; 172#L1559-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1203#L1564-3true assume 1 == ~E_13~0;~E_13~0 := 2; 950#L1569-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1123#L987-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 446#L1059-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 211#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 929#L1954true assume !(0 == start_simulation_~tmp~3#1); 1682#L1954-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1205#L987-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1002#L1059-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1157#L1909true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1296#L1916true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1391#stop_simulation_returnLabel#1true start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1810#L1967true assume !(0 != start_simulation_~tmp___0~1#1); 1991#L1935-2true [2023-11-21 22:09:40,018 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:40,019 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2023-11-21 22:09:40,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:40,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716810794] [2023-11-21 22:09:40,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:40,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:40,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:40,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:40,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:40,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716810794] [2023-11-21 22:09:40,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716810794] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:40,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:40,459 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:40,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [947703680] [2023-11-21 22:09:40,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:40,467 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:40,470 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:40,470 INFO L85 PathProgramCache]: Analyzing trace with hash 826815692, now seen corresponding path program 1 times [2023-11-21 22:09:40,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:40,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989406431] [2023-11-21 22:09:40,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:40,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:40,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:40,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:40,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:40,593 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989406431] [2023-11-21 22:09:40,593 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [989406431] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:40,593 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:40,593 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:09:40,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1241347284] [2023-11-21 22:09:40,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:40,595 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:40,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:40,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-21 22:09:40,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-21 22:09:40,641 INFO L87 Difference]: Start difference. First operand has 2045 states, 2044 states have (on average 1.4921722113502935) internal successors, (3050), 2044 states have internal predecessors, (3050), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:40,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:40,760 INFO L93 Difference]: Finished difference Result 2041 states and 3012 transitions. [2023-11-21 22:09:40,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2041 states and 3012 transitions. [2023-11-21 22:09:40,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:40,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2041 states to 2035 states and 3006 transitions. [2023-11-21 22:09:40,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:40,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:40,815 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 3006 transitions. [2023-11-21 22:09:40,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:40,828 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3006 transitions. [2023-11-21 22:09:40,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 3006 transitions. [2023-11-21 22:09:40,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:40,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4771498771498772) internal successors, (3006), 2034 states have internal predecessors, (3006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:40,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 3006 transitions. [2023-11-21 22:09:40,938 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3006 transitions. [2023-11-21 22:09:40,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-21 22:09:40,945 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 3006 transitions. [2023-11-21 22:09:40,948 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-21 22:09:40,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 3006 transitions. [2023-11-21 22:09:40,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:40,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:40,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:40,967 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:40,967 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:40,968 INFO L748 eck$LassoCheckResult]: Stem: 4406#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5395#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5396#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6111#L909 assume !(1 == ~m_i~0);~m_st~0 := 2; 6112#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4914#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4915#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4961#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5768#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5769#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5882#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5883#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4721#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4722#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5928#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5257#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5258#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5825#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6099#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 5993#L1286-2 assume !(0 == ~T1_E~0); 4626#L1291-1 assume !(0 == ~T2_E~0); 4627#L1296-1 assume !(0 == ~T3_E~0); 5352#L1301-1 assume !(0 == ~T4_E~0); 5353#L1306-1 assume !(0 == ~T5_E~0); 5833#L1311-1 assume !(0 == ~T6_E~0); 4582#L1316-1 assume !(0 == ~T7_E~0); 4583#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5373#L1326-1 assume !(0 == ~T9_E~0); 4391#L1331-1 assume !(0 == ~T10_E~0); 4101#L1336-1 assume !(0 == ~T11_E~0); 4102#L1341-1 assume !(0 == ~T12_E~0); 4151#L1346-1 assume !(0 == ~T13_E~0); 4152#L1351-1 assume !(0 == ~E_M~0); 4519#L1356-1 assume !(0 == ~E_1~0); 4520#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 6062#L1366-1 assume !(0 == ~E_3~0); 4569#L1371-1 assume !(0 == ~E_4~0); 4570#L1376-1 assume !(0 == ~E_5~0); 5429#L1381-1 assume !(0 == ~E_6~0); 5430#L1386-1 assume !(0 == ~E_7~0); 6090#L1391-1 assume !(0 == ~E_8~0); 6103#L1396-1 assume !(0 == ~E_9~0); 5300#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5301#L1406-1 assume !(0 == ~E_11~0); 5594#L1411-1 assume !(0 == ~E_12~0); 5595#L1416-1 assume !(0 == ~E_13~0); 5208#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5058#L635 assume !(1 == ~m_pc~0); 4171#L635-2 is_master_triggered_~__retres1~0#1 := 0; 4172#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4513#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5211#L1598 assume !(0 != activate_threads_~tmp~1#1); 4345#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4346#L654 assume 1 == ~t1_pc~0; 5081#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5082#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5707#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5163#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 5164#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4394#L673 assume 1 == ~t2_pc~0; 4395#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5565#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4599#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4600#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 6121#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5239#L692 assume !(1 == ~t3_pc~0); 5060#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5061#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5692#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4883#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4884#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4422#L711 assume 1 == ~t4_pc~0; 4423#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4931#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4221#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4126#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 4127#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6110#L730 assume !(1 == ~t5_pc~0); 5504#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4304#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4305#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4432#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 4433#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4787#L749 assume 1 == ~t6_pc~0; 4544#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4307#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4584#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4585#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 4997#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4106#L768 assume !(1 == ~t7_pc~0); 4107#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5450#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5965#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5950#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 5470#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4586#L787 assume 1 == ~t8_pc~0; 4587#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5784#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6043#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 6044#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 4149#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4150#L806 assume 1 == ~t9_pc~0; 5793#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4184#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4185#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4434#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 4435#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5777#L825 assume !(1 == ~t10_pc~0); 5778#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5417#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5418#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4514#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4515#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5134#L844 assume 1 == ~t11_pc~0; 4809#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4810#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5878#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5821#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 5764#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5765#L863 assume !(1 == ~t12_pc~0); 4287#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4286#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4167#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4168#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 5856#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5253#L882 assume 1 == ~t13_pc~0; 5254#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5541#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5977#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5826#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 5529#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5530#L1434 assume !(1 == ~M_E~0); 6039#L1434-2 assume !(1 == ~T1_E~0); 6114#L1439-1 assume !(1 == ~T2_E~0); 4414#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4415#L1449-1 assume !(1 == ~T4_E~0); 4878#L1454-1 assume !(1 == ~T5_E~0); 4879#L1459-1 assume !(1 == ~T6_E~0); 5471#L1464-1 assume !(1 == ~T7_E~0); 5472#L1469-1 assume !(1 == ~T8_E~0); 5542#L1474-1 assume !(1 == ~T9_E~0); 5209#L1479-1 assume !(1 == ~T10_E~0); 5210#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5476#L1489-1 assume !(1 == ~T12_E~0); 5093#L1494-1 assume !(1 == ~T13_E~0); 5094#L1499-1 assume !(1 == ~E_M~0); 5279#L1504-1 assume !(1 == ~E_1~0); 5280#L1509-1 assume !(1 == ~E_2~0); 5867#L1514-1 assume !(1 == ~E_3~0); 5576#L1519-1 assume !(1 == ~E_4~0); 5577#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6074#L1529-1 assume !(1 == ~E_6~0); 6075#L1534-1 assume !(1 == ~E_7~0); 4204#L1539-1 assume !(1 == ~E_8~0); 4205#L1544-1 assume !(1 == ~E_9~0); 4647#L1549-1 assume !(1 == ~E_10~0); 6050#L1554-1 assume !(1 == ~E_11~0); 6048#L1559-1 assume !(1 == ~E_12~0); 5909#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 5910#L1569-1 assume { :end_inline_reset_delta_events } true; 6071#L1935-2 [2023-11-21 22:09:40,969 INFO L750 eck$LassoCheckResult]: Loop: 6071#L1935-2 assume !false; 4213#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4111#L1261-1 assume !false; 4112#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5478#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4341#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5767#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4894#L1074 assume !(0 != eval_~tmp~0#1); 4896#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4802#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4803#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5943#L1286-5 assume !(0 == ~T1_E~0); 5657#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5658#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6101#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6059#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5175#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4446#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4447#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4552#L1326-3 assume !(0 == ~T9_E~0); 5323#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5579#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5580#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4871#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4858#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4798#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4799#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5405#L1366-3 assume !(0 == ~E_3~0); 4139#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4140#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5890#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5742#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5743#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5929#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5930#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4512#L1406-3 assume !(0 == ~E_11~0); 4347#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4348#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5012#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4225#L635-45 assume 1 == ~m_pc~0; 4226#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5051#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5531#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5626#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4531#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4532#L654-45 assume 1 == ~t1_pc~0; 5392#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5714#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5715#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4216#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4217#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5070#L673-45 assume !(1 == ~t2_pc~0); 5072#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5411#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5412#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5623#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5824#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4679#L692-45 assume !(1 == ~t3_pc~0); 4386#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 4387#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5845#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4728#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4729#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5055#L711-45 assume 1 == ~t4_pc~0; 5180#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5181#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5893#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5894#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 5451#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4559#L730-45 assume 1 == ~t5_pc~0; 4397#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4398#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6128#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5584#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5585#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4371#L749-45 assume !(1 == ~t6_pc~0); 4372#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 5780#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5296#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5297#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5696#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4704#L768-45 assume 1 == ~t7_pc~0; 4705#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4845#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5393#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5394#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5681#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5682#L787-45 assume 1 == ~t8_pc~0; 5847#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4851#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4852#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5277#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5278#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5583#L806-45 assume 1 == ~t9_pc~0; 6052#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4253#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5095#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4927#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4826#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4827#L825-45 assume !(1 == ~t10_pc~0); 5366#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 5367#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5829#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5615#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5616#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4452#L844-45 assume 1 == ~t11_pc~0; 4453#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5013#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4489#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4490#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5448#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4494#L863-45 assume !(1 == ~t12_pc~0); 4496#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 4099#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4100#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4621#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4622#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5454#L882-45 assume !(1 == ~t13_pc~0); 4978#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 4118#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4119#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5718#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 5919#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5546#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5547#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5713#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4410#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4411#L1449-3 assume !(1 == ~T4_E~0); 4571#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5537#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5538#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5974#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5891#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5892#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5978#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5178#L1489-3 assume !(1 == ~T12_E~0); 5179#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5820#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5480#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5481#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5905#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5948#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5096#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5097#L1529-3 assume !(1 == ~E_6~0); 6000#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5416#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4846#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4847#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5374#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4457#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4458#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5631#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5632#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4343#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4533#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4534#L1954 assume !(0 == start_simulation_~tmp~3#1); 5605#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5841#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4642#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4143#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 4144#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5804#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5901#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5960#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 6071#L1935-2 [2023-11-21 22:09:40,970 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:40,971 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2023-11-21 22:09:40,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:40,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [273047580] [2023-11-21 22:09:40,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:40,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:40,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:41,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:41,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:41,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [273047580] [2023-11-21 22:09:41,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [273047580] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:41,078 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:41,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:41,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677545445] [2023-11-21 22:09:41,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:41,079 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:41,080 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:41,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1185754370, now seen corresponding path program 1 times [2023-11-21 22:09:41,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:41,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872060235] [2023-11-21 22:09:41,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:41,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:41,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:41,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:41,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:41,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872060235] [2023-11-21 22:09:41,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872060235] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:41,325 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:41,325 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:41,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1584303809] [2023-11-21 22:09:41,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:41,326 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:41,326 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:41,327 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:41,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:41,328 INFO L87 Difference]: Start difference. First operand 2035 states and 3006 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:41,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:41,393 INFO L93 Difference]: Finished difference Result 2035 states and 3005 transitions. [2023-11-21 22:09:41,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 3005 transitions. [2023-11-21 22:09:41,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:41,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 3005 transitions. [2023-11-21 22:09:41,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:41,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:41,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 3005 transitions. [2023-11-21 22:09:41,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:41,435 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3005 transitions. [2023-11-21 22:09:41,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 3005 transitions. [2023-11-21 22:09:41,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:41,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4766584766584767) internal successors, (3005), 2034 states have internal predecessors, (3005), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:41,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 3005 transitions. [2023-11-21 22:09:41,483 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3005 transitions. [2023-11-21 22:09:41,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:41,484 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 3005 transitions. [2023-11-21 22:09:41,484 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-21 22:09:41,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 3005 transitions. [2023-11-21 22:09:41,497 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:41,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:41,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:41,501 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:41,501 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:41,502 INFO L748 eck$LassoCheckResult]: Stem: 8483#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8484#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9472#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9473#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10188#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 10189#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8991#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8992#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9038#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9845#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9846#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9959#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9960#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8798#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8799#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10005#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9334#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9335#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9902#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10176#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 10070#L1286-2 assume !(0 == ~T1_E~0); 8703#L1291-1 assume !(0 == ~T2_E~0); 8704#L1296-1 assume !(0 == ~T3_E~0); 9429#L1301-1 assume !(0 == ~T4_E~0); 9430#L1306-1 assume !(0 == ~T5_E~0); 9910#L1311-1 assume !(0 == ~T6_E~0); 8659#L1316-1 assume !(0 == ~T7_E~0); 8660#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9450#L1326-1 assume !(0 == ~T9_E~0); 8468#L1331-1 assume !(0 == ~T10_E~0); 8178#L1336-1 assume !(0 == ~T11_E~0); 8179#L1341-1 assume !(0 == ~T12_E~0); 8228#L1346-1 assume !(0 == ~T13_E~0); 8229#L1351-1 assume !(0 == ~E_M~0); 8596#L1356-1 assume !(0 == ~E_1~0); 8597#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10139#L1366-1 assume !(0 == ~E_3~0); 8646#L1371-1 assume !(0 == ~E_4~0); 8647#L1376-1 assume !(0 == ~E_5~0); 9506#L1381-1 assume !(0 == ~E_6~0); 9507#L1386-1 assume !(0 == ~E_7~0); 10167#L1391-1 assume !(0 == ~E_8~0); 10180#L1396-1 assume !(0 == ~E_9~0); 9377#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9378#L1406-1 assume !(0 == ~E_11~0); 9671#L1411-1 assume !(0 == ~E_12~0); 9672#L1416-1 assume !(0 == ~E_13~0); 9285#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9135#L635 assume !(1 == ~m_pc~0); 8248#L635-2 is_master_triggered_~__retres1~0#1 := 0; 8249#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8590#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9288#L1598 assume !(0 != activate_threads_~tmp~1#1); 8422#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8423#L654 assume 1 == ~t1_pc~0; 9158#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9159#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9784#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9240#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 9241#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8471#L673 assume 1 == ~t2_pc~0; 8472#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9642#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8676#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8677#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 10198#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9316#L692 assume !(1 == ~t3_pc~0); 9137#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9138#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9769#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8960#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8961#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8499#L711 assume 1 == ~t4_pc~0; 8500#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9008#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8298#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8203#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 8204#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10187#L730 assume !(1 == ~t5_pc~0); 9581#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8381#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8382#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8509#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 8510#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8864#L749 assume 1 == ~t6_pc~0; 8621#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8384#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8661#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8662#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 9074#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8183#L768 assume !(1 == ~t7_pc~0); 8184#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9527#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10042#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10027#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 9547#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8663#L787 assume 1 == ~t8_pc~0; 8664#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9861#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10120#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10121#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 8226#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8227#L806 assume 1 == ~t9_pc~0; 9870#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8261#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8262#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8511#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 8512#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9854#L825 assume !(1 == ~t10_pc~0); 9855#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9494#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9495#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8591#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8592#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9211#L844 assume 1 == ~t11_pc~0; 8886#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8887#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9955#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9898#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 9841#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9842#L863 assume !(1 == ~t12_pc~0); 8364#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8363#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8244#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8245#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 9933#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9330#L882 assume 1 == ~t13_pc~0; 9331#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9618#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 10054#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9903#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 9606#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9607#L1434 assume !(1 == ~M_E~0); 10116#L1434-2 assume !(1 == ~T1_E~0); 10191#L1439-1 assume !(1 == ~T2_E~0); 8491#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8492#L1449-1 assume !(1 == ~T4_E~0); 8955#L1454-1 assume !(1 == ~T5_E~0); 8956#L1459-1 assume !(1 == ~T6_E~0); 9548#L1464-1 assume !(1 == ~T7_E~0); 9549#L1469-1 assume !(1 == ~T8_E~0); 9619#L1474-1 assume !(1 == ~T9_E~0); 9286#L1479-1 assume !(1 == ~T10_E~0); 9287#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9553#L1489-1 assume !(1 == ~T12_E~0); 9170#L1494-1 assume !(1 == ~T13_E~0); 9171#L1499-1 assume !(1 == ~E_M~0); 9356#L1504-1 assume !(1 == ~E_1~0); 9357#L1509-1 assume !(1 == ~E_2~0); 9944#L1514-1 assume !(1 == ~E_3~0); 9653#L1519-1 assume !(1 == ~E_4~0); 9654#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 10151#L1529-1 assume !(1 == ~E_6~0); 10152#L1534-1 assume !(1 == ~E_7~0); 8281#L1539-1 assume !(1 == ~E_8~0); 8282#L1544-1 assume !(1 == ~E_9~0); 8724#L1549-1 assume !(1 == ~E_10~0); 10127#L1554-1 assume !(1 == ~E_11~0); 10125#L1559-1 assume !(1 == ~E_12~0); 9986#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 9987#L1569-1 assume { :end_inline_reset_delta_events } true; 10148#L1935-2 [2023-11-21 22:09:41,503 INFO L750 eck$LassoCheckResult]: Loop: 10148#L1935-2 assume !false; 8290#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8188#L1261-1 assume !false; 8189#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9555#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8418#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9844#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8971#L1074 assume !(0 != eval_~tmp~0#1); 8973#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8879#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8880#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10020#L1286-5 assume !(0 == ~T1_E~0); 9734#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9735#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10178#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10136#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9252#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8523#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8524#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8629#L1326-3 assume !(0 == ~T9_E~0); 9400#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9656#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9657#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8948#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8935#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8875#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8876#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9482#L1366-3 assume !(0 == ~E_3~0); 8216#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8217#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9967#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9819#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9820#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10006#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10007#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8589#L1406-3 assume !(0 == ~E_11~0); 8424#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8425#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9089#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8302#L635-45 assume !(1 == ~m_pc~0); 8304#L635-47 is_master_triggered_~__retres1~0#1 := 0; 9128#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9608#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9703#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8608#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8609#L654-45 assume !(1 == ~t1_pc~0); 9468#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 9791#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9792#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8293#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8294#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9147#L673-45 assume 1 == ~t2_pc~0; 9148#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9488#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9489#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9700#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9901#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8756#L692-45 assume 1 == ~t3_pc~0; 8757#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8464#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9922#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8805#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8806#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9132#L711-45 assume 1 == ~t4_pc~0; 9257#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9258#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9970#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9971#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 9528#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8636#L730-45 assume 1 == ~t5_pc~0; 8474#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8475#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10205#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9661#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9662#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8448#L749-45 assume !(1 == ~t6_pc~0); 8449#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 9857#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9373#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9374#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9773#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8781#L768-45 assume 1 == ~t7_pc~0; 8782#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8922#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9470#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9471#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9758#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9759#L787-45 assume 1 == ~t8_pc~0; 9924#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8928#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8929#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9354#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9355#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9660#L806-45 assume 1 == ~t9_pc~0; 10129#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8330#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9172#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9004#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8903#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8904#L825-45 assume !(1 == ~t10_pc~0); 9443#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 9444#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9906#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9692#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9693#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8529#L844-45 assume 1 == ~t11_pc~0; 8530#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9090#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8566#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8567#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9525#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8571#L863-45 assume 1 == ~t12_pc~0; 8572#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8176#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8177#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8698#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8699#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9531#L882-45 assume 1 == ~t13_pc~0; 9850#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8195#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8196#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9795#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 9996#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9623#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9624#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9790#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8487#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8488#L1449-3 assume !(1 == ~T4_E~0); 8648#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9614#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9615#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10051#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9968#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9969#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10055#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9255#L1489-3 assume !(1 == ~T12_E~0); 9256#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9897#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9557#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9558#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9982#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10025#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9173#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9174#L1529-3 assume !(1 == ~E_6~0); 10077#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9493#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8923#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 8924#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9451#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8534#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8535#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9708#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9709#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8420#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8610#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8611#L1954 assume !(0 == start_simulation_~tmp~3#1); 9682#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9918#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8719#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8220#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 8221#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9881#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9978#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10037#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 10148#L1935-2 [2023-11-21 22:09:41,504 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:41,504 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2023-11-21 22:09:41,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:41,505 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386048651] [2023-11-21 22:09:41,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:41,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:41,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:41,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:41,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:41,576 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386048651] [2023-11-21 22:09:41,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386048651] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:41,576 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:41,577 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:41,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56992373] [2023-11-21 22:09:41,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:41,578 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:41,578 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:41,579 INFO L85 PathProgramCache]: Analyzing trace with hash -315807300, now seen corresponding path program 1 times [2023-11-21 22:09:41,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:41,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646648403] [2023-11-21 22:09:41,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:41,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:41,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:41,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:41,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:41,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646648403] [2023-11-21 22:09:41,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646648403] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:41,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:41,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:41,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080815468] [2023-11-21 22:09:41,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:41,675 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:41,676 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:41,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:41,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:41,677 INFO L87 Difference]: Start difference. First operand 2035 states and 3005 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:41,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:41,735 INFO L93 Difference]: Finished difference Result 2035 states and 3004 transitions. [2023-11-21 22:09:41,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 3004 transitions. [2023-11-21 22:09:41,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:41,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 3004 transitions. [2023-11-21 22:09:41,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:41,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:41,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 3004 transitions. [2023-11-21 22:09:41,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:41,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3004 transitions. [2023-11-21 22:09:41,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 3004 transitions. [2023-11-21 22:09:41,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:41,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4761670761670762) internal successors, (3004), 2034 states have internal predecessors, (3004), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:41,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 3004 transitions. [2023-11-21 22:09:41,829 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3004 transitions. [2023-11-21 22:09:41,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:41,830 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 3004 transitions. [2023-11-21 22:09:41,831 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-21 22:09:41,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 3004 transitions. [2023-11-21 22:09:41,844 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:41,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:41,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:41,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:41,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:41,849 INFO L748 eck$LassoCheckResult]: Stem: 12560#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 13549#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13550#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14265#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 14266#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13068#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13069#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13115#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13922#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13923#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14036#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14037#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12875#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12876#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14082#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13411#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13412#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13979#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14253#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 14147#L1286-2 assume !(0 == ~T1_E~0); 12780#L1291-1 assume !(0 == ~T2_E~0); 12781#L1296-1 assume !(0 == ~T3_E~0); 13506#L1301-1 assume !(0 == ~T4_E~0); 13507#L1306-1 assume !(0 == ~T5_E~0); 13987#L1311-1 assume !(0 == ~T6_E~0); 12736#L1316-1 assume !(0 == ~T7_E~0); 12737#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13527#L1326-1 assume !(0 == ~T9_E~0); 12545#L1331-1 assume !(0 == ~T10_E~0); 12255#L1336-1 assume !(0 == ~T11_E~0); 12256#L1341-1 assume !(0 == ~T12_E~0); 12305#L1346-1 assume !(0 == ~T13_E~0); 12306#L1351-1 assume !(0 == ~E_M~0); 12673#L1356-1 assume !(0 == ~E_1~0); 12674#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14216#L1366-1 assume !(0 == ~E_3~0); 12723#L1371-1 assume !(0 == ~E_4~0); 12724#L1376-1 assume !(0 == ~E_5~0); 13583#L1381-1 assume !(0 == ~E_6~0); 13584#L1386-1 assume !(0 == ~E_7~0); 14244#L1391-1 assume !(0 == ~E_8~0); 14257#L1396-1 assume !(0 == ~E_9~0); 13454#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13455#L1406-1 assume !(0 == ~E_11~0); 13748#L1411-1 assume !(0 == ~E_12~0); 13749#L1416-1 assume !(0 == ~E_13~0); 13362#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13212#L635 assume !(1 == ~m_pc~0); 12325#L635-2 is_master_triggered_~__retres1~0#1 := 0; 12326#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12667#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13365#L1598 assume !(0 != activate_threads_~tmp~1#1); 12499#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12500#L654 assume 1 == ~t1_pc~0; 13235#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13236#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13317#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 13318#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12548#L673 assume 1 == ~t2_pc~0; 12549#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13719#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12753#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12754#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 14275#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13393#L692 assume !(1 == ~t3_pc~0); 13214#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13215#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13846#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13037#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13038#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12576#L711 assume 1 == ~t4_pc~0; 12577#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13085#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12375#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12280#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 12281#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14264#L730 assume !(1 == ~t5_pc~0); 13658#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12458#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12459#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12586#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 12587#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12941#L749 assume 1 == ~t6_pc~0; 12698#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12461#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12738#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12739#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 13151#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12260#L768 assume !(1 == ~t7_pc~0); 12261#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13604#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14119#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14104#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 13624#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12740#L787 assume 1 == ~t8_pc~0; 12741#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13938#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14197#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14198#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 12303#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12304#L806 assume 1 == ~t9_pc~0; 13947#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12338#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12339#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12588#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 12589#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13931#L825 assume !(1 == ~t10_pc~0); 13932#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13571#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13572#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12668#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12669#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13288#L844 assume 1 == ~t11_pc~0; 12963#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12964#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14032#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13975#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 13918#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13919#L863 assume !(1 == ~t12_pc~0); 12441#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12440#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12321#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12322#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 14010#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13407#L882 assume 1 == ~t13_pc~0; 13408#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13695#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 14131#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13980#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 13683#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13684#L1434 assume !(1 == ~M_E~0); 14193#L1434-2 assume !(1 == ~T1_E~0); 14268#L1439-1 assume !(1 == ~T2_E~0); 12568#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12569#L1449-1 assume !(1 == ~T4_E~0); 13032#L1454-1 assume !(1 == ~T5_E~0); 13033#L1459-1 assume !(1 == ~T6_E~0); 13625#L1464-1 assume !(1 == ~T7_E~0); 13626#L1469-1 assume !(1 == ~T8_E~0); 13696#L1474-1 assume !(1 == ~T9_E~0); 13363#L1479-1 assume !(1 == ~T10_E~0); 13364#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13630#L1489-1 assume !(1 == ~T12_E~0); 13247#L1494-1 assume !(1 == ~T13_E~0); 13248#L1499-1 assume !(1 == ~E_M~0); 13433#L1504-1 assume !(1 == ~E_1~0); 13434#L1509-1 assume !(1 == ~E_2~0); 14021#L1514-1 assume !(1 == ~E_3~0); 13730#L1519-1 assume !(1 == ~E_4~0); 13731#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14228#L1529-1 assume !(1 == ~E_6~0); 14229#L1534-1 assume !(1 == ~E_7~0); 12358#L1539-1 assume !(1 == ~E_8~0); 12359#L1544-1 assume !(1 == ~E_9~0); 12801#L1549-1 assume !(1 == ~E_10~0); 14204#L1554-1 assume !(1 == ~E_11~0); 14202#L1559-1 assume !(1 == ~E_12~0); 14063#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 14064#L1569-1 assume { :end_inline_reset_delta_events } true; 14225#L1935-2 [2023-11-21 22:09:41,850 INFO L750 eck$LassoCheckResult]: Loop: 14225#L1935-2 assume !false; 12367#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12265#L1261-1 assume !false; 12266#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13632#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12495#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13921#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13048#L1074 assume !(0 != eval_~tmp~0#1); 13050#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12956#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12957#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14097#L1286-5 assume !(0 == ~T1_E~0); 13811#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13812#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14255#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14213#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13329#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12600#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12601#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12706#L1326-3 assume !(0 == ~T9_E~0); 13477#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13733#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13734#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13025#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13012#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12952#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12953#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13559#L1366-3 assume !(0 == ~E_3~0); 12293#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12294#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14044#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13896#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13897#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14083#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14084#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12666#L1406-3 assume !(0 == ~E_11~0); 12501#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 12502#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13166#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12379#L635-45 assume 1 == ~m_pc~0; 12380#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13205#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13685#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13780#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12685#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12686#L654-45 assume !(1 == ~t1_pc~0); 13545#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 13868#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13869#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12370#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12371#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13224#L673-45 assume 1 == ~t2_pc~0; 13225#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13565#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13566#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13777#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13978#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12833#L692-45 assume 1 == ~t3_pc~0; 12834#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12541#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13999#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12882#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12883#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13209#L711-45 assume 1 == ~t4_pc~0; 13334#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13335#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14047#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14048#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 13605#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12713#L730-45 assume 1 == ~t5_pc~0; 12551#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12552#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14282#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13738#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13739#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12525#L749-45 assume !(1 == ~t6_pc~0); 12526#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 13934#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13450#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13451#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13850#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12858#L768-45 assume 1 == ~t7_pc~0; 12859#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12999#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13547#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13548#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13835#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13836#L787-45 assume 1 == ~t8_pc~0; 14001#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13005#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13006#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13431#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13432#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13737#L806-45 assume !(1 == ~t9_pc~0); 12406#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 12407#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13249#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13081#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12980#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12981#L825-45 assume !(1 == ~t10_pc~0); 13520#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 13521#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13983#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13769#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13770#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12606#L844-45 assume !(1 == ~t11_pc~0); 12608#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 13167#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12643#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12644#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13602#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12648#L863-45 assume 1 == ~t12_pc~0; 12649#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12253#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12254#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12775#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12776#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13608#L882-45 assume 1 == ~t13_pc~0; 13927#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12272#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12273#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13872#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 14073#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13700#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13701#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13867#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12564#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12565#L1449-3 assume !(1 == ~T4_E~0); 12725#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13691#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13692#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14128#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14045#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14046#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14132#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13332#L1489-3 assume !(1 == ~T12_E~0); 13333#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13974#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13634#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13635#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14059#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14102#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13250#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13251#L1529-3 assume !(1 == ~E_6~0); 14154#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13570#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13000#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13001#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13528#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12611#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12612#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13785#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13786#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12497#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12687#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12688#L1954 assume !(0 == start_simulation_~tmp~3#1); 13759#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13995#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12796#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12297#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 12298#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13958#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14055#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14114#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 14225#L1935-2 [2023-11-21 22:09:41,850 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:41,851 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2023-11-21 22:09:41,851 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:41,851 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789743042] [2023-11-21 22:09:41,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:41,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:41,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:41,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:41,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:41,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1789743042] [2023-11-21 22:09:41,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1789743042] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:41,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:41,961 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:41,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139484912] [2023-11-21 22:09:41,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:41,962 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:41,962 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:41,962 INFO L85 PathProgramCache]: Analyzing trace with hash -1523001219, now seen corresponding path program 1 times [2023-11-21 22:09:41,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:41,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763979999] [2023-11-21 22:09:41,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:41,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:41,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:42,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:42,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:42,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763979999] [2023-11-21 22:09:42,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763979999] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:42,055 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:42,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:42,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292756098] [2023-11-21 22:09:42,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:42,057 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:42,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:42,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:42,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:42,058 INFO L87 Difference]: Start difference. First operand 2035 states and 3004 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:42,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:42,116 INFO L93 Difference]: Finished difference Result 2035 states and 3003 transitions. [2023-11-21 22:09:42,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 3003 transitions. [2023-11-21 22:09:42,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:42,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 3003 transitions. [2023-11-21 22:09:42,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:42,155 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:42,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 3003 transitions. [2023-11-21 22:09:42,159 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:42,160 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3003 transitions. [2023-11-21 22:09:42,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 3003 transitions. [2023-11-21 22:09:42,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:42,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4756756756756757) internal successors, (3003), 2034 states have internal predecessors, (3003), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:42,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 3003 transitions. [2023-11-21 22:09:42,210 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3003 transitions. [2023-11-21 22:09:42,211 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:42,212 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 3003 transitions. [2023-11-21 22:09:42,212 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-21 22:09:42,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 3003 transitions. [2023-11-21 22:09:42,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:42,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:42,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:42,227 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:42,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:42,228 INFO L748 eck$LassoCheckResult]: Stem: 16637#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16638#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 17626#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17627#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18342#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 18343#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17145#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17146#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17192#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17999#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18000#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18113#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18114#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16952#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16953#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18159#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17488#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17489#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 18056#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18330#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 18224#L1286-2 assume !(0 == ~T1_E~0); 16857#L1291-1 assume !(0 == ~T2_E~0); 16858#L1296-1 assume !(0 == ~T3_E~0); 17583#L1301-1 assume !(0 == ~T4_E~0); 17584#L1306-1 assume !(0 == ~T5_E~0); 18064#L1311-1 assume !(0 == ~T6_E~0); 16813#L1316-1 assume !(0 == ~T7_E~0); 16814#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17604#L1326-1 assume !(0 == ~T9_E~0); 16622#L1331-1 assume !(0 == ~T10_E~0); 16332#L1336-1 assume !(0 == ~T11_E~0); 16333#L1341-1 assume !(0 == ~T12_E~0); 16382#L1346-1 assume !(0 == ~T13_E~0); 16383#L1351-1 assume !(0 == ~E_M~0); 16750#L1356-1 assume !(0 == ~E_1~0); 16751#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 18293#L1366-1 assume !(0 == ~E_3~0); 16800#L1371-1 assume !(0 == ~E_4~0); 16801#L1376-1 assume !(0 == ~E_5~0); 17660#L1381-1 assume !(0 == ~E_6~0); 17661#L1386-1 assume !(0 == ~E_7~0); 18321#L1391-1 assume !(0 == ~E_8~0); 18334#L1396-1 assume !(0 == ~E_9~0); 17531#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 17532#L1406-1 assume !(0 == ~E_11~0); 17825#L1411-1 assume !(0 == ~E_12~0); 17826#L1416-1 assume !(0 == ~E_13~0); 17439#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17289#L635 assume !(1 == ~m_pc~0); 16402#L635-2 is_master_triggered_~__retres1~0#1 := 0; 16403#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16744#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17442#L1598 assume !(0 != activate_threads_~tmp~1#1); 16576#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16577#L654 assume 1 == ~t1_pc~0; 17312#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17313#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17938#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17394#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 17395#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16625#L673 assume 1 == ~t2_pc~0; 16626#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17796#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16830#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16831#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 18352#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17470#L692 assume !(1 == ~t3_pc~0); 17291#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17292#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17923#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17114#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17115#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16653#L711 assume 1 == ~t4_pc~0; 16654#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17162#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16452#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16357#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 16358#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18341#L730 assume !(1 == ~t5_pc~0); 17735#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16535#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16536#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16663#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 16664#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17018#L749 assume 1 == ~t6_pc~0; 16775#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16538#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16815#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16816#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 17228#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16337#L768 assume !(1 == ~t7_pc~0); 16338#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17681#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18196#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18181#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 17701#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16817#L787 assume 1 == ~t8_pc~0; 16818#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18015#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18274#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18275#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 16380#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16381#L806 assume 1 == ~t9_pc~0; 18024#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16415#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16416#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16665#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 16666#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18008#L825 assume !(1 == ~t10_pc~0); 18009#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17648#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17649#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16745#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16746#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17365#L844 assume 1 == ~t11_pc~0; 17040#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17041#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18109#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18052#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 17995#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17996#L863 assume !(1 == ~t12_pc~0); 16518#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 16517#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16398#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16399#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 18087#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17484#L882 assume 1 == ~t13_pc~0; 17485#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17772#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 18208#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18057#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 17760#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17761#L1434 assume !(1 == ~M_E~0); 18270#L1434-2 assume !(1 == ~T1_E~0); 18345#L1439-1 assume !(1 == ~T2_E~0); 16645#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16646#L1449-1 assume !(1 == ~T4_E~0); 17109#L1454-1 assume !(1 == ~T5_E~0); 17110#L1459-1 assume !(1 == ~T6_E~0); 17702#L1464-1 assume !(1 == ~T7_E~0); 17703#L1469-1 assume !(1 == ~T8_E~0); 17773#L1474-1 assume !(1 == ~T9_E~0); 17440#L1479-1 assume !(1 == ~T10_E~0); 17441#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17707#L1489-1 assume !(1 == ~T12_E~0); 17324#L1494-1 assume !(1 == ~T13_E~0); 17325#L1499-1 assume !(1 == ~E_M~0); 17510#L1504-1 assume !(1 == ~E_1~0); 17511#L1509-1 assume !(1 == ~E_2~0); 18098#L1514-1 assume !(1 == ~E_3~0); 17807#L1519-1 assume !(1 == ~E_4~0); 17808#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18305#L1529-1 assume !(1 == ~E_6~0); 18306#L1534-1 assume !(1 == ~E_7~0); 16435#L1539-1 assume !(1 == ~E_8~0); 16436#L1544-1 assume !(1 == ~E_9~0); 16878#L1549-1 assume !(1 == ~E_10~0); 18281#L1554-1 assume !(1 == ~E_11~0); 18279#L1559-1 assume !(1 == ~E_12~0); 18140#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 18141#L1569-1 assume { :end_inline_reset_delta_events } true; 18302#L1935-2 [2023-11-21 22:09:42,229 INFO L750 eck$LassoCheckResult]: Loop: 18302#L1935-2 assume !false; 16444#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16342#L1261-1 assume !false; 16343#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17709#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16572#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17998#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 17125#L1074 assume !(0 != eval_~tmp~0#1); 17127#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17033#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17034#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18174#L1286-5 assume !(0 == ~T1_E~0); 17888#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17889#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18332#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18290#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17406#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16677#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16678#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16783#L1326-3 assume !(0 == ~T9_E~0); 17554#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17810#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17811#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17102#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17089#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17029#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17030#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17636#L1366-3 assume !(0 == ~E_3~0); 16370#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16371#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18121#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17973#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17974#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18160#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18161#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16743#L1406-3 assume !(0 == ~E_11~0); 16578#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 16579#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17243#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16456#L635-45 assume 1 == ~m_pc~0; 16457#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17282#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17762#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17857#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16762#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16763#L654-45 assume !(1 == ~t1_pc~0); 17622#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 17945#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17946#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16447#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16448#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17301#L673-45 assume 1 == ~t2_pc~0; 17302#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17642#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17643#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17854#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18055#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16910#L692-45 assume !(1 == ~t3_pc~0); 16617#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 16618#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18076#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16959#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16960#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17286#L711-45 assume 1 == ~t4_pc~0; 17411#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17412#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18124#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18125#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 17682#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16790#L730-45 assume 1 == ~t5_pc~0; 16628#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16629#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18359#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17815#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17816#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16602#L749-45 assume !(1 == ~t6_pc~0); 16603#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 18011#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17527#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17528#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17927#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16935#L768-45 assume 1 == ~t7_pc~0; 16936#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17076#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17624#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17625#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17912#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17913#L787-45 assume 1 == ~t8_pc~0; 18078#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17082#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17083#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17508#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17509#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17814#L806-45 assume !(1 == ~t9_pc~0); 16483#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 16484#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17326#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17158#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17057#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17058#L825-45 assume 1 == ~t10_pc~0; 17697#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17598#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18060#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17846#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17847#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16683#L844-45 assume 1 == ~t11_pc~0; 16684#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17244#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16720#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16721#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17679#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16725#L863-45 assume 1 == ~t12_pc~0; 16726#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16330#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16331#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16852#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16853#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17685#L882-45 assume 1 == ~t13_pc~0; 18004#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16349#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16350#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17949#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 18150#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17777#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17778#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17944#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16641#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16642#L1449-3 assume !(1 == ~T4_E~0); 16802#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17768#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17769#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18205#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18122#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18123#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18209#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17409#L1489-3 assume !(1 == ~T12_E~0); 17410#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 18051#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17711#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17712#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18136#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18179#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17327#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17328#L1529-3 assume !(1 == ~E_6~0); 18231#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17647#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17077#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17078#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17605#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16688#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16689#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17862#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17863#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16574#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16764#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 16765#L1954 assume !(0 == start_simulation_~tmp~3#1); 17836#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 18072#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16873#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16374#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 16375#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18035#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18132#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18191#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 18302#L1935-2 [2023-11-21 22:09:42,230 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:42,230 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2023-11-21 22:09:42,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:42,231 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959111692] [2023-11-21 22:09:42,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:42,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:42,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:42,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:42,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:42,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959111692] [2023-11-21 22:09:42,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959111692] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:42,298 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:42,298 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:42,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454870371] [2023-11-21 22:09:42,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:42,299 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:42,299 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:42,299 INFO L85 PathProgramCache]: Analyzing trace with hash 501748540, now seen corresponding path program 1 times [2023-11-21 22:09:42,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:42,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766883093] [2023-11-21 22:09:42,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:42,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:42,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:42,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:42,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:42,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [766883093] [2023-11-21 22:09:42,390 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [766883093] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:42,390 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:42,390 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:42,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [67843553] [2023-11-21 22:09:42,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:42,391 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:42,391 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:42,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:42,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:42,392 INFO L87 Difference]: Start difference. First operand 2035 states and 3003 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:42,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:42,450 INFO L93 Difference]: Finished difference Result 2035 states and 3002 transitions. [2023-11-21 22:09:42,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 3002 transitions. [2023-11-21 22:09:42,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:42,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 3002 transitions. [2023-11-21 22:09:42,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:42,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:42,527 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 3002 transitions. [2023-11-21 22:09:42,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:42,531 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3002 transitions. [2023-11-21 22:09:42,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 3002 transitions. [2023-11-21 22:09:42,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:42,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4751842751842752) internal successors, (3002), 2034 states have internal predecessors, (3002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:42,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 3002 transitions. [2023-11-21 22:09:42,586 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3002 transitions. [2023-11-21 22:09:42,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:42,588 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 3002 transitions. [2023-11-21 22:09:42,588 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-21 22:09:42,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 3002 transitions. [2023-11-21 22:09:42,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:42,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:42,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:42,604 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:42,604 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:42,605 INFO L748 eck$LassoCheckResult]: Stem: 20714#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20715#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 21703#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21704#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22419#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 22420#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21222#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21223#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21269#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22076#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 22077#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22190#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22191#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21029#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21030#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22236#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21565#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21566#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 22133#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22407#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 22301#L1286-2 assume !(0 == ~T1_E~0); 20934#L1291-1 assume !(0 == ~T2_E~0); 20935#L1296-1 assume !(0 == ~T3_E~0); 21660#L1301-1 assume !(0 == ~T4_E~0); 21661#L1306-1 assume !(0 == ~T5_E~0); 22141#L1311-1 assume !(0 == ~T6_E~0); 20890#L1316-1 assume !(0 == ~T7_E~0); 20891#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21681#L1326-1 assume !(0 == ~T9_E~0); 20699#L1331-1 assume !(0 == ~T10_E~0); 20409#L1336-1 assume !(0 == ~T11_E~0); 20410#L1341-1 assume !(0 == ~T12_E~0); 20459#L1346-1 assume !(0 == ~T13_E~0); 20460#L1351-1 assume !(0 == ~E_M~0); 20827#L1356-1 assume !(0 == ~E_1~0); 20828#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22370#L1366-1 assume !(0 == ~E_3~0); 20877#L1371-1 assume !(0 == ~E_4~0); 20878#L1376-1 assume !(0 == ~E_5~0); 21737#L1381-1 assume !(0 == ~E_6~0); 21738#L1386-1 assume !(0 == ~E_7~0); 22398#L1391-1 assume !(0 == ~E_8~0); 22411#L1396-1 assume !(0 == ~E_9~0); 21608#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21609#L1406-1 assume !(0 == ~E_11~0); 21902#L1411-1 assume !(0 == ~E_12~0); 21903#L1416-1 assume !(0 == ~E_13~0); 21516#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21366#L635 assume !(1 == ~m_pc~0); 20479#L635-2 is_master_triggered_~__retres1~0#1 := 0; 20480#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20821#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21519#L1598 assume !(0 != activate_threads_~tmp~1#1); 20653#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20654#L654 assume 1 == ~t1_pc~0; 21389#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21390#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22015#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21471#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 21472#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20702#L673 assume 1 == ~t2_pc~0; 20703#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21873#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20907#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20908#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 22429#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21547#L692 assume !(1 == ~t3_pc~0); 21368#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21369#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22000#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21191#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21192#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20730#L711 assume 1 == ~t4_pc~0; 20731#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21239#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20529#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20434#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 20435#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22418#L730 assume !(1 == ~t5_pc~0); 21812#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20612#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20613#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20740#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 20741#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21095#L749 assume 1 == ~t6_pc~0; 20852#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20615#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20892#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20893#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 21305#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20414#L768 assume !(1 == ~t7_pc~0); 20415#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21758#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22273#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22258#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 21778#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20894#L787 assume 1 == ~t8_pc~0; 20895#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22092#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22351#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22352#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 20457#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20458#L806 assume 1 == ~t9_pc~0; 22101#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20492#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20493#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20742#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 20743#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22085#L825 assume !(1 == ~t10_pc~0); 22086#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21725#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21726#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20822#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20823#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21442#L844 assume 1 == ~t11_pc~0; 21117#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21118#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22186#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22129#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 22072#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22073#L863 assume !(1 == ~t12_pc~0); 20595#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 20594#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20475#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20476#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 22164#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21561#L882 assume 1 == ~t13_pc~0; 21562#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21849#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 22285#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22134#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 21837#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21838#L1434 assume !(1 == ~M_E~0); 22347#L1434-2 assume !(1 == ~T1_E~0); 22422#L1439-1 assume !(1 == ~T2_E~0); 20722#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20723#L1449-1 assume !(1 == ~T4_E~0); 21186#L1454-1 assume !(1 == ~T5_E~0); 21187#L1459-1 assume !(1 == ~T6_E~0); 21779#L1464-1 assume !(1 == ~T7_E~0); 21780#L1469-1 assume !(1 == ~T8_E~0); 21850#L1474-1 assume !(1 == ~T9_E~0); 21517#L1479-1 assume !(1 == ~T10_E~0); 21518#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21784#L1489-1 assume !(1 == ~T12_E~0); 21401#L1494-1 assume !(1 == ~T13_E~0); 21402#L1499-1 assume !(1 == ~E_M~0); 21587#L1504-1 assume !(1 == ~E_1~0); 21588#L1509-1 assume !(1 == ~E_2~0); 22175#L1514-1 assume !(1 == ~E_3~0); 21884#L1519-1 assume !(1 == ~E_4~0); 21885#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22382#L1529-1 assume !(1 == ~E_6~0); 22383#L1534-1 assume !(1 == ~E_7~0); 20512#L1539-1 assume !(1 == ~E_8~0); 20513#L1544-1 assume !(1 == ~E_9~0); 20955#L1549-1 assume !(1 == ~E_10~0); 22358#L1554-1 assume !(1 == ~E_11~0); 22356#L1559-1 assume !(1 == ~E_12~0); 22217#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22218#L1569-1 assume { :end_inline_reset_delta_events } true; 22379#L1935-2 [2023-11-21 22:09:42,606 INFO L750 eck$LassoCheckResult]: Loop: 22379#L1935-2 assume !false; 20521#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20419#L1261-1 assume !false; 20420#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21786#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20649#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 22075#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21202#L1074 assume !(0 != eval_~tmp~0#1); 21204#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21110#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21111#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22251#L1286-5 assume !(0 == ~T1_E~0); 21965#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21966#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22409#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22367#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21483#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20754#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20755#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20860#L1326-3 assume !(0 == ~T9_E~0); 21631#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21887#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21888#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21179#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21166#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21106#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21107#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21713#L1366-3 assume !(0 == ~E_3~0); 20447#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20448#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22198#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22050#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22051#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22237#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22238#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20820#L1406-3 assume !(0 == ~E_11~0); 20655#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 20656#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21320#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20533#L635-45 assume 1 == ~m_pc~0; 20534#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21359#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21839#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21934#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20839#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20840#L654-45 assume !(1 == ~t1_pc~0); 21699#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 22022#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22023#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20524#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20525#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21378#L673-45 assume 1 == ~t2_pc~0; 21379#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21719#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21720#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21931#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22132#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20987#L692-45 assume !(1 == ~t3_pc~0); 20694#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 20695#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22153#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21036#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21037#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21363#L711-45 assume 1 == ~t4_pc~0; 21488#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21489#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22201#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22202#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 21759#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20867#L730-45 assume 1 == ~t5_pc~0; 20705#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20706#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22436#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21892#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21893#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20679#L749-45 assume !(1 == ~t6_pc~0); 20680#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 22088#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21604#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21605#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22004#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21012#L768-45 assume 1 == ~t7_pc~0; 21013#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21153#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21701#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21702#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21989#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21990#L787-45 assume 1 == ~t8_pc~0; 22155#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21159#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21160#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21585#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21586#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21891#L806-45 assume !(1 == ~t9_pc~0); 20560#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 20561#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21403#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21235#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21134#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21135#L825-45 assume !(1 == ~t10_pc~0); 21674#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 21675#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22137#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21923#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21924#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20760#L844-45 assume 1 == ~t11_pc~0; 20761#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21321#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20797#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20798#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21756#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20802#L863-45 assume 1 == ~t12_pc~0; 20803#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20407#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20408#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20929#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20930#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21762#L882-45 assume 1 == ~t13_pc~0; 22081#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20426#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20427#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22026#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 22227#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21854#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21855#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22021#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20718#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20719#L1449-3 assume !(1 == ~T4_E~0); 20879#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21845#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21846#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22282#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22199#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22200#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22286#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21486#L1489-3 assume !(1 == ~T12_E~0); 21487#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 22128#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21788#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21789#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22213#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22256#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21404#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21405#L1529-3 assume !(1 == ~E_6~0); 22308#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21724#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21154#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21155#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21682#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20765#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20766#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21939#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21940#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20651#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20841#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 20842#L1954 assume !(0 == start_simulation_~tmp~3#1); 21913#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 22149#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20950#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20451#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 20452#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22112#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22209#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22268#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 22379#L1935-2 [2023-11-21 22:09:42,607 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:42,607 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2023-11-21 22:09:42,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:42,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079832304] [2023-11-21 22:09:42,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:42,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:42,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:42,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:42,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:42,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079832304] [2023-11-21 22:09:42,683 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079832304] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:42,683 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:42,683 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:42,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598598798] [2023-11-21 22:09:42,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:42,684 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:42,685 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:42,685 INFO L85 PathProgramCache]: Analyzing trace with hash 879391357, now seen corresponding path program 1 times [2023-11-21 22:09:42,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:42,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161945120] [2023-11-21 22:09:42,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:42,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:42,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:42,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:42,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:42,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161945120] [2023-11-21 22:09:42,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161945120] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:42,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:42,782 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:42,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952177988] [2023-11-21 22:09:42,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:42,783 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:42,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:42,784 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:42,784 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:42,785 INFO L87 Difference]: Start difference. First operand 2035 states and 3002 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:42,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:42,842 INFO L93 Difference]: Finished difference Result 2035 states and 3001 transitions. [2023-11-21 22:09:42,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 3001 transitions. [2023-11-21 22:09:42,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:42,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 3001 transitions. [2023-11-21 22:09:42,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:42,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:42,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 3001 transitions. [2023-11-21 22:09:42,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:42,879 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3001 transitions. [2023-11-21 22:09:42,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 3001 transitions. [2023-11-21 22:09:42,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:42,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4746928746928747) internal successors, (3001), 2034 states have internal predecessors, (3001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:42,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 3001 transitions. [2023-11-21 22:09:42,927 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3001 transitions. [2023-11-21 22:09:42,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:42,928 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 3001 transitions. [2023-11-21 22:09:42,929 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-21 22:09:42,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 3001 transitions. [2023-11-21 22:09:42,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:42,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:42,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:42,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:42,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:42,943 INFO L748 eck$LassoCheckResult]: Stem: 24791#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 25780#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25781#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26496#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 26497#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25299#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25300#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25346#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26153#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26154#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26267#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26268#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25106#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25107#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26313#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25642#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25643#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 26210#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26484#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 26378#L1286-2 assume !(0 == ~T1_E~0); 25011#L1291-1 assume !(0 == ~T2_E~0); 25012#L1296-1 assume !(0 == ~T3_E~0); 25737#L1301-1 assume !(0 == ~T4_E~0); 25738#L1306-1 assume !(0 == ~T5_E~0); 26218#L1311-1 assume !(0 == ~T6_E~0); 24967#L1316-1 assume !(0 == ~T7_E~0); 24968#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25758#L1326-1 assume !(0 == ~T9_E~0); 24776#L1331-1 assume !(0 == ~T10_E~0); 24486#L1336-1 assume !(0 == ~T11_E~0); 24487#L1341-1 assume !(0 == ~T12_E~0); 24536#L1346-1 assume !(0 == ~T13_E~0); 24537#L1351-1 assume !(0 == ~E_M~0); 24904#L1356-1 assume !(0 == ~E_1~0); 24905#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 26447#L1366-1 assume !(0 == ~E_3~0); 24954#L1371-1 assume !(0 == ~E_4~0); 24955#L1376-1 assume !(0 == ~E_5~0); 25814#L1381-1 assume !(0 == ~E_6~0); 25815#L1386-1 assume !(0 == ~E_7~0); 26475#L1391-1 assume !(0 == ~E_8~0); 26488#L1396-1 assume !(0 == ~E_9~0); 25685#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 25686#L1406-1 assume !(0 == ~E_11~0); 25979#L1411-1 assume !(0 == ~E_12~0); 25980#L1416-1 assume !(0 == ~E_13~0); 25593#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25443#L635 assume !(1 == ~m_pc~0); 24556#L635-2 is_master_triggered_~__retres1~0#1 := 0; 24557#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24898#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25596#L1598 assume !(0 != activate_threads_~tmp~1#1); 24730#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24731#L654 assume 1 == ~t1_pc~0; 25466#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25467#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26092#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25548#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 25549#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24779#L673 assume 1 == ~t2_pc~0; 24780#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25950#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24984#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24985#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 26506#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25624#L692 assume !(1 == ~t3_pc~0); 25445#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25446#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25268#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25269#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24807#L711 assume 1 == ~t4_pc~0; 24808#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25316#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24606#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24511#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 24512#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26495#L730 assume !(1 == ~t5_pc~0); 25889#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24689#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24690#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24817#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 24818#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25172#L749 assume 1 == ~t6_pc~0; 24929#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24692#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24969#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24970#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 25382#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24491#L768 assume !(1 == ~t7_pc~0); 24492#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 25835#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26350#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26335#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 25855#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24971#L787 assume 1 == ~t8_pc~0; 24972#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26169#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26428#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26429#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 24534#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24535#L806 assume 1 == ~t9_pc~0; 26178#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24569#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24570#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24819#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 24820#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26162#L825 assume !(1 == ~t10_pc~0); 26163#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25802#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25803#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24899#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24900#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25519#L844 assume 1 == ~t11_pc~0; 25194#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25195#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26263#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26206#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 26149#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26150#L863 assume !(1 == ~t12_pc~0); 24672#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 24671#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24552#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24553#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 26241#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25638#L882 assume 1 == ~t13_pc~0; 25639#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25926#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 26362#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26211#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 25914#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25915#L1434 assume !(1 == ~M_E~0); 26424#L1434-2 assume !(1 == ~T1_E~0); 26499#L1439-1 assume !(1 == ~T2_E~0); 24799#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24800#L1449-1 assume !(1 == ~T4_E~0); 25263#L1454-1 assume !(1 == ~T5_E~0); 25264#L1459-1 assume !(1 == ~T6_E~0); 25856#L1464-1 assume !(1 == ~T7_E~0); 25857#L1469-1 assume !(1 == ~T8_E~0); 25927#L1474-1 assume !(1 == ~T9_E~0); 25594#L1479-1 assume !(1 == ~T10_E~0); 25595#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25861#L1489-1 assume !(1 == ~T12_E~0); 25478#L1494-1 assume !(1 == ~T13_E~0); 25479#L1499-1 assume !(1 == ~E_M~0); 25664#L1504-1 assume !(1 == ~E_1~0); 25665#L1509-1 assume !(1 == ~E_2~0); 26252#L1514-1 assume !(1 == ~E_3~0); 25961#L1519-1 assume !(1 == ~E_4~0); 25962#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26459#L1529-1 assume !(1 == ~E_6~0); 26460#L1534-1 assume !(1 == ~E_7~0); 24589#L1539-1 assume !(1 == ~E_8~0); 24590#L1544-1 assume !(1 == ~E_9~0); 25032#L1549-1 assume !(1 == ~E_10~0); 26435#L1554-1 assume !(1 == ~E_11~0); 26433#L1559-1 assume !(1 == ~E_12~0); 26294#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 26295#L1569-1 assume { :end_inline_reset_delta_events } true; 26456#L1935-2 [2023-11-21 22:09:42,943 INFO L750 eck$LassoCheckResult]: Loop: 26456#L1935-2 assume !false; 24598#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24496#L1261-1 assume !false; 24497#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25863#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24726#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 26152#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25279#L1074 assume !(0 != eval_~tmp~0#1); 25281#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25187#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25188#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26328#L1286-5 assume !(0 == ~T1_E~0); 26042#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26043#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26486#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26444#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25560#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24831#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24832#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24937#L1326-3 assume !(0 == ~T9_E~0); 25708#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25964#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25965#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25256#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25243#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25183#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25184#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25790#L1366-3 assume !(0 == ~E_3~0); 24524#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24525#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26275#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26127#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26128#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26314#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26315#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24897#L1406-3 assume !(0 == ~E_11~0); 24732#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 24733#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25397#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24610#L635-45 assume 1 == ~m_pc~0; 24611#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25436#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25916#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26011#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24916#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24917#L654-45 assume !(1 == ~t1_pc~0); 25776#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 26099#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26100#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24601#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24602#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25455#L673-45 assume 1 == ~t2_pc~0; 25456#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25796#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25797#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26008#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26209#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25064#L692-45 assume !(1 == ~t3_pc~0); 24771#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 24772#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26230#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25113#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25114#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25440#L711-45 assume 1 == ~t4_pc~0; 25565#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25566#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26278#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26279#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 25836#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24944#L730-45 assume !(1 == ~t5_pc~0); 24784#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 24783#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26513#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25969#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25970#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24756#L749-45 assume !(1 == ~t6_pc~0); 24757#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 26165#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25681#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25682#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26081#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25089#L768-45 assume 1 == ~t7_pc~0; 25090#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25230#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25778#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25779#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26066#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26067#L787-45 assume 1 == ~t8_pc~0; 26232#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25236#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25237#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25662#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25663#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25968#L806-45 assume 1 == ~t9_pc~0; 26437#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24638#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25480#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25312#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25211#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25212#L825-45 assume !(1 == ~t10_pc~0); 25751#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 25752#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26214#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26000#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26001#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24837#L844-45 assume 1 == ~t11_pc~0; 24838#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25398#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24874#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24875#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25833#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24879#L863-45 assume 1 == ~t12_pc~0; 24880#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24484#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24485#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25006#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25007#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25839#L882-45 assume !(1 == ~t13_pc~0); 25363#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 24503#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 24504#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26103#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 26304#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25931#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25932#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26098#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24795#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24796#L1449-3 assume !(1 == ~T4_E~0); 24956#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25922#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25923#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26359#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26276#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26277#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26363#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25563#L1489-3 assume !(1 == ~T12_E~0); 25564#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 26205#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25865#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25866#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26290#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26333#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25481#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25482#L1529-3 assume !(1 == ~E_6~0); 26385#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25801#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25231#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25232#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25759#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24842#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24843#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 26016#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 26017#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24728#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24918#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 24919#L1954 assume !(0 == start_simulation_~tmp~3#1); 25990#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 26226#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 25027#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24528#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 24529#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26189#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26286#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26345#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 26456#L1935-2 [2023-11-21 22:09:42,944 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:42,945 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2023-11-21 22:09:42,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:42,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1729083963] [2023-11-21 22:09:42,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:42,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:42,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:43,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:43,002 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:43,002 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1729083963] [2023-11-21 22:09:43,003 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1729083963] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:43,003 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:43,003 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:43,003 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504769615] [2023-11-21 22:09:43,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:43,004 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:43,004 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:43,005 INFO L85 PathProgramCache]: Analyzing trace with hash 814193918, now seen corresponding path program 1 times [2023-11-21 22:09:43,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:43,005 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152763074] [2023-11-21 22:09:43,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:43,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:43,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:43,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:43,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:43,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152763074] [2023-11-21 22:09:43,093 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1152763074] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:43,093 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:43,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:43,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850934565] [2023-11-21 22:09:43,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:43,094 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:43,094 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:43,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:43,095 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:43,095 INFO L87 Difference]: Start difference. First operand 2035 states and 3001 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:43,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:43,182 INFO L93 Difference]: Finished difference Result 2035 states and 3000 transitions. [2023-11-21 22:09:43,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 3000 transitions. [2023-11-21 22:09:43,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:43,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 3000 transitions. [2023-11-21 22:09:43,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:43,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:43,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 3000 transitions. [2023-11-21 22:09:43,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:43,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3000 transitions. [2023-11-21 22:09:43,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 3000 transitions. [2023-11-21 22:09:43,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:43,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4742014742014742) internal successors, (3000), 2034 states have internal predecessors, (3000), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:43,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 3000 transitions. [2023-11-21 22:09:43,275 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 3000 transitions. [2023-11-21 22:09:43,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:43,278 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 3000 transitions. [2023-11-21 22:09:43,278 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-21 22:09:43,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 3000 transitions. [2023-11-21 22:09:43,287 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:43,287 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:43,287 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:43,290 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:43,290 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:43,291 INFO L748 eck$LassoCheckResult]: Stem: 28868#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28869#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 29857#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29858#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30573#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 30574#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29376#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29377#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29423#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30230#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30231#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30344#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30345#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29183#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29184#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30390#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29719#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29720#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 30287#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30561#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 30455#L1286-2 assume !(0 == ~T1_E~0); 29088#L1291-1 assume !(0 == ~T2_E~0); 29089#L1296-1 assume !(0 == ~T3_E~0); 29814#L1301-1 assume !(0 == ~T4_E~0); 29815#L1306-1 assume !(0 == ~T5_E~0); 30295#L1311-1 assume !(0 == ~T6_E~0); 29044#L1316-1 assume !(0 == ~T7_E~0); 29045#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29835#L1326-1 assume !(0 == ~T9_E~0); 28853#L1331-1 assume !(0 == ~T10_E~0); 28563#L1336-1 assume !(0 == ~T11_E~0); 28564#L1341-1 assume !(0 == ~T12_E~0); 28613#L1346-1 assume !(0 == ~T13_E~0); 28614#L1351-1 assume !(0 == ~E_M~0); 28981#L1356-1 assume !(0 == ~E_1~0); 28982#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 30524#L1366-1 assume !(0 == ~E_3~0); 29031#L1371-1 assume !(0 == ~E_4~0); 29032#L1376-1 assume !(0 == ~E_5~0); 29891#L1381-1 assume !(0 == ~E_6~0); 29892#L1386-1 assume !(0 == ~E_7~0); 30552#L1391-1 assume !(0 == ~E_8~0); 30565#L1396-1 assume !(0 == ~E_9~0); 29762#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 29763#L1406-1 assume !(0 == ~E_11~0); 30056#L1411-1 assume !(0 == ~E_12~0); 30057#L1416-1 assume !(0 == ~E_13~0); 29670#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29520#L635 assume !(1 == ~m_pc~0); 28633#L635-2 is_master_triggered_~__retres1~0#1 := 0; 28634#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28975#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29673#L1598 assume !(0 != activate_threads_~tmp~1#1); 28807#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28808#L654 assume 1 == ~t1_pc~0; 29543#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29544#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30169#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29625#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 29626#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28856#L673 assume 1 == ~t2_pc~0; 28857#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30027#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29061#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29062#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 30583#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29701#L692 assume !(1 == ~t3_pc~0); 29522#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29523#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30154#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29345#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29346#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28884#L711 assume 1 == ~t4_pc~0; 28885#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29393#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28683#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28588#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 28589#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30572#L730 assume !(1 == ~t5_pc~0); 29966#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28766#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28767#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28894#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 28895#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29249#L749 assume 1 == ~t6_pc~0; 29006#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28769#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29046#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29047#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 29459#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28568#L768 assume !(1 == ~t7_pc~0); 28569#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 29912#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30427#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30412#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 29932#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29048#L787 assume 1 == ~t8_pc~0; 29049#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30246#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30505#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30506#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 28611#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28612#L806 assume 1 == ~t9_pc~0; 30255#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28646#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28647#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28896#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 28897#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30239#L825 assume !(1 == ~t10_pc~0); 30240#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29879#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29880#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28976#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28977#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29596#L844 assume 1 == ~t11_pc~0; 29271#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29272#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30340#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30283#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 30226#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30227#L863 assume !(1 == ~t12_pc~0); 28749#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 28748#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28629#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28630#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 30318#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29715#L882 assume 1 == ~t13_pc~0; 29716#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30003#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30439#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30288#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 29991#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29992#L1434 assume !(1 == ~M_E~0); 30501#L1434-2 assume !(1 == ~T1_E~0); 30576#L1439-1 assume !(1 == ~T2_E~0); 28876#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28877#L1449-1 assume !(1 == ~T4_E~0); 29340#L1454-1 assume !(1 == ~T5_E~0); 29341#L1459-1 assume !(1 == ~T6_E~0); 29933#L1464-1 assume !(1 == ~T7_E~0); 29934#L1469-1 assume !(1 == ~T8_E~0); 30004#L1474-1 assume !(1 == ~T9_E~0); 29671#L1479-1 assume !(1 == ~T10_E~0); 29672#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29938#L1489-1 assume !(1 == ~T12_E~0); 29555#L1494-1 assume !(1 == ~T13_E~0); 29556#L1499-1 assume !(1 == ~E_M~0); 29741#L1504-1 assume !(1 == ~E_1~0); 29742#L1509-1 assume !(1 == ~E_2~0); 30329#L1514-1 assume !(1 == ~E_3~0); 30038#L1519-1 assume !(1 == ~E_4~0); 30039#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30536#L1529-1 assume !(1 == ~E_6~0); 30537#L1534-1 assume !(1 == ~E_7~0); 28666#L1539-1 assume !(1 == ~E_8~0); 28667#L1544-1 assume !(1 == ~E_9~0); 29109#L1549-1 assume !(1 == ~E_10~0); 30512#L1554-1 assume !(1 == ~E_11~0); 30510#L1559-1 assume !(1 == ~E_12~0); 30371#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30372#L1569-1 assume { :end_inline_reset_delta_events } true; 30533#L1935-2 [2023-11-21 22:09:43,292 INFO L750 eck$LassoCheckResult]: Loop: 30533#L1935-2 assume !false; 28675#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28573#L1261-1 assume !false; 28574#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29940#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28803#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30229#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29356#L1074 assume !(0 != eval_~tmp~0#1); 29358#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29264#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29265#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30405#L1286-5 assume !(0 == ~T1_E~0); 30119#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30120#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30563#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30521#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29637#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28908#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28909#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29014#L1326-3 assume !(0 == ~T9_E~0); 29785#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30041#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30042#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29333#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29320#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29260#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29261#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29867#L1366-3 assume !(0 == ~E_3~0); 28601#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28602#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30352#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30204#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30205#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30391#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30392#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28974#L1406-3 assume !(0 == ~E_11~0); 28809#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28810#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29474#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28687#L635-45 assume 1 == ~m_pc~0; 28688#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29513#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29993#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30088#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28993#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28994#L654-45 assume !(1 == ~t1_pc~0); 29853#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 30176#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30177#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28678#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28679#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29532#L673-45 assume 1 == ~t2_pc~0; 29533#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29873#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29874#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30085#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30286#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29141#L692-45 assume !(1 == ~t3_pc~0); 28848#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 28849#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30307#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29190#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29191#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29517#L711-45 assume 1 == ~t4_pc~0; 29642#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29643#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30355#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30356#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 29913#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29021#L730-45 assume 1 == ~t5_pc~0; 28859#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28860#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30590#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30046#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30047#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28833#L749-45 assume !(1 == ~t6_pc~0); 28834#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 30242#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29758#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29759#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30158#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29166#L768-45 assume !(1 == ~t7_pc~0); 29168#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 29307#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29855#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29856#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30143#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30144#L787-45 assume 1 == ~t8_pc~0; 30309#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29313#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29314#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29739#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29740#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30045#L806-45 assume 1 == ~t9_pc~0; 30514#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28715#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29557#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29389#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29288#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29289#L825-45 assume !(1 == ~t10_pc~0); 29828#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 29829#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30291#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30077#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30078#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28914#L844-45 assume 1 == ~t11_pc~0; 28915#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29475#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28951#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28952#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29910#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28956#L863-45 assume 1 == ~t12_pc~0; 28957#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28561#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28562#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29083#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29084#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29916#L882-45 assume !(1 == ~t13_pc~0); 29440#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 28580#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 28581#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30180#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 30381#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30008#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30009#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30175#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28872#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28873#L1449-3 assume !(1 == ~T4_E~0); 29033#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29999#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30000#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30436#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30353#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30354#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30440#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29640#L1489-3 assume !(1 == ~T12_E~0); 29641#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 30282#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29942#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29943#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30367#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30410#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29558#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29559#L1529-3 assume !(1 == ~E_6~0); 30462#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29878#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29308#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29309#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29836#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28919#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28920#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 30093#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 30094#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28805#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28995#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 28996#L1954 assume !(0 == start_simulation_~tmp~3#1); 30067#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 30303#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 29104#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28605#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 28606#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30266#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30363#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30422#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 30533#L1935-2 [2023-11-21 22:09:43,293 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:43,293 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2023-11-21 22:09:43,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:43,293 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402272901] [2023-11-21 22:09:43,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:43,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:43,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:43,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:43,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:43,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402272901] [2023-11-21 22:09:43,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402272901] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:43,356 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:43,356 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:43,360 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1073415875] [2023-11-21 22:09:43,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:43,361 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:43,361 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:43,361 INFO L85 PathProgramCache]: Analyzing trace with hash -458877314, now seen corresponding path program 1 times [2023-11-21 22:09:43,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:43,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123796039] [2023-11-21 22:09:43,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:43,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:43,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:43,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:43,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:43,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123796039] [2023-11-21 22:09:43,438 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123796039] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:43,438 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:43,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:43,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1842734646] [2023-11-21 22:09:43,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:43,439 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:43,439 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:43,440 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:43,440 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:43,440 INFO L87 Difference]: Start difference. First operand 2035 states and 3000 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:43,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:43,491 INFO L93 Difference]: Finished difference Result 2035 states and 2999 transitions. [2023-11-21 22:09:43,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 2999 transitions. [2023-11-21 22:09:43,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:43,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 2999 transitions. [2023-11-21 22:09:43,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:43,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:43,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 2999 transitions. [2023-11-21 22:09:43,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:43,522 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2999 transitions. [2023-11-21 22:09:43,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 2999 transitions. [2023-11-21 22:09:43,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:43,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4737100737100737) internal successors, (2999), 2034 states have internal predecessors, (2999), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:43,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 2999 transitions. [2023-11-21 22:09:43,565 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2999 transitions. [2023-11-21 22:09:43,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:43,568 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 2999 transitions. [2023-11-21 22:09:43,569 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-21 22:09:43,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 2999 transitions. [2023-11-21 22:09:43,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:43,578 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:43,578 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:43,581 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:43,581 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:43,582 INFO L748 eck$LassoCheckResult]: Stem: 32945#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32946#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33934#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33935#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34650#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 34651#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33453#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33454#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33500#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34307#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34308#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34421#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34422#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33260#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33261#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 34467#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33796#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33797#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 34364#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34638#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 34532#L1286-2 assume !(0 == ~T1_E~0); 33165#L1291-1 assume !(0 == ~T2_E~0); 33166#L1296-1 assume !(0 == ~T3_E~0); 33891#L1301-1 assume !(0 == ~T4_E~0); 33892#L1306-1 assume !(0 == ~T5_E~0); 34372#L1311-1 assume !(0 == ~T6_E~0); 33121#L1316-1 assume !(0 == ~T7_E~0); 33122#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33912#L1326-1 assume !(0 == ~T9_E~0); 32930#L1331-1 assume !(0 == ~T10_E~0); 32640#L1336-1 assume !(0 == ~T11_E~0); 32641#L1341-1 assume !(0 == ~T12_E~0); 32690#L1346-1 assume !(0 == ~T13_E~0); 32691#L1351-1 assume !(0 == ~E_M~0); 33058#L1356-1 assume !(0 == ~E_1~0); 33059#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 34601#L1366-1 assume !(0 == ~E_3~0); 33108#L1371-1 assume !(0 == ~E_4~0); 33109#L1376-1 assume !(0 == ~E_5~0); 33968#L1381-1 assume !(0 == ~E_6~0); 33969#L1386-1 assume !(0 == ~E_7~0); 34629#L1391-1 assume !(0 == ~E_8~0); 34642#L1396-1 assume !(0 == ~E_9~0); 33839#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 33840#L1406-1 assume !(0 == ~E_11~0); 34133#L1411-1 assume !(0 == ~E_12~0); 34134#L1416-1 assume !(0 == ~E_13~0); 33747#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33597#L635 assume !(1 == ~m_pc~0); 32710#L635-2 is_master_triggered_~__retres1~0#1 := 0; 32711#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33052#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33750#L1598 assume !(0 != activate_threads_~tmp~1#1); 32884#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32885#L654 assume 1 == ~t1_pc~0; 33620#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33621#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34246#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33702#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 33703#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32933#L673 assume 1 == ~t2_pc~0; 32934#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34104#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33138#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33139#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 34660#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33778#L692 assume !(1 == ~t3_pc~0); 33599#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33600#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34231#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33422#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33423#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32961#L711 assume 1 == ~t4_pc~0; 32962#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33470#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32760#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32665#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 32666#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34649#L730 assume !(1 == ~t5_pc~0); 34043#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32843#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32844#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32971#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 32972#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33326#L749 assume 1 == ~t6_pc~0; 33083#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32846#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33123#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33124#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 33536#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32645#L768 assume !(1 == ~t7_pc~0); 32646#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33989#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34504#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34489#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 34009#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33125#L787 assume 1 == ~t8_pc~0; 33126#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34323#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34582#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34583#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 32688#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32689#L806 assume 1 == ~t9_pc~0; 34332#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32723#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32724#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32973#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 32974#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34316#L825 assume !(1 == ~t10_pc~0); 34317#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33956#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33957#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33053#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33054#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33673#L844 assume 1 == ~t11_pc~0; 33348#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33349#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34417#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34360#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 34303#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34304#L863 assume !(1 == ~t12_pc~0); 32826#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 32825#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32706#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 32707#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 34395#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33792#L882 assume 1 == ~t13_pc~0; 33793#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 34080#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34516#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34365#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 34068#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34069#L1434 assume !(1 == ~M_E~0); 34578#L1434-2 assume !(1 == ~T1_E~0); 34653#L1439-1 assume !(1 == ~T2_E~0); 32953#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32954#L1449-1 assume !(1 == ~T4_E~0); 33417#L1454-1 assume !(1 == ~T5_E~0); 33418#L1459-1 assume !(1 == ~T6_E~0); 34010#L1464-1 assume !(1 == ~T7_E~0); 34011#L1469-1 assume !(1 == ~T8_E~0); 34081#L1474-1 assume !(1 == ~T9_E~0); 33748#L1479-1 assume !(1 == ~T10_E~0); 33749#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34015#L1489-1 assume !(1 == ~T12_E~0); 33632#L1494-1 assume !(1 == ~T13_E~0); 33633#L1499-1 assume !(1 == ~E_M~0); 33818#L1504-1 assume !(1 == ~E_1~0); 33819#L1509-1 assume !(1 == ~E_2~0); 34406#L1514-1 assume !(1 == ~E_3~0); 34115#L1519-1 assume !(1 == ~E_4~0); 34116#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34613#L1529-1 assume !(1 == ~E_6~0); 34614#L1534-1 assume !(1 == ~E_7~0); 32743#L1539-1 assume !(1 == ~E_8~0); 32744#L1544-1 assume !(1 == ~E_9~0); 33186#L1549-1 assume !(1 == ~E_10~0); 34589#L1554-1 assume !(1 == ~E_11~0); 34587#L1559-1 assume !(1 == ~E_12~0); 34448#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 34449#L1569-1 assume { :end_inline_reset_delta_events } true; 34610#L1935-2 [2023-11-21 22:09:43,583 INFO L750 eck$LassoCheckResult]: Loop: 34610#L1935-2 assume !false; 32752#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32650#L1261-1 assume !false; 32651#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34017#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32880#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34306#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33433#L1074 assume !(0 != eval_~tmp~0#1); 33435#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33341#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33342#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34482#L1286-5 assume !(0 == ~T1_E~0); 34196#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34197#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34640#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34598#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33714#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32985#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32986#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33091#L1326-3 assume !(0 == ~T9_E~0); 33862#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34118#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34119#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33410#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33397#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33337#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33338#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33944#L1366-3 assume !(0 == ~E_3~0); 32678#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32679#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34429#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34281#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34282#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34468#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34469#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33051#L1406-3 assume !(0 == ~E_11~0); 32886#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32887#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33551#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32764#L635-45 assume 1 == ~m_pc~0; 32765#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33590#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34070#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34165#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33070#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33071#L654-45 assume !(1 == ~t1_pc~0); 33930#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 34253#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34254#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32755#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32756#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33609#L673-45 assume 1 == ~t2_pc~0; 33610#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33950#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33951#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34162#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34363#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33218#L692-45 assume 1 == ~t3_pc~0; 33219#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32926#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34384#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33267#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33268#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33594#L711-45 assume 1 == ~t4_pc~0; 33719#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33720#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34432#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34433#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 33990#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33098#L730-45 assume 1 == ~t5_pc~0; 32936#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32937#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34667#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34123#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34124#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32910#L749-45 assume 1 == ~t6_pc~0; 32912#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34319#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33835#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33836#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34235#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33243#L768-45 assume 1 == ~t7_pc~0; 33244#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33384#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33932#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33933#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34220#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34221#L787-45 assume 1 == ~t8_pc~0; 34386#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33390#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33391#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33816#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33817#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34122#L806-45 assume !(1 == ~t9_pc~0); 32791#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 32792#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33634#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33466#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33365#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33366#L825-45 assume !(1 == ~t10_pc~0); 33905#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 33906#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34368#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34154#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34155#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32991#L844-45 assume 1 == ~t11_pc~0; 32992#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33552#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33028#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33029#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 33987#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33033#L863-45 assume 1 == ~t12_pc~0; 33034#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32638#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32639#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33160#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33161#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33993#L882-45 assume 1 == ~t13_pc~0; 34312#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 32657#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 32658#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34257#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 34458#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34085#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34086#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34252#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32949#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32950#L1449-3 assume !(1 == ~T4_E~0); 33110#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34076#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34077#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34513#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34430#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34431#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34517#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33717#L1489-3 assume !(1 == ~T12_E~0); 33718#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34359#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34019#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34020#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34444#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34487#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33635#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33636#L1529-3 assume !(1 == ~E_6~0); 34539#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33955#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33385#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33386#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33913#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32996#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32997#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 34170#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34171#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32882#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33072#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 33073#L1954 assume !(0 == start_simulation_~tmp~3#1); 34144#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34380#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33181#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32682#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 32683#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34343#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34440#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34499#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 34610#L1935-2 [2023-11-21 22:09:43,583 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:43,584 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2023-11-21 22:09:43,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:43,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972388219] [2023-11-21 22:09:43,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:43,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:43,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:43,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:43,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:43,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972388219] [2023-11-21 22:09:43,639 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972388219] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:43,640 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:43,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:43,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [271389579] [2023-11-21 22:09:43,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:43,641 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:43,641 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:43,641 INFO L85 PathProgramCache]: Analyzing trace with hash 895010875, now seen corresponding path program 1 times [2023-11-21 22:09:43,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:43,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651247615] [2023-11-21 22:09:43,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:43,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:43,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:43,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:43,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:43,724 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651247615] [2023-11-21 22:09:43,724 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [651247615] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:43,724 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:43,725 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:43,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879248142] [2023-11-21 22:09:43,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:43,725 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:43,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:43,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:43,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:43,726 INFO L87 Difference]: Start difference. First operand 2035 states and 2999 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:43,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:43,778 INFO L93 Difference]: Finished difference Result 2035 states and 2998 transitions. [2023-11-21 22:09:43,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 2998 transitions. [2023-11-21 22:09:43,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:43,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 2998 transitions. [2023-11-21 22:09:43,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:43,817 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:43,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 2998 transitions. [2023-11-21 22:09:43,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:43,820 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2998 transitions. [2023-11-21 22:09:43,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 2998 transitions. [2023-11-21 22:09:43,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:43,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4732186732186732) internal successors, (2998), 2034 states have internal predecessors, (2998), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:43,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 2998 transitions. [2023-11-21 22:09:43,884 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2998 transitions. [2023-11-21 22:09:43,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:43,885 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 2998 transitions. [2023-11-21 22:09:43,886 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-21 22:09:43,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 2998 transitions. [2023-11-21 22:09:43,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:43,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:43,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:43,899 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:43,899 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:43,900 INFO L748 eck$LassoCheckResult]: Stem: 37022#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 38011#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38012#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38727#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 38728#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37530#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37531#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37577#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38384#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38385#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38498#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38499#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37337#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37338#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 38544#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37873#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37874#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38441#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38715#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 38609#L1286-2 assume !(0 == ~T1_E~0); 37242#L1291-1 assume !(0 == ~T2_E~0); 37243#L1296-1 assume !(0 == ~T3_E~0); 37968#L1301-1 assume !(0 == ~T4_E~0); 37969#L1306-1 assume !(0 == ~T5_E~0); 38449#L1311-1 assume !(0 == ~T6_E~0); 37198#L1316-1 assume !(0 == ~T7_E~0); 37199#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37989#L1326-1 assume !(0 == ~T9_E~0); 37007#L1331-1 assume !(0 == ~T10_E~0); 36717#L1336-1 assume !(0 == ~T11_E~0); 36718#L1341-1 assume !(0 == ~T12_E~0); 36767#L1346-1 assume !(0 == ~T13_E~0); 36768#L1351-1 assume !(0 == ~E_M~0); 37135#L1356-1 assume !(0 == ~E_1~0); 37136#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 38678#L1366-1 assume !(0 == ~E_3~0); 37185#L1371-1 assume !(0 == ~E_4~0); 37186#L1376-1 assume !(0 == ~E_5~0); 38045#L1381-1 assume !(0 == ~E_6~0); 38046#L1386-1 assume !(0 == ~E_7~0); 38706#L1391-1 assume !(0 == ~E_8~0); 38719#L1396-1 assume !(0 == ~E_9~0); 37916#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 37917#L1406-1 assume !(0 == ~E_11~0); 38210#L1411-1 assume !(0 == ~E_12~0); 38211#L1416-1 assume !(0 == ~E_13~0); 37824#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37674#L635 assume !(1 == ~m_pc~0); 36787#L635-2 is_master_triggered_~__retres1~0#1 := 0; 36788#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37129#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37827#L1598 assume !(0 != activate_threads_~tmp~1#1); 36961#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36962#L654 assume 1 == ~t1_pc~0; 37697#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37698#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38323#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37779#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 37780#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37010#L673 assume 1 == ~t2_pc~0; 37011#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38181#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37215#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37216#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 38737#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37855#L692 assume !(1 == ~t3_pc~0); 37676#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37677#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38308#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37499#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37500#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37038#L711 assume 1 == ~t4_pc~0; 37039#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37547#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36837#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36742#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 36743#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38726#L730 assume !(1 == ~t5_pc~0); 38120#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36920#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36921#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37048#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 37049#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37403#L749 assume 1 == ~t6_pc~0; 37160#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36923#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37200#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37201#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 37613#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36722#L768 assume !(1 == ~t7_pc~0); 36723#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 38066#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38581#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38566#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 38086#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37202#L787 assume 1 == ~t8_pc~0; 37203#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38400#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38659#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38660#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 36765#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36766#L806 assume 1 == ~t9_pc~0; 38409#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36800#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36801#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37050#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 37051#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38393#L825 assume !(1 == ~t10_pc~0); 38394#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38033#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38034#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37130#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37131#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37750#L844 assume 1 == ~t11_pc~0; 37425#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37426#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38494#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38437#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 38380#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38381#L863 assume !(1 == ~t12_pc~0); 36903#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36902#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36783#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 36784#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 38472#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37869#L882 assume 1 == ~t13_pc~0; 37870#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38157#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38593#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38442#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 38145#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38146#L1434 assume !(1 == ~M_E~0); 38655#L1434-2 assume !(1 == ~T1_E~0); 38730#L1439-1 assume !(1 == ~T2_E~0); 37030#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37031#L1449-1 assume !(1 == ~T4_E~0); 37494#L1454-1 assume !(1 == ~T5_E~0); 37495#L1459-1 assume !(1 == ~T6_E~0); 38087#L1464-1 assume !(1 == ~T7_E~0); 38088#L1469-1 assume !(1 == ~T8_E~0); 38158#L1474-1 assume !(1 == ~T9_E~0); 37825#L1479-1 assume !(1 == ~T10_E~0); 37826#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38092#L1489-1 assume !(1 == ~T12_E~0); 37709#L1494-1 assume !(1 == ~T13_E~0); 37710#L1499-1 assume !(1 == ~E_M~0); 37895#L1504-1 assume !(1 == ~E_1~0); 37896#L1509-1 assume !(1 == ~E_2~0); 38483#L1514-1 assume !(1 == ~E_3~0); 38192#L1519-1 assume !(1 == ~E_4~0); 38193#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38690#L1529-1 assume !(1 == ~E_6~0); 38691#L1534-1 assume !(1 == ~E_7~0); 36820#L1539-1 assume !(1 == ~E_8~0); 36821#L1544-1 assume !(1 == ~E_9~0); 37263#L1549-1 assume !(1 == ~E_10~0); 38666#L1554-1 assume !(1 == ~E_11~0); 38664#L1559-1 assume !(1 == ~E_12~0); 38525#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38526#L1569-1 assume { :end_inline_reset_delta_events } true; 38687#L1935-2 [2023-11-21 22:09:43,901 INFO L750 eck$LassoCheckResult]: Loop: 38687#L1935-2 assume !false; 36829#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36727#L1261-1 assume !false; 36728#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38094#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36957#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38383#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37510#L1074 assume !(0 != eval_~tmp~0#1); 37512#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37418#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37419#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38559#L1286-5 assume !(0 == ~T1_E~0); 38273#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38274#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38717#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38675#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37791#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37062#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37063#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37168#L1326-3 assume !(0 == ~T9_E~0); 37939#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38195#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38196#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37487#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37474#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37414#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37415#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38021#L1366-3 assume !(0 == ~E_3~0); 36755#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36756#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38506#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38358#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38359#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38545#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38546#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37128#L1406-3 assume !(0 == ~E_11~0); 36963#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36964#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37628#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36841#L635-45 assume 1 == ~m_pc~0; 36842#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37667#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38147#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38242#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37147#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37148#L654-45 assume !(1 == ~t1_pc~0); 38007#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 38330#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38331#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36832#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36833#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37686#L673-45 assume 1 == ~t2_pc~0; 37687#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38027#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38028#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38239#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38440#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37295#L692-45 assume 1 == ~t3_pc~0; 37296#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37003#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38461#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37344#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37345#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37671#L711-45 assume 1 == ~t4_pc~0; 37796#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37797#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38509#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38510#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 38067#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37175#L730-45 assume 1 == ~t5_pc~0; 37013#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37014#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38744#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38200#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38201#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36987#L749-45 assume !(1 == ~t6_pc~0); 36988#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 38396#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37912#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37913#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38312#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37320#L768-45 assume 1 == ~t7_pc~0; 37321#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37461#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38009#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38010#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38297#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38298#L787-45 assume !(1 == ~t8_pc~0); 38464#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 37467#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37468#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37893#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37894#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38199#L806-45 assume !(1 == ~t9_pc~0); 36868#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 36869#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37711#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37543#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37442#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37443#L825-45 assume 1 == ~t10_pc~0; 38082#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37983#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38445#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38231#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38232#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37068#L844-45 assume 1 == ~t11_pc~0; 37069#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37629#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37105#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37106#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38064#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37110#L863-45 assume 1 == ~t12_pc~0; 37111#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36715#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36716#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37237#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37238#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38070#L882-45 assume 1 == ~t13_pc~0; 38389#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 36734#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 36735#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38334#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 38535#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38162#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38163#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38329#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37026#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37027#L1449-3 assume !(1 == ~T4_E~0); 37187#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38153#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38154#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38590#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38507#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38508#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38594#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37794#L1489-3 assume !(1 == ~T12_E~0); 37795#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38436#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38096#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38097#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38521#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38564#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37712#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37713#L1529-3 assume !(1 == ~E_6~0); 38616#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38032#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37462#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37463#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37990#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37073#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37074#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38247#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38248#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36959#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37149#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37150#L1954 assume !(0 == start_simulation_~tmp~3#1); 38221#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38457#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37258#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36759#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 36760#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38420#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38517#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38576#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 38687#L1935-2 [2023-11-21 22:09:43,901 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:43,902 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2023-11-21 22:09:43,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:43,902 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846162133] [2023-11-21 22:09:43,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:43,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:43,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:43,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:43,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:43,997 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [846162133] [2023-11-21 22:09:43,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [846162133] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:43,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:43,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:44,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [599850974] [2023-11-21 22:09:44,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:44,001 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:44,002 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:44,002 INFO L85 PathProgramCache]: Analyzing trace with hash 1583340284, now seen corresponding path program 1 times [2023-11-21 22:09:44,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:44,002 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147905819] [2023-11-21 22:09:44,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:44,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:44,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:44,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:44,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:44,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147905819] [2023-11-21 22:09:44,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147905819] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:44,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:44,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:44,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799189929] [2023-11-21 22:09:44,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:44,078 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:44,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:44,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:44,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:44,080 INFO L87 Difference]: Start difference. First operand 2035 states and 2998 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:44,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:44,131 INFO L93 Difference]: Finished difference Result 2035 states and 2997 transitions. [2023-11-21 22:09:44,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 2997 transitions. [2023-11-21 22:09:44,143 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:44,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 2997 transitions. [2023-11-21 22:09:44,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:44,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:44,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 2997 transitions. [2023-11-21 22:09:44,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:44,161 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2997 transitions. [2023-11-21 22:09:44,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 2997 transitions. [2023-11-21 22:09:44,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:44,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4727272727272727) internal successors, (2997), 2034 states have internal predecessors, (2997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:44,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 2997 transitions. [2023-11-21 22:09:44,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2997 transitions. [2023-11-21 22:09:44,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:44,207 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 2997 transitions. [2023-11-21 22:09:44,207 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-21 22:09:44,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 2997 transitions. [2023-11-21 22:09:44,216 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:44,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:44,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:44,220 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:44,220 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:44,221 INFO L748 eck$LassoCheckResult]: Stem: 41099#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41100#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42088#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42089#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42804#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 42805#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41607#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41608#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41654#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42461#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42462#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42575#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42576#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41414#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41415#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 42621#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41950#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41951#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42518#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42792#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 42686#L1286-2 assume !(0 == ~T1_E~0); 41319#L1291-1 assume !(0 == ~T2_E~0); 41320#L1296-1 assume !(0 == ~T3_E~0); 42045#L1301-1 assume !(0 == ~T4_E~0); 42046#L1306-1 assume !(0 == ~T5_E~0); 42526#L1311-1 assume !(0 == ~T6_E~0); 41275#L1316-1 assume !(0 == ~T7_E~0); 41276#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42066#L1326-1 assume !(0 == ~T9_E~0); 41084#L1331-1 assume !(0 == ~T10_E~0); 40794#L1336-1 assume !(0 == ~T11_E~0); 40795#L1341-1 assume !(0 == ~T12_E~0); 40844#L1346-1 assume !(0 == ~T13_E~0); 40845#L1351-1 assume !(0 == ~E_M~0); 41212#L1356-1 assume !(0 == ~E_1~0); 41213#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 42755#L1366-1 assume !(0 == ~E_3~0); 41262#L1371-1 assume !(0 == ~E_4~0); 41263#L1376-1 assume !(0 == ~E_5~0); 42122#L1381-1 assume !(0 == ~E_6~0); 42123#L1386-1 assume !(0 == ~E_7~0); 42783#L1391-1 assume !(0 == ~E_8~0); 42796#L1396-1 assume !(0 == ~E_9~0); 41993#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 41994#L1406-1 assume !(0 == ~E_11~0); 42287#L1411-1 assume !(0 == ~E_12~0); 42288#L1416-1 assume !(0 == ~E_13~0); 41901#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41751#L635 assume !(1 == ~m_pc~0); 40864#L635-2 is_master_triggered_~__retres1~0#1 := 0; 40865#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41206#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41904#L1598 assume !(0 != activate_threads_~tmp~1#1); 41038#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41039#L654 assume 1 == ~t1_pc~0; 41774#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41775#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42400#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41856#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 41857#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41087#L673 assume 1 == ~t2_pc~0; 41088#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42258#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41292#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41293#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 42814#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41932#L692 assume !(1 == ~t3_pc~0); 41753#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41754#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42385#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41576#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41577#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41115#L711 assume 1 == ~t4_pc~0; 41116#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41624#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40914#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40819#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 40820#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42803#L730 assume !(1 == ~t5_pc~0); 42197#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40997#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40998#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41125#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 41126#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41480#L749 assume 1 == ~t6_pc~0; 41237#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41000#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41277#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41278#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 41690#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40799#L768 assume !(1 == ~t7_pc~0); 40800#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 42143#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42658#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42643#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 42163#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41279#L787 assume 1 == ~t8_pc~0; 41280#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42477#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42736#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42737#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 40842#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40843#L806 assume 1 == ~t9_pc~0; 42486#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40877#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40878#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41127#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 41128#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42470#L825 assume !(1 == ~t10_pc~0); 42471#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42110#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42111#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41207#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41208#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41827#L844 assume 1 == ~t11_pc~0; 41502#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41503#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42571#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42514#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 42457#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42458#L863 assume !(1 == ~t12_pc~0); 40980#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40979#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40860#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 40861#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 42549#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41946#L882 assume 1 == ~t13_pc~0; 41947#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42234#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42670#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42519#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 42222#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42223#L1434 assume !(1 == ~M_E~0); 42732#L1434-2 assume !(1 == ~T1_E~0); 42807#L1439-1 assume !(1 == ~T2_E~0); 41107#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41108#L1449-1 assume !(1 == ~T4_E~0); 41571#L1454-1 assume !(1 == ~T5_E~0); 41572#L1459-1 assume !(1 == ~T6_E~0); 42164#L1464-1 assume !(1 == ~T7_E~0); 42165#L1469-1 assume !(1 == ~T8_E~0); 42235#L1474-1 assume !(1 == ~T9_E~0); 41902#L1479-1 assume !(1 == ~T10_E~0); 41903#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42169#L1489-1 assume !(1 == ~T12_E~0); 41786#L1494-1 assume !(1 == ~T13_E~0); 41787#L1499-1 assume !(1 == ~E_M~0); 41972#L1504-1 assume !(1 == ~E_1~0); 41973#L1509-1 assume !(1 == ~E_2~0); 42560#L1514-1 assume !(1 == ~E_3~0); 42269#L1519-1 assume !(1 == ~E_4~0); 42270#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42767#L1529-1 assume !(1 == ~E_6~0); 42768#L1534-1 assume !(1 == ~E_7~0); 40897#L1539-1 assume !(1 == ~E_8~0); 40898#L1544-1 assume !(1 == ~E_9~0); 41340#L1549-1 assume !(1 == ~E_10~0); 42743#L1554-1 assume !(1 == ~E_11~0); 42741#L1559-1 assume !(1 == ~E_12~0); 42602#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 42603#L1569-1 assume { :end_inline_reset_delta_events } true; 42764#L1935-2 [2023-11-21 22:09:44,221 INFO L750 eck$LassoCheckResult]: Loop: 42764#L1935-2 assume !false; 40906#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40804#L1261-1 assume !false; 40805#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42171#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41034#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42460#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41587#L1074 assume !(0 != eval_~tmp~0#1); 41589#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41495#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41496#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42636#L1286-5 assume !(0 == ~T1_E~0); 42350#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42351#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42794#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42752#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41868#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41139#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41140#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41245#L1326-3 assume !(0 == ~T9_E~0); 42016#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 42272#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 42273#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41564#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41551#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41491#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41492#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42098#L1366-3 assume !(0 == ~E_3~0); 40832#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40833#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42583#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42435#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42436#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42622#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42623#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41205#L1406-3 assume !(0 == ~E_11~0); 41040#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 41041#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41705#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40918#L635-45 assume 1 == ~m_pc~0; 40919#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41744#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42224#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42319#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41224#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41225#L654-45 assume !(1 == ~t1_pc~0); 42084#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 42407#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42408#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40909#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40910#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41763#L673-45 assume 1 == ~t2_pc~0; 41764#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42104#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42105#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42316#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42517#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41372#L692-45 assume !(1 == ~t3_pc~0); 41079#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 41080#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42538#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41421#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41422#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41748#L711-45 assume 1 == ~t4_pc~0; 41873#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41874#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42586#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42587#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 42144#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41252#L730-45 assume 1 == ~t5_pc~0; 41090#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41091#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42821#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42277#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42278#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41064#L749-45 assume !(1 == ~t6_pc~0); 41065#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 42473#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41989#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41990#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42389#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41397#L768-45 assume 1 == ~t7_pc~0; 41398#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41538#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42086#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42087#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42374#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42375#L787-45 assume 1 == ~t8_pc~0; 42540#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41544#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41545#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41970#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41971#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42276#L806-45 assume !(1 == ~t9_pc~0); 40945#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 40946#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41788#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41620#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41519#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41520#L825-45 assume !(1 == ~t10_pc~0); 42059#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 42060#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42522#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42308#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42309#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41145#L844-45 assume 1 == ~t11_pc~0; 41146#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41706#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41182#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41183#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42141#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41187#L863-45 assume 1 == ~t12_pc~0; 41188#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40792#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40793#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41314#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41315#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42147#L882-45 assume 1 == ~t13_pc~0; 42466#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 40811#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 40812#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42411#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 42612#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42239#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42240#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42406#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41103#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41104#L1449-3 assume !(1 == ~T4_E~0); 41264#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42230#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42231#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42667#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42584#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42585#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42671#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41871#L1489-3 assume !(1 == ~T12_E~0); 41872#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42513#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 42173#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42174#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42598#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42641#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41789#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41790#L1529-3 assume !(1 == ~E_6~0); 42693#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42109#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41539#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41540#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 42067#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41150#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41151#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42324#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42325#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41036#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41226#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41227#L1954 assume !(0 == start_simulation_~tmp~3#1); 42298#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42534#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41335#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40836#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 40837#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42497#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42594#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 42653#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 42764#L1935-2 [2023-11-21 22:09:44,222 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:44,222 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2023-11-21 22:09:44,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:44,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591475970] [2023-11-21 22:09:44,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:44,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:44,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:44,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:44,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:44,289 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591475970] [2023-11-21 22:09:44,289 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1591475970] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:44,289 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:44,289 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:44,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180089429] [2023-11-21 22:09:44,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:44,290 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:44,292 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:44,292 INFO L85 PathProgramCache]: Analyzing trace with hash 879391357, now seen corresponding path program 2 times [2023-11-21 22:09:44,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:44,293 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680071607] [2023-11-21 22:09:44,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:44,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:44,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:44,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:44,395 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:44,395 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680071607] [2023-11-21 22:09:44,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [680071607] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:44,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:44,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:44,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414113898] [2023-11-21 22:09:44,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:44,397 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:44,397 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:44,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:44,398 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:44,398 INFO L87 Difference]: Start difference. First operand 2035 states and 2997 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:44,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:44,449 INFO L93 Difference]: Finished difference Result 2035 states and 2996 transitions. [2023-11-21 22:09:44,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 2996 transitions. [2023-11-21 22:09:44,462 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:44,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 2996 transitions. [2023-11-21 22:09:44,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:44,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:44,477 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 2996 transitions. [2023-11-21 22:09:44,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:44,480 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2996 transitions. [2023-11-21 22:09:44,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 2996 transitions. [2023-11-21 22:09:44,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:44,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4722358722358722) internal successors, (2996), 2034 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:44,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 2996 transitions. [2023-11-21 22:09:44,528 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2996 transitions. [2023-11-21 22:09:44,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:44,529 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 2996 transitions. [2023-11-21 22:09:44,529 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-21 22:09:44,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 2996 transitions. [2023-11-21 22:09:44,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:44,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:44,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:44,543 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:44,544 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:44,544 INFO L748 eck$LassoCheckResult]: Stem: 45176#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46165#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46166#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46881#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 46882#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45684#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45685#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45731#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46538#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46539#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46652#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46653#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45491#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45492#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46698#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 46027#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 46028#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46595#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46869#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 46763#L1286-2 assume !(0 == ~T1_E~0); 45396#L1291-1 assume !(0 == ~T2_E~0); 45397#L1296-1 assume !(0 == ~T3_E~0); 46122#L1301-1 assume !(0 == ~T4_E~0); 46123#L1306-1 assume !(0 == ~T5_E~0); 46603#L1311-1 assume !(0 == ~T6_E~0); 45352#L1316-1 assume !(0 == ~T7_E~0); 45353#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 46143#L1326-1 assume !(0 == ~T9_E~0); 45161#L1331-1 assume !(0 == ~T10_E~0); 44871#L1336-1 assume !(0 == ~T11_E~0); 44872#L1341-1 assume !(0 == ~T12_E~0); 44921#L1346-1 assume !(0 == ~T13_E~0); 44922#L1351-1 assume !(0 == ~E_M~0); 45289#L1356-1 assume !(0 == ~E_1~0); 45290#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 46832#L1366-1 assume !(0 == ~E_3~0); 45339#L1371-1 assume !(0 == ~E_4~0); 45340#L1376-1 assume !(0 == ~E_5~0); 46199#L1381-1 assume !(0 == ~E_6~0); 46200#L1386-1 assume !(0 == ~E_7~0); 46860#L1391-1 assume !(0 == ~E_8~0); 46873#L1396-1 assume !(0 == ~E_9~0); 46070#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46071#L1406-1 assume !(0 == ~E_11~0); 46364#L1411-1 assume !(0 == ~E_12~0); 46365#L1416-1 assume !(0 == ~E_13~0); 45978#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45828#L635 assume !(1 == ~m_pc~0); 44941#L635-2 is_master_triggered_~__retres1~0#1 := 0; 44942#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45283#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45981#L1598 assume !(0 != activate_threads_~tmp~1#1); 45115#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45116#L654 assume 1 == ~t1_pc~0; 45851#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45852#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46477#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45933#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 45934#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45164#L673 assume 1 == ~t2_pc~0; 45165#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46335#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45369#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45370#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 46891#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46009#L692 assume !(1 == ~t3_pc~0); 45830#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45831#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46462#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45653#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45654#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45192#L711 assume 1 == ~t4_pc~0; 45193#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45701#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44991#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44896#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 44897#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46880#L730 assume !(1 == ~t5_pc~0); 46274#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 45074#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45075#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45202#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 45203#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45557#L749 assume 1 == ~t6_pc~0; 45314#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45077#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45354#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45355#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 45767#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44876#L768 assume !(1 == ~t7_pc~0); 44877#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 46220#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46735#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46720#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 46240#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45356#L787 assume 1 == ~t8_pc~0; 45357#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46554#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46813#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46814#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 44919#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44920#L806 assume 1 == ~t9_pc~0; 46563#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44954#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44955#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45204#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 45205#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46547#L825 assume !(1 == ~t10_pc~0); 46548#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46187#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46188#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45284#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45285#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45904#L844 assume 1 == ~t11_pc~0; 45579#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45580#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46648#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46591#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 46534#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46535#L863 assume !(1 == ~t12_pc~0); 45057#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45056#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44937#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 44938#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 46626#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46023#L882 assume 1 == ~t13_pc~0; 46024#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46311#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46747#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46596#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 46299#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46300#L1434 assume !(1 == ~M_E~0); 46809#L1434-2 assume !(1 == ~T1_E~0); 46884#L1439-1 assume !(1 == ~T2_E~0); 45184#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45185#L1449-1 assume !(1 == ~T4_E~0); 45648#L1454-1 assume !(1 == ~T5_E~0); 45649#L1459-1 assume !(1 == ~T6_E~0); 46241#L1464-1 assume !(1 == ~T7_E~0); 46242#L1469-1 assume !(1 == ~T8_E~0); 46312#L1474-1 assume !(1 == ~T9_E~0); 45979#L1479-1 assume !(1 == ~T10_E~0); 45980#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46246#L1489-1 assume !(1 == ~T12_E~0); 45863#L1494-1 assume !(1 == ~T13_E~0); 45864#L1499-1 assume !(1 == ~E_M~0); 46049#L1504-1 assume !(1 == ~E_1~0); 46050#L1509-1 assume !(1 == ~E_2~0); 46637#L1514-1 assume !(1 == ~E_3~0); 46346#L1519-1 assume !(1 == ~E_4~0); 46347#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46844#L1529-1 assume !(1 == ~E_6~0); 46845#L1534-1 assume !(1 == ~E_7~0); 44974#L1539-1 assume !(1 == ~E_8~0); 44975#L1544-1 assume !(1 == ~E_9~0); 45417#L1549-1 assume !(1 == ~E_10~0); 46820#L1554-1 assume !(1 == ~E_11~0); 46818#L1559-1 assume !(1 == ~E_12~0); 46679#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46680#L1569-1 assume { :end_inline_reset_delta_events } true; 46841#L1935-2 [2023-11-21 22:09:44,545 INFO L750 eck$LassoCheckResult]: Loop: 46841#L1935-2 assume !false; 44983#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44881#L1261-1 assume !false; 44882#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46248#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45111#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46537#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 45664#L1074 assume !(0 != eval_~tmp~0#1); 45666#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45572#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45573#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46713#L1286-5 assume !(0 == ~T1_E~0); 46427#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46428#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46871#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46829#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45945#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45216#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45217#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45322#L1326-3 assume !(0 == ~T9_E~0); 46093#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46349#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46350#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45641#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45628#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45568#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45569#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46175#L1366-3 assume !(0 == ~E_3~0); 44909#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44910#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46660#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46512#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46513#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46699#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46700#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45282#L1406-3 assume !(0 == ~E_11~0); 45117#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 45118#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45782#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44995#L635-45 assume 1 == ~m_pc~0; 44996#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45821#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46301#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46396#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45301#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45302#L654-45 assume !(1 == ~t1_pc~0); 46161#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 46484#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46485#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44986#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44987#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45840#L673-45 assume 1 == ~t2_pc~0; 45841#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46181#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46182#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46393#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46594#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45449#L692-45 assume !(1 == ~t3_pc~0); 45156#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 45157#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46615#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45498#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45499#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45825#L711-45 assume !(1 == ~t4_pc~0); 45952#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 45951#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46663#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46664#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 46221#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45329#L730-45 assume !(1 == ~t5_pc~0); 45169#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 45168#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46898#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46354#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46355#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45141#L749-45 assume !(1 == ~t6_pc~0); 45142#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 46550#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46066#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46067#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46466#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45474#L768-45 assume 1 == ~t7_pc~0; 45475#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45615#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46163#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46164#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46451#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46452#L787-45 assume 1 == ~t8_pc~0; 46617#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45621#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45622#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46047#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46048#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46353#L806-45 assume 1 == ~t9_pc~0; 46822#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45023#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45865#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45697#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45596#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45597#L825-45 assume !(1 == ~t10_pc~0); 46136#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 46137#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46599#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46385#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46386#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45222#L844-45 assume 1 == ~t11_pc~0; 45223#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45783#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45259#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45260#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46218#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45264#L863-45 assume 1 == ~t12_pc~0; 45265#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44869#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44870#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45391#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45392#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46224#L882-45 assume !(1 == ~t13_pc~0); 45748#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 44888#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 44889#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46488#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 46689#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46316#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46317#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46483#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45180#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45181#L1449-3 assume !(1 == ~T4_E~0); 45341#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46307#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46308#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46744#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46661#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46662#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46748#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45948#L1489-3 assume !(1 == ~T12_E~0); 45949#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46590#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46250#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46251#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46675#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46718#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45866#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45867#L1529-3 assume !(1 == ~E_6~0); 46770#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46186#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45616#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45617#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 46144#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45227#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 45228#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46401#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46402#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45113#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45303#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 45304#L1954 assume !(0 == start_simulation_~tmp~3#1); 46375#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46611#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45412#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44913#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 44914#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46574#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46671#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46730#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 46841#L1935-2 [2023-11-21 22:09:44,546 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:44,546 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2023-11-21 22:09:44,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:44,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62836198] [2023-11-21 22:09:44,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:44,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:44,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:44,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:44,617 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:44,617 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62836198] [2023-11-21 22:09:44,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [62836198] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:44,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:44,618 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:44,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1126156414] [2023-11-21 22:09:44,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:44,619 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:44,620 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:44,620 INFO L85 PathProgramCache]: Analyzing trace with hash -215797825, now seen corresponding path program 1 times [2023-11-21 22:09:44,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:44,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616580261] [2023-11-21 22:09:44,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:44,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:44,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:44,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:44,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:44,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [616580261] [2023-11-21 22:09:44,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [616580261] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:44,731 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:44,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:44,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892212061] [2023-11-21 22:09:44,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:44,732 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:44,732 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:44,733 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:44,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:44,733 INFO L87 Difference]: Start difference. First operand 2035 states and 2996 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:44,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:44,783 INFO L93 Difference]: Finished difference Result 2035 states and 2995 transitions. [2023-11-21 22:09:44,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 2995 transitions. [2023-11-21 22:09:44,795 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:44,805 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 2995 transitions. [2023-11-21 22:09:44,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:44,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:44,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 2995 transitions. [2023-11-21 22:09:44,811 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:44,811 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2995 transitions. [2023-11-21 22:09:44,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 2995 transitions. [2023-11-21 22:09:44,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:44,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4717444717444716) internal successors, (2995), 2034 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:44,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 2995 transitions. [2023-11-21 22:09:44,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2995 transitions. [2023-11-21 22:09:44,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:44,855 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 2995 transitions. [2023-11-21 22:09:44,855 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-21 22:09:44,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 2995 transitions. [2023-11-21 22:09:44,865 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:44,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:44,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:44,868 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:44,868 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:44,869 INFO L748 eck$LassoCheckResult]: Stem: 49253#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50242#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50243#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50958#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 50959#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49761#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49762#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49808#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50615#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50616#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50729#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50730#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49568#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49569#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50775#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50104#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50105#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50672#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50946#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 50840#L1286-2 assume !(0 == ~T1_E~0); 49473#L1291-1 assume !(0 == ~T2_E~0); 49474#L1296-1 assume !(0 == ~T3_E~0); 50199#L1301-1 assume !(0 == ~T4_E~0); 50200#L1306-1 assume !(0 == ~T5_E~0); 50680#L1311-1 assume !(0 == ~T6_E~0); 49429#L1316-1 assume !(0 == ~T7_E~0); 49430#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50220#L1326-1 assume !(0 == ~T9_E~0); 49238#L1331-1 assume !(0 == ~T10_E~0); 48948#L1336-1 assume !(0 == ~T11_E~0); 48949#L1341-1 assume !(0 == ~T12_E~0); 48998#L1346-1 assume !(0 == ~T13_E~0); 48999#L1351-1 assume !(0 == ~E_M~0); 49366#L1356-1 assume !(0 == ~E_1~0); 49367#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 50909#L1366-1 assume !(0 == ~E_3~0); 49416#L1371-1 assume !(0 == ~E_4~0); 49417#L1376-1 assume !(0 == ~E_5~0); 50276#L1381-1 assume !(0 == ~E_6~0); 50277#L1386-1 assume !(0 == ~E_7~0); 50937#L1391-1 assume !(0 == ~E_8~0); 50950#L1396-1 assume !(0 == ~E_9~0); 50147#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50148#L1406-1 assume !(0 == ~E_11~0); 50441#L1411-1 assume !(0 == ~E_12~0); 50442#L1416-1 assume !(0 == ~E_13~0); 50055#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49905#L635 assume !(1 == ~m_pc~0); 49018#L635-2 is_master_triggered_~__retres1~0#1 := 0; 49019#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49360#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50058#L1598 assume !(0 != activate_threads_~tmp~1#1); 49192#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49193#L654 assume 1 == ~t1_pc~0; 49928#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49929#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50554#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50010#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 50011#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49241#L673 assume 1 == ~t2_pc~0; 49242#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50412#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49446#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49447#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 50968#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50086#L692 assume !(1 == ~t3_pc~0); 49907#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49908#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50539#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49730#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49731#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49269#L711 assume 1 == ~t4_pc~0; 49270#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49778#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49068#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48973#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 48974#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50957#L730 assume !(1 == ~t5_pc~0); 50351#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 49151#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49152#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49279#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 49280#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49634#L749 assume 1 == ~t6_pc~0; 49391#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49154#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49431#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49432#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 49844#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48953#L768 assume !(1 == ~t7_pc~0); 48954#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 50297#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50812#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50797#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 50317#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49433#L787 assume 1 == ~t8_pc~0; 49434#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50631#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50890#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50891#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 48996#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48997#L806 assume 1 == ~t9_pc~0; 50640#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49031#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49032#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49281#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 49282#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50624#L825 assume !(1 == ~t10_pc~0); 50625#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50264#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50265#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49361#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49362#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49981#L844 assume 1 == ~t11_pc~0; 49656#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49657#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50725#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50668#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 50611#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50612#L863 assume !(1 == ~t12_pc~0); 49134#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 49133#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49014#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49015#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 50703#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50100#L882 assume 1 == ~t13_pc~0; 50101#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50388#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50824#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50673#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 50376#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50377#L1434 assume !(1 == ~M_E~0); 50886#L1434-2 assume !(1 == ~T1_E~0); 50961#L1439-1 assume !(1 == ~T2_E~0); 49261#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49262#L1449-1 assume !(1 == ~T4_E~0); 49725#L1454-1 assume !(1 == ~T5_E~0); 49726#L1459-1 assume !(1 == ~T6_E~0); 50318#L1464-1 assume !(1 == ~T7_E~0); 50319#L1469-1 assume !(1 == ~T8_E~0); 50389#L1474-1 assume !(1 == ~T9_E~0); 50056#L1479-1 assume !(1 == ~T10_E~0); 50057#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50323#L1489-1 assume !(1 == ~T12_E~0); 49940#L1494-1 assume !(1 == ~T13_E~0); 49941#L1499-1 assume !(1 == ~E_M~0); 50126#L1504-1 assume !(1 == ~E_1~0); 50127#L1509-1 assume !(1 == ~E_2~0); 50714#L1514-1 assume !(1 == ~E_3~0); 50423#L1519-1 assume !(1 == ~E_4~0); 50424#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50921#L1529-1 assume !(1 == ~E_6~0); 50922#L1534-1 assume !(1 == ~E_7~0); 49051#L1539-1 assume !(1 == ~E_8~0); 49052#L1544-1 assume !(1 == ~E_9~0); 49494#L1549-1 assume !(1 == ~E_10~0); 50897#L1554-1 assume !(1 == ~E_11~0); 50895#L1559-1 assume !(1 == ~E_12~0); 50756#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 50757#L1569-1 assume { :end_inline_reset_delta_events } true; 50918#L1935-2 [2023-11-21 22:09:44,870 INFO L750 eck$LassoCheckResult]: Loop: 50918#L1935-2 assume !false; 49060#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48958#L1261-1 assume !false; 48959#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50325#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49188#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50614#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49741#L1074 assume !(0 != eval_~tmp~0#1); 49743#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49649#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49650#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50790#L1286-5 assume !(0 == ~T1_E~0); 50504#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50505#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50948#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50906#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50022#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49293#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49294#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49399#L1326-3 assume !(0 == ~T9_E~0); 50170#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50426#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50427#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49718#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49705#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49645#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49646#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50252#L1366-3 assume !(0 == ~E_3~0); 48986#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48987#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50737#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50589#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50590#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50776#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50777#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49359#L1406-3 assume !(0 == ~E_11~0); 49194#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 49195#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49859#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49072#L635-45 assume 1 == ~m_pc~0; 49073#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49898#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50378#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50473#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49378#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49379#L654-45 assume !(1 == ~t1_pc~0); 50238#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 50561#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50562#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49063#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49064#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49917#L673-45 assume 1 == ~t2_pc~0; 49918#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50258#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50259#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50470#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50671#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49526#L692-45 assume !(1 == ~t3_pc~0); 49233#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 49234#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50692#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49575#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49576#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49902#L711-45 assume 1 == ~t4_pc~0; 50027#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50028#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50740#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50741#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 50298#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49406#L730-45 assume 1 == ~t5_pc~0; 49244#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49245#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50975#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50431#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50432#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49218#L749-45 assume !(1 == ~t6_pc~0); 49219#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 50627#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50143#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50144#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50543#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49551#L768-45 assume 1 == ~t7_pc~0; 49552#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49692#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50240#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50241#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50528#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50529#L787-45 assume 1 == ~t8_pc~0; 50694#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49698#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49699#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50124#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50125#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50430#L806-45 assume 1 == ~t9_pc~0; 50899#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49100#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49942#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49774#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49673#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49674#L825-45 assume !(1 == ~t10_pc~0); 50213#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 50214#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50676#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50462#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50463#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49299#L844-45 assume 1 == ~t11_pc~0; 49300#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49860#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49336#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49337#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50295#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49341#L863-45 assume 1 == ~t12_pc~0; 49342#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48946#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48947#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49468#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49469#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50301#L882-45 assume !(1 == ~t13_pc~0); 49825#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 48965#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 48966#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50565#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 50766#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50393#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50394#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50560#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49257#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49258#L1449-3 assume !(1 == ~T4_E~0); 49418#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50384#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50385#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50821#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50738#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50739#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50825#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50025#L1489-3 assume !(1 == ~T12_E~0); 50026#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50667#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50327#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50328#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50752#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50795#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49943#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49944#L1529-3 assume !(1 == ~E_6~0); 50847#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50263#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49693#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49694#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50221#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49304#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 49305#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50478#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50479#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49190#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49380#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 49381#L1954 assume !(0 == start_simulation_~tmp~3#1); 50452#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50688#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49489#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48990#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 48991#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50651#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50748#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 50807#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 50918#L1935-2 [2023-11-21 22:09:44,870 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:44,871 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2023-11-21 22:09:44,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:44,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510068615] [2023-11-21 22:09:44,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:44,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:44,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:44,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:44,928 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:44,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510068615] [2023-11-21 22:09:44,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510068615] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:44,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:44,929 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:44,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342523917] [2023-11-21 22:09:44,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:44,929 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:44,930 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:44,930 INFO L85 PathProgramCache]: Analyzing trace with hash 941270397, now seen corresponding path program 1 times [2023-11-21 22:09:44,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:44,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983691573] [2023-11-21 22:09:44,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:44,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:44,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:45,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:45,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:45,005 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983691573] [2023-11-21 22:09:45,005 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983691573] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:45,005 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:45,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:45,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223433083] [2023-11-21 22:09:45,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:45,006 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:45,006 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:45,007 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:45,007 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:45,007 INFO L87 Difference]: Start difference. First operand 2035 states and 2995 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:45,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:45,054 INFO L93 Difference]: Finished difference Result 2035 states and 2994 transitions. [2023-11-21 22:09:45,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2035 states and 2994 transitions. [2023-11-21 22:09:45,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:45,076 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2035 states to 2035 states and 2994 transitions. [2023-11-21 22:09:45,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2035 [2023-11-21 22:09:45,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2035 [2023-11-21 22:09:45,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2035 states and 2994 transitions. [2023-11-21 22:09:45,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:45,083 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2994 transitions. [2023-11-21 22:09:45,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states and 2994 transitions. [2023-11-21 22:09:45,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2035. [2023-11-21 22:09:45,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2035 states, 2035 states have (on average 1.4712530712530711) internal successors, (2994), 2034 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:45,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 2035 states and 2994 transitions. [2023-11-21 22:09:45,127 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2035 states and 2994 transitions. [2023-11-21 22:09:45,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:45,128 INFO L428 stractBuchiCegarLoop]: Abstraction has 2035 states and 2994 transitions. [2023-11-21 22:09:45,128 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-21 22:09:45,128 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2035 states and 2994 transitions. [2023-11-21 22:09:45,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-21 22:09:45,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:45,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:45,141 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:45,141 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:45,141 INFO L748 eck$LassoCheckResult]: Stem: 53330#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53331#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54319#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54320#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55035#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 55036#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53838#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53839#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53885#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54692#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54693#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54806#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54807#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53645#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53646#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54852#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54181#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54182#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54749#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55023#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 54917#L1286-2 assume !(0 == ~T1_E~0); 53550#L1291-1 assume !(0 == ~T2_E~0); 53551#L1296-1 assume !(0 == ~T3_E~0); 54276#L1301-1 assume !(0 == ~T4_E~0); 54277#L1306-1 assume !(0 == ~T5_E~0); 54757#L1311-1 assume !(0 == ~T6_E~0); 53506#L1316-1 assume !(0 == ~T7_E~0); 53507#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 54297#L1326-1 assume !(0 == ~T9_E~0); 53315#L1331-1 assume !(0 == ~T10_E~0); 53025#L1336-1 assume !(0 == ~T11_E~0); 53026#L1341-1 assume !(0 == ~T12_E~0); 53075#L1346-1 assume !(0 == ~T13_E~0); 53076#L1351-1 assume !(0 == ~E_M~0); 53443#L1356-1 assume !(0 == ~E_1~0); 53444#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 54986#L1366-1 assume !(0 == ~E_3~0); 53493#L1371-1 assume !(0 == ~E_4~0); 53494#L1376-1 assume !(0 == ~E_5~0); 54353#L1381-1 assume !(0 == ~E_6~0); 54354#L1386-1 assume !(0 == ~E_7~0); 55014#L1391-1 assume !(0 == ~E_8~0); 55027#L1396-1 assume !(0 == ~E_9~0); 54224#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54225#L1406-1 assume !(0 == ~E_11~0); 54518#L1411-1 assume !(0 == ~E_12~0); 54519#L1416-1 assume !(0 == ~E_13~0); 54132#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53982#L635 assume !(1 == ~m_pc~0); 53095#L635-2 is_master_triggered_~__retres1~0#1 := 0; 53096#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53437#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54135#L1598 assume !(0 != activate_threads_~tmp~1#1); 53269#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53270#L654 assume 1 == ~t1_pc~0; 54005#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54006#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54087#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 54088#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53318#L673 assume 1 == ~t2_pc~0; 53319#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54489#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53523#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53524#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 55045#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54163#L692 assume !(1 == ~t3_pc~0); 53984#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53985#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54616#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53807#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53808#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53346#L711 assume 1 == ~t4_pc~0; 53347#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53855#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53145#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53050#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 53051#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55034#L730 assume !(1 == ~t5_pc~0); 54428#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 53228#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53229#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53356#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 53357#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53711#L749 assume 1 == ~t6_pc~0; 53468#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53231#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53508#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53509#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 53921#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53030#L768 assume !(1 == ~t7_pc~0); 53031#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 54374#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54889#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54874#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 54394#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53510#L787 assume 1 == ~t8_pc~0; 53511#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54708#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54967#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54968#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 53073#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53074#L806 assume 1 == ~t9_pc~0; 54717#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53108#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53109#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53358#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 53359#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54701#L825 assume !(1 == ~t10_pc~0); 54702#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 54341#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54342#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53438#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53439#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54058#L844 assume 1 == ~t11_pc~0; 53733#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53734#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54802#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54745#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 54688#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54689#L863 assume !(1 == ~t12_pc~0); 53211#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53210#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53091#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53092#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 54780#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54177#L882 assume 1 == ~t13_pc~0; 54178#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54465#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54901#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54750#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 54453#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54454#L1434 assume !(1 == ~M_E~0); 54963#L1434-2 assume !(1 == ~T1_E~0); 55038#L1439-1 assume !(1 == ~T2_E~0); 53338#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53339#L1449-1 assume !(1 == ~T4_E~0); 53802#L1454-1 assume !(1 == ~T5_E~0); 53803#L1459-1 assume !(1 == ~T6_E~0); 54395#L1464-1 assume !(1 == ~T7_E~0); 54396#L1469-1 assume !(1 == ~T8_E~0); 54466#L1474-1 assume !(1 == ~T9_E~0); 54133#L1479-1 assume !(1 == ~T10_E~0); 54134#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54400#L1489-1 assume !(1 == ~T12_E~0); 54017#L1494-1 assume !(1 == ~T13_E~0); 54018#L1499-1 assume !(1 == ~E_M~0); 54203#L1504-1 assume !(1 == ~E_1~0); 54204#L1509-1 assume !(1 == ~E_2~0); 54791#L1514-1 assume !(1 == ~E_3~0); 54500#L1519-1 assume !(1 == ~E_4~0); 54501#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54998#L1529-1 assume !(1 == ~E_6~0); 54999#L1534-1 assume !(1 == ~E_7~0); 53128#L1539-1 assume !(1 == ~E_8~0); 53129#L1544-1 assume !(1 == ~E_9~0); 53571#L1549-1 assume !(1 == ~E_10~0); 54974#L1554-1 assume !(1 == ~E_11~0); 54972#L1559-1 assume !(1 == ~E_12~0); 54833#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 54834#L1569-1 assume { :end_inline_reset_delta_events } true; 54995#L1935-2 [2023-11-21 22:09:45,142 INFO L750 eck$LassoCheckResult]: Loop: 54995#L1935-2 assume !false; 53137#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53035#L1261-1 assume !false; 53036#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54402#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53265#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54691#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53818#L1074 assume !(0 != eval_~tmp~0#1); 53820#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53726#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53727#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54867#L1286-5 assume !(0 == ~T1_E~0); 54581#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54582#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55025#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54983#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54099#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53370#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53371#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53476#L1326-3 assume !(0 == ~T9_E~0); 54247#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54503#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54504#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53795#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53782#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53722#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53723#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54329#L1366-3 assume !(0 == ~E_3~0); 53063#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53064#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54814#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54666#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54667#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54853#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54854#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53436#L1406-3 assume !(0 == ~E_11~0); 53271#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 53272#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53936#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53149#L635-45 assume 1 == ~m_pc~0; 53150#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53975#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54455#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54550#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53455#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53456#L654-45 assume !(1 == ~t1_pc~0); 54315#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 54638#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54639#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53140#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53141#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53994#L673-45 assume 1 == ~t2_pc~0; 53995#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54335#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54336#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54547#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54748#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53603#L692-45 assume 1 == ~t3_pc~0; 53604#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53311#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54769#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53652#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53653#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53979#L711-45 assume 1 == ~t4_pc~0; 54104#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54105#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54817#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54818#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 54375#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53483#L730-45 assume 1 == ~t5_pc~0; 53321#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53322#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55052#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54508#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54509#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53295#L749-45 assume !(1 == ~t6_pc~0); 53296#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 54704#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54220#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54221#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54620#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53628#L768-45 assume 1 == ~t7_pc~0; 53629#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53769#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54317#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54318#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54605#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54606#L787-45 assume 1 == ~t8_pc~0; 54771#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53775#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53776#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54201#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54202#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54507#L806-45 assume 1 == ~t9_pc~0; 54976#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53177#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54019#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53851#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53750#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53751#L825-45 assume !(1 == ~t10_pc~0); 54290#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 54291#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54753#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54539#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54540#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53376#L844-45 assume 1 == ~t11_pc~0; 53377#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53937#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53413#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53414#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54372#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53418#L863-45 assume 1 == ~t12_pc~0; 53419#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 53023#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53024#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53545#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53546#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54378#L882-45 assume 1 == ~t13_pc~0; 54697#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53042#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53043#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54642#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 54843#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54470#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54471#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54637#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53334#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53335#L1449-3 assume !(1 == ~T4_E~0); 53495#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54461#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54462#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54898#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54815#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54816#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54902#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54102#L1489-3 assume !(1 == ~T12_E~0); 54103#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54744#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54404#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54405#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54829#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54872#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54020#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54021#L1529-3 assume !(1 == ~E_6~0); 54924#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54340#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53770#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53771#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54298#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53381#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53382#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54555#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54556#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53267#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53457#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 53458#L1954 assume !(0 == start_simulation_~tmp~3#1); 54529#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54765#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53566#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53067#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 53068#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54728#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54825#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54884#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 54995#L1935-2 [2023-11-21 22:09:45,143 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:45,143 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2023-11-21 22:09:45,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:45,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385060533] [2023-11-21 22:09:45,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:45,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:45,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:45,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:45,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:45,221 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1385060533] [2023-11-21 22:09:45,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1385060533] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:45,221 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:45,221 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:09:45,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638022859] [2023-11-21 22:09:45,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:45,222 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:45,223 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:45,223 INFO L85 PathProgramCache]: Analyzing trace with hash 1463650811, now seen corresponding path program 1 times [2023-11-21 22:09:45,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:45,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731389340] [2023-11-21 22:09:45,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:45,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:45,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:45,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:45,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:45,298 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731389340] [2023-11-21 22:09:45,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1731389340] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:45,299 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:45,299 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:45,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2041009378] [2023-11-21 22:09:45,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:45,300 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:45,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:45,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:45,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:45,301 INFO L87 Difference]: Start difference. First operand 2035 states and 2994 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:45,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:45,451 INFO L93 Difference]: Finished difference Result 3795 states and 5566 transitions. [2023-11-21 22:09:45,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3795 states and 5566 transitions. [2023-11-21 22:09:45,476 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3620 [2023-11-21 22:09:45,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3795 states to 3795 states and 5566 transitions. [2023-11-21 22:09:45,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3795 [2023-11-21 22:09:45,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3795 [2023-11-21 22:09:45,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3795 states and 5566 transitions. [2023-11-21 22:09:45,504 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:45,504 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3795 states and 5566 transitions. [2023-11-21 22:09:45,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3795 states and 5566 transitions. [2023-11-21 22:09:45,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3795 to 3795. [2023-11-21 22:09:45,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3795 states, 3795 states have (on average 1.4666666666666666) internal successors, (5566), 3794 states have internal predecessors, (5566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:45,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3795 states to 3795 states and 5566 transitions. [2023-11-21 22:09:45,606 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3795 states and 5566 transitions. [2023-11-21 22:09:45,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:45,607 INFO L428 stractBuchiCegarLoop]: Abstraction has 3795 states and 5566 transitions. [2023-11-21 22:09:45,607 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-21 22:09:45,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3795 states and 5566 transitions. [2023-11-21 22:09:45,628 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3620 [2023-11-21 22:09:45,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:45,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:45,633 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:45,633 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:45,634 INFO L748 eck$LassoCheckResult]: Stem: 59169#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59170#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60164#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60165#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60930#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 60931#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59679#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59680#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59724#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60543#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60544#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60661#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60662#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59482#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59483#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 60708#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 60022#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60023#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 60601#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60913#L1286 assume !(0 == ~M_E~0); 60774#L1286-2 assume !(0 == ~T1_E~0); 59387#L1291-1 assume !(0 == ~T2_E~0); 59388#L1296-1 assume !(0 == ~T3_E~0); 60119#L1301-1 assume !(0 == ~T4_E~0); 60120#L1306-1 assume !(0 == ~T5_E~0); 60610#L1311-1 assume !(0 == ~T6_E~0); 59343#L1316-1 assume !(0 == ~T7_E~0); 59344#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60139#L1326-1 assume !(0 == ~T9_E~0); 59152#L1331-1 assume !(0 == ~T10_E~0); 58862#L1336-1 assume !(0 == ~T11_E~0); 58863#L1341-1 assume !(0 == ~T12_E~0); 58912#L1346-1 assume !(0 == ~T13_E~0); 58913#L1351-1 assume !(0 == ~E_M~0); 59280#L1356-1 assume !(0 == ~E_1~0); 59281#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 60862#L1366-1 assume !(0 == ~E_3~0); 59330#L1371-1 assume !(0 == ~E_4~0); 59331#L1376-1 assume !(0 == ~E_5~0); 60198#L1381-1 assume !(0 == ~E_6~0); 60199#L1386-1 assume !(0 == ~E_7~0); 60897#L1391-1 assume !(0 == ~E_8~0); 60920#L1396-1 assume !(0 == ~E_9~0); 60065#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 60066#L1406-1 assume !(0 == ~E_11~0); 60365#L1411-1 assume !(0 == ~E_12~0); 60366#L1416-1 assume !(0 == ~E_13~0); 59973#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59821#L635 assume !(1 == ~m_pc~0); 58934#L635-2 is_master_triggered_~__retres1~0#1 := 0; 58935#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59277#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59976#L1598 assume !(0 != activate_threads_~tmp~1#1); 59106#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59107#L654 assume 1 == ~t1_pc~0; 59844#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59845#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60482#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59928#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 59929#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59158#L673 assume 1 == ~t2_pc~0; 59159#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60332#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59360#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59361#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 60942#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60004#L692 assume !(1 == ~t3_pc~0); 59823#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59824#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60464#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59646#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59647#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59183#L711 assume 1 == ~t4_pc~0; 59184#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59694#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58982#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58887#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 58888#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60929#L730 assume !(1 == ~t5_pc~0); 60271#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 59065#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59066#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59193#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 59194#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59549#L749 assume 1 == ~t6_pc~0; 59305#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59073#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59346#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 59760#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58869#L768 assume !(1 == ~t7_pc~0); 58870#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 60217#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60745#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60730#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 60237#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59347#L787 assume 1 == ~t8_pc~0; 59348#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60559#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60836#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60837#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 58910#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58911#L806 assume 1 == ~t9_pc~0; 60568#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58947#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58948#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59195#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 59196#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60552#L825 assume !(1 == ~t10_pc~0); 60553#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 60184#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60185#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59278#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59279#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59897#L844 assume 1 == ~t11_pc~0; 59574#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59575#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60657#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60597#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 60539#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60540#L863 assume !(1 == ~t12_pc~0); 59050#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 59049#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58928#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58929#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 60634#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60018#L882 assume 1 == ~t13_pc~0; 60019#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 60308#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60757#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60602#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 60296#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60297#L1434 assume !(1 == ~M_E~0); 60829#L1434-2 assume !(1 == ~T1_E~0); 60933#L1439-1 assume !(1 == ~T2_E~0); 59175#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59176#L1449-1 assume !(1 == ~T4_E~0); 59644#L1454-1 assume !(1 == ~T5_E~0); 59645#L1459-1 assume !(1 == ~T6_E~0); 60238#L1464-1 assume !(1 == ~T7_E~0); 60239#L1469-1 assume !(1 == ~T8_E~0); 60311#L1474-1 assume !(1 == ~T9_E~0); 59974#L1479-1 assume !(1 == ~T10_E~0); 59975#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 60243#L1489-1 assume !(1 == ~T12_E~0); 59856#L1494-1 assume !(1 == ~T13_E~0); 59857#L1499-1 assume !(1 == ~E_M~0); 60044#L1504-1 assume !(1 == ~E_1~0); 60045#L1509-1 assume !(1 == ~E_2~0); 60645#L1514-1 assume !(1 == ~E_3~0); 60343#L1519-1 assume !(1 == ~E_4~0); 60344#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60879#L1529-1 assume !(1 == ~E_6~0); 60880#L1534-1 assume !(1 == ~E_7~0); 58965#L1539-1 assume !(1 == ~E_8~0); 58966#L1544-1 assume !(1 == ~E_9~0); 59410#L1549-1 assume !(1 == ~E_10~0); 60842#L1554-1 assume !(1 == ~E_11~0); 60840#L1559-1 assume !(1 == ~E_12~0); 60691#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 60692#L1569-1 assume { :end_inline_reset_delta_events } true; 60872#L1935-2 [2023-11-21 22:09:45,635 INFO L750 eck$LassoCheckResult]: Loop: 60872#L1935-2 assume !false; 58974#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58872#L1261-1 assume !false; 58873#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60245#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59102#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60542#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 59657#L1074 assume !(0 != eval_~tmp~0#1); 59659#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59565#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59566#L1286-3 assume !(0 == ~M_E~0); 60725#L1286-5 assume !(0 == ~T1_E~0); 62508#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62507#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62506#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62505#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62504#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62503#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62502#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62501#L1326-3 assume !(0 == ~T9_E~0); 62500#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62499#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62498#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 62497#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 62496#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62495#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62494#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62493#L1366-3 assume !(0 == ~E_3~0); 62492#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62491#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62490#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62489#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62488#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62487#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62486#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62485#L1406-3 assume !(0 == ~E_11~0); 62484#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 62483#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 62482#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62481#L635-45 assume !(1 == ~m_pc~0); 62480#L635-47 is_master_triggered_~__retres1~0#1 := 0; 62478#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62477#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62476#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62475#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62474#L654-45 assume 1 == ~t1_pc~0; 60905#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 60487#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60488#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58977#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58978#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59833#L673-45 assume 1 == ~t2_pc~0; 59834#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60178#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60179#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60395#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60600#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59440#L692-45 assume 1 == ~t3_pc~0; 59441#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 59148#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60622#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59489#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59490#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59818#L711-45 assume 1 == ~t4_pc~0; 59945#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59946#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60672#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60673#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 60218#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59319#L730-45 assume 1 == ~t5_pc~0; 59155#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59156#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60951#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60353#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 60354#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59132#L749-45 assume !(1 == ~t6_pc~0); 59133#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 60555#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60623#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62247#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62246#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62245#L768-45 assume 1 == ~t7_pc~0; 62243#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62242#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62241#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62240#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62239#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62238#L787-45 assume !(1 == ~t8_pc~0); 62236#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 62235#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62234#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62233#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62232#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62231#L806-45 assume 1 == ~t9_pc~0; 62229#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62228#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62227#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62226#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 62225#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62224#L825-45 assume !(1 == ~t10_pc~0); 62222#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 62221#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62220#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60387#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 60388#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59213#L844-45 assume 1 == ~t11_pc~0; 59214#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59776#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59250#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59251#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 60215#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59255#L863-45 assume 1 == ~t12_pc~0; 59256#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58860#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58861#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59382#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 59383#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60221#L882-45 assume 1 == ~t13_pc~0; 60548#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 58879#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58880#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60491#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 60699#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60313#L1434-3 assume !(1 == ~M_E~0); 60314#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62301#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62300#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62299#L1449-3 assume !(1 == ~T4_E~0); 62298#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62297#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62296#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62295#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62294#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62293#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62292#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 62291#L1489-3 assume !(1 == ~T12_E~0); 62290#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 62289#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62288#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62287#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62286#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62285#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62284#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62283#L1529-3 assume !(1 == ~E_6~0); 62282#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60183#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59609#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59610#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 60140#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 59218#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 59219#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 60403#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60404#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59104#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 59294#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 59295#L1954 assume !(0 == start_simulation_~tmp~3#1); 60377#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60618#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59403#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58904#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 58905#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60579#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60680#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 60740#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 60872#L1935-2 [2023-11-21 22:09:45,636 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:45,636 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2023-11-21 22:09:45,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:45,636 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668518858] [2023-11-21 22:09:45,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:45,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:45,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:45,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:45,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:45,775 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668518858] [2023-11-21 22:09:45,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668518858] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:45,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:45,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:45,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [986053066] [2023-11-21 22:09:45,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:45,777 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:45,777 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:45,777 INFO L85 PathProgramCache]: Analyzing trace with hash -920647876, now seen corresponding path program 1 times [2023-11-21 22:09:45,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:45,778 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716699245] [2023-11-21 22:09:45,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:45,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:45,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:45,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:45,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:45,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716699245] [2023-11-21 22:09:45,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716699245] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:45,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:45,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:45,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1470537507] [2023-11-21 22:09:45,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:45,854 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:45,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:45,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 22:09:45,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 22:09:45,855 INFO L87 Difference]: Start difference. First operand 3795 states and 5566 transitions. cyclomatic complexity: 1772 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:46,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:46,059 INFO L93 Difference]: Finished difference Result 7441 states and 10902 transitions. [2023-11-21 22:09:46,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7441 states and 10902 transitions. [2023-11-21 22:09:46,092 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7240 [2023-11-21 22:09:46,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7441 states to 7441 states and 10902 transitions. [2023-11-21 22:09:46,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7441 [2023-11-21 22:09:46,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7441 [2023-11-21 22:09:46,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7441 states and 10902 transitions. [2023-11-21 22:09:46,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:46,137 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7441 states and 10902 transitions. [2023-11-21 22:09:46,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7441 states and 10902 transitions. [2023-11-21 22:09:46,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7441 to 7441. [2023-11-21 22:09:46,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7441 states, 7441 states have (on average 1.4651256551538772) internal successors, (10902), 7440 states have internal predecessors, (10902), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:46,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7441 states to 7441 states and 10902 transitions. [2023-11-21 22:09:46,289 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7441 states and 10902 transitions. [2023-11-21 22:09:46,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 22:09:46,290 INFO L428 stractBuchiCegarLoop]: Abstraction has 7441 states and 10902 transitions. [2023-11-21 22:09:46,290 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-21 22:09:46,290 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7441 states and 10902 transitions. [2023-11-21 22:09:46,344 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7240 [2023-11-21 22:09:46,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:46,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:46,348 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:46,348 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:46,349 INFO L748 eck$LassoCheckResult]: Stem: 70419#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 70420#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 71448#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71449#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 72463#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 72464#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70938#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70939#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70984#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71904#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71905#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 72058#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 72059#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 70739#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70740#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 72120#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 71297#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 71298#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 71973#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 72429#L1286 assume !(0 == ~M_E~0); 72215#L1286-2 assume !(0 == ~T1_E~0); 70640#L1291-1 assume !(0 == ~T2_E~0); 70641#L1296-1 assume !(0 == ~T3_E~0); 71402#L1301-1 assume !(0 == ~T4_E~0); 71403#L1306-1 assume !(0 == ~T5_E~0); 71982#L1311-1 assume !(0 == ~T6_E~0); 70596#L1316-1 assume !(0 == ~T7_E~0); 70597#L1321-1 assume !(0 == ~T8_E~0); 71423#L1326-1 assume !(0 == ~T9_E~0); 70402#L1331-1 assume !(0 == ~T10_E~0); 70108#L1336-1 assume !(0 == ~T11_E~0); 70109#L1341-1 assume !(0 == ~T12_E~0); 70158#L1346-1 assume !(0 == ~T13_E~0); 70159#L1351-1 assume !(0 == ~E_M~0); 70530#L1356-1 assume !(0 == ~E_1~0); 70531#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 72347#L1366-1 assume !(0 == ~E_3~0); 70583#L1371-1 assume !(0 == ~E_4~0); 70584#L1376-1 assume !(0 == ~E_5~0); 71487#L1381-1 assume !(0 == ~E_6~0); 71488#L1386-1 assume !(0 == ~E_7~0); 72401#L1391-1 assume !(0 == ~E_8~0); 72441#L1396-1 assume !(0 == ~E_9~0); 71342#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 71343#L1406-1 assume !(0 == ~E_11~0); 71681#L1411-1 assume !(0 == ~E_12~0); 71682#L1416-1 assume !(0 == ~E_13~0); 71247#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71091#L635 assume !(1 == ~m_pc~0); 70180#L635-2 is_master_triggered_~__retres1~0#1 := 0; 70181#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70527#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71250#L1598 assume !(0 != activate_threads_~tmp~1#1); 70355#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70356#L654 assume 1 == ~t1_pc~0; 71114#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 71115#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71826#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71200#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 71201#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70408#L673 assume 1 == ~t2_pc~0; 70409#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 71643#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70613#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70614#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 72490#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71279#L692 assume !(1 == ~t3_pc~0); 71093#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 71094#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71802#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70905#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70906#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70433#L711 assume 1 == ~t4_pc~0; 70434#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70954#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70228#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70133#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 70134#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 72462#L730 assume !(1 == ~t5_pc~0); 71576#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 70314#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70315#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70443#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 70444#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70807#L749 assume 1 == ~t6_pc~0; 70555#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 70322#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70598#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70599#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 71021#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70115#L768 assume !(1 == ~t7_pc~0); 70116#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 71512#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72178#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72149#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 71535#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70600#L787 assume 1 == ~t8_pc~0; 70601#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 71920#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 72314#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 72315#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 70156#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70157#L806 assume 1 == ~t9_pc~0; 71931#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 70193#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70194#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 70445#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 70446#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 71913#L825 assume !(1 == ~t10_pc~0); 71914#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 71470#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 71471#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 70528#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 70529#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 71168#L844 assume 1 == ~t11_pc~0; 70832#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 70833#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 72049#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 71965#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 71899#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 71900#L863 assume !(1 == ~t12_pc~0); 70297#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 70296#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70174#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 70175#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 72017#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 71293#L882 assume 1 == ~t13_pc~0; 71294#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 71617#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 72194#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 71974#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 71605#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71606#L1434 assume !(1 == ~M_E~0); 72304#L1434-2 assume !(1 == ~T1_E~0); 72469#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72470#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77527#L1449-1 assume !(1 == ~T4_E~0); 77526#L1454-1 assume !(1 == ~T5_E~0); 77525#L1459-1 assume !(1 == ~T6_E~0); 77524#L1464-1 assume !(1 == ~T7_E~0); 77523#L1469-1 assume !(1 == ~T8_E~0); 71620#L1474-1 assume !(1 == ~T9_E~0); 77522#L1479-1 assume !(1 == ~T10_E~0); 77521#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77520#L1489-1 assume !(1 == ~T12_E~0); 77519#L1494-1 assume !(1 == ~T13_E~0); 77518#L1499-1 assume !(1 == ~E_M~0); 77517#L1504-1 assume !(1 == ~E_1~0); 77516#L1509-1 assume !(1 == ~E_2~0); 77515#L1514-1 assume !(1 == ~E_3~0); 77514#L1519-1 assume !(1 == ~E_4~0); 77513#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 77512#L1529-1 assume !(1 == ~E_6~0); 77511#L1534-1 assume !(1 == ~E_7~0); 77510#L1539-1 assume !(1 == ~E_8~0); 77509#L1544-1 assume !(1 == ~E_9~0); 77508#L1549-1 assume !(1 == ~E_10~0); 77505#L1554-1 assume !(1 == ~E_11~0); 77503#L1559-1 assume !(1 == ~E_12~0); 77501#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 74623#L1569-1 assume { :end_inline_reset_delta_events } true; 74622#L1935-2 [2023-11-21 22:09:46,350 INFO L750 eck$LassoCheckResult]: Loop: 74622#L1935-2 assume !false; 70220#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70118#L1261-1 assume !false; 70119#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 71548#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 71902#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 71903#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 70916#L1074 assume !(0 != eval_~tmp~0#1); 70918#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70823#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70824#L1286-3 assume !(0 == ~M_E~0); 74559#L1286-5 assume !(0 == ~T1_E~0); 74556#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 74555#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74554#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 74553#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 74552#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 74551#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 74550#L1321-3 assume !(0 == ~T8_E~0); 74549#L1326-3 assume !(0 == ~T9_E~0); 74548#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 74547#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 74546#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 74545#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 74544#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 74543#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 74542#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 74541#L1366-3 assume !(0 == ~E_3~0); 74540#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 74539#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 74538#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 74537#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 74536#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 74535#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 74534#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 74533#L1406-3 assume !(0 == ~E_11~0); 74532#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 74531#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 74530#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74529#L635-45 assume !(1 == ~m_pc~0); 74528#L635-47 is_master_triggered_~__retres1~0#1 := 0; 74526#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74525#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74524#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 74523#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74522#L654-45 assume 1 == ~t1_pc~0; 74521#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 74519#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74518#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74517#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74516#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74515#L673-45 assume 1 == ~t2_pc~0; 74513#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 74512#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74511#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74510#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 74509#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74506#L692-45 assume 1 == ~t3_pc~0; 74507#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75655#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75654#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75653#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 75652#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75651#L711-45 assume 1 == ~t4_pc~0; 75649#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 75648#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75647#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75646#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 75645#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75644#L730-45 assume !(1 == ~t5_pc~0); 75643#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 75641#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75640#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75639#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 75638#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75637#L749-45 assume 1 == ~t6_pc~0; 75635#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 75634#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75633#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75632#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 75631#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75630#L768-45 assume !(1 == ~t7_pc~0); 75629#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 75627#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75626#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75625#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 75624#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75623#L787-45 assume !(1 == ~t8_pc~0); 75621#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 75620#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75619#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75618#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75617#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75616#L806-45 assume !(1 == ~t9_pc~0); 75615#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 75613#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75612#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75611#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 75610#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75609#L825-45 assume !(1 == ~t10_pc~0); 75607#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 75606#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75605#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75604#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 75603#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75602#L844-45 assume !(1 == ~t11_pc~0); 75601#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 75599#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75598#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75597#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 75596#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75595#L863-45 assume !(1 == ~t12_pc~0); 75593#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 75592#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75591#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 75590#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 75589#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 75588#L882-45 assume !(1 == ~t13_pc~0); 75587#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 75585#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 75584#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 75583#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 75582#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75581#L1434-3 assume !(1 == ~M_E~0); 75579#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 75578#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71833#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75577#L1449-3 assume !(1 == ~T4_E~0); 75576#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75575#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 75574#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 75573#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 72191#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 75572#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 75571#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 75570#L1489-3 assume !(1 == ~T12_E~0); 75569#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 75568#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 75567#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 75566#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 75565#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 75564#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 75563#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 75562#L1529-3 assume !(1 == ~E_6~0); 75561#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 75560#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 75559#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 75558#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 75557#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 75556#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 75555#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 75554#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 75540#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75539#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75538#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 75537#L1954 assume !(0 == start_simulation_~tmp~3#1); 75535#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74630#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 74629#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74628#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 74627#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 74626#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 74625#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 74624#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 74622#L1935-2 [2023-11-21 22:09:46,351 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:46,351 INFO L85 PathProgramCache]: Analyzing trace with hash -113531325, now seen corresponding path program 1 times [2023-11-21 22:09:46,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:46,351 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74411090] [2023-11-21 22:09:46,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:46,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:46,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:46,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:46,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:46,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [74411090] [2023-11-21 22:09:46,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [74411090] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:46,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:46,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:09:46,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278806324] [2023-11-21 22:09:46,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:46,424 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:46,425 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:46,425 INFO L85 PathProgramCache]: Analyzing trace with hash 1051692159, now seen corresponding path program 1 times [2023-11-21 22:09:46,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:46,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323118755] [2023-11-21 22:09:46,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:46,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:46,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:46,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:46,494 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:46,494 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323118755] [2023-11-21 22:09:46,494 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [323118755] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:46,494 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:46,494 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:46,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1945967359] [2023-11-21 22:09:46,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:46,495 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:46,495 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:46,496 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:46,496 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:46,496 INFO L87 Difference]: Start difference. First operand 7441 states and 10902 transitions. cyclomatic complexity: 3463 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:46,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:46,600 INFO L93 Difference]: Finished difference Result 7441 states and 10828 transitions. [2023-11-21 22:09:46,601 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7441 states and 10828 transitions. [2023-11-21 22:09:46,632 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7240 [2023-11-21 22:09:46,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7441 states to 7441 states and 10828 transitions. [2023-11-21 22:09:46,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7441 [2023-11-21 22:09:46,668 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7441 [2023-11-21 22:09:46,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7441 states and 10828 transitions. [2023-11-21 22:09:46,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:46,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7441 states and 10828 transitions. [2023-11-21 22:09:46,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7441 states and 10828 transitions. [2023-11-21 22:09:46,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7441 to 7441. [2023-11-21 22:09:46,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7441 states, 7441 states have (on average 1.4551807552748286) internal successors, (10828), 7440 states have internal predecessors, (10828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:46,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7441 states to 7441 states and 10828 transitions. [2023-11-21 22:09:46,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7441 states and 10828 transitions. [2023-11-21 22:09:46,822 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:46,822 INFO L428 stractBuchiCegarLoop]: Abstraction has 7441 states and 10828 transitions. [2023-11-21 22:09:46,823 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-21 22:09:46,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7441 states and 10828 transitions. [2023-11-21 22:09:46,849 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7240 [2023-11-21 22:09:46,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:46,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:46,853 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:46,853 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:46,854 INFO L748 eck$LassoCheckResult]: Stem: 85304#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86302#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86303#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87152#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 87153#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85811#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85812#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85856#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86704#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86705#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86832#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86833#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85617#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 85618#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86885#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 86155#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 86156#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86771#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87133#L1286 assume !(0 == ~M_E~0); 86963#L1286-2 assume !(0 == ~T1_E~0); 85522#L1291-1 assume !(0 == ~T2_E~0); 85523#L1296-1 assume !(0 == ~T3_E~0); 86254#L1301-1 assume !(0 == ~T4_E~0); 86255#L1306-1 assume !(0 == ~T5_E~0); 86779#L1311-1 assume !(0 == ~T6_E~0); 85478#L1316-1 assume !(0 == ~T7_E~0); 85479#L1321-1 assume !(0 == ~T8_E~0); 86274#L1326-1 assume !(0 == ~T9_E~0); 85287#L1331-1 assume !(0 == ~T10_E~0); 84997#L1336-1 assume !(0 == ~T11_E~0); 84998#L1341-1 assume !(0 == ~T12_E~0); 85047#L1346-1 assume !(0 == ~T13_E~0); 85048#L1351-1 assume !(0 == ~E_M~0); 85414#L1356-1 assume !(0 == ~E_1~0); 85415#L1361-1 assume !(0 == ~E_2~0); 87075#L1366-1 assume !(0 == ~E_3~0); 85465#L1371-1 assume !(0 == ~E_4~0); 85466#L1376-1 assume !(0 == ~E_5~0); 86336#L1381-1 assume !(0 == ~E_6~0); 86337#L1386-1 assume !(0 == ~E_7~0); 87117#L1391-1 assume !(0 == ~E_8~0); 87139#L1396-1 assume !(0 == ~E_9~0); 86198#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 86199#L1406-1 assume !(0 == ~E_11~0); 86507#L1411-1 assume !(0 == ~E_12~0); 86508#L1416-1 assume !(0 == ~E_13~0); 86106#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85956#L635 assume !(1 == ~m_pc~0); 85069#L635-2 is_master_triggered_~__retres1~0#1 := 0; 85070#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85411#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86109#L1598 assume !(0 != activate_threads_~tmp~1#1); 85241#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85242#L654 assume 1 == ~t1_pc~0; 85978#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85979#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86633#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86061#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 86062#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85293#L673 assume !(1 == ~t2_pc~0); 85295#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86477#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85495#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85496#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 87163#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86137#L692 assume !(1 == ~t3_pc~0); 85958#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85959#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86614#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85778#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85779#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85318#L711 assume 1 == ~t4_pc~0; 85319#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85826#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85117#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85022#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 85023#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87150#L730 assume !(1 == ~t5_pc~0); 86412#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 85200#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85201#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85328#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 85329#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85682#L749 assume 1 == ~t6_pc~0; 85440#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85208#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85480#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85481#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 85892#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85004#L768 assume !(1 == ~t7_pc~0); 85005#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 86355#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86929#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86913#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 86377#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85482#L787 assume 1 == ~t8_pc~0; 85483#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86724#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87042#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87043#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 85045#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85046#L806 assume 1 == ~t9_pc~0; 86733#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85082#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85083#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85330#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 85331#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86713#L825 assume !(1 == ~t10_pc~0); 86714#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 86321#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86322#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85412#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85413#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86031#L844 assume 1 == ~t11_pc~0; 85706#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85707#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86827#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86765#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 86700#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86701#L863 assume !(1 == ~t12_pc~0); 85185#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 85184#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85063#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85064#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 86805#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86151#L882 assume 1 == ~t13_pc~0; 86152#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86452#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86941#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86772#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 86439#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86440#L1434 assume !(1 == ~M_E~0); 87033#L1434-2 assume !(1 == ~T1_E~0); 87155#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87156#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90951#L1449-1 assume !(1 == ~T4_E~0); 90950#L1454-1 assume !(1 == ~T5_E~0); 90949#L1459-1 assume !(1 == ~T6_E~0); 90948#L1464-1 assume !(1 == ~T7_E~0); 90947#L1469-1 assume !(1 == ~T8_E~0); 86455#L1474-1 assume !(1 == ~T9_E~0); 90946#L1479-1 assume !(1 == ~T10_E~0); 90945#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 90944#L1489-1 assume !(1 == ~T12_E~0); 90943#L1494-1 assume !(1 == ~T13_E~0); 90942#L1499-1 assume !(1 == ~E_M~0); 90941#L1504-1 assume !(1 == ~E_1~0); 90940#L1509-1 assume !(1 == ~E_2~0); 90939#L1514-1 assume !(1 == ~E_3~0); 90938#L1519-1 assume !(1 == ~E_4~0); 90937#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 90936#L1529-1 assume !(1 == ~E_6~0); 90935#L1534-1 assume !(1 == ~E_7~0); 90934#L1539-1 assume !(1 == ~E_8~0); 90933#L1544-1 assume !(1 == ~E_9~0); 87049#L1549-1 assume !(1 == ~E_10~0); 87050#L1554-1 assume !(1 == ~E_11~0); 87046#L1559-1 assume !(1 == ~E_12~0); 86865#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 86866#L1569-1 assume { :end_inline_reset_delta_events } true; 87084#L1935-2 [2023-11-21 22:09:46,855 INFO L750 eck$LassoCheckResult]: Loop: 87084#L1935-2 assume !false; 85109#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85007#L1261-1 assume !false; 85008#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86385#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85237#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86703#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 85789#L1074 assume !(0 != eval_~tmp~0#1); 85791#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85697#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85698#L1286-3 assume !(0 == ~M_E~0); 86908#L1286-5 assume !(0 == ~T1_E~0); 86576#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 86577#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87136#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87066#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86073#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85342#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85343#L1321-3 assume !(0 == ~T8_E~0); 85455#L1326-3 assume !(0 == ~T9_E~0); 86221#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 86491#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 86492#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85766#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85753#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85693#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85694#L1361-3 assume !(0 == ~E_2~0); 86309#L1366-3 assume !(0 == ~E_3~0); 85035#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 85036#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86842#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86671#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 86672#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86887#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 86888#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 85407#L1406-3 assume !(0 == ~E_11~0); 85243#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 85244#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 85907#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85121#L635-45 assume !(1 == ~m_pc~0); 85123#L635-47 is_master_triggered_~__retres1~0#1 := 0; 85949#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90835#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86698#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 86699#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86294#L654-45 assume !(1 == ~t1_pc~0); 86295#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 90834#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90833#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90832#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86961#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86962#L673-45 assume !(1 == ~t2_pc~0); 90211#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 90210#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86536#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86537#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86770#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85575#L692-45 assume !(1 == ~t3_pc~0); 85282#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 85283#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86792#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85624#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85625#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85953#L711-45 assume !(1 == ~t4_pc~0); 86080#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 86079#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86845#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86846#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 86356#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85454#L730-45 assume 1 == ~t5_pc~0; 85290#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 85291#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87180#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86496#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 86497#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85267#L749-45 assume 1 == ~t6_pc~0; 85269#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86716#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86194#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86195#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86620#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85600#L768-45 assume 1 == ~t7_pc~0; 85601#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85740#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86297#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86298#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86601#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86602#L787-45 assume 1 == ~t8_pc~0; 86795#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85746#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85747#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86173#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 86174#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86495#L806-45 assume 1 == ~t9_pc~0; 87052#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85149#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85992#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85822#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85721#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85722#L825-45 assume 1 == ~t10_pc~0; 86373#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 86268#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86775#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86528#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86529#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85348#L844-45 assume 1 == ~t11_pc~0; 85349#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85908#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85384#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85385#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 86353#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85389#L863-45 assume !(1 == ~t12_pc~0); 85391#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 84995#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84996#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85517#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 85518#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86361#L882-45 assume !(1 == ~t13_pc~0); 85873#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 85014#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85015#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86645#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 86875#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86458#L1434-3 assume !(1 == ~M_E~0); 86459#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88436#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88434#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88432#L1449-3 assume !(1 == ~T4_E~0); 88430#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 88343#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 88342#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 88340#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 88338#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 88335#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 88333#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 88331#L1489-3 assume !(1 == ~T12_E~0); 88329#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 88327#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 88325#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 88324#L1509-3 assume !(1 == ~E_2~0); 88321#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88319#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88317#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88315#L1529-3 assume !(1 == ~E_6~0); 87092#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86320#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85741#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 85742#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86275#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85353#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 85354#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 86544#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86545#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85239#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85428#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 85429#L1954 assume !(0 == start_simulation_~tmp~3#1); 86518#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 91058#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 91057#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 90928#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 86745#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86746#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86854#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 86924#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 87084#L1935-2 [2023-11-21 22:09:46,856 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:46,856 INFO L85 PathProgramCache]: Analyzing trace with hash -1573181374, now seen corresponding path program 1 times [2023-11-21 22:09:46,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:46,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498121054] [2023-11-21 22:09:46,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:46,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:46,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:46,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:46,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:46,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498121054] [2023-11-21 22:09:46,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1498121054] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:46,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:46,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:46,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854200862] [2023-11-21 22:09:46,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:46,964 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:46,965 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:46,965 INFO L85 PathProgramCache]: Analyzing trace with hash 672537405, now seen corresponding path program 1 times [2023-11-21 22:09:46,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:46,965 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717469328] [2023-11-21 22:09:46,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:46,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:46,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:47,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:47,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:47,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717469328] [2023-11-21 22:09:47,035 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1717469328] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:47,035 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:47,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:47,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [581795387] [2023-11-21 22:09:47,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:47,036 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:47,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:47,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-21 22:09:47,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-21 22:09:47,037 INFO L87 Difference]: Start difference. First operand 7441 states and 10828 transitions. cyclomatic complexity: 3389 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:47,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:47,418 INFO L93 Difference]: Finished difference Result 14309 states and 20812 transitions. [2023-11-21 22:09:47,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14309 states and 20812 transitions. [2023-11-21 22:09:47,484 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 14080 [2023-11-21 22:09:47,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14309 states to 14309 states and 20812 transitions. [2023-11-21 22:09:47,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14309 [2023-11-21 22:09:47,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14309 [2023-11-21 22:09:47,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14309 states and 20812 transitions. [2023-11-21 22:09:47,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:47,567 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14309 states and 20812 transitions. [2023-11-21 22:09:47,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14309 states and 20812 transitions. [2023-11-21 22:09:47,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14309 to 14305. [2023-11-21 22:09:47,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14305 states, 14305 states have (on average 1.4545962950017477) internal successors, (20808), 14304 states have internal predecessors, (20808), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:47,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14305 states to 14305 states and 20808 transitions. [2023-11-21 22:09:47,850 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14305 states and 20808 transitions. [2023-11-21 22:09:47,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-21 22:09:47,851 INFO L428 stractBuchiCegarLoop]: Abstraction has 14305 states and 20808 transitions. [2023-11-21 22:09:47,852 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-21 22:09:47,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14305 states and 20808 transitions. [2023-11-21 22:09:47,901 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 14080 [2023-11-21 22:09:47,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:47,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:47,905 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:47,905 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:47,905 INFO L748 eck$LassoCheckResult]: Stem: 107064#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 107065#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 108079#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 108080#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 108922#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 108923#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 107575#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 107576#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 107621#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 108473#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 108474#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 108610#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 108611#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 107376#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 107377#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 108662#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 107936#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 107937#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 108539#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108905#L1286 assume !(0 == ~M_E~0); 108736#L1286-2 assume !(0 == ~T1_E~0); 107281#L1291-1 assume !(0 == ~T2_E~0); 107282#L1296-1 assume !(0 == ~T3_E~0); 108034#L1301-1 assume !(0 == ~T4_E~0); 108035#L1306-1 assume !(0 == ~T5_E~0); 108549#L1311-1 assume !(0 == ~T6_E~0); 107237#L1316-1 assume !(0 == ~T7_E~0); 107238#L1321-1 assume !(0 == ~T8_E~0); 108054#L1326-1 assume !(0 == ~T9_E~0); 107047#L1331-1 assume !(0 == ~T10_E~0); 106757#L1336-1 assume !(0 == ~T11_E~0); 106758#L1341-1 assume !(0 == ~T12_E~0); 106807#L1346-1 assume !(0 == ~T13_E~0); 106808#L1351-1 assume !(0 == ~E_M~0); 107174#L1356-1 assume !(0 == ~E_1~0); 107175#L1361-1 assume !(0 == ~E_2~0); 108848#L1366-1 assume !(0 == ~E_3~0); 107224#L1371-1 assume !(0 == ~E_4~0); 107225#L1376-1 assume !(0 == ~E_5~0); 108113#L1381-1 assume !(0 == ~E_6~0); 108114#L1386-1 assume !(0 == ~E_7~0); 108891#L1391-1 assume !(0 == ~E_8~0); 108909#L1396-1 assume !(0 == ~E_9~0); 107979#L1401-1 assume !(0 == ~E_10~0); 107980#L1406-1 assume !(0 == ~E_11~0); 108283#L1411-1 assume !(0 == ~E_12~0); 108284#L1416-1 assume !(0 == ~E_13~0); 107886#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107719#L635 assume !(1 == ~m_pc~0); 106829#L635-2 is_master_triggered_~__retres1~0#1 := 0; 106830#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107171#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 107889#L1598 assume !(0 != activate_threads_~tmp~1#1); 107001#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107002#L654 assume 1 == ~t1_pc~0; 107741#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 107742#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108411#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 107836#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 107837#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107053#L673 assume !(1 == ~t2_pc~0); 107055#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 108253#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107254#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 107255#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 108941#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107917#L692 assume !(1 == ~t3_pc~0); 107721#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 107722#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108390#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 107542#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 107543#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107078#L711 assume 1 == ~t4_pc~0; 107079#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 107591#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106877#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 106782#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 106783#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108921#L730 assume !(1 == ~t5_pc~0); 108189#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 106960#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106961#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 107088#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 107089#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 107442#L749 assume 1 == ~t6_pc~0; 107199#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 106968#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 107239#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 107240#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 107657#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 106764#L768 assume !(1 == ~t7_pc~0); 106765#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 108132#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 108704#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 108689#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 108153#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 107241#L787 assume 1 == ~t8_pc~0; 107242#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 108492#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 108818#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 108819#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 106805#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 106806#L806 assume 1 == ~t9_pc~0; 108501#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 106842#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 106843#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 107090#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 107091#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 108485#L825 assume !(1 == ~t10_pc~0); 108486#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 108098#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 108099#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 107172#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 107173#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 107799#L844 assume 1 == ~t11_pc~0; 107467#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 107468#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 108606#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 108535#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 108469#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 108470#L863 assume !(1 == ~t12_pc~0); 106945#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 106944#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 106823#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 106824#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 108580#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 107932#L882 assume 1 == ~t13_pc~0; 107933#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 108228#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 108717#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 108540#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 108216#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108217#L1434 assume !(1 == ~M_E~0); 108809#L1434-2 assume !(1 == ~T1_E~0); 108926#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 108927#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 113028#L1449-1 assume !(1 == ~T4_E~0); 113025#L1454-1 assume !(1 == ~T5_E~0); 108759#L1459-1 assume !(1 == ~T6_E~0); 108760#L1464-1 assume !(1 == ~T7_E~0); 108231#L1469-1 assume !(1 == ~T8_E~0); 108232#L1474-1 assume !(1 == ~T9_E~0); 107887#L1479-1 assume !(1 == ~T10_E~0); 107888#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 108159#L1489-1 assume !(1 == ~T12_E~0); 107754#L1494-1 assume !(1 == ~T13_E~0); 107755#L1499-1 assume !(1 == ~E_M~0); 107958#L1504-1 assume !(1 == ~E_1~0); 107959#L1509-1 assume !(1 == ~E_2~0); 108592#L1514-1 assume !(1 == ~E_3~0); 108264#L1519-1 assume !(1 == ~E_4~0); 108265#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 108865#L1529-1 assume !(1 == ~E_6~0); 108866#L1534-1 assume !(1 == ~E_7~0); 106862#L1539-1 assume !(1 == ~E_8~0); 106863#L1544-1 assume !(1 == ~E_9~0); 107304#L1549-1 assume !(1 == ~E_10~0); 108824#L1554-1 assume !(1 == ~E_11~0); 108822#L1559-1 assume !(1 == ~E_12~0); 108643#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 108644#L1569-1 assume { :end_inline_reset_delta_events } true; 108861#L1935-2 [2023-11-21 22:09:47,906 INFO L750 eck$LassoCheckResult]: Loop: 108861#L1935-2 assume !false; 106869#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 106767#L1261-1 assume !false; 106768#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 108161#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 106997#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 108472#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 107553#L1074 assume !(0 != eval_~tmp~0#1); 107555#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 120840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 120838#L1286-3 assume !(0 == ~M_E~0); 120835#L1286-5 assume !(0 == ~T1_E~0); 120833#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 108930#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 108907#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 108839#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 107849#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 107102#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 107103#L1321-3 assume !(0 == ~T8_E~0); 107207#L1326-3 assume !(0 == ~T9_E~0); 108003#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 108269#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 108270#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 107530#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 107516#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 107454#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 107455#L1361-3 assume !(0 == ~E_2~0); 108086#L1366-3 assume !(0 == ~E_3~0); 106797#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 106798#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 108620#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 108445#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 108446#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 108664#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 108665#L1401-3 assume !(0 == ~E_10~0); 107167#L1406-3 assume !(0 == ~E_11~0); 107003#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 107004#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 107672#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106883#L635-45 assume !(1 == ~m_pc~0); 106885#L635-47 is_master_triggered_~__retres1~0#1 := 0; 107712#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108218#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 108318#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 107186#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107187#L654-45 assume 1 == ~t1_pc~0; 108073#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 108416#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108417#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 106872#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 106873#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107730#L673-45 assume !(1 == ~t2_pc~0); 107732#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 108092#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108093#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 108312#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 108538#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107334#L692-45 assume !(1 == ~t3_pc~0); 107045#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 107046#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108563#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 107383#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 107384#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107716#L711-45 assume !(1 == ~t4_pc~0); 107856#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 107855#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108623#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 108624#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 108134#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 107214#L730-45 assume 1 == ~t5_pc~0; 107050#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 107051#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108953#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 108273#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 108274#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 107027#L749-45 assume 1 == ~t6_pc~0; 107029#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 108488#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 107975#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 107976#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 108394#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 107359#L768-45 assume !(1 == ~t7_pc~0); 107361#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 107506#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 108074#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 108075#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 108378#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 108379#L787-45 assume !(1 == ~t8_pc~0); 108569#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 107509#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 107510#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 107956#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 107957#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 108272#L806-45 assume 1 == ~t9_pc~0; 108827#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 106909#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 107756#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 107587#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 107482#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 107483#L825-45 assume 1 == ~t10_pc~0; 108149#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 108048#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 108543#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 108304#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 108305#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 107107#L844-45 assume !(1 == ~t11_pc~0); 107109#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 107673#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 107674#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 110351#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 110350#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 110349#L863-45 assume !(1 == ~t12_pc~0); 110347#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 110346#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 108483#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 107273#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 107274#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 108135#L882-45 assume !(1 == ~t13_pc~0); 107638#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 106774#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 106775#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 108419#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 108651#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108234#L1434-3 assume !(1 == ~M_E~0); 108235#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 108415#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 107066#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 107067#L1449-3 assume !(1 == ~T4_E~0); 107226#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 108224#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 108225#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 108714#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 108621#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 108622#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 108718#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 107852#L1489-3 assume !(1 == ~T12_E~0); 107853#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 108534#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 108162#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 108163#L1509-3 assume !(1 == ~E_2~0); 108634#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 108687#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 107757#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107758#L1529-3 assume !(1 == ~E_6~0); 108748#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 108094#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 107502#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 107503#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 108055#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 107113#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 107114#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 108323#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 108324#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 106999#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 107188#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 107189#L1954 assume !(0 == start_simulation_~tmp~3#1); 108294#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 108558#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 107297#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 106799#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 106800#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 108514#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 108631#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 108699#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 108861#L1935-2 [2023-11-21 22:09:47,907 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:47,907 INFO L85 PathProgramCache]: Analyzing trace with hash 879310208, now seen corresponding path program 1 times [2023-11-21 22:09:47,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:47,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561603358] [2023-11-21 22:09:47,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:47,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:47,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:48,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:48,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:48,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1561603358] [2023-11-21 22:09:48,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1561603358] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:48,056 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:48,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:09:48,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [986165307] [2023-11-21 22:09:48,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:48,057 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:48,057 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:48,058 INFO L85 PathProgramCache]: Analyzing trace with hash -1500999235, now seen corresponding path program 1 times [2023-11-21 22:09:48,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:48,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162879476] [2023-11-21 22:09:48,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:48,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:48,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:48,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:48,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:48,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162879476] [2023-11-21 22:09:48,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162879476] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:48,131 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:48,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:48,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199435768] [2023-11-21 22:09:48,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:48,133 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:48,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:48,133 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:48,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:48,134 INFO L87 Difference]: Start difference. First operand 14305 states and 20808 transitions. cyclomatic complexity: 6507 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:48,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:48,398 INFO L93 Difference]: Finished difference Result 27464 states and 39763 transitions. [2023-11-21 22:09:48,398 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27464 states and 39763 transitions. [2023-11-21 22:09:48,524 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27224 [2023-11-21 22:09:48,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27464 states to 27464 states and 39763 transitions. [2023-11-21 22:09:48,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27464 [2023-11-21 22:09:48,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27464 [2023-11-21 22:09:48,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27464 states and 39763 transitions. [2023-11-21 22:09:48,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:48,689 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27464 states and 39763 transitions. [2023-11-21 22:09:48,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27464 states and 39763 transitions. [2023-11-21 22:09:49,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27464 to 27448. [2023-11-21 22:09:49,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27448 states, 27448 states have (on average 1.4480836490819002) internal successors, (39747), 27447 states have internal predecessors, (39747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:49,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27448 states to 27448 states and 39747 transitions. [2023-11-21 22:09:49,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27448 states and 39747 transitions. [2023-11-21 22:09:49,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:49,599 INFO L428 stractBuchiCegarLoop]: Abstraction has 27448 states and 39747 transitions. [2023-11-21 22:09:49,599 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-21 22:09:49,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27448 states and 39747 transitions. [2023-11-21 22:09:49,702 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27208 [2023-11-21 22:09:49,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:49,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:49,707 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:49,707 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:49,708 INFO L748 eck$LassoCheckResult]: Stem: 148843#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 148844#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 149875#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 149876#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 150902#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 150903#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 149360#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 149361#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 149406#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 150326#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 150327#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 150485#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 150486#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 149157#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 149158#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 150546#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 149715#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 149716#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 150400#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 150874#L1286 assume !(0 == ~M_E~0); 150648#L1286-2 assume !(0 == ~T1_E~0); 149060#L1291-1 assume !(0 == ~T2_E~0); 149061#L1296-1 assume !(0 == ~T3_E~0); 149825#L1301-1 assume !(0 == ~T4_E~0); 149826#L1306-1 assume !(0 == ~T5_E~0); 150413#L1311-1 assume !(0 == ~T6_E~0); 149014#L1316-1 assume !(0 == ~T7_E~0); 149015#L1321-1 assume !(0 == ~T8_E~0); 149848#L1326-1 assume !(0 == ~T9_E~0); 148826#L1331-1 assume !(0 == ~T10_E~0); 148533#L1336-1 assume !(0 == ~T11_E~0); 148534#L1341-1 assume !(0 == ~T12_E~0); 148583#L1346-1 assume !(0 == ~T13_E~0); 148584#L1351-1 assume !(0 == ~E_M~0); 148951#L1356-1 assume !(0 == ~E_1~0); 148952#L1361-1 assume !(0 == ~E_2~0); 150788#L1366-1 assume !(0 == ~E_3~0); 149001#L1371-1 assume !(0 == ~E_4~0); 149002#L1376-1 assume !(0 == ~E_5~0); 149914#L1381-1 assume !(0 == ~E_6~0); 149915#L1386-1 assume !(0 == ~E_7~0); 150854#L1391-1 assume !(0 == ~E_8~0); 150883#L1396-1 assume !(0 == ~E_9~0); 149762#L1401-1 assume !(0 == ~E_10~0); 149763#L1406-1 assume !(0 == ~E_11~0); 150100#L1411-1 assume !(0 == ~E_12~0); 150101#L1416-1 assume !(0 == ~E_13~0); 149665#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 149506#L635 assume !(1 == ~m_pc~0); 148605#L635-2 is_master_triggered_~__retres1~0#1 := 0; 148606#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148948#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 149668#L1598 assume !(0 != activate_threads_~tmp~1#1); 148779#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148780#L654 assume !(1 == ~t1_pc~0); 149618#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 150548#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 150252#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 149614#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 149615#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 148832#L673 assume !(1 == ~t2_pc~0); 148834#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 150068#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 149032#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 149033#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 150931#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149696#L692 assume !(1 == ~t3_pc~0); 149508#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 149509#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 150227#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 149326#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 149327#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 148857#L711 assume 1 == ~t4_pc~0; 148858#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 149376#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 148653#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 148558#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 148559#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 150901#L730 assume !(1 == ~t5_pc~0); 150001#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 148738#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 148739#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 148867#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 148868#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 149226#L749 assume 1 == ~t6_pc~0; 148976#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 148746#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 149016#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 149017#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 149441#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 148540#L768 assume !(1 == ~t7_pc~0); 148541#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 149936#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 150599#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 150581#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 149962#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 149018#L787 assume 1 == ~t8_pc~0; 149019#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 150344#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 150746#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 150747#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 148581#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 148582#L806 assume 1 == ~t9_pc~0; 150355#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 148618#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 148619#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 148869#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 148870#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 150335#L825 assume !(1 == ~t10_pc~0); 150336#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 149899#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 149900#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 148949#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 148950#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 149581#L844 assume 1 == ~t11_pc~0; 149250#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 149251#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 150478#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 150395#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 150322#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 150323#L863 assume !(1 == ~t12_pc~0); 148721#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 148720#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 148599#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 148600#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 150448#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 149711#L882 assume 1 == ~t13_pc~0; 149712#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 150042#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 150617#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 150401#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 150029#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150030#L1434 assume !(1 == ~M_E~0); 150731#L1434-2 assume !(1 == ~T1_E~0); 150913#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 150914#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 155186#L1449-1 assume !(1 == ~T4_E~0); 155184#L1454-1 assume !(1 == ~T5_E~0); 155181#L1459-1 assume !(1 == ~T6_E~0); 155179#L1464-1 assume !(1 == ~T7_E~0); 155177#L1469-1 assume !(1 == ~T8_E~0); 155175#L1474-1 assume !(1 == ~T9_E~0); 149666#L1479-1 assume !(1 == ~T10_E~0); 149667#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 149969#L1489-1 assume !(1 == ~T12_E~0); 149537#L1494-1 assume !(1 == ~T13_E~0); 149538#L1499-1 assume !(1 == ~E_M~0); 149739#L1504-1 assume !(1 == ~E_1~0); 149740#L1509-1 assume !(1 == ~E_2~0); 150466#L1514-1 assume !(1 == ~E_3~0); 150079#L1519-1 assume !(1 == ~E_4~0); 150080#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 150818#L1529-1 assume !(1 == ~E_6~0); 150819#L1534-1 assume !(1 == ~E_7~0); 148638#L1539-1 assume !(1 == ~E_8~0); 148639#L1544-1 assume !(1 == ~E_9~0); 149084#L1549-1 assume !(1 == ~E_10~0); 150753#L1554-1 assume !(1 == ~E_11~0); 154148#L1559-1 assume !(1 == ~E_12~0); 154145#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 154082#L1569-1 assume { :end_inline_reset_delta_events } true; 154078#L1935-2 [2023-11-21 22:09:49,709 INFO L750 eck$LassoCheckResult]: Loop: 154078#L1935-2 assume !false; 154060#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 154050#L1261-1 assume !false; 154043#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 154029#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 153993#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 153990#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 153986#L1074 assume !(0 != eval_~tmp~0#1); 153981#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 153978#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 153975#L1286-3 assume !(0 == ~M_E~0); 153972#L1286-5 assume !(0 == ~T1_E~0); 153969#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 153966#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 153962#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 153958#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 153954#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 153950#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 153946#L1321-3 assume !(0 == ~T8_E~0); 153942#L1326-3 assume !(0 == ~T9_E~0); 153938#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 153934#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 153930#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 153926#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 153922#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 153918#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 153914#L1361-3 assume !(0 == ~E_2~0); 153910#L1366-3 assume !(0 == ~E_3~0); 153906#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 153902#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 153898#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 153894#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 153890#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 153886#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 153882#L1401-3 assume !(0 == ~E_10~0); 153878#L1406-3 assume !(0 == ~E_11~0); 153874#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 153870#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 153866#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153862#L635-45 assume 1 == ~m_pc~0; 153856#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 153850#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153846#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 153842#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 153838#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153834#L654-45 assume !(1 == ~t1_pc~0); 153830#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 153826#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153822#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 153818#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 153814#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153809#L673-45 assume !(1 == ~t2_pc~0); 153802#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 153798#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153794#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 153790#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 153786#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153782#L692-45 assume !(1 == ~t3_pc~0); 153776#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 153770#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153766#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 153762#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 153758#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153754#L711-45 assume 1 == ~t4_pc~0; 153748#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 153742#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153738#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 153734#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 153730#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 153726#L730-45 assume 1 == ~t5_pc~0; 153720#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 153714#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 153710#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 153706#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 153702#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 153698#L749-45 assume 1 == ~t6_pc~0; 153692#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 153686#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 153682#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 153678#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 153674#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 153670#L768-45 assume 1 == ~t7_pc~0; 153664#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 153658#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 153654#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 153650#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 153646#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 153642#L787-45 assume !(1 == ~t8_pc~0); 153636#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 153630#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 153626#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 153622#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 153618#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 153614#L806-45 assume 1 == ~t9_pc~0; 153608#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 153602#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 153598#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 153594#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 153590#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 153586#L825-45 assume !(1 == ~t10_pc~0); 153580#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 153574#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 153570#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 153566#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 153562#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 153558#L844-45 assume 1 == ~t11_pc~0; 153552#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 153546#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 153542#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 153538#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 153534#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 153530#L863-45 assume !(1 == ~t12_pc~0); 153524#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 153518#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 153514#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 153510#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 153506#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 153503#L882-45 assume 1 == ~t13_pc~0; 153498#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 153491#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 153486#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 153480#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 153475#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153470#L1434-3 assume !(1 == ~M_E~0); 153464#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 153461#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 153456#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 153453#L1449-3 assume !(1 == ~T4_E~0); 153450#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 153447#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 153444#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 153441#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 153436#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 153434#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 153432#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 153430#L1489-3 assume !(1 == ~T12_E~0); 153428#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 153426#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 153424#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 153421#L1509-3 assume !(1 == ~E_2~0); 153419#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 153417#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 153415#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 153413#L1529-3 assume !(1 == ~E_6~0); 153411#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 153408#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 153406#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 153404#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 153400#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 153399#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 153398#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 153397#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 153382#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 153380#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 153377#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 153374#L1954 assume !(0 == start_simulation_~tmp~3#1); 153375#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 154160#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 154158#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 154157#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 154153#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 154151#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 154149#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 154083#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 154078#L1935-2 [2023-11-21 22:09:49,709 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:49,710 INFO L85 PathProgramCache]: Analyzing trace with hash -2044595327, now seen corresponding path program 1 times [2023-11-21 22:09:49,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:49,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501395647] [2023-11-21 22:09:49,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:49,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:49,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:49,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:49,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:49,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501395647] [2023-11-21 22:09:49,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501395647] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:49,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:49,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-21 22:09:49,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855406548] [2023-11-21 22:09:49,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:49,839 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:49,840 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:49,840 INFO L85 PathProgramCache]: Analyzing trace with hash 290951290, now seen corresponding path program 1 times [2023-11-21 22:09:49,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:49,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535699896] [2023-11-21 22:09:49,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:49,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:49,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:50,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:50,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:50,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535699896] [2023-11-21 22:09:50,070 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535699896] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:50,070 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:50,070 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:50,071 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178056430] [2023-11-21 22:09:50,071 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:50,072 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:50,072 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:50,073 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-21 22:09:50,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-21 22:09:50,073 INFO L87 Difference]: Start difference. First operand 27448 states and 39747 transitions. cyclomatic complexity: 12307 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:50,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:50,868 INFO L93 Difference]: Finished difference Result 70672 states and 101530 transitions. [2023-11-21 22:09:50,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70672 states and 101530 transitions. [2023-11-21 22:09:51,272 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 70192 [2023-11-21 22:09:51,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70672 states to 70672 states and 101530 transitions. [2023-11-21 22:09:51,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70672 [2023-11-21 22:09:51,601 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70672 [2023-11-21 22:09:51,601 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70672 states and 101530 transitions. [2023-11-21 22:09:51,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:51,783 INFO L218 hiAutomatonCegarLoop]: Abstraction has 70672 states and 101530 transitions. [2023-11-21 22:09:51,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70672 states and 101530 transitions. [2023-11-21 22:09:52,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70672 to 28147. [2023-11-21 22:09:52,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28147 states, 28147 states have (on average 1.436955981099229) internal successors, (40446), 28146 states have internal predecessors, (40446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:52,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28147 states to 28147 states and 40446 transitions. [2023-11-21 22:09:52,428 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28147 states and 40446 transitions. [2023-11-21 22:09:52,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-21 22:09:52,429 INFO L428 stractBuchiCegarLoop]: Abstraction has 28147 states and 40446 transitions. [2023-11-21 22:09:52,430 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-21 22:09:52,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28147 states and 40446 transitions. [2023-11-21 22:09:52,519 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27904 [2023-11-21 22:09:52,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:52,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:52,523 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:52,523 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:52,524 INFO L748 eck$LassoCheckResult]: Stem: 246971#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 246972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 247990#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 247991#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 248916#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 248917#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 247483#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 247484#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 247530#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 248425#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 248426#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 248564#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 248565#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 247286#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 247287#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 248618#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 247836#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 247837#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 248495#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 248884#L1286 assume !(0 == ~M_E~0); 248704#L1286-2 assume !(0 == ~T1_E~0); 247189#L1291-1 assume !(0 == ~T2_E~0); 247190#L1296-1 assume !(0 == ~T3_E~0); 247945#L1301-1 assume !(0 == ~T4_E~0); 247946#L1306-1 assume !(0 == ~T5_E~0); 248504#L1311-1 assume !(0 == ~T6_E~0); 247144#L1316-1 assume !(0 == ~T7_E~0); 247145#L1321-1 assume !(0 == ~T8_E~0); 247968#L1326-1 assume !(0 == ~T9_E~0); 246956#L1331-1 assume !(0 == ~T10_E~0); 246666#L1336-1 assume !(0 == ~T11_E~0); 246667#L1341-1 assume !(0 == ~T12_E~0); 246716#L1346-1 assume !(0 == ~T13_E~0); 246717#L1351-1 assume !(0 == ~E_M~0); 247081#L1356-1 assume !(0 == ~E_1~0); 247082#L1361-1 assume !(0 == ~E_2~0); 248815#L1366-1 assume !(0 == ~E_3~0); 247131#L1371-1 assume !(0 == ~E_4~0); 247132#L1376-1 assume !(0 == ~E_5~0); 248029#L1381-1 assume !(0 == ~E_6~0); 248030#L1386-1 assume !(0 == ~E_7~0); 248864#L1391-1 assume !(0 == ~E_8~0); 248897#L1396-1 assume !(0 == ~E_9~0); 247884#L1401-1 assume !(0 == ~E_10~0); 247885#L1406-1 assume !(0 == ~E_11~0); 248213#L1411-1 assume !(0 == ~E_12~0); 248214#L1416-1 assume !(0 == ~E_13~0); 247786#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247634#L635 assume !(1 == ~m_pc~0); 246736#L635-2 is_master_triggered_~__retres1~0#1 := 0; 246737#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247075#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247789#L1598 assume !(0 != activate_threads_~tmp~1#1); 246910#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 246911#L654 assume !(1 == ~t1_pc~0); 247741#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 248621#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 248350#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 247739#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 247740#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 246959#L673 assume !(1 == ~t2_pc~0); 246961#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 248180#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247161#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 247162#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 248936#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247818#L692 assume !(1 == ~t3_pc~0); 247636#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 247637#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 248889#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 247453#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 247454#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 246987#L711 assume 1 == ~t4_pc~0; 246988#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 247500#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 246786#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 246691#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 246692#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 248915#L730 assume !(1 == ~t5_pc~0); 248113#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 246869#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 246870#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 246997#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 246998#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 247353#L749 assume 1 == ~t6_pc~0; 247106#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 246872#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247146#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 247147#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 247568#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246671#L768 assume !(1 == ~t7_pc~0); 246672#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 248052#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 248667#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 248651#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 248073#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 247148#L787 assume 1 == ~t8_pc~0; 247149#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 248447#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 248786#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 248787#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 246714#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 246715#L806 assume 1 == ~t9_pc~0; 248458#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 246749#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 246750#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 246999#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 247000#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 248436#L825 assume !(1 == ~t10_pc~0); 248437#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 248016#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 248017#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 247076#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 247077#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 247707#L844 assume 1 == ~t11_pc~0; 247376#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 247377#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 248559#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 248490#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 248421#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 248422#L863 assume !(1 == ~t12_pc~0); 246852#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 246851#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 246732#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 246733#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 248530#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 247832#L882 assume 1 == ~t13_pc~0; 247833#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 248154#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 248686#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 248496#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 248142#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 248143#L1434 assume !(1 == ~M_E~0); 248777#L1434-2 assume !(1 == ~T1_E~0); 248924#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 248925#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 248217#L1449-1 assume !(1 == ~T4_E~0); 248218#L1454-1 assume !(1 == ~T5_E~0); 248729#L1459-1 assume !(1 == ~T6_E~0); 248730#L1464-1 assume !(1 == ~T7_E~0); 248155#L1469-1 assume !(1 == ~T8_E~0); 248156#L1474-1 assume !(1 == ~T9_E~0); 257866#L1479-1 assume !(1 == ~T10_E~0); 257864#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 257861#L1489-1 assume !(1 == ~T12_E~0); 257857#L1494-1 assume !(1 == ~T13_E~0); 257851#L1499-1 assume !(1 == ~E_M~0); 257726#L1504-1 assume !(1 == ~E_1~0); 257711#L1509-1 assume !(1 == ~E_2~0); 257709#L1514-1 assume !(1 == ~E_3~0); 257707#L1519-1 assume !(1 == ~E_4~0); 257704#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 257702#L1529-1 assume !(1 == ~E_6~0); 257700#L1534-1 assume !(1 == ~E_7~0); 257665#L1539-1 assume !(1 == ~E_8~0); 257659#L1544-1 assume !(1 == ~E_9~0); 257642#L1549-1 assume !(1 == ~E_10~0); 248797#L1554-1 assume !(1 == ~E_11~0); 257621#L1559-1 assume !(1 == ~E_12~0); 257610#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 257602#L1569-1 assume { :end_inline_reset_delta_events } true; 257597#L1935-2 [2023-11-21 22:09:52,525 INFO L750 eck$LassoCheckResult]: Loop: 257597#L1935-2 assume !false; 257592#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 257590#L1261-1 assume !false; 257589#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 257582#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 257574#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 257572#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 257569#L1074 assume !(0 != eval_~tmp~0#1); 257570#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 258425#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 258424#L1286-3 assume !(0 == ~M_E~0); 258423#L1286-5 assume !(0 == ~T1_E~0); 258422#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 258421#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 258420#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 258419#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 258418#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 258417#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 258416#L1321-3 assume !(0 == ~T8_E~0); 258415#L1326-3 assume !(0 == ~T9_E~0); 258414#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 258413#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 258412#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 258411#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 258410#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 258409#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 258408#L1361-3 assume !(0 == ~E_2~0); 258407#L1366-3 assume !(0 == ~E_3~0); 258406#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 258405#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 258404#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 258403#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 258402#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 258401#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 258400#L1401-3 assume !(0 == ~E_10~0); 258399#L1406-3 assume !(0 == ~E_11~0); 258398#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 258397#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 258396#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 258395#L635-45 assume !(1 == ~m_pc~0); 258394#L635-47 is_master_triggered_~__retres1~0#1 := 0; 258392#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 258391#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 258390#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 258389#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 258388#L654-45 assume !(1 == ~t1_pc~0); 258387#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 258386#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 258385#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 258384#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 258383#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 258382#L673-45 assume !(1 == ~t2_pc~0); 258380#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 258379#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 258378#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 258377#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 258376#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 258375#L692-45 assume !(1 == ~t3_pc~0); 258374#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 258372#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 258370#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 258368#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 258365#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 258363#L711-45 assume !(1 == ~t4_pc~0); 258361#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 258358#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 258356#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 258353#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 258351#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 258349#L730-45 assume !(1 == ~t5_pc~0); 258347#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 258344#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 258342#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 258339#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 258337#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 258335#L749-45 assume !(1 == ~t6_pc~0); 258333#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 258330#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 258328#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 258325#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 258323#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 258321#L768-45 assume !(1 == ~t7_pc~0); 258319#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 258316#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 258314#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 258311#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 258309#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 258307#L787-45 assume 1 == ~t8_pc~0; 258305#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 258302#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 258300#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 258297#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 258295#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 258293#L806-45 assume !(1 == ~t9_pc~0); 258291#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 258288#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 258286#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 258283#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 258281#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 258279#L825-45 assume 1 == ~t10_pc~0; 258277#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 258274#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 258272#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 258269#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 258267#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 258265#L844-45 assume !(1 == ~t11_pc~0); 258263#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 258260#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 258258#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 258255#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 258253#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 258251#L863-45 assume 1 == ~t12_pc~0; 258249#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 258246#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 258244#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 258241#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 258239#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 258237#L882-45 assume !(1 == ~t13_pc~0); 258235#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 258233#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 258232#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 258231#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 257994#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 257992#L1434-3 assume !(1 == ~M_E~0); 250127#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 257989#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 248360#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 257986#L1449-3 assume !(1 == ~T4_E~0); 257984#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 257982#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 257980#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 257978#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 248681#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 257974#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 257972#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 257970#L1489-3 assume !(1 == ~T12_E~0); 257968#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 257869#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 257868#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 257867#L1509-3 assume !(1 == ~E_2~0); 257865#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 257863#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 257860#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 257856#L1529-3 assume !(1 == ~E_6~0); 257850#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 257847#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 257843#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 257739#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 257733#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 257731#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 257729#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 257727#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 257712#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 257710#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 257708#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 257706#L1954 assume !(0 == start_simulation_~tmp~3#1); 257703#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 257666#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 257660#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 257643#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 257631#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 257622#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 257611#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 257603#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 257597#L1935-2 [2023-11-21 22:09:52,525 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:52,526 INFO L85 PathProgramCache]: Analyzing trace with hash 309789955, now seen corresponding path program 1 times [2023-11-21 22:09:52,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:52,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541291045] [2023-11-21 22:09:52,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:52,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:52,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:52,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:52,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:52,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [541291045] [2023-11-21 22:09:52,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [541291045] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:52,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:52,610 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:09:52,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705798116] [2023-11-21 22:09:52,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:52,611 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:52,612 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:52,612 INFO L85 PathProgramCache]: Analyzing trace with hash -2017508223, now seen corresponding path program 1 times [2023-11-21 22:09:52,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:52,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118796554] [2023-11-21 22:09:52,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:52,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:52,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:52,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:52,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:52,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1118796554] [2023-11-21 22:09:52,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1118796554] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:52,684 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:52,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:52,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455064417] [2023-11-21 22:09:52,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:52,685 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:52,685 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:52,685 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:52,686 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:52,686 INFO L87 Difference]: Start difference. First operand 28147 states and 40446 transitions. cyclomatic complexity: 12307 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:53,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:53,194 INFO L93 Difference]: Finished difference Result 54194 states and 77567 transitions. [2023-11-21 22:09:53,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54194 states and 77567 transitions. [2023-11-21 22:09:53,608 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53904 [2023-11-21 22:09:53,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54194 states to 54194 states and 77567 transitions. [2023-11-21 22:09:53,790 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54194 [2023-11-21 22:09:53,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54194 [2023-11-21 22:09:53,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54194 states and 77567 transitions. [2023-11-21 22:09:54,004 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:54,004 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54194 states and 77567 transitions. [2023-11-21 22:09:54,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54194 states and 77567 transitions. [2023-11-21 22:09:54,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54194 to 54162. [2023-11-21 22:09:55,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54162 states, 54162 states have (on average 1.431538717181788) internal successors, (77535), 54161 states have internal predecessors, (77535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:55,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54162 states to 54162 states and 77535 transitions. [2023-11-21 22:09:55,202 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54162 states and 77535 transitions. [2023-11-21 22:09:55,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:55,203 INFO L428 stractBuchiCegarLoop]: Abstraction has 54162 states and 77535 transitions. [2023-11-21 22:09:55,203 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-21 22:09:55,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54162 states and 77535 transitions. [2023-11-21 22:09:55,413 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53872 [2023-11-21 22:09:55,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:09:55,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:09:55,419 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:55,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:09:55,420 INFO L748 eck$LassoCheckResult]: Stem: 329320#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 329321#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 330337#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 330338#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 331250#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 331251#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 329836#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 329837#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 329883#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 330766#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 330767#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 330914#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 330915#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 329638#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 329639#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 330977#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 330193#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 330194#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 330834#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 331220#L1286 assume !(0 == ~M_E~0); 331063#L1286-2 assume !(0 == ~T1_E~0); 329540#L1291-1 assume !(0 == ~T2_E~0); 329541#L1296-1 assume !(0 == ~T3_E~0); 330294#L1301-1 assume !(0 == ~T4_E~0); 330295#L1306-1 assume !(0 == ~T5_E~0); 330850#L1311-1 assume !(0 == ~T6_E~0); 329495#L1316-1 assume !(0 == ~T7_E~0); 329496#L1321-1 assume !(0 == ~T8_E~0); 330315#L1326-1 assume !(0 == ~T9_E~0); 329305#L1331-1 assume !(0 == ~T10_E~0); 329014#L1336-1 assume !(0 == ~T11_E~0); 329015#L1341-1 assume !(0 == ~T12_E~0); 329064#L1346-1 assume !(0 == ~T13_E~0); 329065#L1351-1 assume !(0 == ~E_M~0); 329431#L1356-1 assume !(0 == ~E_1~0); 329432#L1361-1 assume !(0 == ~E_2~0); 331162#L1366-1 assume !(0 == ~E_3~0); 329482#L1371-1 assume !(0 == ~E_4~0); 329483#L1376-1 assume !(0 == ~E_5~0); 330374#L1381-1 assume !(0 == ~E_6~0); 330375#L1386-1 assume !(0 == ~E_7~0); 331203#L1391-1 assume !(0 == ~E_8~0); 331234#L1396-1 assume !(0 == ~E_9~0); 330239#L1401-1 assume !(0 == ~E_10~0); 330240#L1406-1 assume !(0 == ~E_11~0); 330555#L1411-1 assume !(0 == ~E_12~0); 330556#L1416-1 assume !(0 == ~E_13~0); 330140#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 329986#L635 assume !(1 == ~m_pc~0); 329084#L635-2 is_master_triggered_~__retres1~0#1 := 0; 329085#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 329425#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 330143#L1598 assume !(0 != activate_threads_~tmp~1#1); 329259#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 329260#L654 assume !(1 == ~t1_pc~0); 330095#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 330979#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 330685#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 330093#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 330094#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329308#L673 assume !(1 == ~t2_pc~0); 329310#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 330522#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 329512#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 329513#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 331271#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 330174#L692 assume !(1 == ~t3_pc~0); 329988#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 329989#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 330667#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 329805#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 329806#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 329337#L711 assume !(1 == ~t4_pc~0); 329338#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 330968#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 329135#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 329039#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 329040#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 331249#L730 assume !(1 == ~t5_pc~0); 330457#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 329219#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 329220#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 329346#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 329347#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 329705#L749 assume 1 == ~t6_pc~0; 329456#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 329222#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 329497#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 329498#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 329921#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 329019#L768 assume !(1 == ~t7_pc~0); 329020#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 330397#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 331024#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 331005#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 330419#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 329499#L787 assume 1 == ~t8_pc~0; 329500#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 330785#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 331141#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 331142#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 329062#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 329063#L806 assume 1 == ~t9_pc~0; 330796#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 329097#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 329098#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 329348#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 329349#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 330776#L825 assume !(1 == ~t10_pc~0); 330777#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 330361#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 330362#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 329426#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 329427#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 330060#L844 assume 1 == ~t11_pc~0; 329728#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 329729#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 330907#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 330829#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 330762#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 330763#L863 assume !(1 == ~t12_pc~0); 329202#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 329201#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 329080#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 329081#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 330877#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 330189#L882 assume 1 == ~t13_pc~0; 330190#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 330496#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 331042#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 330837#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 330484#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 330485#L1434 assume !(1 == ~M_E~0); 331135#L1434-2 assume !(1 == ~T1_E~0); 331262#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 329328#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 329329#L1449-1 assume !(1 == ~T4_E~0); 330558#L1454-1 assume !(1 == ~T5_E~0); 338440#L1459-1 assume !(1 == ~T6_E~0); 338438#L1464-1 assume !(1 == ~T7_E~0); 330497#L1469-1 assume !(1 == ~T8_E~0); 330498#L1474-1 assume !(1 == ~T9_E~0); 330141#L1479-1 assume !(1 == ~T10_E~0); 330142#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 330426#L1489-1 assume !(1 == ~T12_E~0); 330018#L1494-1 assume !(1 == ~T13_E~0); 330019#L1499-1 assume !(1 == ~E_M~0); 338441#L1504-1 assume !(1 == ~E_1~0); 338439#L1509-1 assume !(1 == ~E_2~0); 338437#L1514-1 assume !(1 == ~E_3~0); 338436#L1519-1 assume !(1 == ~E_4~0); 338434#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 338432#L1529-1 assume !(1 == ~E_6~0); 331225#L1534-1 assume !(1 == ~E_7~0); 329117#L1539-1 assume !(1 == ~E_8~0); 329118#L1544-1 assume !(1 == ~E_9~0); 329563#L1549-1 assume !(1 == ~E_10~0); 331148#L1554-1 assume !(1 == ~E_11~0); 331146#L1559-1 assume !(1 == ~E_12~0); 330952#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 330953#L1569-1 assume { :end_inline_reset_delta_events } true; 331175#L1935-2 [2023-11-21 22:09:55,420 INFO L750 eck$LassoCheckResult]: Loop: 331175#L1935-2 assume !false; 347460#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 347457#L1261-1 assume !false; 347000#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 345017#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 345009#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 345008#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 345006#L1074 assume !(0 != eval_~tmp~0#1); 344991#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 344989#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 344987#L1286-3 assume !(0 == ~M_E~0); 344984#L1286-5 assume !(0 == ~T1_E~0); 344982#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 344980#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 344978#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 344976#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 344974#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 344972#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 344970#L1321-3 assume !(0 == ~T8_E~0); 344968#L1326-3 assume !(0 == ~T9_E~0); 344966#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 344964#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 344962#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 344960#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 344958#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 344956#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 344954#L1361-3 assume !(0 == ~E_2~0); 344952#L1366-3 assume !(0 == ~E_3~0); 344950#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 344948#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 344946#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 344944#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 344942#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 344940#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 344938#L1401-3 assume !(0 == ~E_10~0); 344936#L1406-3 assume !(0 == ~E_11~0); 344934#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 344932#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 344930#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 344928#L635-45 assume 1 == ~m_pc~0; 344925#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 344923#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 344921#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 344919#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 344918#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 344915#L654-45 assume !(1 == ~t1_pc~0); 344913#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 344911#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 344909#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 344907#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 344905#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 344903#L673-45 assume !(1 == ~t2_pc~0); 344900#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 344898#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 344896#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 344894#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 344891#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 344889#L692-45 assume !(1 == ~t3_pc~0); 344887#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 346997#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 346996#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 344871#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 344868#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 344866#L711-45 assume !(1 == ~t4_pc~0); 344864#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 344862#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 344860#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 344858#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 344856#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 344854#L730-45 assume !(1 == ~t5_pc~0); 344851#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 344848#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 344846#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 344844#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 344842#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 344840#L749-45 assume !(1 == ~t6_pc~0); 344837#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 344834#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 344832#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 344830#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 344828#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 344826#L768-45 assume !(1 == ~t7_pc~0); 344823#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 344820#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 344818#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 344816#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 344814#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 344812#L787-45 assume 1 == ~t8_pc~0; 344809#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 344806#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 344804#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 344802#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 344800#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 344798#L806-45 assume !(1 == ~t9_pc~0); 344795#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 344792#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 344790#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 344788#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 344786#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 344784#L825-45 assume 1 == ~t10_pc~0; 344781#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 344778#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 344776#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 344774#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 344772#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 344770#L844-45 assume !(1 == ~t11_pc~0); 344767#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 344764#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 344762#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 344760#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 344758#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 344756#L863-45 assume 1 == ~t12_pc~0; 344753#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 344750#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 344748#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 344746#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 344744#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 344742#L882-45 assume !(1 == ~t13_pc~0); 344739#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 344736#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 344734#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 344732#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 344730#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 344728#L1434-3 assume !(1 == ~M_E~0); 342813#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 344727#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 336989#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 344723#L1449-3 assume !(1 == ~T4_E~0); 344721#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 344719#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 344717#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 344716#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 344713#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 344712#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 344711#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 344710#L1489-3 assume !(1 == ~T12_E~0); 344709#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 344708#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 344707#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 344705#L1509-3 assume !(1 == ~E_2~0); 344702#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 344700#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 344698#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 344696#L1529-3 assume !(1 == ~E_6~0); 344694#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 344692#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 344690#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 344688#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 336939#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 344685#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 344683#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 344680#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 344546#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 344544#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 344542#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 344539#L1954 assume !(0 == start_simulation_~tmp~3#1); 344540#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 349838#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 349836#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 349834#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 349832#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 349830#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 349827#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 349825#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 331175#L1935-2 [2023-11-21 22:09:55,421 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:55,422 INFO L85 PathProgramCache]: Analyzing trace with hash -1076891324, now seen corresponding path program 1 times [2023-11-21 22:09:55,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:55,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617841631] [2023-11-21 22:09:55,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:55,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:55,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:55,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:55,514 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:55,514 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1617841631] [2023-11-21 22:09:55,515 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1617841631] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:55,515 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:55,515 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:09:55,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [575743913] [2023-11-21 22:09:55,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:55,516 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:09:55,516 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:09:55,517 INFO L85 PathProgramCache]: Analyzing trace with hash -238050112, now seen corresponding path program 1 times [2023-11-21 22:09:55,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:09:55,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765835539] [2023-11-21 22:09:55,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:09:55,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:09:55,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:09:55,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:09:55,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:09:55,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765835539] [2023-11-21 22:09:55,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765835539] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:09:55,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:09:55,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:09:55,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22795660] [2023-11-21 22:09:55,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:09:55,607 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:09:55,608 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:09:55,608 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:09:55,608 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:09:55,609 INFO L87 Difference]: Start difference. First operand 54162 states and 77535 transitions. cyclomatic complexity: 23389 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:56,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:09:56,190 INFO L93 Difference]: Finished difference Result 104385 states and 148884 transitions. [2023-11-21 22:09:56,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104385 states and 148884 transitions. [2023-11-21 22:09:57,089 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 103968 [2023-11-21 22:09:57,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104385 states to 104385 states and 148884 transitions. [2023-11-21 22:09:57,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 104385 [2023-11-21 22:09:57,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 104385 [2023-11-21 22:09:57,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104385 states and 148884 transitions. [2023-11-21 22:09:57,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:09:57,660 INFO L218 hiAutomatonCegarLoop]: Abstraction has 104385 states and 148884 transitions. [2023-11-21 22:09:57,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104385 states and 148884 transitions. [2023-11-21 22:09:59,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104385 to 104321. [2023-11-21 22:09:59,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104321 states, 104321 states have (on average 1.4265584110581762) internal successors, (148820), 104320 states have internal predecessors, (148820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:09:59,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104321 states to 104321 states and 148820 transitions. [2023-11-21 22:09:59,743 INFO L240 hiAutomatonCegarLoop]: Abstraction has 104321 states and 148820 transitions. [2023-11-21 22:09:59,744 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:09:59,744 INFO L428 stractBuchiCegarLoop]: Abstraction has 104321 states and 148820 transitions. [2023-11-21 22:09:59,745 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-21 22:09:59,745 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 104321 states and 148820 transitions. [2023-11-21 22:10:00,020 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 103904 [2023-11-21 22:10:00,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:00,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:00,026 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:00,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:00,027 INFO L748 eck$LassoCheckResult]: Stem: 487871#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 487872#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 488883#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 488884#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 489741#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 489742#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 488380#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 488381#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 488425#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 489287#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 489288#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 489438#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 489439#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 488185#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 488186#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 489492#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 488737#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 488738#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 489364#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 489722#L1286 assume !(0 == ~M_E~0); 489570#L1286-2 assume !(0 == ~T1_E~0); 488089#L1291-1 assume !(0 == ~T2_E~0); 488090#L1296-1 assume !(0 == ~T3_E~0); 488840#L1301-1 assume !(0 == ~T4_E~0); 488841#L1306-1 assume !(0 == ~T5_E~0); 489373#L1311-1 assume !(0 == ~T6_E~0); 488045#L1316-1 assume !(0 == ~T7_E~0); 488046#L1321-1 assume !(0 == ~T8_E~0); 488862#L1326-1 assume !(0 == ~T9_E~0); 487856#L1331-1 assume !(0 == ~T10_E~0); 487568#L1336-1 assume !(0 == ~T11_E~0); 487569#L1341-1 assume !(0 == ~T12_E~0); 487618#L1346-1 assume !(0 == ~T13_E~0); 487619#L1351-1 assume !(0 == ~E_M~0); 487982#L1356-1 assume !(0 == ~E_1~0); 487983#L1361-1 assume !(0 == ~E_2~0); 489669#L1366-1 assume !(0 == ~E_3~0); 488032#L1371-1 assume !(0 == ~E_4~0); 488033#L1376-1 assume !(0 == ~E_5~0); 488920#L1381-1 assume !(0 == ~E_6~0); 488921#L1386-1 assume !(0 == ~E_7~0); 489705#L1391-1 assume !(0 == ~E_8~0); 489729#L1396-1 assume !(0 == ~E_9~0); 488782#L1401-1 assume !(0 == ~E_10~0); 488783#L1406-1 assume !(0 == ~E_11~0); 489087#L1411-1 assume !(0 == ~E_12~0); 489088#L1416-1 assume !(0 == ~E_13~0); 488686#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488526#L635 assume !(1 == ~m_pc~0); 487638#L635-2 is_master_triggered_~__retres1~0#1 := 0; 487639#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 487976#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 488689#L1598 assume !(0 != activate_threads_~tmp~1#1); 487811#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 487812#L654 assume !(1 == ~t1_pc~0); 488637#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 489494#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 489211#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 488635#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 488636#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 487859#L673 assume !(1 == ~t2_pc~0); 487861#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 489058#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 488062#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 488063#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 489761#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 488719#L692 assume !(1 == ~t3_pc~0); 488528#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 488529#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 489196#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 488347#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 488348#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 487888#L711 assume !(1 == ~t4_pc~0); 487889#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 489483#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 487688#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 487593#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 487594#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 489740#L730 assume !(1 == ~t5_pc~0); 488998#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 487771#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 487772#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 487897#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 487898#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 488250#L749 assume !(1 == ~t6_pc~0); 487773#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 487774#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 488047#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 488048#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 488461#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 487573#L768 assume !(1 == ~t7_pc~0); 487574#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 488941#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 489539#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 489520#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 488961#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488049#L787 assume 1 == ~t8_pc~0; 488050#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 489310#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 489642#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 489643#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 487616#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 487617#L806 assume 1 == ~t9_pc~0; 489320#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 487651#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 487652#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 487899#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 487900#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 489298#L825 assume !(1 == ~t10_pc~0); 489299#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 488907#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 488908#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 487977#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 487978#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 488602#L844 assume 1 == ~t11_pc~0; 488273#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 488274#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 489431#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 489360#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 489283#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 489284#L863 assume !(1 == ~t12_pc~0); 487754#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 487753#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 487634#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 487635#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 489406#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 488733#L882 assume 1 == ~t13_pc~0; 488734#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 489035#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 489553#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 489365#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 489023#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 489024#L1434 assume !(1 == ~M_E~0); 489636#L1434-2 assume !(1 == ~T1_E~0); 489747#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 487879#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 487880#L1449-1 assume !(1 == ~T4_E~0); 488341#L1454-1 assume !(1 == ~T5_E~0); 488342#L1459-1 assume !(1 == ~T6_E~0); 488962#L1464-1 assume !(1 == ~T7_E~0); 488963#L1469-1 assume !(1 == ~T8_E~0); 489036#L1474-1 assume !(1 == ~T9_E~0); 531115#L1479-1 assume !(1 == ~T10_E~0); 531114#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 531074#L1489-1 assume !(1 == ~T12_E~0); 531064#L1494-1 assume !(1 == ~T13_E~0); 531056#L1499-1 assume !(1 == ~E_M~0); 531047#L1504-1 assume !(1 == ~E_1~0); 531042#L1509-1 assume !(1 == ~E_2~0); 530871#L1514-1 assume !(1 == ~E_3~0); 530697#L1519-1 assume !(1 == ~E_4~0); 530696#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 530695#L1529-1 assume !(1 == ~E_6~0); 530534#L1534-1 assume !(1 == ~E_7~0); 527482#L1539-1 assume !(1 == ~E_8~0); 488111#L1544-1 assume !(1 == ~E_9~0); 488112#L1549-1 assume !(1 == ~E_10~0); 489650#L1554-1 assume !(1 == ~E_11~0); 489648#L1559-1 assume !(1 == ~E_12~0); 489471#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 489472#L1569-1 assume { :end_inline_reset_delta_events } true; 489679#L1935-2 [2023-11-21 22:10:00,028 INFO L750 eck$LassoCheckResult]: Loop: 489679#L1935-2 assume !false; 528961#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 528958#L1261-1 assume !false; 528956#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 528939#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 528930#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 528928#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 528925#L1074 assume !(0 != eval_~tmp~0#1); 528922#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 528920#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 528918#L1286-3 assume !(0 == ~M_E~0); 528916#L1286-5 assume !(0 == ~T1_E~0); 528914#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 528912#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 528909#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 528907#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 528905#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 528903#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 528901#L1321-3 assume !(0 == ~T8_E~0); 528899#L1326-3 assume !(0 == ~T9_E~0); 528896#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 528894#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 528892#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 528890#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 528888#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 528886#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 528883#L1361-3 assume !(0 == ~E_2~0); 528881#L1366-3 assume !(0 == ~E_3~0); 528879#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 528877#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 528875#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 528873#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 528870#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 528868#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 528866#L1401-3 assume !(0 == ~E_10~0); 528864#L1406-3 assume !(0 == ~E_11~0); 528862#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 528860#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 528857#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 528855#L635-45 assume 1 == ~m_pc~0; 528852#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 528850#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 528848#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 528846#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 528843#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 528841#L654-45 assume !(1 == ~t1_pc~0); 528839#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 528837#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 528835#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 528833#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 528832#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 528829#L673-45 assume !(1 == ~t2_pc~0); 528827#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 528826#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 528825#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 528824#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 528823#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 528822#L692-45 assume !(1 == ~t3_pc~0); 528820#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 528818#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 528816#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 528815#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 528813#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 528812#L711-45 assume !(1 == ~t4_pc~0); 528811#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 528810#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 528809#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 528808#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 528807#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 528806#L730-45 assume 1 == ~t5_pc~0; 528804#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 528803#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 528802#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 528801#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 528799#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 528798#L749-45 assume !(1 == ~t6_pc~0); 528797#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 528796#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 528795#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 528794#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 528793#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 528792#L768-45 assume 1 == ~t7_pc~0; 528790#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 528789#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 528787#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 528784#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 528782#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 528780#L787-45 assume !(1 == ~t8_pc~0); 528777#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 528775#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 528773#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 528771#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 528769#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 528767#L806-45 assume 1 == ~t9_pc~0; 528764#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 528762#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 528759#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 528757#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 528755#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 528753#L825-45 assume !(1 == ~t10_pc~0); 528750#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 528748#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 528744#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 528742#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 528740#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 528738#L844-45 assume 1 == ~t11_pc~0; 528734#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 528732#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 528730#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 528728#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 528726#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 528724#L863-45 assume !(1 == ~t12_pc~0); 528721#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 528719#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 528717#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 528714#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 528712#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 528710#L882-45 assume 1 == ~t13_pc~0; 528707#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 528705#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 528703#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 528701#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 528699#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 528697#L1434-3 assume !(1 == ~M_E~0); 528325#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 528694#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 509661#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 528690#L1449-3 assume !(1 == ~T4_E~0); 528688#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 528686#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 528684#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 528682#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 511810#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 528678#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 528676#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 528674#L1489-3 assume !(1 == ~T12_E~0); 528672#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 528670#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 528668#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 528665#L1509-3 assume !(1 == ~E_2~0); 528663#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 528661#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 528659#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 528657#L1529-3 assume !(1 == ~E_6~0); 528655#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 528652#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 528650#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 528648#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 525617#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 528645#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 528643#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 528640#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 528608#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 528607#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 528603#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 528600#L1954 assume !(0 == start_simulation_~tmp~3#1); 528601#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 530010#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 530008#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 530006#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 530004#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 530002#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 530001#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 529997#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 489679#L1935-2 [2023-11-21 22:10:00,029 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:00,029 INFO L85 PathProgramCache]: Analyzing trace with hash 1375762181, now seen corresponding path program 1 times [2023-11-21 22:10:00,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:00,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864893432] [2023-11-21 22:10:00,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:00,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:00,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:00,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:00,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:00,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864893432] [2023-11-21 22:10:00,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864893432] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:00,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:00,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:10:00,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320883591] [2023-11-21 22:10:00,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:00,105 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:00,105 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:00,105 INFO L85 PathProgramCache]: Analyzing trace with hash 135851518, now seen corresponding path program 1 times [2023-11-21 22:10:00,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:00,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816459670] [2023-11-21 22:10:00,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:00,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:00,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:00,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:00,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:00,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816459670] [2023-11-21 22:10:00,174 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816459670] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:00,174 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:00,174 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:00,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [592316616] [2023-11-21 22:10:00,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:00,175 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:00,175 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:00,175 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:00,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:00,176 INFO L87 Difference]: Start difference. First operand 104321 states and 148820 transitions. cyclomatic complexity: 44531 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:01,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:01,584 INFO L93 Difference]: Finished difference Result 201056 states and 285825 transitions. [2023-11-21 22:10:01,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201056 states and 285825 transitions. [2023-11-21 22:10:03,019 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 200320 [2023-11-21 22:10:03,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201056 states to 201056 states and 285825 transitions. [2023-11-21 22:10:03,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201056 [2023-11-21 22:10:03,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201056 [2023-11-21 22:10:03,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201056 states and 285825 transitions. [2023-11-21 22:10:03,669 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:03,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201056 states and 285825 transitions. [2023-11-21 22:10:03,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201056 states and 285825 transitions. [2023-11-21 22:10:06,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201056 to 200928. [2023-11-21 22:10:06,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 200928 states, 200928 states have (on average 1.421887442267877) internal successors, (285697), 200927 states have internal predecessors, (285697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:06,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200928 states to 200928 states and 285697 transitions. [2023-11-21 22:10:06,851 INFO L240 hiAutomatonCegarLoop]: Abstraction has 200928 states and 285697 transitions. [2023-11-21 22:10:06,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-21 22:10:06,852 INFO L428 stractBuchiCegarLoop]: Abstraction has 200928 states and 285697 transitions. [2023-11-21 22:10:06,852 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-21 22:10:06,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 200928 states and 285697 transitions. [2023-11-21 22:10:08,182 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 200192 [2023-11-21 22:10:08,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-21 22:10:08,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-21 22:10:08,186 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:08,186 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-21 22:10:08,187 INFO L748 eck$LassoCheckResult]: Stem: 793256#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 793257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 794291#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 794292#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 795288#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 795289#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 793766#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 793767#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 793815#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 794744#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 794745#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 794893#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 794894#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 793568#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 793569#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 794955#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 794136#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 794137#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 794813#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 795260#L1286 assume !(0 == ~M_E~0); 795053#L1286-2 assume !(0 == ~T1_E~0); 793470#L1291-1 assume !(0 == ~T2_E~0); 793471#L1296-1 assume !(0 == ~T3_E~0); 794246#L1301-1 assume !(0 == ~T4_E~0); 794247#L1306-1 assume !(0 == ~T5_E~0); 794824#L1311-1 assume !(0 == ~T6_E~0); 793427#L1316-1 assume !(0 == ~T7_E~0); 793428#L1321-1 assume !(0 == ~T8_E~0); 794268#L1326-1 assume !(0 == ~T9_E~0); 793241#L1331-1 assume !(0 == ~T10_E~0); 792952#L1336-1 assume !(0 == ~T11_E~0); 792953#L1341-1 assume !(0 == ~T12_E~0); 793002#L1346-1 assume !(0 == ~T13_E~0); 793003#L1351-1 assume !(0 == ~E_M~0); 793366#L1356-1 assume !(0 == ~E_1~0); 793367#L1361-1 assume !(0 == ~E_2~0); 795178#L1366-1 assume !(0 == ~E_3~0); 793414#L1371-1 assume !(0 == ~E_4~0); 793415#L1376-1 assume !(0 == ~E_5~0); 794330#L1381-1 assume !(0 == ~E_6~0); 794331#L1386-1 assume !(0 == ~E_7~0); 795238#L1391-1 assume !(0 == ~E_8~0); 795271#L1396-1 assume !(0 == ~E_9~0); 794185#L1401-1 assume !(0 == ~E_10~0); 794186#L1406-1 assume !(0 == ~E_11~0); 794521#L1411-1 assume !(0 == ~E_12~0); 794522#L1416-1 assume !(0 == ~E_13~0); 794086#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 793916#L635 assume !(1 == ~m_pc~0); 793022#L635-2 is_master_triggered_~__retres1~0#1 := 0; 793023#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 793360#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 794089#L1598 assume !(0 != activate_threads_~tmp~1#1); 793195#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 793196#L654 assume !(1 == ~t1_pc~0); 794035#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 794957#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 794661#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 794033#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 794034#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 793244#L673 assume !(1 == ~t2_pc~0); 793246#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 794486#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 793443#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 793444#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 795316#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 794117#L692 assume !(1 == ~t3_pc~0); 793918#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 793919#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 794639#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 793735#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 793736#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 793273#L711 assume !(1 == ~t4_pc~0); 793274#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 794944#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 793072#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 792977#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 792978#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 795287#L730 assume !(1 == ~t5_pc~0); 794420#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 793155#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 793156#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 793282#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 793283#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 793637#L749 assume !(1 == ~t6_pc~0); 793157#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 793158#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 793431#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 793432#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 793853#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 792957#L768 assume !(1 == ~t7_pc~0); 792958#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 794356#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 795011#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 794994#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 794379#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 793429#L787 assume !(1 == ~t8_pc~0); 793430#L787-2 is_transmit8_triggered_~__retres1~8#1 := 0; 795073#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 795150#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 795151#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 793000#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 793001#L806 assume 1 == ~t9_pc~0; 794771#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 793035#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 793036#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 793284#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 793285#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 794754#L825 assume !(1 == ~t10_pc~0); 794755#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 794316#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 794317#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 793361#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 793362#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 793995#L844 assume 1 == ~t11_pc~0; 793660#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 793661#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 794888#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 794809#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 794740#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 794741#L863 assume !(1 == ~t12_pc~0); 793138#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 793137#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 793018#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 793019#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 794861#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 794132#L882 assume 1 == ~t13_pc~0; 794133#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 794462#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 795029#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 794814#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 794449#L1702-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 794450#L1434 assume !(1 == ~M_E~0); 795141#L1434-2 assume !(1 == ~T1_E~0); 795294#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 793264#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 793265#L1449-1 assume !(1 == ~T4_E~0); 793730#L1454-1 assume !(1 == ~T5_E~0); 793731#L1459-1 assume !(1 == ~T6_E~0); 794380#L1464-1 assume !(1 == ~T7_E~0); 794381#L1469-1 assume !(1 == ~T8_E~0); 794463#L1474-1 assume !(1 == ~T9_E~0); 794087#L1479-1 assume !(1 == ~T10_E~0); 794088#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 794388#L1489-1 assume !(1 == ~T12_E~0); 793948#L1494-1 assume !(1 == ~T13_E~0); 793949#L1499-1 assume !(1 == ~E_M~0); 794158#L1504-1 assume !(1 == ~E_1~0); 794159#L1509-1 assume !(1 == ~E_2~0); 794876#L1514-1 assume !(1 == ~E_3~0); 794497#L1519-1 assume !(1 == ~E_4~0); 794498#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 795201#L1529-1 assume !(1 == ~E_6~0); 795202#L1534-1 assume !(1 == ~E_7~0); 793055#L1539-1 assume !(1 == ~E_8~0); 793056#L1544-1 assume !(1 == ~E_9~0); 793494#L1549-1 assume !(1 == ~E_10~0); 795159#L1554-1 assume !(1 == ~E_11~0); 795157#L1559-1 assume !(1 == ~E_12~0); 794930#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 794931#L1569-1 assume { :end_inline_reset_delta_events } true; 795192#L1935-2 [2023-11-21 22:10:08,188 INFO L750 eck$LassoCheckResult]: Loop: 795192#L1935-2 assume !false; 821943#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 821938#L1261-1 assume !false; 821936#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 821850#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 821836#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 821830#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 821822#L1074 assume !(0 != eval_~tmp~0#1); 821823#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 823460#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 823458#L1286-3 assume !(0 == ~M_E~0); 823457#L1286-5 assume !(0 == ~T1_E~0); 823455#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 823453#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 823451#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 823450#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 823449#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 823448#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 823447#L1321-3 assume !(0 == ~T8_E~0); 823445#L1326-3 assume !(0 == ~T9_E~0); 823444#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 823441#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 823439#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 823437#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 823435#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 823433#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 823431#L1361-3 assume !(0 == ~E_2~0); 823429#L1366-3 assume !(0 == ~E_3~0); 823427#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 823425#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 823423#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 823421#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 823418#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 823416#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 823414#L1401-3 assume !(0 == ~E_10~0); 823412#L1406-3 assume !(0 == ~E_11~0); 823410#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 823408#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 823406#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 823386#L635-45 assume 1 == ~m_pc~0; 823378#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 823370#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 823362#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 823357#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 823351#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 823342#L654-45 assume !(1 == ~t1_pc~0); 823337#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 823332#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 823327#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 823322#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 823317#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 823310#L673-45 assume !(1 == ~t2_pc~0); 823302#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 823296#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 823290#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 823283#L1614-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 823276#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 823269#L692-45 assume 1 == ~t3_pc~0; 823262#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 823254#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 823246#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 823238#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 823232#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 823226#L711-45 assume !(1 == ~t4_pc~0); 823221#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 823215#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 823208#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 823202#L1630-45 assume !(0 != activate_threads_~tmp___3~0#1); 823195#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 823189#L730-45 assume 1 == ~t5_pc~0; 823182#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 823176#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 823171#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 823166#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 823160#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 823152#L749-45 assume !(1 == ~t6_pc~0); 823146#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 823139#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 823133#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 823126#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 823120#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 823114#L768-45 assume !(1 == ~t7_pc~0); 823108#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 823100#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 823093#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 823086#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 823077#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 823068#L787-45 assume !(1 == ~t8_pc~0); 823061#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 823054#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 823048#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 823042#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 823036#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 823029#L806-45 assume 1 == ~t9_pc~0; 823021#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 823013#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 823005#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 822999#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 822991#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 822982#L825-45 assume !(1 == ~t10_pc~0); 822974#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 822966#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 822959#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 822952#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 822945#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 822936#L844-45 assume 1 == ~t11_pc~0; 822928#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 822920#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 822912#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 822905#L1686-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 822896#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 822888#L863-45 assume !(1 == ~t12_pc~0); 822880#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 822872#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 822865#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 822858#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 822851#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 822841#L882-45 assume 1 == ~t13_pc~0; 822832#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 822823#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 822814#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 822807#L1702-45 assume !(0 != activate_threads_~tmp___12~0#1); 822799#L1702-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 822791#L1434-3 assume !(1 == ~M_E~0); 822783#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 822777#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 806356#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 822765#L1449-3 assume !(1 == ~T4_E~0); 822757#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 822749#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 822743#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 822738#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 817484#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 822726#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 822719#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 822712#L1489-3 assume !(1 == ~T12_E~0); 822706#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 822701#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 822694#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 822688#L1509-3 assume !(1 == ~E_2~0); 822681#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 822673#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 822667#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 822661#L1529-3 assume !(1 == ~E_6~0); 822654#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 822648#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 822641#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 822634#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 806301#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 822621#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 822615#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 822608#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 822398#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 822384#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 822375#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 822367#L1954 assume !(0 == start_simulation_~tmp~3#1); 822362#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 821996#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 821995#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 821991#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 821989#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 821987#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 821973#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 821961#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 795192#L1935-2 [2023-11-21 22:10:08,189 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:08,189 INFO L85 PathProgramCache]: Analyzing trace with hash 1753404998, now seen corresponding path program 1 times [2023-11-21 22:10:08,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:08,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428778885] [2023-11-21 22:10:08,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:08,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:08,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:08,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:08,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:08,289 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428778885] [2023-11-21 22:10:08,289 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428778885] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:08,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:08,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-21 22:10:08,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455130907] [2023-11-21 22:10:08,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:08,291 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-21 22:10:08,291 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-21 22:10:08,292 INFO L85 PathProgramCache]: Analyzing trace with hash -601963908, now seen corresponding path program 1 times [2023-11-21 22:10:08,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-21 22:10:08,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597796996] [2023-11-21 22:10:08,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-21 22:10:08,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-21 22:10:08,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-21 22:10:08,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-21 22:10:08,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-21 22:10:08,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597796996] [2023-11-21 22:10:08,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597796996] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-21 22:10:08,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-21 22:10:08,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-21 22:10:08,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [791142166] [2023-11-21 22:10:08,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-21 22:10:08,386 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-21 22:10:08,386 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-21 22:10:08,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-21 22:10:08,387 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-21 22:10:08,387 INFO L87 Difference]: Start difference. First operand 200928 states and 285697 transitions. cyclomatic complexity: 84833 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-21 22:10:10,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-21 22:10:10,638 INFO L93 Difference]: Finished difference Result 393439 states and 557150 transitions. [2023-11-21 22:10:10,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 393439 states and 557150 transitions. [2023-11-21 22:10:12,780 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 391936 [2023-11-21 22:10:13,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 393439 states to 393439 states and 557150 transitions. [2023-11-21 22:10:13,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 393439 [2023-11-21 22:10:13,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 393439 [2023-11-21 22:10:13,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 393439 states and 557150 transitions. [2023-11-21 22:10:13,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-21 22:10:13,909 INFO L218 hiAutomatonCegarLoop]: Abstraction has 393439 states and 557150 transitions. [2023-11-21 22:10:14,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393439 states and 557150 transitions. [2023-11-21 22:10:18,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393439 to 393183. [2023-11-21 22:10:18,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393183 states, 393183 states have (on average 1.4163735461604392) internal successors, (556894), 393182 states have internal predecessors, (556894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)