./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 30e01a73 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-30e01a7 [2023-11-23 21:36:39,946 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-23 21:36:40,062 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-23 21:36:40,073 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-23 21:36:40,075 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-23 21:36:40,117 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-23 21:36:40,118 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-23 21:36:40,118 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-23 21:36:40,119 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-23 21:36:40,124 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-23 21:36:40,126 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-23 21:36:40,126 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-23 21:36:40,127 INFO L153 SettingsManager]: * Use SBE=true [2023-11-23 21:36:40,129 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-23 21:36:40,130 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-23 21:36:40,130 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-23 21:36:40,130 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-23 21:36:40,131 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-23 21:36:40,131 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-23 21:36:40,132 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-23 21:36:40,132 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-23 21:36:40,133 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-23 21:36:40,133 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-23 21:36:40,134 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-23 21:36:40,134 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-23 21:36:40,134 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-23 21:36:40,135 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-23 21:36:40,135 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-23 21:36:40,136 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-23 21:36:40,136 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-23 21:36:40,137 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-23 21:36:40,138 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-23 21:36:40,138 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-23 21:36:40,138 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-23 21:36:40,139 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-23 21:36:40,139 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-23 21:36:40,139 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-23 21:36:40,140 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-23 21:36:40,140 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 [2023-11-23 21:36:40,450 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-23 21:36:40,484 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-23 21:36:40,487 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-23 21:36:40,488 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-23 21:36:40,489 INFO L274 PluginConnector]: CDTParser initialized [2023-11-23 21:36:40,490 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2023-11-23 21:36:43,598 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-23 21:36:43,858 INFO L384 CDTParser]: Found 1 translation units. [2023-11-23 21:36:43,859 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2023-11-23 21:36:43,875 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/data/16491f523/bb96aab64729441584d4bc092b689136/FLAGc8242fb80 [2023-11-23 21:36:43,890 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/data/16491f523/bb96aab64729441584d4bc092b689136 [2023-11-23 21:36:43,893 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-23 21:36:43,895 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-23 21:36:43,897 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-23 21:36:43,897 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-23 21:36:43,905 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-23 21:36:43,906 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 09:36:43" (1/1) ... [2023-11-23 21:36:43,907 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3bd2ff92 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:43, skipping insertion in model container [2023-11-23 21:36:43,907 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 09:36:43" (1/1) ... [2023-11-23 21:36:43,990 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-23 21:36:44,255 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-23 21:36:44,272 INFO L202 MainTranslator]: Completed pre-run [2023-11-23 21:36:44,348 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-23 21:36:44,371 INFO L206 MainTranslator]: Completed translation [2023-11-23 21:36:44,372 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44 WrapperNode [2023-11-23 21:36:44,372 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-23 21:36:44,373 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-23 21:36:44,373 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-23 21:36:44,374 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-23 21:36:44,381 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,396 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,511 INFO L138 Inliner]: procedures = 44, calls = 56, calls flagged for inlining = 51, calls inlined = 158, statements flattened = 2377 [2023-11-23 21:36:44,512 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-23 21:36:44,513 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-23 21:36:44,513 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-23 21:36:44,513 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-23 21:36:44,525 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,526 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,538 INFO L184 PluginConnector]: Executing the observer HeapSplitter from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,601 INFO L189 HeapSplitter]: Split 2 memory accesses to 1 slices as follows [2] [2023-11-23 21:36:44,602 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,602 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,647 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,706 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,710 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,719 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,741 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-23 21:36:44,746 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-23 21:36:44,746 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-23 21:36:44,747 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-23 21:36:44,747 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (1/1) ... [2023-11-23 21:36:44,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-23 21:36:44,766 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/z3 [2023-11-23 21:36:44,778 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-23 21:36:44,804 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e7f7af69-37db-4071-a3f3-8b6d0b6e064b/bin/uautomizer-verify-zZY32mL2XJ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-23 21:36:44,829 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-23 21:36:44,830 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-23 21:36:44,830 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-23 21:36:44,830 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-23 21:36:44,966 INFO L241 CfgBuilder]: Building ICFG [2023-11-23 21:36:44,968 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-23 21:36:46,731 INFO L282 CfgBuilder]: Performing block encoding [2023-11-23 21:36:46,771 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-23 21:36:46,771 INFO L309 CfgBuilder]: Removed 11 assume(true) statements. [2023-11-23 21:36:46,774 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 09:36:46 BoogieIcfgContainer [2023-11-23 21:36:46,774 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-23 21:36:46,775 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-23 21:36:46,775 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-23 21:36:46,779 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-23 21:36:46,780 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-23 21:36:46,781 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 09:36:43" (1/3) ... [2023-11-23 21:36:46,782 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@304a3cb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 09:36:46, skipping insertion in model container [2023-11-23 21:36:46,782 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-23 21:36:46,783 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:36:44" (2/3) ... [2023-11-23 21:36:46,786 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@304a3cb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 09:36:46, skipping insertion in model container [2023-11-23 21:36:46,787 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-23 21:36:46,787 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 09:36:46" (3/3) ... [2023-11-23 21:36:46,788 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-1.c [2023-11-23 21:36:46,866 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-23 21:36:46,866 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-23 21:36:46,866 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-23 21:36:46,866 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-23 21:36:46,866 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-23 21:36:46,867 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-23 21:36:46,867 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-23 21:36:46,867 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-23 21:36:46,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:46,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2023-11-23 21:36:46,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:46,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:46,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:46,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:46,975 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-23 21:36:46,977 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:46,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2023-11-23 21:36:46,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:46,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:47,000 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:47,000 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:47,011 INFO L748 eck$LassoCheckResult]: Stem: 155#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 920#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 743#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 916#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 867#L597true assume !(1 == ~m_i~0);~m_st~0 := 2; 447#L597-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 987#L602-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 163#L607-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 494#L612-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 129#L617-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 284#L622-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 970#L627-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 265#L632-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 567#L637-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 504#L854true assume !(0 == ~M_E~0); 332#L854-2true assume !(0 == ~T1_E~0); 639#L859-1true assume !(0 == ~T2_E~0); 68#L864-1true assume !(0 == ~T3_E~0); 123#L869-1true assume !(0 == ~T4_E~0); 877#L874-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 815#L879-1true assume !(0 == ~T6_E~0); 325#L884-1true assume !(0 == ~T7_E~0); 8#L889-1true assume !(0 == ~T8_E~0); 171#L894-1true assume !(0 == ~E_M~0); 981#L899-1true assume !(0 == ~E_1~0); 509#L904-1true assume !(0 == ~E_2~0); 277#L909-1true assume !(0 == ~E_3~0); 438#L914-1true assume 0 == ~E_4~0;~E_4~0 := 1; 463#L919-1true assume !(0 == ~E_5~0); 218#L924-1true assume !(0 == ~E_6~0); 115#L929-1true assume !(0 == ~E_7~0); 834#L934-1true assume !(0 == ~E_8~0); 263#L939-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16#L418true assume !(1 == ~m_pc~0); 903#L418-2true is_master_triggered_~__retres1~0#1 := 0; 717#L429true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 642#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 626#L1061true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 532#L1061-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 890#L437true assume 1 == ~t1_pc~0; 974#L438true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 632#L448true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 188#L1069true assume !(0 != activate_threads_~tmp___0~0#1); 826#L1069-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 617#L456true assume !(1 == ~t2_pc~0); 436#L456-2true is_transmit2_triggered_~__retres1~2#1 := 0; 882#L467true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 240#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 661#L1077true assume !(0 != activate_threads_~tmp___1~0#1); 358#L1077-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66#L475true assume 1 == ~t3_pc~0; 298#L476true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 97#L486true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 797#L1085true assume !(0 != activate_threads_~tmp___2~0#1); 190#L1085-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 713#L494true assume !(1 == ~t4_pc~0); 214#L494-2true is_transmit4_triggered_~__retres1~4#1 := 0; 417#L505true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 953#L1093true assume !(0 != activate_threads_~tmp___3~0#1); 460#L1093-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95#L513true assume 1 == ~t5_pc~0; 584#L514true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 911#L524true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 645#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71#L1101true assume !(0 != activate_threads_~tmp___4~0#1); 895#L1101-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51#L532true assume !(1 == ~t6_pc~0); 407#L532-2true is_transmit6_triggered_~__retres1~6#1 := 0; 303#L543true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 227#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 849#L1109true assume !(0 != activate_threads_~tmp___5~0#1); 175#L1109-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 665#L551true assume 1 == ~t7_pc~0; 675#L552true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 465#L562true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 934#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1007#L1117true assume !(0 != activate_threads_~tmp___6~0#1); 945#L1117-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 292#L570true assume 1 == ~t8_pc~0; 379#L571true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 749#L581true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 585#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 376#L1125true assume !(0 != activate_threads_~tmp___7~0#1); 63#L1125-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 636#L952true assume 1 == ~M_E~0;~M_E~0 := 2; 38#L952-2true assume !(1 == ~T1_E~0); 597#L957-1true assume !(1 == ~T2_E~0); 899#L962-1true assume !(1 == ~T3_E~0); 391#L967-1true assume !(1 == ~T4_E~0); 869#L972-1true assume !(1 == ~T5_E~0); 668#L977-1true assume !(1 == ~T6_E~0); 950#L982-1true assume !(1 == ~T7_E~0); 126#L987-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 130#L992-1true assume !(1 == ~E_M~0); 356#L997-1true assume !(1 == ~E_1~0); 821#L1002-1true assume !(1 == ~E_2~0); 346#L1007-1true assume !(1 == ~E_3~0); 9#L1012-1true assume !(1 == ~E_4~0); 564#L1017-1true assume !(1 == ~E_5~0); 349#L1022-1true assume !(1 == ~E_6~0); 370#L1027-1true assume 1 == ~E_7~0;~E_7~0 := 2; 823#L1032-1true assume !(1 == ~E_8~0); 487#L1037-1true assume { :end_inline_reset_delta_events } true; 588#L1303-2true [2023-11-23 21:36:47,014 INFO L750 eck$LassoCheckResult]: Loop: 588#L1303-2true assume !false; 627#L1304true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 982#L829-1true assume !true; 589#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 375#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 475#L854-3true assume !(0 == ~M_E~0); 453#L854-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 965#L859-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 926#L864-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 809#L869-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 304#L874-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 357#L879-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 390#L884-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 342#L889-3true assume !(0 == ~T8_E~0); 110#L894-3true assume 0 == ~E_M~0;~E_M~0 := 1; 499#L899-3true assume 0 == ~E_1~0;~E_1~0 := 1; 128#L904-3true assume 0 == ~E_2~0;~E_2~0 := 1; 323#L909-3true assume 0 == ~E_3~0;~E_3~0 := 1; 100#L914-3true assume 0 == ~E_4~0;~E_4~0 := 1; 121#L919-3true assume 0 == ~E_5~0;~E_5~0 := 1; 730#L924-3true assume 0 == ~E_6~0;~E_6~0 := 1; 537#L929-3true assume !(0 == ~E_7~0); 440#L934-3true assume 0 == ~E_8~0;~E_8~0 := 1; 670#L939-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 569#L418-30true assume !(1 == ~m_pc~0); 384#L418-32true is_master_triggered_~__retres1~0#1 := 0; 581#L429-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 249#is_master_triggered_returnLabel#11true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 839#L1061-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 146#L1061-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216#L437-30true assume !(1 == ~t1_pc~0); 679#L437-32true is_transmit1_triggered_~__retres1~1#1 := 0; 374#L448-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 402#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 909#L1069-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 883#L1069-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193#L456-30true assume 1 == ~t2_pc~0; 719#L457-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 527#L467-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89#L1077-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 285#L1077-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 766#L475-30true assume !(1 == ~t3_pc~0); 30#L475-32true is_transmit3_triggered_~__retres1~3#1 := 0; 452#L486-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 389#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 901#L1085-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 206#L1085-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 999#L494-30true assume 1 == ~t4_pc~0; 200#L495-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3#L505-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 833#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 919#L1093-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 698#L1093-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 956#L513-30true assume 1 == ~t5_pc~0; 988#L514-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 340#L524-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 474#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552#L1101-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 796#L1101-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 295#L532-30true assume 1 == ~t6_pc~0; 957#L533-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65#L543-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 629#L1109-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 105#L1109-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 133#L551-30true assume 1 == ~t7_pc~0; 165#L552-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 643#L562-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 540#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10#L1117-30true assume !(0 != activate_threads_~tmp___6~0#1); 191#L1117-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 758#L570-30true assume 1 == ~t8_pc~0; 634#L571-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 131#L581-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 973#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36#L1125-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 236#L1125-32true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261#L952-3true assume 1 == ~M_E~0;~M_E~0 := 2; 958#L952-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 752#L957-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 769#L962-3true assume !(1 == ~T3_E~0); 615#L967-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 800#L972-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 508#L977-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 996#L982-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 977#L987-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 226#L992-3true assume 1 == ~E_M~0;~E_M~0 := 2; 365#L997-3true assume 1 == ~E_1~0;~E_1~0 := 2; 224#L1002-3true assume !(1 == ~E_2~0); 464#L1007-3true assume 1 == ~E_3~0;~E_3~0 := 2; 117#L1012-3true assume 1 == ~E_4~0;~E_4~0 := 2; 170#L1017-3true assume 1 == ~E_5~0;~E_5~0 := 2; 324#L1022-3true assume 1 == ~E_6~0;~E_6~0 := 2; 347#L1027-3true assume 1 == ~E_7~0;~E_7~0 := 2; 23#L1032-3true assume 1 == ~E_8~0;~E_8~0 := 2; 434#L1037-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 141#L650-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 768#L697-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 205#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 830#L1322true assume !(0 == start_simulation_~tmp~3#1); 246#L1322-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 61#L650-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 753#L697-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 17#L1277true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 510#L1284true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 388#stop_simulation_returnLabel#1true start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 673#L1335true assume !(0 != start_simulation_~tmp___0~1#1); 588#L1303-2true [2023-11-23 21:36:47,022 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:47,022 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2023-11-23 21:36:47,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:47,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108092871] [2023-11-23 21:36:47,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:47,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:47,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:47,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:47,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:47,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108092871] [2023-11-23 21:36:47,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108092871] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:47,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:47,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:47,368 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1887163626] [2023-11-23 21:36:47,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:47,375 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:47,377 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:47,377 INFO L85 PathProgramCache]: Analyzing trace with hash -118307812, now seen corresponding path program 1 times [2023-11-23 21:36:47,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:47,378 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804934978] [2023-11-23 21:36:47,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:47,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:47,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:47,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:47,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:47,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804934978] [2023-11-23 21:36:47,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804934978] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:47,475 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:47,475 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 21:36:47,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1981621406] [2023-11-23 21:36:47,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:47,477 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:47,478 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:47,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:47,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:47,514 INFO L87 Difference]: Start difference. First operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:47,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:47,618 INFO L93 Difference]: Finished difference Result 1007 states and 1495 transitions. [2023-11-23 21:36:47,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1495 transitions. [2023-11-23 21:36:47,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:47,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1002 states and 1490 transitions. [2023-11-23 21:36:47,678 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-23 21:36:47,681 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-23 21:36:47,681 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1490 transitions. [2023-11-23 21:36:47,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:47,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2023-11-23 21:36:47,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1490 transitions. [2023-11-23 21:36:47,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-23 21:36:47,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4870259481037924) internal successors, (1490), 1001 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:47,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1490 transitions. [2023-11-23 21:36:47,771 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2023-11-23 21:36:47,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:47,780 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2023-11-23 21:36:47,780 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-23 21:36:47,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1490 transitions. [2023-11-23 21:36:47,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:47,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:47,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:47,801 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:47,801 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:47,802 INFO L748 eck$LassoCheckResult]: Stem: 2347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3011#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2766#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2767#L602-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2364#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2365#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2297#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2298#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2560#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2532#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2533#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2816#L854 assume !(0 == ~M_E~0); 2623#L854-2 assume !(0 == ~T1_E~0); 2624#L859-1 assume !(0 == ~T2_E~0); 2177#L864-1 assume !(0 == ~T3_E~0); 2178#L869-1 assume !(0 == ~T4_E~0); 2288#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2997#L879-1 assume !(0 == ~T6_E~0); 2613#L884-1 assume !(0 == ~T7_E~0); 2040#L889-1 assume !(0 == ~T8_E~0); 2041#L894-1 assume !(0 == ~E_M~0); 2377#L899-1 assume !(0 == ~E_1~0); 2822#L904-1 assume !(0 == ~E_2~0); 2550#L909-1 assume !(0 == ~E_3~0); 2551#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2757#L919-1 assume !(0 == ~E_5~0); 2456#L924-1 assume !(0 == ~E_6~0); 2270#L929-1 assume !(0 == ~E_7~0); 2271#L934-1 assume !(0 == ~E_8~0); 2529#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2057#L418 assume !(1 == ~m_pc~0); 2032#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2031#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2926#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2912#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2845#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2846#L437 assume 1 == ~t1_pc~0; 3014#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2919#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2080#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2081#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2406#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2902#L456 assume !(1 == ~t2_pc~0); 2328#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2327#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2488#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2489#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2661#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2171#L475 assume 1 == ~t3_pc~0; 2172#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2235#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2049#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2409#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2410#L494 assume !(1 == ~t4_pc~0); 2450#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2451#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2188#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2781#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2230#L513 assume 1 == ~t5_pc~0; 2231#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2452#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2184#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2185#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2137#L532 assume !(1 == ~t6_pc~0); 2138#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2289#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2470#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2471#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2381#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2382#L551 assume 1 == ~t7_pc~0; 2939#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2783#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2784#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3023#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 3024#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2571#L570 assume 1 == ~t8_pc~0; 2572#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2687#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2877#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2683#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2165#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2166#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 2106#L952-2 assume !(1 == ~T1_E~0); 2107#L957-1 assume !(1 == ~T2_E~0); 2883#L962-1 assume !(1 == ~T3_E~0); 2699#L967-1 assume !(1 == ~T4_E~0); 2700#L972-1 assume !(1 == ~T5_E~0); 2942#L977-1 assume !(1 == ~T6_E~0); 2943#L982-1 assume !(1 == ~T7_E~0); 2291#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2292#L992-1 assume !(1 == ~E_M~0); 2299#L997-1 assume !(1 == ~E_1~0); 2659#L1002-1 assume !(1 == ~E_2~0); 2644#L1007-1 assume !(1 == ~E_3~0); 2042#L1012-1 assume !(1 == ~E_4~0); 2043#L1017-1 assume !(1 == ~E_5~0); 2647#L1022-1 assume !(1 == ~E_6~0); 2648#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2673#L1032-1 assume !(1 == ~E_8~0); 2804#L1037-1 assume { :end_inline_reset_delta_events } true; 2805#L1303-2 [2023-11-23 21:36:47,803 INFO L750 eck$LassoCheckResult]: Loop: 2805#L1303-2 assume !false; 2879#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2546#L829-1 assume !false; 2842#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2432#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2367#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2510#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2511#L712 assume !(0 != eval_~tmp~0#1); 2772#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2682#L854-3 assume !(0 == ~M_E~0); 2773#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2774#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3022#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2996#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2589#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2590#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2660#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2638#L889-3 assume !(0 == ~T8_E~0); 2261#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2262#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2295#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2296#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2240#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2241#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2284#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2848#L929-3 assume !(0 == ~E_7~0); 2759#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2760#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2867#L418-30 assume 1 == ~m_pc~0; 2124#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2125#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2501#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2502#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2329#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2330#L437-30 assume 1 == ~t1_pc~0; 2453#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2679#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2680#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2717#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3013#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2413#L456-30 assume !(1 == ~t2_pc~0); 2414#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2840#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2412#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2218#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2219#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2561#L475-30 assume 1 == ~t3_pc~0; 2935#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2089#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2697#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2698#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2436#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2437#L494-30 assume !(1 == ~t4_pc~0); 2245#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2028#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2029#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3001#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2951#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2952#L513-30 assume 1 == ~t5_pc~0; 3025#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2567#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2636#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2793#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2859#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2579#L532-30 assume 1 == ~t6_pc~0; 2580#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2169#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2170#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2194#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2250#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2251#L551-30 assume 1 == ~t7_pc~0; 2304#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2369#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2849#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2044#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 2045#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2411#L570-30 assume 1 == ~t8_pc~0; 2920#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2300#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2301#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2102#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2103#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2482#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2526#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2977#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2978#L962-3 assume !(1 == ~T3_E~0); 2900#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2901#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2820#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2821#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3026#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2468#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2469#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2464#L1002-3 assume !(1 == ~E_2~0); 2465#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2274#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2275#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2376#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2612#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2072#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2073#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2318#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2319#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2434#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2435#L1322 assume !(0 == start_simulation_~tmp~3#1); 2496#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2159#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2160#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2076#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2058#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2059#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2695#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2696#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2805#L1303-2 [2023-11-23 21:36:47,806 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:47,807 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2023-11-23 21:36:47,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:47,807 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297708995] [2023-11-23 21:36:47,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:47,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:47,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:47,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:47,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:47,926 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297708995] [2023-11-23 21:36:47,926 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297708995] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:47,927 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:47,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:47,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461756459] [2023-11-23 21:36:47,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:47,928 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:47,928 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:47,928 INFO L85 PathProgramCache]: Analyzing trace with hash -221898915, now seen corresponding path program 1 times [2023-11-23 21:36:47,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:47,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1810753475] [2023-11-23 21:36:47,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:47,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:47,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:48,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:48,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:48,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1810753475] [2023-11-23 21:36:48,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1810753475] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:48,034 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:48,034 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:48,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1979389847] [2023-11-23 21:36:48,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:48,035 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:48,035 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:48,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:48,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:48,037 INFO L87 Difference]: Start difference. First operand 1002 states and 1490 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:48,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:48,078 INFO L93 Difference]: Finished difference Result 1002 states and 1489 transitions. [2023-11-23 21:36:48,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1489 transitions. [2023-11-23 21:36:48,088 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:48,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1489 transitions. [2023-11-23 21:36:48,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-23 21:36:48,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-23 21:36:48,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1489 transitions. [2023-11-23 21:36:48,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:48,106 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2023-11-23 21:36:48,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1489 transitions. [2023-11-23 21:36:48,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-23 21:36:48,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4860279441117765) internal successors, (1489), 1001 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:48,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1489 transitions. [2023-11-23 21:36:48,140 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2023-11-23 21:36:48,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:48,143 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2023-11-23 21:36:48,143 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-23 21:36:48,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1489 transitions. [2023-11-23 21:36:48,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:48,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:48,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:48,156 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:48,156 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:48,158 INFO L748 eck$LassoCheckResult]: Stem: 4358#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4359#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5022#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 4777#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4778#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4375#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4376#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4308#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4309#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4571#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4543#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4544#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4827#L854 assume !(0 == ~M_E~0); 4634#L854-2 assume !(0 == ~T1_E~0); 4635#L859-1 assume !(0 == ~T2_E~0); 4188#L864-1 assume !(0 == ~T3_E~0); 4189#L869-1 assume !(0 == ~T4_E~0); 4299#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5008#L879-1 assume !(0 == ~T6_E~0); 4624#L884-1 assume !(0 == ~T7_E~0); 4051#L889-1 assume !(0 == ~T8_E~0); 4052#L894-1 assume !(0 == ~E_M~0); 4388#L899-1 assume !(0 == ~E_1~0); 4833#L904-1 assume !(0 == ~E_2~0); 4561#L909-1 assume !(0 == ~E_3~0); 4562#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4768#L919-1 assume !(0 == ~E_5~0); 4467#L924-1 assume !(0 == ~E_6~0); 4281#L929-1 assume !(0 == ~E_7~0); 4282#L934-1 assume !(0 == ~E_8~0); 4540#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4068#L418 assume !(1 == ~m_pc~0); 4043#L418-2 is_master_triggered_~__retres1~0#1 := 0; 4042#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4937#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4923#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4856#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4857#L437 assume 1 == ~t1_pc~0; 5025#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4930#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4091#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4092#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 4417#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4913#L456 assume !(1 == ~t2_pc~0); 4339#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4338#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4499#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4500#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 4672#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4182#L475 assume 1 == ~t3_pc~0; 4183#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4246#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4059#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4060#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 4420#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4421#L494 assume !(1 == ~t4_pc~0); 4461#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4462#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4198#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4199#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 4792#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4241#L513 assume 1 == ~t5_pc~0; 4242#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4463#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4939#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4195#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 4196#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4148#L532 assume !(1 == ~t6_pc~0); 4149#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4300#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4481#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4482#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 4392#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4393#L551 assume 1 == ~t7_pc~0; 4950#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4794#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5034#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 5035#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4582#L570 assume 1 == ~t8_pc~0; 4583#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4698#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4888#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4694#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 4176#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4177#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 4117#L952-2 assume !(1 == ~T1_E~0); 4118#L957-1 assume !(1 == ~T2_E~0); 4894#L962-1 assume !(1 == ~T3_E~0); 4710#L967-1 assume !(1 == ~T4_E~0); 4711#L972-1 assume !(1 == ~T5_E~0); 4953#L977-1 assume !(1 == ~T6_E~0); 4954#L982-1 assume !(1 == ~T7_E~0); 4302#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4303#L992-1 assume !(1 == ~E_M~0); 4310#L997-1 assume !(1 == ~E_1~0); 4670#L1002-1 assume !(1 == ~E_2~0); 4655#L1007-1 assume !(1 == ~E_3~0); 4053#L1012-1 assume !(1 == ~E_4~0); 4054#L1017-1 assume !(1 == ~E_5~0); 4658#L1022-1 assume !(1 == ~E_6~0); 4659#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4684#L1032-1 assume !(1 == ~E_8~0); 4815#L1037-1 assume { :end_inline_reset_delta_events } true; 4816#L1303-2 [2023-11-23 21:36:48,160 INFO L750 eck$LassoCheckResult]: Loop: 4816#L1303-2 assume !false; 4890#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4557#L829-1 assume !false; 4853#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4443#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4378#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4521#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4522#L712 assume !(0 != eval_~tmp~0#1); 4783#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4693#L854-3 assume !(0 == ~M_E~0); 4784#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4785#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5033#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5007#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4600#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4601#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4671#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4649#L889-3 assume !(0 == ~T8_E~0); 4272#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4273#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4306#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4307#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4251#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4252#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4295#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4859#L929-3 assume !(0 == ~E_7~0); 4770#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4771#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4878#L418-30 assume 1 == ~m_pc~0; 4135#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4136#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4512#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4513#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4340#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4341#L437-30 assume 1 == ~t1_pc~0; 4464#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4690#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4691#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4728#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5024#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4424#L456-30 assume !(1 == ~t2_pc~0); 4425#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 4851#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4423#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4229#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4230#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4572#L475-30 assume 1 == ~t3_pc~0; 4946#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4100#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4708#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4709#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4447#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4448#L494-30 assume !(1 == ~t4_pc~0); 4256#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4039#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4040#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5012#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4962#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4963#L513-30 assume !(1 == ~t5_pc~0); 4577#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4578#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4647#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4804#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4870#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4590#L532-30 assume !(1 == ~t6_pc~0); 4592#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4180#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4181#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4205#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4261#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4262#L551-30 assume !(1 == ~t7_pc~0); 4314#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 4380#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4860#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4055#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 4056#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4422#L570-30 assume 1 == ~t8_pc~0; 4931#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4311#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4312#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4113#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4114#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4493#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4537#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4988#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4989#L962-3 assume !(1 == ~T3_E~0); 4911#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4912#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4831#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4832#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5037#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4479#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4480#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4475#L1002-3 assume !(1 == ~E_2~0); 4476#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4285#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4286#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4387#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4623#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4083#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4084#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4329#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4330#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4445#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4446#L1322 assume !(0 == start_simulation_~tmp~3#1); 4507#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4170#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4171#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4087#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 4069#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4070#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4706#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4707#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 4816#L1303-2 [2023-11-23 21:36:48,161 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:48,161 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2023-11-23 21:36:48,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:48,162 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691876238] [2023-11-23 21:36:48,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:48,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:48,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:48,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:48,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:48,299 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691876238] [2023-11-23 21:36:48,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691876238] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:48,300 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:48,300 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:48,300 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [355935274] [2023-11-23 21:36:48,300 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:48,301 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:48,301 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:48,301 INFO L85 PathProgramCache]: Analyzing trace with hash 2036706080, now seen corresponding path program 1 times [2023-11-23 21:36:48,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:48,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485444671] [2023-11-23 21:36:48,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:48,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:48,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:48,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:48,492 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:48,493 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485444671] [2023-11-23 21:36:48,493 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485444671] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:48,493 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:48,493 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:48,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834766975] [2023-11-23 21:36:48,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:48,494 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:48,495 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:48,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:48,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:48,496 INFO L87 Difference]: Start difference. First operand 1002 states and 1489 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:48,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:48,533 INFO L93 Difference]: Finished difference Result 1002 states and 1488 transitions. [2023-11-23 21:36:48,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1488 transitions. [2023-11-23 21:36:48,544 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:48,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1488 transitions. [2023-11-23 21:36:48,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-23 21:36:48,556 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-23 21:36:48,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1488 transitions. [2023-11-23 21:36:48,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:48,559 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2023-11-23 21:36:48,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1488 transitions. [2023-11-23 21:36:48,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-23 21:36:48,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4850299401197604) internal successors, (1488), 1001 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:48,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1488 transitions. [2023-11-23 21:36:48,591 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2023-11-23 21:36:48,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:48,593 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2023-11-23 21:36:48,594 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-23 21:36:48,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1488 transitions. [2023-11-23 21:36:48,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:48,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:48,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:48,608 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:48,608 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:48,609 INFO L748 eck$LassoCheckResult]: Stem: 6369#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7033#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 6788#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6789#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6386#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6387#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6319#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6320#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6582#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6554#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6555#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6838#L854 assume !(0 == ~M_E~0); 6645#L854-2 assume !(0 == ~T1_E~0); 6646#L859-1 assume !(0 == ~T2_E~0); 6199#L864-1 assume !(0 == ~T3_E~0); 6200#L869-1 assume !(0 == ~T4_E~0); 6310#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7019#L879-1 assume !(0 == ~T6_E~0); 6635#L884-1 assume !(0 == ~T7_E~0); 6062#L889-1 assume !(0 == ~T8_E~0); 6063#L894-1 assume !(0 == ~E_M~0); 6399#L899-1 assume !(0 == ~E_1~0); 6844#L904-1 assume !(0 == ~E_2~0); 6572#L909-1 assume !(0 == ~E_3~0); 6573#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6779#L919-1 assume !(0 == ~E_5~0); 6478#L924-1 assume !(0 == ~E_6~0); 6292#L929-1 assume !(0 == ~E_7~0); 6293#L934-1 assume !(0 == ~E_8~0); 6551#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6079#L418 assume !(1 == ~m_pc~0); 6054#L418-2 is_master_triggered_~__retres1~0#1 := 0; 6053#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6948#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6934#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6867#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6868#L437 assume 1 == ~t1_pc~0; 7036#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6941#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6103#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 6428#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6924#L456 assume !(1 == ~t2_pc~0); 6350#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6349#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6510#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6511#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 6683#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6193#L475 assume 1 == ~t3_pc~0; 6194#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6257#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6070#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6071#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 6431#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6432#L494 assume !(1 == ~t4_pc~0); 6472#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6473#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6209#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6210#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 6803#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6252#L513 assume 1 == ~t5_pc~0; 6253#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6474#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6950#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6206#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 6207#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6159#L532 assume !(1 == ~t6_pc~0); 6160#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6311#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6493#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 6403#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6404#L551 assume 1 == ~t7_pc~0; 6961#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6805#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6806#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7045#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 7046#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6593#L570 assume 1 == ~t8_pc~0; 6594#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6709#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6899#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6705#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 6187#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6188#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 6128#L952-2 assume !(1 == ~T1_E~0); 6129#L957-1 assume !(1 == ~T2_E~0); 6905#L962-1 assume !(1 == ~T3_E~0); 6721#L967-1 assume !(1 == ~T4_E~0); 6722#L972-1 assume !(1 == ~T5_E~0); 6964#L977-1 assume !(1 == ~T6_E~0); 6965#L982-1 assume !(1 == ~T7_E~0); 6313#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6314#L992-1 assume !(1 == ~E_M~0); 6321#L997-1 assume !(1 == ~E_1~0); 6681#L1002-1 assume !(1 == ~E_2~0); 6666#L1007-1 assume !(1 == ~E_3~0); 6064#L1012-1 assume !(1 == ~E_4~0); 6065#L1017-1 assume !(1 == ~E_5~0); 6669#L1022-1 assume !(1 == ~E_6~0); 6670#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6695#L1032-1 assume !(1 == ~E_8~0); 6826#L1037-1 assume { :end_inline_reset_delta_events } true; 6827#L1303-2 [2023-11-23 21:36:48,609 INFO L750 eck$LassoCheckResult]: Loop: 6827#L1303-2 assume !false; 6901#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6568#L829-1 assume !false; 6864#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6454#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6389#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6532#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6533#L712 assume !(0 != eval_~tmp~0#1); 6794#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6703#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6704#L854-3 assume !(0 == ~M_E~0); 6795#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6796#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7044#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7018#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6611#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6612#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6682#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6660#L889-3 assume !(0 == ~T8_E~0); 6283#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6284#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6317#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6318#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6262#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6263#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6306#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6870#L929-3 assume !(0 == ~E_7~0); 6781#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6782#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6889#L418-30 assume 1 == ~m_pc~0; 6146#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6147#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6523#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6524#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6351#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6352#L437-30 assume 1 == ~t1_pc~0; 6475#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6701#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6702#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6739#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7035#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6435#L456-30 assume !(1 == ~t2_pc~0); 6436#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 6862#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6434#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6240#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6241#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6583#L475-30 assume 1 == ~t3_pc~0; 6957#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6111#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6719#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6720#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6458#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6459#L494-30 assume 1 == ~t4_pc~0; 6449#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6050#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6051#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7023#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6973#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6974#L513-30 assume 1 == ~t5_pc~0; 7047#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6589#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6658#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6815#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6881#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6601#L532-30 assume 1 == ~t6_pc~0; 6602#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6191#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6192#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6216#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6272#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6273#L551-30 assume !(1 == ~t7_pc~0); 6325#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 6391#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6871#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6066#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 6067#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6433#L570-30 assume !(1 == ~t8_pc~0); 6787#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6322#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6323#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6124#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6125#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6504#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6548#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6999#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7000#L962-3 assume !(1 == ~T3_E~0); 6922#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6923#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6842#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6843#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7048#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6490#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6491#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6486#L1002-3 assume !(1 == ~E_2~0); 6487#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6296#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6297#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6398#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6634#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6094#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6095#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6340#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6341#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6456#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6457#L1322 assume !(0 == start_simulation_~tmp~3#1); 6518#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6181#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6182#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 6080#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6081#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6717#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6718#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 6827#L1303-2 [2023-11-23 21:36:48,610 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:48,610 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2023-11-23 21:36:48,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:48,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885554504] [2023-11-23 21:36:48,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:48,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:48,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:48,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:48,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:48,706 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885554504] [2023-11-23 21:36:48,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885554504] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:48,707 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:48,707 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:48,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687119119] [2023-11-23 21:36:48,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:48,708 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:48,709 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:48,710 INFO L85 PathProgramCache]: Analyzing trace with hash 1773359198, now seen corresponding path program 1 times [2023-11-23 21:36:48,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:48,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93316426] [2023-11-23 21:36:48,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:48,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:48,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:48,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:48,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:48,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [93316426] [2023-11-23 21:36:48,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [93316426] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:48,820 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:48,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:48,821 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [430471391] [2023-11-23 21:36:48,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:48,821 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:48,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:48,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:48,822 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:48,822 INFO L87 Difference]: Start difference. First operand 1002 states and 1488 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:48,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:48,850 INFO L93 Difference]: Finished difference Result 1002 states and 1487 transitions. [2023-11-23 21:36:48,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1487 transitions. [2023-11-23 21:36:48,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:48,868 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1487 transitions. [2023-11-23 21:36:48,868 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-23 21:36:48,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-23 21:36:48,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1487 transitions. [2023-11-23 21:36:48,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:48,872 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2023-11-23 21:36:48,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1487 transitions. [2023-11-23 21:36:48,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-23 21:36:48,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4840319361277445) internal successors, (1487), 1001 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:48,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1487 transitions. [2023-11-23 21:36:48,902 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2023-11-23 21:36:48,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:48,904 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2023-11-23 21:36:48,904 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-23 21:36:48,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1487 transitions. [2023-11-23 21:36:48,911 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:48,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:48,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:48,913 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:48,916 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:48,916 INFO L748 eck$LassoCheckResult]: Stem: 8380#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9005#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9006#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9044#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 8799#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8800#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8397#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8398#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8330#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8331#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8593#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8565#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8566#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8849#L854 assume !(0 == ~M_E~0); 8656#L854-2 assume !(0 == ~T1_E~0); 8657#L859-1 assume !(0 == ~T2_E~0); 8210#L864-1 assume !(0 == ~T3_E~0); 8211#L869-1 assume !(0 == ~T4_E~0); 8321#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9030#L879-1 assume !(0 == ~T6_E~0); 8646#L884-1 assume !(0 == ~T7_E~0); 8073#L889-1 assume !(0 == ~T8_E~0); 8074#L894-1 assume !(0 == ~E_M~0); 8410#L899-1 assume !(0 == ~E_1~0); 8855#L904-1 assume !(0 == ~E_2~0); 8583#L909-1 assume !(0 == ~E_3~0); 8584#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8790#L919-1 assume !(0 == ~E_5~0); 8489#L924-1 assume !(0 == ~E_6~0); 8303#L929-1 assume !(0 == ~E_7~0); 8304#L934-1 assume !(0 == ~E_8~0); 8562#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8090#L418 assume !(1 == ~m_pc~0); 8065#L418-2 is_master_triggered_~__retres1~0#1 := 0; 8064#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8959#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8945#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8878#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8879#L437 assume 1 == ~t1_pc~0; 9047#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8952#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8113#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8114#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 8439#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8935#L456 assume !(1 == ~t2_pc~0); 8361#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8360#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8521#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8522#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 8694#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8204#L475 assume 1 == ~t3_pc~0; 8205#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8268#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8081#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8082#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 8442#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8443#L494 assume !(1 == ~t4_pc~0); 8483#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8484#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8220#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8221#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 8814#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8263#L513 assume 1 == ~t5_pc~0; 8264#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8485#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8961#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8217#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 8218#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8170#L532 assume !(1 == ~t6_pc~0); 8171#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8322#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8503#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8504#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 8414#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8415#L551 assume 1 == ~t7_pc~0; 8972#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8816#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8817#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9056#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 9057#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8604#L570 assume 1 == ~t8_pc~0; 8605#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8720#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8910#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8716#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 8198#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8199#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 8139#L952-2 assume !(1 == ~T1_E~0); 8140#L957-1 assume !(1 == ~T2_E~0); 8916#L962-1 assume !(1 == ~T3_E~0); 8732#L967-1 assume !(1 == ~T4_E~0); 8733#L972-1 assume !(1 == ~T5_E~0); 8975#L977-1 assume !(1 == ~T6_E~0); 8976#L982-1 assume !(1 == ~T7_E~0); 8324#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8325#L992-1 assume !(1 == ~E_M~0); 8332#L997-1 assume !(1 == ~E_1~0); 8692#L1002-1 assume !(1 == ~E_2~0); 8677#L1007-1 assume !(1 == ~E_3~0); 8075#L1012-1 assume !(1 == ~E_4~0); 8076#L1017-1 assume !(1 == ~E_5~0); 8680#L1022-1 assume !(1 == ~E_6~0); 8681#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 8706#L1032-1 assume !(1 == ~E_8~0); 8837#L1037-1 assume { :end_inline_reset_delta_events } true; 8838#L1303-2 [2023-11-23 21:36:48,917 INFO L750 eck$LassoCheckResult]: Loop: 8838#L1303-2 assume !false; 8912#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8579#L829-1 assume !false; 8875#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8465#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8400#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8543#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8544#L712 assume !(0 != eval_~tmp~0#1); 8805#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8714#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8715#L854-3 assume !(0 == ~M_E~0); 8806#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8807#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9055#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9029#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8622#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8623#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8693#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8671#L889-3 assume !(0 == ~T8_E~0); 8294#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8295#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8328#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8329#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8273#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8274#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8317#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8881#L929-3 assume !(0 == ~E_7~0); 8792#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8793#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8900#L418-30 assume 1 == ~m_pc~0; 8157#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8158#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8534#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8535#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8362#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8363#L437-30 assume 1 == ~t1_pc~0; 8486#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8712#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8713#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8750#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9046#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8446#L456-30 assume 1 == ~t2_pc~0; 8448#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8873#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8445#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8251#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8252#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8594#L475-30 assume 1 == ~t3_pc~0; 8968#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8122#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8730#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8731#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8469#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8470#L494-30 assume !(1 == ~t4_pc~0); 8278#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 8061#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8062#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9034#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8984#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8985#L513-30 assume 1 == ~t5_pc~0; 9058#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8600#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8669#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8826#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8892#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8612#L532-30 assume 1 == ~t6_pc~0; 8613#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8202#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8203#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8227#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8283#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8284#L551-30 assume !(1 == ~t7_pc~0); 8336#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 8402#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8882#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8077#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 8078#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8444#L570-30 assume 1 == ~t8_pc~0; 8953#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8333#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8334#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8135#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8136#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8515#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8559#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9010#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9011#L962-3 assume !(1 == ~T3_E~0); 8933#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8934#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8853#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8854#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9059#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8501#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8502#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8497#L1002-3 assume !(1 == ~E_2~0); 8498#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8307#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8308#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8409#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8645#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8105#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8106#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8351#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8352#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8467#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8468#L1322 assume !(0 == start_simulation_~tmp~3#1); 8529#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8192#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8193#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8109#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 8091#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8092#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8728#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8729#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 8838#L1303-2 [2023-11-23 21:36:48,917 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:48,918 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2023-11-23 21:36:48,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:48,918 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011050994] [2023-11-23 21:36:48,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:48,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:48,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:48,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:48,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:48,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2011050994] [2023-11-23 21:36:48,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2011050994] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:48,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:48,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:48,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094523901] [2023-11-23 21:36:48,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:48,988 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:48,988 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:48,989 INFO L85 PathProgramCache]: Analyzing trace with hash -455356643, now seen corresponding path program 1 times [2023-11-23 21:36:48,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:48,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436527398] [2023-11-23 21:36:48,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:48,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:49,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:49,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:49,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:49,088 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [436527398] [2023-11-23 21:36:49,088 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [436527398] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:49,088 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:49,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:49,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785894621] [2023-11-23 21:36:49,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:49,089 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:49,089 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:49,089 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:49,090 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:49,090 INFO L87 Difference]: Start difference. First operand 1002 states and 1487 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:49,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:49,116 INFO L93 Difference]: Finished difference Result 1002 states and 1486 transitions. [2023-11-23 21:36:49,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1486 transitions. [2023-11-23 21:36:49,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:49,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1486 transitions. [2023-11-23 21:36:49,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-23 21:36:49,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-23 21:36:49,135 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1486 transitions. [2023-11-23 21:36:49,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:49,137 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2023-11-23 21:36:49,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1486 transitions. [2023-11-23 21:36:49,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-23 21:36:49,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4830339321357286) internal successors, (1486), 1001 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:49,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1486 transitions. [2023-11-23 21:36:49,162 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2023-11-23 21:36:49,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:49,165 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2023-11-23 21:36:49,165 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-23 21:36:49,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1486 transitions. [2023-11-23 21:36:49,172 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:49,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:49,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:49,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:49,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:49,175 INFO L748 eck$LassoCheckResult]: Stem: 10391#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 11016#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11017#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11055#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 10810#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10811#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10408#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10409#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10341#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10342#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10604#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10576#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10577#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10860#L854 assume !(0 == ~M_E~0); 10667#L854-2 assume !(0 == ~T1_E~0); 10668#L859-1 assume !(0 == ~T2_E~0); 10221#L864-1 assume !(0 == ~T3_E~0); 10222#L869-1 assume !(0 == ~T4_E~0); 10332#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11041#L879-1 assume !(0 == ~T6_E~0); 10657#L884-1 assume !(0 == ~T7_E~0); 10084#L889-1 assume !(0 == ~T8_E~0); 10085#L894-1 assume !(0 == ~E_M~0); 10421#L899-1 assume !(0 == ~E_1~0); 10866#L904-1 assume !(0 == ~E_2~0); 10594#L909-1 assume !(0 == ~E_3~0); 10595#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10801#L919-1 assume !(0 == ~E_5~0); 10500#L924-1 assume !(0 == ~E_6~0); 10314#L929-1 assume !(0 == ~E_7~0); 10315#L934-1 assume !(0 == ~E_8~0); 10573#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10101#L418 assume !(1 == ~m_pc~0); 10076#L418-2 is_master_triggered_~__retres1~0#1 := 0; 10075#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10970#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10956#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10889#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10890#L437 assume 1 == ~t1_pc~0; 11058#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10963#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10125#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 10450#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10946#L456 assume !(1 == ~t2_pc~0); 10372#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10371#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10532#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10533#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 10705#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10215#L475 assume 1 == ~t3_pc~0; 10216#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10279#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10092#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10093#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 10453#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10454#L494 assume !(1 == ~t4_pc~0); 10494#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10495#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10231#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10232#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 10825#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10274#L513 assume 1 == ~t5_pc~0; 10275#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10496#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10972#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10228#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 10229#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10181#L532 assume !(1 == ~t6_pc~0); 10182#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10333#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10514#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10515#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 10425#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10426#L551 assume 1 == ~t7_pc~0; 10983#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10827#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10828#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11067#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 11068#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10615#L570 assume 1 == ~t8_pc~0; 10616#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10731#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10921#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10727#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 10209#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10210#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 10150#L952-2 assume !(1 == ~T1_E~0); 10151#L957-1 assume !(1 == ~T2_E~0); 10927#L962-1 assume !(1 == ~T3_E~0); 10743#L967-1 assume !(1 == ~T4_E~0); 10744#L972-1 assume !(1 == ~T5_E~0); 10986#L977-1 assume !(1 == ~T6_E~0); 10987#L982-1 assume !(1 == ~T7_E~0); 10335#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10336#L992-1 assume !(1 == ~E_M~0); 10343#L997-1 assume !(1 == ~E_1~0); 10703#L1002-1 assume !(1 == ~E_2~0); 10688#L1007-1 assume !(1 == ~E_3~0); 10086#L1012-1 assume !(1 == ~E_4~0); 10087#L1017-1 assume !(1 == ~E_5~0); 10691#L1022-1 assume !(1 == ~E_6~0); 10692#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10717#L1032-1 assume !(1 == ~E_8~0); 10848#L1037-1 assume { :end_inline_reset_delta_events } true; 10849#L1303-2 [2023-11-23 21:36:49,175 INFO L750 eck$LassoCheckResult]: Loop: 10849#L1303-2 assume !false; 10923#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10590#L829-1 assume !false; 10886#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10476#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10411#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10554#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10555#L712 assume !(0 != eval_~tmp~0#1); 10816#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10725#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10726#L854-3 assume !(0 == ~M_E~0); 10817#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10818#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11066#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11040#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10633#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10634#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10704#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10682#L889-3 assume !(0 == ~T8_E~0); 10305#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10306#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10339#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10340#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10284#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10285#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10328#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10892#L929-3 assume !(0 == ~E_7~0); 10803#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10804#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10911#L418-30 assume 1 == ~m_pc~0; 10168#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10169#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10545#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10546#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10373#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10374#L437-30 assume 1 == ~t1_pc~0; 10497#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10723#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10724#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10761#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11057#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10457#L456-30 assume !(1 == ~t2_pc~0); 10458#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 10884#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10456#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10262#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10263#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10605#L475-30 assume 1 == ~t3_pc~0; 10979#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10133#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10741#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10742#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10480#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10481#L494-30 assume !(1 == ~t4_pc~0); 10289#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10072#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10073#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11045#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10995#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10996#L513-30 assume !(1 == ~t5_pc~0); 10610#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 10611#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10680#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10837#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10903#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10623#L532-30 assume 1 == ~t6_pc~0; 10624#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10213#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10214#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10238#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10294#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10295#L551-30 assume !(1 == ~t7_pc~0); 10347#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 10413#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10893#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10088#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 10089#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10455#L570-30 assume 1 == ~t8_pc~0; 10964#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10344#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10345#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10146#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10147#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10526#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10570#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11021#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11022#L962-3 assume !(1 == ~T3_E~0); 10944#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10945#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10864#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10865#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11070#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10512#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10513#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10508#L1002-3 assume !(1 == ~E_2~0); 10509#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10318#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10319#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10420#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10656#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10116#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10117#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10362#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10363#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10479#L1322 assume !(0 == start_simulation_~tmp~3#1); 10540#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10203#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10204#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10120#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 10102#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10103#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10739#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10740#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 10849#L1303-2 [2023-11-23 21:36:49,176 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:49,176 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2023-11-23 21:36:49,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:49,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210355181] [2023-11-23 21:36:49,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:49,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:49,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:49,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:49,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:49,233 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1210355181] [2023-11-23 21:36:49,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1210355181] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:49,233 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:49,233 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:49,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667422714] [2023-11-23 21:36:49,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:49,239 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:49,240 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:49,240 INFO L85 PathProgramCache]: Analyzing trace with hash 568502751, now seen corresponding path program 1 times [2023-11-23 21:36:49,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:49,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534777608] [2023-11-23 21:36:49,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:49,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:49,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:49,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:49,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:49,301 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534777608] [2023-11-23 21:36:49,301 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534777608] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:49,301 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:49,301 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:49,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1598070120] [2023-11-23 21:36:49,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:49,303 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:49,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:49,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:49,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:49,304 INFO L87 Difference]: Start difference. First operand 1002 states and 1486 transitions. cyclomatic complexity: 485 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:49,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:49,338 INFO L93 Difference]: Finished difference Result 1002 states and 1485 transitions. [2023-11-23 21:36:49,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1485 transitions. [2023-11-23 21:36:49,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:49,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1485 transitions. [2023-11-23 21:36:49,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-23 21:36:49,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-23 21:36:49,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1485 transitions. [2023-11-23 21:36:49,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:49,360 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2023-11-23 21:36:49,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1485 transitions. [2023-11-23 21:36:49,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-23 21:36:49,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4820359281437125) internal successors, (1485), 1001 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:49,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1485 transitions. [2023-11-23 21:36:49,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2023-11-23 21:36:49,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:49,387 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2023-11-23 21:36:49,387 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-23 21:36:49,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1485 transitions. [2023-11-23 21:36:49,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:49,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:49,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:49,396 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:49,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:49,397 INFO L748 eck$LassoCheckResult]: Stem: 12402#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12403#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13027#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13028#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13066#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 12821#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12822#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12419#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12420#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12352#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12353#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12615#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12587#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12588#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12871#L854 assume !(0 == ~M_E~0); 12678#L854-2 assume !(0 == ~T1_E~0); 12679#L859-1 assume !(0 == ~T2_E~0); 12232#L864-1 assume !(0 == ~T3_E~0); 12233#L869-1 assume !(0 == ~T4_E~0); 12343#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13052#L879-1 assume !(0 == ~T6_E~0); 12668#L884-1 assume !(0 == ~T7_E~0); 12095#L889-1 assume !(0 == ~T8_E~0); 12096#L894-1 assume !(0 == ~E_M~0); 12432#L899-1 assume !(0 == ~E_1~0); 12877#L904-1 assume !(0 == ~E_2~0); 12605#L909-1 assume !(0 == ~E_3~0); 12606#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12812#L919-1 assume !(0 == ~E_5~0); 12511#L924-1 assume !(0 == ~E_6~0); 12325#L929-1 assume !(0 == ~E_7~0); 12326#L934-1 assume !(0 == ~E_8~0); 12584#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12112#L418 assume !(1 == ~m_pc~0); 12087#L418-2 is_master_triggered_~__retres1~0#1 := 0; 12086#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12981#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12967#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12900#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12901#L437 assume 1 == ~t1_pc~0; 13069#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12974#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12136#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 12461#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12957#L456 assume !(1 == ~t2_pc~0); 12383#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12382#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12543#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12544#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 12716#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12226#L475 assume 1 == ~t3_pc~0; 12227#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12290#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12103#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12104#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 12464#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12465#L494 assume !(1 == ~t4_pc~0); 12505#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12506#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12242#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12243#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 12836#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12285#L513 assume 1 == ~t5_pc~0; 12286#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12507#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12983#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12239#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 12240#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12192#L532 assume !(1 == ~t6_pc~0); 12193#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12344#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12525#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12526#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 12436#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12437#L551 assume 1 == ~t7_pc~0; 12994#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12838#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12839#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13078#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 13079#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12626#L570 assume 1 == ~t8_pc~0; 12627#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12742#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12932#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12738#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 12220#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12221#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 12161#L952-2 assume !(1 == ~T1_E~0); 12162#L957-1 assume !(1 == ~T2_E~0); 12938#L962-1 assume !(1 == ~T3_E~0); 12754#L967-1 assume !(1 == ~T4_E~0); 12755#L972-1 assume !(1 == ~T5_E~0); 12997#L977-1 assume !(1 == ~T6_E~0); 12998#L982-1 assume !(1 == ~T7_E~0); 12346#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12347#L992-1 assume !(1 == ~E_M~0); 12354#L997-1 assume !(1 == ~E_1~0); 12714#L1002-1 assume !(1 == ~E_2~0); 12699#L1007-1 assume !(1 == ~E_3~0); 12097#L1012-1 assume !(1 == ~E_4~0); 12098#L1017-1 assume !(1 == ~E_5~0); 12702#L1022-1 assume !(1 == ~E_6~0); 12703#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12728#L1032-1 assume !(1 == ~E_8~0); 12859#L1037-1 assume { :end_inline_reset_delta_events } true; 12860#L1303-2 [2023-11-23 21:36:49,397 INFO L750 eck$LassoCheckResult]: Loop: 12860#L1303-2 assume !false; 12934#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12601#L829-1 assume !false; 12897#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12487#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12422#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12565#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12566#L712 assume !(0 != eval_~tmp~0#1); 12827#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12737#L854-3 assume !(0 == ~M_E~0); 12828#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12829#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13077#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13051#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12644#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12645#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12715#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12693#L889-3 assume !(0 == ~T8_E~0); 12316#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12317#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12350#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12351#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12295#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12296#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12339#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12903#L929-3 assume !(0 == ~E_7~0); 12814#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12815#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12922#L418-30 assume 1 == ~m_pc~0; 12179#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12180#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12556#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12557#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12384#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12385#L437-30 assume 1 == ~t1_pc~0; 12508#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12734#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12735#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12772#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13068#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12468#L456-30 assume !(1 == ~t2_pc~0); 12469#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 12895#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12467#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12273#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12274#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12616#L475-30 assume 1 == ~t3_pc~0; 12990#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12144#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12752#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12753#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12491#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12492#L494-30 assume 1 == ~t4_pc~0; 12482#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12083#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12084#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13056#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13006#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13007#L513-30 assume 1 == ~t5_pc~0; 13080#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12622#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12691#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12848#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12914#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12634#L532-30 assume 1 == ~t6_pc~0; 12635#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12224#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12225#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12249#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12305#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12306#L551-30 assume !(1 == ~t7_pc~0); 12358#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 12424#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12904#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12099#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 12100#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12466#L570-30 assume !(1 == ~t8_pc~0); 12820#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 12355#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12356#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12157#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12158#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12537#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12581#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13032#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13033#L962-3 assume !(1 == ~T3_E~0); 12955#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12956#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12875#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12876#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13081#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12523#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12524#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12519#L1002-3 assume !(1 == ~E_2~0); 12520#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12329#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12330#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12431#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12667#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12127#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12128#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12373#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12374#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12490#L1322 assume !(0 == start_simulation_~tmp~3#1); 12551#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12214#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12215#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12131#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 12113#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12114#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12750#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12751#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 12860#L1303-2 [2023-11-23 21:36:49,399 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:49,399 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2023-11-23 21:36:49,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:49,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189378210] [2023-11-23 21:36:49,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:49,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:49,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:49,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:49,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:49,446 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189378210] [2023-11-23 21:36:49,446 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [189378210] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:49,446 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:49,446 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:49,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816511018] [2023-11-23 21:36:49,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:49,447 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:49,447 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:49,447 INFO L85 PathProgramCache]: Analyzing trace with hash 1773359198, now seen corresponding path program 2 times [2023-11-23 21:36:49,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:49,448 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966489085] [2023-11-23 21:36:49,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:49,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:49,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:49,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:49,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:49,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966489085] [2023-11-23 21:36:49,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1966489085] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:49,519 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:49,519 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:49,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209560244] [2023-11-23 21:36:49,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:49,520 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:49,520 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:49,520 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:49,520 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:49,521 INFO L87 Difference]: Start difference. First operand 1002 states and 1485 transitions. cyclomatic complexity: 484 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:49,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:49,548 INFO L93 Difference]: Finished difference Result 1002 states and 1484 transitions. [2023-11-23 21:36:49,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1484 transitions. [2023-11-23 21:36:49,557 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:49,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1484 transitions. [2023-11-23 21:36:49,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-23 21:36:49,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-23 21:36:49,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1484 transitions. [2023-11-23 21:36:49,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:49,570 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2023-11-23 21:36:49,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1484 transitions. [2023-11-23 21:36:49,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-23 21:36:49,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4810379241516967) internal successors, (1484), 1001 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:49,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1484 transitions. [2023-11-23 21:36:49,624 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2023-11-23 21:36:49,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:49,626 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2023-11-23 21:36:49,626 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-23 21:36:49,626 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1484 transitions. [2023-11-23 21:36:49,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:49,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:49,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:49,635 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:49,635 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:49,636 INFO L748 eck$LassoCheckResult]: Stem: 14413#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15038#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15039#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15077#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 14832#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14833#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14430#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14431#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14363#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14364#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14626#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14598#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14599#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14882#L854 assume !(0 == ~M_E~0); 14689#L854-2 assume !(0 == ~T1_E~0); 14690#L859-1 assume !(0 == ~T2_E~0); 14243#L864-1 assume !(0 == ~T3_E~0); 14244#L869-1 assume !(0 == ~T4_E~0); 14354#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15063#L879-1 assume !(0 == ~T6_E~0); 14679#L884-1 assume !(0 == ~T7_E~0); 14106#L889-1 assume !(0 == ~T8_E~0); 14107#L894-1 assume !(0 == ~E_M~0); 14443#L899-1 assume !(0 == ~E_1~0); 14888#L904-1 assume !(0 == ~E_2~0); 14616#L909-1 assume !(0 == ~E_3~0); 14617#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14823#L919-1 assume !(0 == ~E_5~0); 14522#L924-1 assume !(0 == ~E_6~0); 14336#L929-1 assume !(0 == ~E_7~0); 14337#L934-1 assume !(0 == ~E_8~0); 14595#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14123#L418 assume !(1 == ~m_pc~0); 14098#L418-2 is_master_triggered_~__retres1~0#1 := 0; 14097#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14992#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14978#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14911#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14912#L437 assume 1 == ~t1_pc~0; 15080#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14985#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14146#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14147#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 14472#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14968#L456 assume !(1 == ~t2_pc~0); 14394#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14393#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14554#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14555#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 14727#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14237#L475 assume 1 == ~t3_pc~0; 14238#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14301#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14114#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14115#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 14475#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14476#L494 assume !(1 == ~t4_pc~0); 14516#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14517#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14253#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14254#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 14847#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14296#L513 assume 1 == ~t5_pc~0; 14297#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14518#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14994#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14250#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 14251#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14203#L532 assume !(1 == ~t6_pc~0); 14204#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14355#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14536#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14537#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 14447#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14448#L551 assume 1 == ~t7_pc~0; 15005#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14849#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14850#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15089#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 15090#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14637#L570 assume 1 == ~t8_pc~0; 14638#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14753#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14943#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14749#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 14231#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14232#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 14172#L952-2 assume !(1 == ~T1_E~0); 14173#L957-1 assume !(1 == ~T2_E~0); 14949#L962-1 assume !(1 == ~T3_E~0); 14765#L967-1 assume !(1 == ~T4_E~0); 14766#L972-1 assume !(1 == ~T5_E~0); 15008#L977-1 assume !(1 == ~T6_E~0); 15009#L982-1 assume !(1 == ~T7_E~0); 14357#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14358#L992-1 assume !(1 == ~E_M~0); 14365#L997-1 assume !(1 == ~E_1~0); 14725#L1002-1 assume !(1 == ~E_2~0); 14710#L1007-1 assume !(1 == ~E_3~0); 14108#L1012-1 assume !(1 == ~E_4~0); 14109#L1017-1 assume !(1 == ~E_5~0); 14713#L1022-1 assume !(1 == ~E_6~0); 14714#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14739#L1032-1 assume !(1 == ~E_8~0); 14870#L1037-1 assume { :end_inline_reset_delta_events } true; 14871#L1303-2 [2023-11-23 21:36:49,636 INFO L750 eck$LassoCheckResult]: Loop: 14871#L1303-2 assume !false; 14945#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14612#L829-1 assume !false; 14908#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14498#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14433#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14577#L712 assume !(0 != eval_~tmp~0#1); 14838#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14747#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14748#L854-3 assume !(0 == ~M_E~0); 14839#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14840#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15088#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15062#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14655#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14656#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14726#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14704#L889-3 assume !(0 == ~T8_E~0); 14327#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14328#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14361#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14362#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14306#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14307#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14350#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14914#L929-3 assume !(0 == ~E_7~0); 14825#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14826#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14933#L418-30 assume !(1 == ~m_pc~0); 14192#L418-32 is_master_triggered_~__retres1~0#1 := 0; 14191#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14567#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14568#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14395#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14396#L437-30 assume 1 == ~t1_pc~0; 14519#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14745#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14746#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14783#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15079#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14479#L456-30 assume !(1 == ~t2_pc~0); 14480#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 14906#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14478#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14284#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14285#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14627#L475-30 assume 1 == ~t3_pc~0; 15001#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14155#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14763#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14764#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14502#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14503#L494-30 assume !(1 == ~t4_pc~0); 14311#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14094#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14095#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15067#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15017#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15018#L513-30 assume 1 == ~t5_pc~0; 15091#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14633#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14702#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14859#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14925#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14645#L532-30 assume 1 == ~t6_pc~0; 14646#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14235#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14236#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14260#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14316#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14317#L551-30 assume !(1 == ~t7_pc~0); 14369#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 14435#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14915#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14110#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 14111#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14477#L570-30 assume 1 == ~t8_pc~0; 14986#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14366#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14367#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14168#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14169#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14548#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14592#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15043#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15044#L962-3 assume !(1 == ~T3_E~0); 14966#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14967#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14886#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14887#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15092#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14534#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14535#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14530#L1002-3 assume !(1 == ~E_2~0); 14531#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14340#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14341#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14442#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14678#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14138#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14139#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14384#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14385#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14500#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14501#L1322 assume !(0 == start_simulation_~tmp~3#1); 14562#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14225#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14226#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14142#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 14124#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14125#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14761#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14762#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 14871#L1303-2 [2023-11-23 21:36:49,637 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:49,637 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2023-11-23 21:36:49,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:49,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690432846] [2023-11-23 21:36:49,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:49,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:49,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:49,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:49,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:49,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690432846] [2023-11-23 21:36:49,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1690432846] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:49,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:49,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:49,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101423659] [2023-11-23 21:36:49,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:49,704 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:49,705 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:49,705 INFO L85 PathProgramCache]: Analyzing trace with hash 459444767, now seen corresponding path program 1 times [2023-11-23 21:36:49,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:49,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976963897] [2023-11-23 21:36:49,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:49,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:49,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:49,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:49,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:49,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976963897] [2023-11-23 21:36:49,783 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [976963897] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:49,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:49,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:49,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918536672] [2023-11-23 21:36:49,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:49,784 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:49,784 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:49,784 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:49,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:49,785 INFO L87 Difference]: Start difference. First operand 1002 states and 1484 transitions. cyclomatic complexity: 483 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:49,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:49,813 INFO L93 Difference]: Finished difference Result 1002 states and 1483 transitions. [2023-11-23 21:36:49,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1483 transitions. [2023-11-23 21:36:49,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:49,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1483 transitions. [2023-11-23 21:36:49,831 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-23 21:36:49,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-23 21:36:49,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1483 transitions. [2023-11-23 21:36:49,834 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:49,834 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2023-11-23 21:36:49,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1483 transitions. [2023-11-23 21:36:49,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-23 21:36:49,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4800399201596806) internal successors, (1483), 1001 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:49,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1483 transitions. [2023-11-23 21:36:49,859 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2023-11-23 21:36:49,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:49,862 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2023-11-23 21:36:49,862 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-23 21:36:49,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1483 transitions. [2023-11-23 21:36:49,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-23 21:36:49,869 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:49,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:49,871 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:49,871 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:49,872 INFO L748 eck$LassoCheckResult]: Stem: 16424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17088#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 16843#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16844#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16441#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16442#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16374#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16375#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16637#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16609#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16610#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16893#L854 assume !(0 == ~M_E~0); 16700#L854-2 assume !(0 == ~T1_E~0); 16701#L859-1 assume !(0 == ~T2_E~0); 16254#L864-1 assume !(0 == ~T3_E~0); 16255#L869-1 assume !(0 == ~T4_E~0); 16365#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17074#L879-1 assume !(0 == ~T6_E~0); 16690#L884-1 assume !(0 == ~T7_E~0); 16117#L889-1 assume !(0 == ~T8_E~0); 16118#L894-1 assume !(0 == ~E_M~0); 16454#L899-1 assume !(0 == ~E_1~0); 16899#L904-1 assume !(0 == ~E_2~0); 16627#L909-1 assume !(0 == ~E_3~0); 16628#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16834#L919-1 assume !(0 == ~E_5~0); 16533#L924-1 assume !(0 == ~E_6~0); 16347#L929-1 assume !(0 == ~E_7~0); 16348#L934-1 assume !(0 == ~E_8~0); 16606#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16134#L418 assume !(1 == ~m_pc~0); 16109#L418-2 is_master_triggered_~__retres1~0#1 := 0; 16108#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17003#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16989#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16922#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16923#L437 assume 1 == ~t1_pc~0; 17091#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16996#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16158#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 16483#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16979#L456 assume !(1 == ~t2_pc~0); 16405#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16404#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16565#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16566#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 16738#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16248#L475 assume 1 == ~t3_pc~0; 16249#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16312#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16126#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 16486#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16487#L494 assume !(1 == ~t4_pc~0); 16527#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16528#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16264#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16265#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 16858#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16307#L513 assume 1 == ~t5_pc~0; 16308#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16529#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17005#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16261#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 16262#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16214#L532 assume !(1 == ~t6_pc~0); 16215#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16366#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16547#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16548#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 16458#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16459#L551 assume 1 == ~t7_pc~0; 17016#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16860#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16861#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17100#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 17101#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16648#L570 assume 1 == ~t8_pc~0; 16649#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16764#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16954#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16760#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 16242#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16243#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 16183#L952-2 assume !(1 == ~T1_E~0); 16184#L957-1 assume !(1 == ~T2_E~0); 16960#L962-1 assume !(1 == ~T3_E~0); 16776#L967-1 assume !(1 == ~T4_E~0); 16777#L972-1 assume !(1 == ~T5_E~0); 17019#L977-1 assume !(1 == ~T6_E~0); 17020#L982-1 assume !(1 == ~T7_E~0); 16368#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16369#L992-1 assume !(1 == ~E_M~0); 16376#L997-1 assume !(1 == ~E_1~0); 16736#L1002-1 assume !(1 == ~E_2~0); 16721#L1007-1 assume !(1 == ~E_3~0); 16119#L1012-1 assume !(1 == ~E_4~0); 16120#L1017-1 assume !(1 == ~E_5~0); 16724#L1022-1 assume !(1 == ~E_6~0); 16725#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16750#L1032-1 assume !(1 == ~E_8~0); 16881#L1037-1 assume { :end_inline_reset_delta_events } true; 16882#L1303-2 [2023-11-23 21:36:49,872 INFO L750 eck$LassoCheckResult]: Loop: 16882#L1303-2 assume !false; 16956#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16623#L829-1 assume !false; 16919#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16509#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16444#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16587#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16588#L712 assume !(0 != eval_~tmp~0#1); 16849#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16758#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16759#L854-3 assume !(0 == ~M_E~0); 16850#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16851#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17099#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17073#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16666#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16667#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16737#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16715#L889-3 assume !(0 == ~T8_E~0); 16338#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16339#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16372#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16373#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16317#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16318#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16361#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16925#L929-3 assume !(0 == ~E_7~0); 16836#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16837#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16944#L418-30 assume 1 == ~m_pc~0; 16201#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16202#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16578#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16579#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16406#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16407#L437-30 assume 1 == ~t1_pc~0; 16530#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16756#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16757#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16794#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17090#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16490#L456-30 assume !(1 == ~t2_pc~0); 16491#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 16917#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16489#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16295#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16296#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16638#L475-30 assume 1 == ~t3_pc~0; 17012#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16166#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16774#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16775#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16513#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16514#L494-30 assume !(1 == ~t4_pc~0); 16322#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 16105#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16106#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17078#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17028#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17029#L513-30 assume !(1 == ~t5_pc~0); 16643#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 16644#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16713#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16870#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16936#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16656#L532-30 assume 1 == ~t6_pc~0; 16657#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16246#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16247#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16271#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16327#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16328#L551-30 assume !(1 == ~t7_pc~0); 16380#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 16446#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16926#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16121#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 16122#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16488#L570-30 assume 1 == ~t8_pc~0; 16997#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16377#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16378#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16179#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16180#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16559#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16603#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17054#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17055#L962-3 assume !(1 == ~T3_E~0); 16977#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16978#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16897#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16898#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17103#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16545#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16546#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16541#L1002-3 assume !(1 == ~E_2~0); 16542#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16351#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16352#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16453#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16689#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16149#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16150#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16395#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16396#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16511#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 16512#L1322 assume !(0 == start_simulation_~tmp~3#1); 16573#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16236#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16237#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16153#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 16135#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16136#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16772#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16773#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 16882#L1303-2 [2023-11-23 21:36:49,873 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:49,873 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2023-11-23 21:36:49,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:49,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052740766] [2023-11-23 21:36:49,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:49,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:49,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:49,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:49,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:49,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052740766] [2023-11-23 21:36:49,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052740766] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:49,964 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:49,964 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:49,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711853572] [2023-11-23 21:36:49,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:49,965 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:49,965 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:49,966 INFO L85 PathProgramCache]: Analyzing trace with hash 568502751, now seen corresponding path program 2 times [2023-11-23 21:36:49,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:49,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45381023] [2023-11-23 21:36:49,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:49,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:49,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:50,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:50,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:50,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45381023] [2023-11-23 21:36:50,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [45381023] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:50,021 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:50,021 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:50,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56906917] [2023-11-23 21:36:50,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:50,022 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:50,022 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:50,023 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 21:36:50,023 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 21:36:50,023 INFO L87 Difference]: Start difference. First operand 1002 states and 1483 transitions. cyclomatic complexity: 482 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:50,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:50,204 INFO L93 Difference]: Finished difference Result 1824 states and 2689 transitions. [2023-11-23 21:36:50,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1824 states and 2689 transitions. [2023-11-23 21:36:50,221 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1691 [2023-11-23 21:36:50,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1824 states to 1824 states and 2689 transitions. [2023-11-23 21:36:50,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1824 [2023-11-23 21:36:50,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1824 [2023-11-23 21:36:50,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1824 states and 2689 transitions. [2023-11-23 21:36:50,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:50,244 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2023-11-23 21:36:50,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1824 states and 2689 transitions. [2023-11-23 21:36:50,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1824 to 1824. [2023-11-23 21:36:50,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1824 states, 1824 states have (on average 1.4742324561403508) internal successors, (2689), 1823 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:50,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1824 states to 1824 states and 2689 transitions. [2023-11-23 21:36:50,333 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2023-11-23 21:36:50,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 21:36:50,335 INFO L428 stractBuchiCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2023-11-23 21:36:50,336 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-23 21:36:50,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1824 states and 2689 transitions. [2023-11-23 21:36:50,348 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1691 [2023-11-23 21:36:50,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:50,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:50,350 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:50,351 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:50,351 INFO L748 eck$LassoCheckResult]: Stem: 19262#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19263#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 19933#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19934#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19980#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 19692#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19693#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19279#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19280#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19211#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19212#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19481#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19451#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19452#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19747#L854 assume !(0 == ~M_E~0); 19547#L854-2 assume !(0 == ~T1_E~0); 19548#L859-1 assume !(0 == ~T2_E~0); 19090#L864-1 assume !(0 == ~T3_E~0); 19091#L869-1 assume !(0 == ~T4_E~0); 19202#L874-1 assume !(0 == ~T5_E~0); 19965#L879-1 assume !(0 == ~T6_E~0); 19537#L884-1 assume !(0 == ~T7_E~0); 18953#L889-1 assume !(0 == ~T8_E~0); 18954#L894-1 assume !(0 == ~E_M~0); 19292#L899-1 assume !(0 == ~E_1~0); 19753#L904-1 assume !(0 == ~E_2~0); 19470#L909-1 assume !(0 == ~E_3~0); 19471#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19683#L919-1 assume !(0 == ~E_5~0); 19373#L924-1 assume !(0 == ~E_6~0); 19184#L929-1 assume !(0 == ~E_7~0); 19185#L934-1 assume !(0 == ~E_8~0); 19448#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18970#L418 assume !(1 == ~m_pc~0); 18945#L418-2 is_master_triggered_~__retres1~0#1 := 0; 18944#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19877#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19861#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19781#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19782#L437 assume 1 == ~t1_pc~0; 19985#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19869#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18993#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18994#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 19322#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19851#L456 assume !(1 == ~t2_pc~0); 19243#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19242#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19408#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 19585#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19084#L475 assume 1 == ~t3_pc~0; 19085#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19149#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18961#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18962#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 19325#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19326#L494 assume !(1 == ~t4_pc~0); 19367#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19368#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19100#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19101#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 19708#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19143#L513 assume 1 == ~t5_pc~0; 19144#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19369#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19879#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19097#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 19098#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19050#L532 assume !(1 == ~t6_pc~0); 19051#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19203#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19388#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19389#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 19297#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19298#L551 assume 1 == ~t7_pc~0; 19892#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19710#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19711#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19994#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 19995#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19492#L570 assume 1 == ~t8_pc~0; 19493#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19611#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19819#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19607#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 19078#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19079#L952 assume !(1 == ~M_E~0); 19019#L952-2 assume !(1 == ~T1_E~0); 19020#L957-1 assume !(1 == ~T2_E~0); 20076#L962-1 assume !(1 == ~T3_E~0); 20074#L967-1 assume !(1 == ~T4_E~0); 20073#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19895#L977-1 assume !(1 == ~T6_E~0); 19896#L982-1 assume !(1 == ~T7_E~0); 19205#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19206#L992-1 assume !(1 == ~E_M~0); 19213#L997-1 assume !(1 == ~E_1~0); 19583#L1002-1 assume !(1 == ~E_2~0); 19568#L1007-1 assume !(1 == ~E_3~0); 18955#L1012-1 assume !(1 == ~E_4~0); 18956#L1017-1 assume !(1 == ~E_5~0); 19571#L1022-1 assume !(1 == ~E_6~0); 19572#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19597#L1032-1 assume !(1 == ~E_8~0); 19734#L1037-1 assume { :end_inline_reset_delta_events } true; 19735#L1303-2 [2023-11-23 21:36:50,352 INFO L750 eck$LassoCheckResult]: Loop: 19735#L1303-2 assume !false; 19862#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19466#L829-1 assume !false; 19999#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20008#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19897#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19898#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20003#L712 assume !(0 != eval_~tmp~0#1); 19823#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19605#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19606#L854-3 assume !(0 == ~M_E~0); 20001#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20585#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20584#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20583#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20582#L874-3 assume !(0 == ~T5_E~0); 20581#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20580#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20579#L889-3 assume !(0 == ~T8_E~0); 20578#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20577#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20576#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20575#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20574#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20573#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20572#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20571#L929-3 assume !(0 == ~E_7~0); 20570#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20569#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20568#L418-30 assume 1 == ~m_pc~0; 20566#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20565#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20564#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20563#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20562#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20561#L437-30 assume !(1 == ~t1_pc~0); 20560#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 20558#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20557#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20556#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20555#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20554#L456-30 assume !(1 == ~t2_pc~0); 20552#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 20551#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20550#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20549#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20548#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20547#L475-30 assume 1 == ~t3_pc~0; 20545#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20544#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20543#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20542#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20541#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20540#L494-30 assume !(1 == ~t4_pc~0); 20538#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 20537#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20536#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20535#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20534#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20533#L513-30 assume 1 == ~t5_pc~0; 20531#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20530#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20529#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20528#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20527#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20526#L532-30 assume !(1 == ~t6_pc~0); 20524#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 20523#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20522#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20521#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20520#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20519#L551-30 assume 1 == ~t7_pc~0; 20517#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20516#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20515#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18957#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 18958#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19327#L570-30 assume !(1 == ~t8_pc~0); 19691#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 19214#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19215#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19015#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19016#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19401#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19445#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19938#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19939#L962-3 assume !(1 == ~T3_E~0); 19848#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19849#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19751#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19752#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19998#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19386#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19387#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19382#L1002-3 assume !(1 == ~E_2~0); 19383#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19188#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19189#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19291#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19536#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18985#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18986#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19233#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19234#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20199#L1322 assume !(0 == start_simulation_~tmp~3#1); 19771#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20088#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19940#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18989#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 18971#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18972#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20060#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19900#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 19735#L1303-2 [2023-11-23 21:36:50,353 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:50,353 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2023-11-23 21:36:50,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:50,353 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31508444] [2023-11-23 21:36:50,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:50,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:50,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:50,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:50,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:50,437 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31508444] [2023-11-23 21:36:50,437 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [31508444] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:50,437 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:50,437 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:50,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110322015] [2023-11-23 21:36:50,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:50,439 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:50,440 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:50,440 INFO L85 PathProgramCache]: Analyzing trace with hash -1829389214, now seen corresponding path program 1 times [2023-11-23 21:36:50,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:50,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780006663] [2023-11-23 21:36:50,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:50,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:50,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:50,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:50,495 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:50,495 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780006663] [2023-11-23 21:36:50,495 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [780006663] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:50,496 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:50,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:50,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [125141320] [2023-11-23 21:36:50,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:50,497 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:50,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:50,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 21:36:50,498 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 21:36:50,498 INFO L87 Difference]: Start difference. First operand 1824 states and 2689 transitions. cyclomatic complexity: 867 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:50,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:50,722 INFO L93 Difference]: Finished difference Result 3322 states and 4884 transitions. [2023-11-23 21:36:50,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3322 states and 4884 transitions. [2023-11-23 21:36:50,747 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3169 [2023-11-23 21:36:50,779 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3322 states to 3322 states and 4884 transitions. [2023-11-23 21:36:50,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3322 [2023-11-23 21:36:50,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3322 [2023-11-23 21:36:50,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3322 states and 4884 transitions. [2023-11-23 21:36:50,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:50,792 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3322 states and 4884 transitions. [2023-11-23 21:36:50,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3322 states and 4884 transitions. [2023-11-23 21:36:50,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3322 to 3320. [2023-11-23 21:36:50,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3320 states, 3320 states have (on average 1.4704819277108434) internal successors, (4882), 3319 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:50,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3320 states to 3320 states and 4882 transitions. [2023-11-23 21:36:50,890 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3320 states and 4882 transitions. [2023-11-23 21:36:50,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 21:36:50,891 INFO L428 stractBuchiCegarLoop]: Abstraction has 3320 states and 4882 transitions. [2023-11-23 21:36:50,892 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-23 21:36:50,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3320 states and 4882 transitions. [2023-11-23 21:36:50,908 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3169 [2023-11-23 21:36:50,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:50,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:50,911 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:50,911 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:50,911 INFO L748 eck$LassoCheckResult]: Stem: 24421#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24422#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25092#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25093#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25141#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 24856#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24857#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24438#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24439#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24371#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24372#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24643#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24615#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24616#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24910#L854 assume !(0 == ~M_E~0); 24709#L854-2 assume !(0 == ~T1_E~0); 24710#L859-1 assume !(0 == ~T2_E~0); 24250#L864-1 assume !(0 == ~T3_E~0); 24251#L869-1 assume !(0 == ~T4_E~0); 24362#L874-1 assume !(0 == ~T5_E~0); 25125#L879-1 assume !(0 == ~T6_E~0); 24699#L884-1 assume !(0 == ~T7_E~0); 24109#L889-1 assume !(0 == ~T8_E~0); 24110#L894-1 assume !(0 == ~E_M~0); 24453#L899-1 assume !(0 == ~E_1~0); 24916#L904-1 assume !(0 == ~E_2~0); 24633#L909-1 assume !(0 == ~E_3~0); 24634#L914-1 assume !(0 == ~E_4~0); 24846#L919-1 assume !(0 == ~E_5~0); 24536#L924-1 assume !(0 == ~E_6~0); 24344#L929-1 assume !(0 == ~E_7~0); 24345#L934-1 assume !(0 == ~E_8~0); 24612#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24127#L418 assume !(1 == ~m_pc~0); 24101#L418-2 is_master_triggered_~__retres1~0#1 := 0; 24100#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25035#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25020#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24940#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24941#L437 assume 1 == ~t1_pc~0; 25148#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25027#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24150#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24151#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 24484#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25008#L456 assume !(1 == ~t2_pc~0); 24402#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24401#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24570#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24571#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 24749#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24244#L475 assume 1 == ~t3_pc~0; 24245#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24309#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24118#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24119#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 24487#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24488#L494 assume !(1 == ~t4_pc~0); 24530#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24531#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24260#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24261#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 24871#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24304#L513 assume 1 == ~t5_pc~0; 24305#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24532#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25037#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24257#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 24258#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24208#L532 assume !(1 == ~t6_pc~0); 24209#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24363#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24552#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24553#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 24459#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24460#L551 assume 1 == ~t7_pc~0; 25050#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24875#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24876#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25167#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 25168#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24656#L570 assume 1 == ~t8_pc~0; 24657#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24776#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24981#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24772#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 24238#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24239#L952 assume !(1 == ~M_E~0); 25031#L952-2 assume !(1 == ~T1_E~0); 24987#L957-1 assume !(1 == ~T2_E~0); 24988#L962-1 assume !(1 == ~T3_E~0); 24788#L967-1 assume !(1 == ~T4_E~0); 24789#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25615#L977-1 assume !(1 == ~T6_E~0); 25613#L982-1 assume !(1 == ~T7_E~0); 25611#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25609#L992-1 assume !(1 == ~E_M~0); 24746#L997-1 assume !(1 == ~E_1~0); 24747#L1002-1 assume !(1 == ~E_2~0); 24730#L1007-1 assume !(1 == ~E_3~0); 24731#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25277#L1017-1 assume !(1 == ~E_5~0); 25251#L1022-1 assume !(1 == ~E_6~0); 25235#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25223#L1032-1 assume !(1 == ~E_8~0); 25214#L1037-1 assume { :end_inline_reset_delta_events } true; 25207#L1303-2 [2023-11-23 21:36:50,912 INFO L750 eck$LassoCheckResult]: Loop: 25207#L1303-2 assume !false; 25201#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25197#L829-1 assume !false; 25196#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25191#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25186#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25185#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25183#L712 assume !(0 != eval_~tmp~0#1); 25182#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25181#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25180#L854-3 assume !(0 == ~M_E~0); 24863#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24864#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25163#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25122#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24674#L874-3 assume !(0 == ~T5_E~0); 24675#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24748#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24724#L889-3 assume !(0 == ~T8_E~0); 24335#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24336#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24369#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24370#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24314#L914-3 assume !(0 == ~E_4~0); 24315#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24358#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24943#L929-3 assume !(0 == ~E_7~0); 24849#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24850#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24967#L418-30 assume 1 == ~m_pc~0; 24195#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24196#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24583#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24584#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24403#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24404#L437-30 assume 1 == ~t1_pc~0; 24533#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24768#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24769#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24806#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25157#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26466#L456-30 assume !(1 == ~t2_pc~0); 26462#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 26460#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26458#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26456#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26454#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26452#L475-30 assume 1 == ~t3_pc~0; 26448#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26446#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26444#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26442#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26440#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26438#L494-30 assume !(1 == ~t4_pc~0); 26434#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 26432#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26430#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26428#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26426#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26424#L513-30 assume 1 == ~t5_pc~0; 26420#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26418#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26416#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26414#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26412#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26410#L532-30 assume !(1 == ~t6_pc~0); 26406#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 26404#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26402#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26400#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26398#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26397#L551-30 assume 1 == ~t7_pc~0; 26392#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26390#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26388#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26387#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 26386#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26385#L570-30 assume !(1 == ~t8_pc~0); 26384#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 26382#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26381#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26380#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26379#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26378#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24608#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26377#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26376#L962-3 assume !(1 == ~T3_E~0); 26374#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26373#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25120#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26369#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26367#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26365#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26363#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26361#L1002-3 assume !(1 == ~E_2~0); 24873#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24874#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25698#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25692#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25686#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25680#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25677#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25667#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25654#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25648#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 25642#L1322 assume !(0 == start_simulation_~tmp~3#1); 24930#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25346#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25315#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25281#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 25253#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25236#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25224#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25215#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 25207#L1303-2 [2023-11-23 21:36:50,913 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:50,913 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2023-11-23 21:36:50,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:50,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841819761] [2023-11-23 21:36:50,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:50,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:50,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:51,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:51,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:51,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841819761] [2023-11-23 21:36:51,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [841819761] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:51,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:51,033 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 21:36:51,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406082738] [2023-11-23 21:36:51,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:51,035 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:51,035 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:51,035 INFO L85 PathProgramCache]: Analyzing trace with hash 1462023267, now seen corresponding path program 1 times [2023-11-23 21:36:51,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:51,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635801221] [2023-11-23 21:36:51,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:51,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:51,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:51,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:51,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:51,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635801221] [2023-11-23 21:36:51,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1635801221] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:51,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:51,114 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:51,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806728776] [2023-11-23 21:36:51,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:51,114 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:51,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:51,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 21:36:51,116 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 21:36:51,116 INFO L87 Difference]: Start difference. First operand 3320 states and 4882 transitions. cyclomatic complexity: 1566 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:51,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:51,533 INFO L93 Difference]: Finished difference Result 8767 states and 12715 transitions. [2023-11-23 21:36:51,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8767 states and 12715 transitions. [2023-11-23 21:36:51,591 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8444 [2023-11-23 21:36:51,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8767 states to 8767 states and 12715 transitions. [2023-11-23 21:36:51,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8767 [2023-11-23 21:36:51,674 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8767 [2023-11-23 21:36:51,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8767 states and 12715 transitions. [2023-11-23 21:36:51,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:51,686 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8767 states and 12715 transitions. [2023-11-23 21:36:51,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8767 states and 12715 transitions. [2023-11-23 21:36:51,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8767 to 3440. [2023-11-23 21:36:51,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3440 states, 3440 states have (on average 1.4540697674418606) internal successors, (5002), 3439 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:51,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3440 states to 3440 states and 5002 transitions. [2023-11-23 21:36:51,805 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3440 states and 5002 transitions. [2023-11-23 21:36:51,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-23 21:36:51,806 INFO L428 stractBuchiCegarLoop]: Abstraction has 3440 states and 5002 transitions. [2023-11-23 21:36:51,806 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-23 21:36:51,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3440 states and 5002 transitions. [2023-11-23 21:36:51,822 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3286 [2023-11-23 21:36:51,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:51,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:51,824 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:51,825 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:51,825 INFO L748 eck$LassoCheckResult]: Stem: 36518#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 36519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 37200#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37201#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37253#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 36951#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36952#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36536#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36537#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36470#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36471#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36733#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36705#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36706#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37007#L854 assume !(0 == ~M_E~0); 36800#L854-2 assume !(0 == ~T1_E~0); 36801#L859-1 assume !(0 == ~T2_E~0); 36347#L864-1 assume !(0 == ~T3_E~0); 36348#L869-1 assume !(0 == ~T4_E~0); 36459#L874-1 assume !(0 == ~T5_E~0); 37236#L879-1 assume !(0 == ~T6_E~0); 36789#L884-1 assume !(0 == ~T7_E~0); 36209#L889-1 assume !(0 == ~T8_E~0); 36210#L894-1 assume !(0 == ~E_M~0); 36550#L899-1 assume !(0 == ~E_1~0); 37013#L904-1 assume !(0 == ~E_2~0); 36724#L909-1 assume !(0 == ~E_3~0); 36725#L914-1 assume !(0 == ~E_4~0); 36942#L919-1 assume !(0 == ~E_5~0); 36627#L924-1 assume !(0 == ~E_6~0); 36445#L929-1 assume !(0 == ~E_7~0); 36446#L934-1 assume !(0 == ~E_8~0); 36702#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36227#L418 assume !(1 == ~m_pc~0); 36201#L418-2 is_master_triggered_~__retres1~0#1 := 0; 37185#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37186#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37123#L1061 assume !(0 != activate_threads_~tmp~1#1); 37040#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37041#L437 assume 1 == ~t1_pc~0; 37259#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37130#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36253#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36254#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 36577#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37112#L456 assume !(1 == ~t2_pc~0); 36499#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36498#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36659#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36660#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 36840#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36341#L475 assume 1 == ~t3_pc~0; 36342#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36407#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36218#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36219#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 36580#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36581#L494 assume !(1 == ~t4_pc~0); 36621#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36622#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36357#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36358#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 36966#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36400#L513 assume 1 == ~t5_pc~0; 36401#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36624#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37143#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36354#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 36355#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36307#L532 assume !(1 == ~t6_pc~0); 36308#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36460#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36641#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36642#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 36552#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36553#L551 assume 1 == ~t7_pc~0; 37157#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36968#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36969#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37279#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 37282#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36744#L570 assume 1 == ~t8_pc~0; 36745#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36866#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37082#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36864#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 36339#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36340#L952 assume !(1 == ~M_E~0); 36276#L952-2 assume !(1 == ~T1_E~0); 36277#L957-1 assume !(1 == ~T2_E~0); 37261#L962-1 assume !(1 == ~T3_E~0); 37262#L967-1 assume !(1 == ~T4_E~0); 37254#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37160#L977-1 assume !(1 == ~T6_E~0); 37161#L982-1 assume !(1 == ~T7_E~0); 36462#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36463#L992-1 assume !(1 == ~E_M~0); 36472#L997-1 assume !(1 == ~E_1~0); 36838#L1002-1 assume !(1 == ~E_2~0); 37395#L1007-1 assume !(1 == ~E_3~0); 37380#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 37378#L1017-1 assume !(1 == ~E_5~0); 37365#L1022-1 assume !(1 == ~E_6~0); 37352#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37340#L1032-1 assume !(1 == ~E_8~0); 37331#L1037-1 assume { :end_inline_reset_delta_events } true; 37324#L1303-2 [2023-11-23 21:36:51,826 INFO L750 eck$LassoCheckResult]: Loop: 37324#L1303-2 assume !false; 37318#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37314#L829-1 assume !false; 37313#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37308#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37303#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37302#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37300#L712 assume !(0 != eval_~tmp~0#1); 37299#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37298#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37297#L854-3 assume !(0 == ~M_E~0); 36958#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36959#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37276#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37235#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36762#L874-3 assume !(0 == ~T5_E~0); 36763#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36839#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36816#L889-3 assume !(0 == ~T8_E~0); 36431#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36432#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36466#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36467#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36410#L914-3 assume !(0 == ~E_4~0); 36411#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36455#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37043#L929-3 assume !(0 == ~E_7~0); 36944#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36945#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37162#L418-30 assume 1 == ~m_pc~0; 36298#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36299#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39582#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39581#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36500#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36501#L437-30 assume 1 == ~t1_pc~0; 36625#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36858#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36859#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36900#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37258#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36587#L456-30 assume !(1 == ~t2_pc~0); 36588#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 37035#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36583#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36391#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36392#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36734#L475-30 assume 1 == ~t3_pc~0; 39153#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39151#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39149#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39147#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39144#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39142#L494-30 assume !(1 == ~t4_pc~0); 39139#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 38777#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38773#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38767#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38763#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38750#L513-30 assume 1 == ~t5_pc~0; 38745#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38741#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38736#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38730#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38726#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38723#L532-30 assume !(1 == ~t6_pc~0); 38710#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 38706#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38701#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38695#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38691#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38687#L551-30 assume 1 == ~t7_pc~0; 38682#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38679#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38675#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38573#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 38568#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38564#L570-30 assume 1 == ~t8_pc~0; 38557#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38553#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38549#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38546#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37505#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37504#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36698#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37503#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37502#L962-3 assume !(1 == ~T3_E~0); 37501#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37499#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37496#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37495#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37494#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37493#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37492#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37491#L1002-3 assume !(1 == ~E_2~0); 37490#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37489#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37486#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37485#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37484#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37455#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37454#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37453#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37443#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37440#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 37435#L1322 assume !(0 == start_simulation_~tmp~3#1); 37030#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37415#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37393#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37379#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 37366#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37353#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37341#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 37332#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 37324#L1303-2 [2023-11-23 21:36:51,827 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:51,827 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2023-11-23 21:36:51,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:51,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442958995] [2023-11-23 21:36:51,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:51,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:51,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:51,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:51,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:51,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442958995] [2023-11-23 21:36:51,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [442958995] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:51,908 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:51,908 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 21:36:51,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [426777108] [2023-11-23 21:36:51,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:51,910 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:51,910 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:51,910 INFO L85 PathProgramCache]: Analyzing trace with hash 336763298, now seen corresponding path program 1 times [2023-11-23 21:36:51,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:51,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [701836803] [2023-11-23 21:36:51,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:51,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:51,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:51,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:51,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:51,992 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [701836803] [2023-11-23 21:36:51,993 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [701836803] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:51,993 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:51,993 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:51,993 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860477606] [2023-11-23 21:36:51,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:51,994 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:51,994 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:51,994 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:51,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:51,995 INFO L87 Difference]: Start difference. First operand 3440 states and 5002 transitions. cyclomatic complexity: 1566 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:52,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:52,114 INFO L93 Difference]: Finished difference Result 6414 states and 9260 transitions. [2023-11-23 21:36:52,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6414 states and 9260 transitions. [2023-11-23 21:36:52,154 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6253 [2023-11-23 21:36:52,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6414 states to 6414 states and 9260 transitions. [2023-11-23 21:36:52,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6414 [2023-11-23 21:36:52,203 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6414 [2023-11-23 21:36:52,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6414 states and 9260 transitions. [2023-11-23 21:36:52,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:52,213 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6414 states and 9260 transitions. [2023-11-23 21:36:52,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6414 states and 9260 transitions. [2023-11-23 21:36:52,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6414 to 6406. [2023-11-23 21:36:52,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6406 states, 6406 states have (on average 1.444270995941305) internal successors, (9252), 6405 states have internal predecessors, (9252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:52,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6406 states to 6406 states and 9252 transitions. [2023-11-23 21:36:52,410 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6406 states and 9252 transitions. [2023-11-23 21:36:52,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:52,412 INFO L428 stractBuchiCegarLoop]: Abstraction has 6406 states and 9252 transitions. [2023-11-23 21:36:52,412 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-23 21:36:52,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6406 states and 9252 transitions. [2023-11-23 21:36:52,442 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6245 [2023-11-23 21:36:52,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:52,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:52,444 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:52,444 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:52,445 INFO L748 eck$LassoCheckResult]: Stem: 46381#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 46382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 47149#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47150#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47230#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 46846#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46847#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46398#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46399#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46328#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46329#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46608#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46576#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46577#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46923#L854 assume !(0 == ~M_E~0); 46682#L854-2 assume !(0 == ~T1_E~0); 46683#L859-1 assume !(0 == ~T2_E~0); 46207#L864-1 assume !(0 == ~T3_E~0); 46208#L869-1 assume !(0 == ~T4_E~0); 46319#L874-1 assume !(0 == ~T5_E~0); 47205#L879-1 assume !(0 == ~T6_E~0); 46671#L884-1 assume !(0 == ~T7_E~0); 46070#L889-1 assume !(0 == ~T8_E~0); 46071#L894-1 assume !(0 == ~E_M~0); 46412#L899-1 assume !(0 == ~E_1~0); 46929#L904-1 assume !(0 == ~E_2~0); 46597#L909-1 assume !(0 == ~E_3~0); 46598#L914-1 assume !(0 == ~E_4~0); 46834#L919-1 assume !(0 == ~E_5~0); 46495#L924-1 assume !(0 == ~E_6~0); 46301#L929-1 assume !(0 == ~E_7~0); 46302#L934-1 assume !(0 == ~E_8~0); 46573#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46087#L418 assume !(1 == ~m_pc~0); 46062#L418-2 is_master_triggered_~__retres1~0#1 := 0; 47128#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47072#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47053#L1061 assume !(0 != activate_threads_~tmp~1#1); 46957#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46958#L437 assume !(1 == ~t1_pc~0); 47189#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47061#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46110#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46111#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 46443#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47041#L456 assume !(1 == ~t2_pc~0); 46360#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46359#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46530#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46531#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 46723#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46201#L475 assume 1 == ~t3_pc~0; 46202#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46266#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46078#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46079#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 46446#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46447#L494 assume !(1 == ~t4_pc~0); 46490#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46491#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46217#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46218#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 46862#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46260#L513 assume 1 == ~t5_pc~0; 46261#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46492#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47075#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46214#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 46215#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46167#L532 assume !(1 == ~t6_pc~0); 46168#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46320#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46512#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46513#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 46418#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46419#L551 assume 1 == ~t7_pc~0; 47091#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46867#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46868#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47255#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 47262#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46623#L570 assume 1 == ~t8_pc~0; 46624#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46752#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47005#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46747#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 46195#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46196#L952 assume !(1 == ~M_E~0); 47065#L952-2 assume !(1 == ~T1_E~0); 47018#L957-1 assume !(1 == ~T2_E~0); 47019#L962-1 assume !(1 == ~T3_E~0); 46766#L967-1 assume !(1 == ~T4_E~0); 46767#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49632#L977-1 assume !(1 == ~T6_E~0); 49631#L982-1 assume !(1 == ~T7_E~0); 49630#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49629#L992-1 assume !(1 == ~E_M~0); 49627#L997-1 assume !(1 == ~E_1~0); 49625#L1002-1 assume !(1 == ~E_2~0); 49623#L1007-1 assume !(1 == ~E_3~0); 49598#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 46073#L1017-1 assume !(1 == ~E_5~0); 51743#L1022-1 assume !(1 == ~E_6~0); 51742#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 51741#L1032-1 assume !(1 == ~E_8~0); 51739#L1037-1 assume { :end_inline_reset_delta_events } true; 51738#L1303-2 [2023-11-23 21:36:52,445 INFO L750 eck$LassoCheckResult]: Loop: 51738#L1303-2 assume !false; 47722#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46593#L829-1 assume !false; 47718#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 47719#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 47581#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 47582#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 47573#L712 assume !(0 != eval_~tmp~0#1); 47575#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46745#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46746#L854-3 assume !(0 == ~M_E~0); 46854#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46855#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47249#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47201#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46643#L874-3 assume !(0 == ~T5_E~0); 46644#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49980#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49949#L889-3 assume !(0 == ~T8_E~0); 49939#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49938#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49937#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49936#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49935#L914-3 assume !(0 == ~E_4~0); 49934#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49933#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49932#L929-3 assume !(0 == ~E_7~0); 49931#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49930#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49929#L418-30 assume !(1 == ~m_pc~0); 49927#L418-32 is_master_triggered_~__retres1~0#1 := 0; 49925#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49923#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49922#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 49920#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49919#L437-30 assume !(1 == ~t1_pc~0); 49918#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 49917#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49916#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49915#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49914#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49913#L456-30 assume !(1 == ~t2_pc~0); 49911#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 49910#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49909#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49908#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49907#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49906#L475-30 assume 1 == ~t3_pc~0; 49904#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49903#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49902#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49901#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49900#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49899#L494-30 assume !(1 == ~t4_pc~0); 49897#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 49896#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49895#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49894#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49893#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49892#L513-30 assume 1 == ~t5_pc~0; 49890#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49889#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49888#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49887#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49886#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49885#L532-30 assume !(1 == ~t6_pc~0); 49883#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 49882#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49881#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49880#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49879#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49878#L551-30 assume 1 == ~t7_pc~0; 49876#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49875#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49874#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49873#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 49872#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49869#L570-30 assume 1 == ~t8_pc~0; 49870#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52332#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52331#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52330#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52329#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52328#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46569#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52327#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52326#L962-3 assume !(1 == ~T3_E~0); 52325#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52324#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47193#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52323#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52322#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52321#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 52320#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52319#L1002-3 assume !(1 == ~E_2~0); 52318#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 52317#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49758#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52316#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52315#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52314#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47916#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 47917#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 52305#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 52304#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 52303#L1322 assume !(0 == start_simulation_~tmp~3#1); 47760#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 52298#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 52293#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 52292#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 52291#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 52290#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52289#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 51740#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 51738#L1303-2 [2023-11-23 21:36:52,446 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:52,447 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2023-11-23 21:36:52,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:52,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585353290] [2023-11-23 21:36:52,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:52,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:52,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:52,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:52,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:52,511 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585353290] [2023-11-23 21:36:52,511 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585353290] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:52,511 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:52,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 21:36:52,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1877329117] [2023-11-23 21:36:52,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:52,513 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:52,513 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:52,514 INFO L85 PathProgramCache]: Analyzing trace with hash 1419678694, now seen corresponding path program 1 times [2023-11-23 21:36:52,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:52,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930743802] [2023-11-23 21:36:52,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:52,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:52,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:52,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:52,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:52,566 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930743802] [2023-11-23 21:36:52,566 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930743802] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:52,566 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:52,566 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:52,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140576047] [2023-11-23 21:36:52,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:52,568 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:52,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:52,569 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:52,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:52,570 INFO L87 Difference]: Start difference. First operand 6406 states and 9252 transitions. cyclomatic complexity: 2854 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:52,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:52,755 INFO L93 Difference]: Finished difference Result 12302 states and 17640 transitions. [2023-11-23 21:36:52,755 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12302 states and 17640 transitions. [2023-11-23 21:36:52,841 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12126 [2023-11-23 21:36:52,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12302 states to 12302 states and 17640 transitions. [2023-11-23 21:36:52,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12302 [2023-11-23 21:36:52,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12302 [2023-11-23 21:36:52,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12302 states and 17640 transitions. [2023-11-23 21:36:52,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:52,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12302 states and 17640 transitions. [2023-11-23 21:36:52,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12302 states and 17640 transitions. [2023-11-23 21:36:53,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12302 to 12286. [2023-11-23 21:36:53,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12286 states, 12286 states have (on average 1.434478267947257) internal successors, (17624), 12285 states have internal predecessors, (17624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:53,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12286 states to 12286 states and 17624 transitions. [2023-11-23 21:36:53,162 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12286 states and 17624 transitions. [2023-11-23 21:36:53,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:53,163 INFO L428 stractBuchiCegarLoop]: Abstraction has 12286 states and 17624 transitions. [2023-11-23 21:36:53,164 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-23 21:36:53,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12286 states and 17624 transitions. [2023-11-23 21:36:53,214 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12110 [2023-11-23 21:36:53,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:53,215 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:53,217 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:53,217 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:53,218 INFO L748 eck$LassoCheckResult]: Stem: 65095#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 65096#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 65817#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65818#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65898#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 65543#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65544#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65111#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65112#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65042#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65043#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65317#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65287#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65288#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65608#L854 assume !(0 == ~M_E~0); 65385#L854-2 assume !(0 == ~T1_E~0); 65386#L859-1 assume !(0 == ~T2_E~0); 64920#L864-1 assume !(0 == ~T3_E~0); 64921#L869-1 assume !(0 == ~T4_E~0); 65033#L874-1 assume !(0 == ~T5_E~0); 65871#L879-1 assume !(0 == ~T6_E~0); 65375#L884-1 assume !(0 == ~T7_E~0); 64785#L889-1 assume !(0 == ~T8_E~0); 64786#L894-1 assume !(0 == ~E_M~0); 65125#L899-1 assume !(0 == ~E_1~0); 65615#L904-1 assume !(0 == ~E_2~0); 65307#L909-1 assume !(0 == ~E_3~0); 65308#L914-1 assume !(0 == ~E_4~0); 65531#L919-1 assume !(0 == ~E_5~0); 65205#L924-1 assume !(0 == ~E_6~0); 65014#L929-1 assume !(0 == ~E_7~0); 65015#L934-1 assume !(0 == ~E_8~0); 65284#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64802#L418 assume !(1 == ~m_pc~0); 64777#L418-2 is_master_triggered_~__retres1~0#1 := 0; 65909#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65946#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 65727#L1061 assume !(0 != activate_threads_~tmp~1#1); 65639#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65640#L437 assume !(1 == ~t1_pc~0); 65857#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65737#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64825#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64826#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 65154#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65717#L456 assume !(1 == ~t2_pc~0); 65073#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 65072#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65241#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 65242#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 65424#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64915#L475 assume !(1 == ~t3_pc~0); 64916#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64979#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64793#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64794#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 65157#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65158#L494 assume !(1 == ~t4_pc~0); 65199#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 65200#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64930#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64931#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 65560#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64973#L513 assume 1 == ~t5_pc~0; 64974#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65201#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65749#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64927#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 64928#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64881#L532 assume !(1 == ~t6_pc~0); 64882#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 65034#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65220#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65221#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 65129#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65130#L551 assume 1 == ~t7_pc~0; 65768#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65563#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65564#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65925#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 65929#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65328#L570 assume 1 == ~t8_pc~0; 65329#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65452#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65686#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65447#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 64909#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64910#L952 assume !(1 == ~M_E~0); 64850#L952-2 assume !(1 == ~T1_E~0); 64851#L957-1 assume !(1 == ~T2_E~0); 65694#L962-1 assume !(1 == ~T3_E~0); 69004#L967-1 assume !(1 == ~T4_E~0); 69001#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 68999#L977-1 assume !(1 == ~T6_E~0); 68997#L982-1 assume !(1 == ~T7_E~0); 68995#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 68993#L992-1 assume !(1 == ~E_M~0); 68990#L997-1 assume !(1 == ~E_1~0); 68988#L1002-1 assume !(1 == ~E_2~0); 68986#L1007-1 assume !(1 == ~E_3~0); 68984#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 64788#L1017-1 assume !(1 == ~E_5~0); 65409#L1022-1 assume !(1 == ~E_6~0); 65410#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 65436#L1032-1 assume !(1 == ~E_8~0); 68350#L1037-1 assume { :end_inline_reset_delta_events } true; 68348#L1303-2 [2023-11-23 21:36:53,218 INFO L750 eck$LassoCheckResult]: Loop: 68348#L1303-2 assume !false; 68346#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68341#L829-1 assume !false; 68339#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 68309#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 68269#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 68231#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 68162#L712 assume !(0 != eval_~tmp~0#1); 68163#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72149#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 72148#L854-3 assume !(0 == ~M_E~0); 72147#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 72146#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 72145#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72144#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72143#L874-3 assume !(0 == ~T5_E~0); 72142#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 72141#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 72140#L889-3 assume !(0 == ~T8_E~0); 72139#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 72138#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 72137#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 72136#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 72135#L914-3 assume !(0 == ~E_4~0); 72134#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 72133#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 72132#L929-3 assume !(0 == ~E_7~0); 72131#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 72130#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72129#L418-30 assume 1 == ~m_pc~0; 72128#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 72126#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72124#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 72121#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72120#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72119#L437-30 assume !(1 == ~t1_pc~0); 72118#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 72117#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72116#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 72115#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72114#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72113#L456-30 assume 1 == ~t2_pc~0; 72112#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 72109#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72108#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 72107#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72106#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72105#L475-30 assume !(1 == ~t3_pc~0); 72104#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 72103#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72101#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 72099#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 72095#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 72093#L494-30 assume 1 == ~t4_pc~0; 72091#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 72088#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72085#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 72083#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 72081#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 72079#L513-30 assume !(1 == ~t5_pc~0); 72077#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 72074#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 72072#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72070#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 72068#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72065#L532-30 assume 1 == ~t6_pc~0; 72063#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 72060#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72058#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72056#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 72054#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72052#L551-30 assume 1 == ~t7_pc~0; 72049#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72047#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72045#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 72043#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 72041#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 72038#L570-30 assume 1 == ~t8_pc~0; 72035#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 72033#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 72031#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 72029#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 72027#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72024#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 70206#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72021#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72019#L962-3 assume !(1 == ~T3_E~0); 72017#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 72015#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 71513#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 72011#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72009#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 72007#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 72005#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 72003#L1002-3 assume !(1 == ~E_2~0); 72000#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 71998#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70174#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 71995#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 71993#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 71991#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 71988#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 68447#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 68436#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 68434#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 68432#L1322 assume !(0 == start_simulation_~tmp~3#1); 65629#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 68367#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 68361#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 68359#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 68357#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68355#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68353#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 68351#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 68348#L1303-2 [2023-11-23 21:36:53,219 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:53,220 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2023-11-23 21:36:53,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:53,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454102027] [2023-11-23 21:36:53,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:53,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:53,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:53,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:53,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:53,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454102027] [2023-11-23 21:36:53,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454102027] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:53,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:53,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 21:36:53,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317198959] [2023-11-23 21:36:53,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:53,397 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:53,400 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:53,400 INFO L85 PathProgramCache]: Analyzing trace with hash 95345506, now seen corresponding path program 1 times [2023-11-23 21:36:53,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:53,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488231063] [2023-11-23 21:36:53,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:53,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:53,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:53,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:53,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:53,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488231063] [2023-11-23 21:36:53,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1488231063] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:53,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:53,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:53,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [313386609] [2023-11-23 21:36:53,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:53,457 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:53,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:53,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:53,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:53,458 INFO L87 Difference]: Start difference. First operand 12286 states and 17624 transitions. cyclomatic complexity: 5354 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:53,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:53,664 INFO L93 Difference]: Finished difference Result 23203 states and 33115 transitions. [2023-11-23 21:36:53,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23203 states and 33115 transitions. [2023-11-23 21:36:53,789 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22972 [2023-11-23 21:36:54,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23203 states to 23203 states and 33115 transitions. [2023-11-23 21:36:54,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23203 [2023-11-23 21:36:54,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23203 [2023-11-23 21:36:54,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23203 states and 33115 transitions. [2023-11-23 21:36:54,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:54,071 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23203 states and 33115 transitions. [2023-11-23 21:36:54,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23203 states and 33115 transitions. [2023-11-23 21:36:54,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23203 to 23171. [2023-11-23 21:36:54,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23171 states, 23171 states have (on average 1.4277760994346382) internal successors, (33083), 23170 states have internal predecessors, (33083), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:54,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23171 states to 23171 states and 33083 transitions. [2023-11-23 21:36:54,730 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23171 states and 33083 transitions. [2023-11-23 21:36:54,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:36:54,732 INFO L428 stractBuchiCegarLoop]: Abstraction has 23171 states and 33083 transitions. [2023-11-23 21:36:54,732 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-23 21:36:54,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23171 states and 33083 transitions. [2023-11-23 21:36:54,815 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22940 [2023-11-23 21:36:54,815 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:54,815 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:54,817 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:54,817 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:54,818 INFO L748 eck$LassoCheckResult]: Stem: 100591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 100592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 101293#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101294#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 101358#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 101044#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 101045#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100608#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 100609#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100540#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100541#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 100813#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 100783#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 100784#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 101098#L854 assume !(0 == ~M_E~0); 100882#L854-2 assume !(0 == ~T1_E~0); 100883#L859-1 assume !(0 == ~T2_E~0); 100417#L864-1 assume !(0 == ~T3_E~0); 100418#L869-1 assume !(0 == ~T4_E~0); 100529#L874-1 assume !(0 == ~T5_E~0); 101336#L879-1 assume !(0 == ~T6_E~0); 100872#L884-1 assume !(0 == ~T7_E~0); 100280#L889-1 assume !(0 == ~T8_E~0); 100281#L894-1 assume !(0 == ~E_M~0); 100622#L899-1 assume !(0 == ~E_1~0); 101105#L904-1 assume !(0 == ~E_2~0); 100802#L909-1 assume !(0 == ~E_3~0); 100803#L914-1 assume !(0 == ~E_4~0); 101031#L919-1 assume !(0 == ~E_5~0); 100704#L924-1 assume !(0 == ~E_6~0); 100513#L929-1 assume !(0 == ~E_7~0); 100514#L934-1 assume !(0 == ~E_8~0); 100780#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100298#L418 assume !(1 == ~m_pc~0); 100272#L418-2 is_master_triggered_~__retres1~0#1 := 0; 101275#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101276#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 101214#L1061 assume !(0 != activate_threads_~tmp~1#1); 101132#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101133#L437 assume !(1 == ~t1_pc~0); 101325#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 101221#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100321#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100322#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 100653#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101204#L456 assume !(1 == ~t2_pc~0); 100570#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 100569#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100735#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100736#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 100924#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100412#L475 assume !(1 == ~t3_pc~0); 100413#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 100475#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100289#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 100290#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 100656#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100657#L494 assume !(1 == ~t4_pc~0); 100698#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100699#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100427#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 100428#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 101059#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100470#L513 assume !(1 == ~t5_pc~0); 100471#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 100700#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101232#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100424#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 100425#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100378#L532 assume !(1 == ~t6_pc~0); 100379#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 100530#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100717#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100718#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 100626#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100627#L551 assume 1 == ~t7_pc~0; 101245#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 101062#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101063#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101379#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 101385#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100826#L570 assume 1 == ~t8_pc~0; 100827#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 100953#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101171#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100948#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 100406#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100407#L952 assume !(1 == ~M_E~0); 101225#L952-2 assume !(1 == ~T1_E~0); 101180#L957-1 assume !(1 == ~T2_E~0); 101181#L962-1 assume !(1 == ~T3_E~0); 100968#L967-1 assume !(1 == ~T4_E~0); 100969#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101248#L977-1 assume !(1 == ~T6_E~0); 101249#L982-1 assume !(1 == ~T7_E~0); 100532#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 100533#L992-1 assume !(1 == ~E_M~0); 100542#L997-1 assume !(1 == ~E_1~0); 100922#L1002-1 assume !(1 == ~E_2~0); 102920#L1007-1 assume !(1 == ~E_3~0); 102881#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 102872#L1017-1 assume !(1 == ~E_5~0); 102861#L1022-1 assume !(1 == ~E_6~0); 102859#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 102840#L1032-1 assume !(1 == ~E_8~0); 102831#L1037-1 assume { :end_inline_reset_delta_events } true; 102824#L1303-2 [2023-11-23 21:36:54,819 INFO L750 eck$LassoCheckResult]: Loop: 102824#L1303-2 assume !false; 102818#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102814#L829-1 assume !false; 102813#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 102808#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 102803#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 102802#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 102800#L712 assume !(0 != eval_~tmp~0#1); 102799#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 102798#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 102796#L854-3 assume !(0 == ~M_E~0); 102797#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103416#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 103417#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103414#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103415#L874-3 assume !(0 == ~T5_E~0); 103412#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 103413#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 103410#L889-3 assume !(0 == ~T8_E~0); 103411#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 103408#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 103409#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 103406#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103407#L914-3 assume !(0 == ~E_4~0); 103404#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 103405#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 103402#L929-3 assume !(0 == ~E_7~0); 103403#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103400#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103401#L418-30 assume !(1 == ~m_pc~0); 104237#L418-32 is_master_triggered_~__retres1~0#1 := 0; 104236#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104235#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 104234#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 104232#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104231#L437-30 assume !(1 == ~t1_pc~0); 104230#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 104229#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104228#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104227#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 104226#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104225#L456-30 assume 1 == ~t2_pc~0; 103399#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 102067#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102068#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 102063#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 102064#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102059#L475-30 assume !(1 == ~t3_pc~0); 102060#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 102055#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102056#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 102051#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 102052#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102046#L494-30 assume 1 == ~t4_pc~0; 102048#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 102041#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102042#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 102033#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 102034#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102029#L513-30 assume !(1 == ~t5_pc~0); 102030#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 102018#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102019#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 102010#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 102011#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102000#L532-30 assume 1 == ~t6_pc~0; 102001#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 101991#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101992#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101983#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 101984#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101974#L551-30 assume !(1 == ~t7_pc~0); 101975#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 101964#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101965#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101955#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 101956#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 101946#L570-30 assume 1 == ~t8_pc~0; 101947#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 101936#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101937#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103397#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 103784#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101919#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 101920#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101913#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 101914#L962-3 assume !(1 == ~T3_E~0); 101906#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101907#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 103731#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103729#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 103728#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 101893#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 101891#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 101889#L1002-3 assume !(1 == ~E_2~0); 101886#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 101887#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 103238#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 103233#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 103227#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 103222#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 103217#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 103126#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 103113#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 103108#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 103104#L1322 assume !(0 == start_simulation_~tmp~3#1); 103100#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 102926#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 102921#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 102919#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 102862#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 102860#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102841#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 102832#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 102824#L1303-2 [2023-11-23 21:36:54,820 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:54,820 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2023-11-23 21:36:54,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:54,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880261515] [2023-11-23 21:36:54,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:54,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:54,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:55,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:55,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:55,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [880261515] [2023-11-23 21:36:55,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [880261515] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:55,040 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:55,041 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:55,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076521824] [2023-11-23 21:36:55,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:55,041 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:55,042 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:55,042 INFO L85 PathProgramCache]: Analyzing trace with hash -281148890, now seen corresponding path program 1 times [2023-11-23 21:36:55,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:55,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005950491] [2023-11-23 21:36:55,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:55,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:55,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:55,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:55,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:55,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005950491] [2023-11-23 21:36:55,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005950491] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:55,100 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:55,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:55,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661628287] [2023-11-23 21:36:55,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:55,102 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:55,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:55,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 21:36:55,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 21:36:55,103 INFO L87 Difference]: Start difference. First operand 23171 states and 33083 transitions. cyclomatic complexity: 9944 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:55,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:55,656 INFO L93 Difference]: Finished difference Result 54194 states and 76824 transitions. [2023-11-23 21:36:55,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54194 states and 76824 transitions. [2023-11-23 21:36:56,098 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 53740 [2023-11-23 21:36:56,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54194 states to 54194 states and 76824 transitions. [2023-11-23 21:36:56,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54194 [2023-11-23 21:36:56,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54194 [2023-11-23 21:36:56,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54194 states and 76824 transitions. [2023-11-23 21:36:56,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:56,445 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54194 states and 76824 transitions. [2023-11-23 21:36:56,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54194 states and 76824 transitions. [2023-11-23 21:36:57,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54194 to 43726. [2023-11-23 21:36:57,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43726 states, 43726 states have (on average 1.4220372318529022) internal successors, (62180), 43725 states have internal predecessors, (62180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:57,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43726 states to 43726 states and 62180 transitions. [2023-11-23 21:36:57,387 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43726 states and 62180 transitions. [2023-11-23 21:36:57,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 21:36:57,388 INFO L428 stractBuchiCegarLoop]: Abstraction has 43726 states and 62180 transitions. [2023-11-23 21:36:57,388 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-23 21:36:57,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43726 states and 62180 transitions. [2023-11-23 21:36:57,731 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43416 [2023-11-23 21:36:57,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:36:57,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:36:57,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:57,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:36:57,735 INFO L748 eck$LassoCheckResult]: Stem: 177962#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 177963#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 178708#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 178709#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 178784#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 178426#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 178427#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 177986#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 177987#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 177914#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 177915#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 178193#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 178164#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 178165#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 178490#L854 assume !(0 == ~M_E~0); 178263#L854-2 assume !(0 == ~T1_E~0); 178264#L859-1 assume !(0 == ~T2_E~0); 177792#L864-1 assume !(0 == ~T3_E~0); 177793#L869-1 assume !(0 == ~T4_E~0); 177903#L874-1 assume !(0 == ~T5_E~0); 178751#L879-1 assume !(0 == ~T6_E~0); 178248#L884-1 assume !(0 == ~T7_E~0); 177655#L889-1 assume !(0 == ~T8_E~0); 177656#L894-1 assume !(0 == ~E_M~0); 177998#L899-1 assume !(0 == ~E_1~0); 178496#L904-1 assume !(0 == ~E_2~0); 178187#L909-1 assume !(0 == ~E_3~0); 178188#L914-1 assume !(0 == ~E_4~0); 178416#L919-1 assume !(0 == ~E_5~0); 178082#L924-1 assume !(0 == ~E_6~0); 177889#L929-1 assume !(0 == ~E_7~0); 177890#L934-1 assume !(0 == ~E_8~0); 178163#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 177673#L418 assume !(1 == ~m_pc~0); 177647#L418-2 is_master_triggered_~__retres1~0#1 := 0; 178801#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 178842#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 178617#L1061 assume !(0 != activate_threads_~tmp~1#1); 178527#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 178528#L437 assume !(1 == ~t1_pc~0); 178739#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 178625#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 177698#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 177699#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 178027#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 178610#L456 assume !(1 == ~t2_pc~0); 177945#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 177944#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 178116#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 178117#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 178298#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 177787#L475 assume !(1 == ~t3_pc~0); 177788#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 177852#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 177664#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 177665#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 178030#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 178031#L494 assume !(1 == ~t4_pc~0); 178076#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 178077#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 177802#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 177803#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 178443#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 177848#L513 assume !(1 == ~t5_pc~0); 177849#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 178081#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 178637#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 177799#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 177800#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 177753#L532 assume !(1 == ~t6_pc~0); 177754#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 177904#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 178098#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 178099#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 178000#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 178001#L551 assume !(1 == ~t7_pc~0); 178497#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 178445#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 178446#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 178815#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 178824#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 178205#L570 assume 1 == ~t8_pc~0; 178206#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 178332#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 178571#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 178329#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 177785#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 177786#L952 assume !(1 == ~M_E~0); 178630#L952-2 assume !(1 == ~T1_E~0); 178584#L957-1 assume !(1 == ~T2_E~0); 178585#L962-1 assume !(1 == ~T3_E~0); 178349#L967-1 assume !(1 == ~T4_E~0); 178350#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 178657#L977-1 assume !(1 == ~T6_E~0); 178658#L982-1 assume !(1 == ~T7_E~0); 188381#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 188382#L992-1 assume !(1 == ~E_M~0); 188375#L997-1 assume !(1 == ~E_1~0); 188376#L1002-1 assume !(1 == ~E_2~0); 178280#L1007-1 assume !(1 == ~E_3~0); 178281#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 188369#L1017-1 assume !(1 == ~E_5~0); 188368#L1022-1 assume !(1 == ~E_6~0); 188367#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 188366#L1032-1 assume !(1 == ~E_8~0); 188364#L1037-1 assume { :end_inline_reset_delta_events } true; 188354#L1303-2 [2023-11-23 21:36:57,736 INFO L750 eck$LassoCheckResult]: Loop: 188354#L1303-2 assume !false; 188352#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 188347#L829-1 assume !false; 188344#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 188330#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 188315#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 188306#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 188292#L712 assume !(0 != eval_~tmp~0#1); 188293#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 189836#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 189834#L854-3 assume !(0 == ~M_E~0); 189831#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 189828#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 189825#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 189823#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 189821#L874-3 assume !(0 == ~T5_E~0); 189818#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 189815#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 189812#L889-3 assume !(0 == ~T8_E~0); 189809#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 189805#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 189802#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 189799#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 189797#L914-3 assume !(0 == ~E_4~0); 189794#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 189791#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 189788#L929-3 assume !(0 == ~E_7~0); 189785#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 189784#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189783#L418-30 assume !(1 == ~m_pc~0); 189782#L418-32 is_master_triggered_~__retres1~0#1 := 0; 189770#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189766#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189762#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 189757#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189754#L437-30 assume !(1 == ~t1_pc~0); 189751#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 189747#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189743#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 189739#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 189735#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189733#L456-30 assume 1 == ~t2_pc~0; 189730#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 189726#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189723#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189720#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 189717#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189713#L475-30 assume !(1 == ~t3_pc~0); 189710#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 189706#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189703#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 189700#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 189698#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189696#L494-30 assume !(1 == ~t4_pc~0); 189692#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 189689#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189686#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 189683#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 189680#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189677#L513-30 assume !(1 == ~t5_pc~0); 189674#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 189670#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189667#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 189664#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 189661#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 189658#L532-30 assume !(1 == ~t6_pc~0); 189654#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 189651#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 189648#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 189645#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 189642#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 189639#L551-30 assume !(1 == ~t7_pc~0); 183528#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 189633#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 189630#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 189626#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 189622#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 189618#L570-30 assume !(1 == ~t8_pc~0); 189614#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 189611#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 189608#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 189605#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 189602#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189599#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 188777#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 189591#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 189588#L962-3 assume !(1 == ~T3_E~0); 189584#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 189581#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 189576#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 189573#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 189570#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 189567#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 189564#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 189561#L1002-3 assume !(1 == ~E_2~0); 189558#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 189555#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 189348#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 189550#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 189546#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 189543#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 189539#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 189533#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 189522#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 189519#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 189516#L1322 assume !(0 == start_simulation_~tmp~3#1); 189513#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 188415#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 188383#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 188380#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 188377#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 188374#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 188373#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 188365#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 188354#L1303-2 [2023-11-23 21:36:57,737 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:57,738 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2023-11-23 21:36:57,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:57,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697694359] [2023-11-23 21:36:57,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:57,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:57,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:57,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:57,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:57,816 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697694359] [2023-11-23 21:36:57,816 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [697694359] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:57,816 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:57,816 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 21:36:57,817 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033468991] [2023-11-23 21:36:57,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:57,817 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:36:57,818 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:36:57,818 INFO L85 PathProgramCache]: Analyzing trace with hash -954120727, now seen corresponding path program 1 times [2023-11-23 21:36:57,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:36:57,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545710748] [2023-11-23 21:36:57,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:36:57,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:36:57,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:36:57,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:36:57,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:36:57,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545710748] [2023-11-23 21:36:57,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545710748] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:36:57,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:36:57,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:36:57,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680570975] [2023-11-23 21:36:57,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:36:57,887 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:36:57,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:36:57,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:36:57,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:36:57,889 INFO L87 Difference]: Start difference. First operand 43726 states and 62180 transitions. cyclomatic complexity: 18486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:36:58,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:36:58,458 INFO L93 Difference]: Finished difference Result 82565 states and 116953 transitions. [2023-11-23 21:36:58,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82565 states and 116953 transitions. [2023-11-23 21:36:59,111 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 81968 [2023-11-23 21:36:59,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82565 states to 82565 states and 116953 transitions. [2023-11-23 21:36:59,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82565 [2023-11-23 21:36:59,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82565 [2023-11-23 21:36:59,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82565 states and 116953 transitions. [2023-11-23 21:36:59,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:36:59,756 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82565 states and 116953 transitions. [2023-11-23 21:36:59,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82565 states and 116953 transitions. [2023-11-23 21:37:01,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82565 to 82437. [2023-11-23 21:37:01,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82437 states, 82437 states have (on average 1.417142787825855) internal successors, (116825), 82436 states have internal predecessors, (116825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:01,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82437 states to 82437 states and 116825 transitions. [2023-11-23 21:37:01,308 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82437 states and 116825 transitions. [2023-11-23 21:37:01,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:37:01,309 INFO L428 stractBuchiCegarLoop]: Abstraction has 82437 states and 116825 transitions. [2023-11-23 21:37:01,309 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-23 21:37:01,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82437 states and 116825 transitions. [2023-11-23 21:37:01,906 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 81840 [2023-11-23 21:37:01,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:01,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:01,908 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:01,920 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:01,920 INFO L748 eck$LassoCheckResult]: Stem: 304264#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 304265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 305023#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 305024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 305108#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 304728#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 304729#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 304283#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 304284#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 304213#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 304214#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 304491#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 304460#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 304461#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 304795#L854 assume !(0 == ~M_E~0); 304566#L854-2 assume !(0 == ~T1_E~0); 304567#L859-1 assume !(0 == ~T2_E~0); 304090#L864-1 assume !(0 == ~T3_E~0); 304091#L869-1 assume !(0 == ~T4_E~0); 304202#L874-1 assume !(0 == ~T5_E~0); 305082#L879-1 assume !(0 == ~T6_E~0); 304553#L884-1 assume !(0 == ~T7_E~0); 303952#L889-1 assume !(0 == ~T8_E~0); 303953#L894-1 assume !(0 == ~E_M~0); 304297#L899-1 assume !(0 == ~E_1~0); 304801#L904-1 assume !(0 == ~E_2~0); 304484#L909-1 assume !(0 == ~E_3~0); 304485#L914-1 assume !(0 == ~E_4~0); 304716#L919-1 assume !(0 == ~E_5~0); 304381#L924-1 assume !(0 == ~E_6~0); 304188#L929-1 assume !(0 == ~E_7~0); 304189#L934-1 assume !(0 == ~E_8~0); 304459#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 303971#L418 assume !(1 == ~m_pc~0); 303945#L418-2 is_master_triggered_~__retres1~0#1 := 0; 305008#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 305009#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 304927#L1061 assume !(0 != activate_threads_~tmp~1#1); 304830#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 304831#L437 assume !(1 == ~t1_pc~0); 305064#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 304936#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 303996#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 303997#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 304328#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 304917#L456 assume !(1 == ~t2_pc~0); 304247#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 304246#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 304416#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 304417#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 304604#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 304085#L475 assume !(1 == ~t3_pc~0); 304086#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 304151#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 303962#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 303963#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 304331#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 304332#L494 assume !(1 == ~t4_pc~0); 304376#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 304377#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 304100#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304101#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 304746#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 304144#L513 assume !(1 == ~t5_pc~0); 304145#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 304380#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 304950#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 304097#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 304098#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 304051#L532 assume !(1 == ~t6_pc~0); 304052#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 304203#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 304395#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 304396#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 304301#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 304302#L551 assume !(1 == ~t7_pc~0); 304803#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 304748#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 304749#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 305131#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 305136#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 304507#L570 assume !(1 == ~t8_pc~0); 304508#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 305033#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 304881#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 304629#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 304083#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 304084#L952 assume !(1 == ~M_E~0); 304942#L952-2 assume !(1 == ~T1_E~0); 344353#L957-1 assume !(1 == ~T2_E~0); 344350#L962-1 assume !(1 == ~T3_E~0); 344347#L967-1 assume !(1 == ~T4_E~0); 344344#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 304972#L977-1 assume !(1 == ~T6_E~0); 304973#L982-1 assume !(1 == ~T7_E~0); 304205#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 304206#L992-1 assume !(1 == ~E_M~0); 304215#L997-1 assume !(1 == ~E_1~0); 304602#L1002-1 assume !(1 == ~E_2~0); 304587#L1007-1 assume !(1 == ~E_3~0); 303954#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 303955#L1017-1 assume !(1 == ~E_5~0); 351379#L1022-1 assume !(1 == ~E_6~0); 351375#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 351373#L1032-1 assume !(1 == ~E_8~0); 349607#L1037-1 assume { :end_inline_reset_delta_events } true; 349606#L1303-2 [2023-11-23 21:37:01,921 INFO L750 eck$LassoCheckResult]: Loop: 349606#L1303-2 assume !false; 349604#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 349602#L829-1 assume !false; 349600#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 349588#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 349582#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 349581#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 349577#L712 assume !(0 != eval_~tmp~0#1); 349578#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 354540#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 354538#L854-3 assume !(0 == ~M_E~0); 354536#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 354534#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 354532#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 354531#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 354530#L874-3 assume !(0 == ~T5_E~0); 354526#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 354524#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 354522#L889-3 assume !(0 == ~T8_E~0); 354521#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 354518#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 354517#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 354515#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 354514#L914-3 assume !(0 == ~E_4~0); 354513#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 354512#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 354510#L929-3 assume !(0 == ~E_7~0); 354509#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 354508#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 354506#L418-30 assume !(1 == ~m_pc~0); 354502#L418-32 is_master_triggered_~__retres1~0#1 := 0; 354500#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 354498#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 354496#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 354493#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 354491#L437-30 assume !(1 == ~t1_pc~0); 354489#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 354487#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 354485#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 354483#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 349789#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 349788#L456-30 assume !(1 == ~t2_pc~0); 349785#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 349783#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 349781#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 349779#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 349777#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 349774#L475-30 assume !(1 == ~t3_pc~0); 349772#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 349770#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 349768#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 349766#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 349763#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 349761#L494-30 assume 1 == ~t4_pc~0; 349759#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 349756#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 349754#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349752#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 349750#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 349748#L513-30 assume !(1 == ~t5_pc~0); 349746#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 349744#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 349742#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 349740#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 349738#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 349736#L532-30 assume !(1 == ~t6_pc~0); 349733#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 349731#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 349729#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 349728#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 349727#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 349725#L551-30 assume !(1 == ~t7_pc~0); 341762#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 349724#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 349723#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 349722#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 349721#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 349718#L570-30 assume !(1 == ~t8_pc~0); 349716#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 349714#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 349710#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 349708#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 349706#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 349704#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 349699#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 349697#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 349695#L962-3 assume !(1 == ~T3_E~0); 349693#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 349691#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 349687#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 349685#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 349683#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 349681#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 349678#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 349676#L1002-3 assume !(1 == ~E_2~0); 349674#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 349672#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 349668#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 349666#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 349664#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 349662#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 349660#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 349654#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 349644#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 349642#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 349640#L1322 assume !(0 == start_simulation_~tmp~3#1); 349637#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 349625#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 349618#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 349616#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 349614#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 349612#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 349610#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 349608#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 349606#L1303-2 [2023-11-23 21:37:01,921 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:01,922 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2023-11-23 21:37:01,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:01,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241887685] [2023-11-23 21:37:01,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:01,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:01,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:02,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:02,026 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:02,026 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241887685] [2023-11-23 21:37:02,027 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1241887685] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:02,027 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:02,027 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:02,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873346432] [2023-11-23 21:37:02,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:02,028 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:37:02,028 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:02,028 INFO L85 PathProgramCache]: Analyzing trace with hash 149335145, now seen corresponding path program 1 times [2023-11-23 21:37:02,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:02,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2072358495] [2023-11-23 21:37:02,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:02,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:02,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:02,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:02,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:02,080 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2072358495] [2023-11-23 21:37:02,080 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2072358495] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:02,080 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:02,080 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:02,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26722890] [2023-11-23 21:37:02,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:02,081 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:02,081 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:02,082 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 21:37:02,082 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 21:37:02,082 INFO L87 Difference]: Start difference. First operand 82437 states and 116825 transitions. cyclomatic complexity: 34452 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:02,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:02,405 INFO L93 Difference]: Finished difference Result 63030 states and 89131 transitions. [2023-11-23 21:37:02,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63030 states and 89131 transitions. [2023-11-23 21:37:02,733 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 62576 [2023-11-23 21:37:03,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63030 states to 63030 states and 89131 transitions. [2023-11-23 21:37:03,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63030 [2023-11-23 21:37:03,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63030 [2023-11-23 21:37:03,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63030 states and 89131 transitions. [2023-11-23 21:37:03,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:03,357 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63030 states and 89131 transitions. [2023-11-23 21:37:03,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63030 states and 89131 transitions. [2023-11-23 21:37:04,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63030 to 43649. [2023-11-23 21:37:04,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.4146028545900249) internal successors, (61746), 43648 states have internal predecessors, (61746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:04,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 61746 transitions. [2023-11-23 21:37:04,332 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61746 transitions. [2023-11-23 21:37:04,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 21:37:04,333 INFO L428 stractBuchiCegarLoop]: Abstraction has 43649 states and 61746 transitions. [2023-11-23 21:37:04,333 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-23 21:37:04,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 61746 transitions. [2023-11-23 21:37:04,501 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2023-11-23 21:37:04,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:04,502 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:04,505 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:04,505 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:04,505 INFO L748 eck$LassoCheckResult]: Stem: 449740#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 449741#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 450446#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 450447#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 450505#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 450186#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 450187#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 449763#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 449764#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 449691#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 449692#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 449965#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 449933#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 449934#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 450249#L854 assume !(0 == ~M_E~0); 450036#L854-2 assume !(0 == ~T1_E~0); 450037#L859-1 assume !(0 == ~T2_E~0); 449568#L864-1 assume !(0 == ~T3_E~0); 449569#L869-1 assume !(0 == ~T4_E~0); 449680#L874-1 assume !(0 == ~T5_E~0); 450483#L879-1 assume !(0 == ~T6_E~0); 450021#L884-1 assume !(0 == ~T7_E~0); 449430#L889-1 assume !(0 == ~T8_E~0); 449431#L894-1 assume !(0 == ~E_M~0); 449774#L899-1 assume !(0 == ~E_1~0); 450255#L904-1 assume !(0 == ~E_2~0); 449957#L909-1 assume !(0 == ~E_3~0); 449958#L914-1 assume !(0 == ~E_4~0); 450176#L919-1 assume !(0 == ~E_5~0); 449854#L924-1 assume !(0 == ~E_6~0); 449666#L929-1 assume !(0 == ~E_7~0); 449667#L934-1 assume !(0 == ~E_8~0); 449932#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 449447#L418 assume !(1 == ~m_pc~0); 449422#L418-2 is_master_triggered_~__retres1~0#1 := 0; 450432#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 450433#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 450369#L1061 assume !(0 != activate_threads_~tmp~1#1); 450281#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 450282#L437 assume !(1 == ~t1_pc~0); 450476#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 450376#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 449472#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 449473#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 449802#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 450362#L456 assume !(1 == ~t2_pc~0); 449723#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 449722#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 449887#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 449888#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 450069#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 449563#L475 assume !(1 == ~t3_pc~0); 449564#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 449629#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 449438#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 449439#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 449805#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 449806#L494 assume !(1 == ~t4_pc~0); 449849#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 449850#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 449578#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 449579#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 450202#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 449625#L513 assume !(1 == ~t5_pc~0); 449626#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 449853#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 450387#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 449575#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 449576#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 449529#L532 assume !(1 == ~t6_pc~0); 449530#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 449681#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 449869#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 449870#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 449777#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 449778#L551 assume !(1 == ~t7_pc~0); 450256#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 450206#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 450207#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 450528#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 450534#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 449979#L570 assume !(1 == ~t8_pc~0); 449980#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 450453#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 450327#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 450094#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 449561#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 449562#L952 assume !(1 == ~M_E~0); 449496#L952-2 assume !(1 == ~T1_E~0); 449497#L957-1 assume !(1 == ~T2_E~0); 450339#L962-1 assume !(1 == ~T3_E~0); 450112#L967-1 assume !(1 == ~T4_E~0); 450113#L972-1 assume !(1 == ~T5_E~0); 450402#L977-1 assume !(1 == ~T6_E~0); 450403#L982-1 assume !(1 == ~T7_E~0); 449683#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 449684#L992-1 assume !(1 == ~E_M~0); 449693#L997-1 assume !(1 == ~E_1~0); 450067#L1002-1 assume !(1 == ~E_2~0); 450052#L1007-1 assume !(1 == ~E_3~0); 449432#L1012-1 assume !(1 == ~E_4~0); 449433#L1017-1 assume !(1 == ~E_5~0); 450058#L1022-1 assume !(1 == ~E_6~0); 450059#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 450082#L1032-1 assume !(1 == ~E_8~0); 450236#L1037-1 assume { :end_inline_reset_delta_events } true; 450237#L1303-2 [2023-11-23 21:37:04,506 INFO L750 eck$LassoCheckResult]: Loop: 450237#L1303-2 assume !false; 463519#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 463510#L829-1 assume !false; 463504#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 463258#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 463252#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 463250#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 463246#L712 assume !(0 != eval_~tmp~0#1); 463247#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 470894#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 470888#L854-3 assume !(0 == ~M_E~0); 470882#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 470876#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 470872#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 470868#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 470863#L874-3 assume !(0 == ~T5_E~0); 470857#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 470851#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 470845#L889-3 assume !(0 == ~T8_E~0); 470840#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 470835#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 470830#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 470824#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 470818#L914-3 assume !(0 == ~E_4~0); 470812#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 470807#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 470802#L929-3 assume !(0 == ~E_7~0); 470799#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 470795#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 470792#L418-30 assume !(1 == ~m_pc~0); 470787#L418-32 is_master_triggered_~__retres1~0#1 := 0; 470780#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 470772#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 470764#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 470757#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 470752#L437-30 assume !(1 == ~t1_pc~0); 470745#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 470739#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 470733#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 470727#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 470722#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 470718#L456-30 assume 1 == ~t2_pc~0; 470702#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 470693#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 470687#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 470681#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 470676#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 470671#L475-30 assume !(1 == ~t3_pc~0); 470665#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 470660#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 470655#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 470650#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 470645#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 470640#L494-30 assume 1 == ~t4_pc~0; 470633#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 470625#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 470620#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 470615#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 470610#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 470605#L513-30 assume !(1 == ~t5_pc~0); 470598#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 470591#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 470586#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 470581#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 470576#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 470572#L532-30 assume 1 == ~t6_pc~0; 470567#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 470559#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 470553#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 470547#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 470541#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 460144#L551-30 assume !(1 == ~t7_pc~0); 460143#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 460133#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 460131#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 460129#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 460126#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 460124#L570-30 assume !(1 == ~t8_pc~0); 460122#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 460120#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 460118#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 460116#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 460114#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 460112#L952-3 assume !(1 == ~M_E~0); 460110#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 460108#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 460106#L962-3 assume !(1 == ~T3_E~0); 460104#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 460102#L972-3 assume !(1 == ~T5_E~0); 460100#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 460098#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 460096#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 460094#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 460092#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 460090#L1002-3 assume !(1 == ~E_2~0); 460088#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 460086#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 460084#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 460082#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 460079#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 460077#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 460075#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 459932#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 459923#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 459844#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 457526#L1322 assume !(0 == start_simulation_~tmp~3#1); 457527#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 463587#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 463581#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 463579#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 463577#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 463575#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 463572#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 463538#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 450237#L1303-2 [2023-11-23 21:37:04,507 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:04,507 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2023-11-23 21:37:04,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:04,508 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152822714] [2023-11-23 21:37:04,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:04,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:04,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:04,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:04,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:04,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152822714] [2023-11-23 21:37:04,597 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1152822714] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:04,597 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:04,597 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:04,597 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1212522295] [2023-11-23 21:37:04,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:04,598 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:37:04,598 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:04,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1607750567, now seen corresponding path program 1 times [2023-11-23 21:37:04,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:04,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1640532478] [2023-11-23 21:37:04,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:04,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:04,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:04,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:04,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:04,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1640532478] [2023-11-23 21:37:04,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1640532478] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:04,658 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:04,658 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:04,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655023735] [2023-11-23 21:37:04,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:04,659 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:04,660 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:04,660 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 21:37:04,660 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 21:37:04,661 INFO L87 Difference]: Start difference. First operand 43649 states and 61746 transitions. cyclomatic complexity: 18129 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:04,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:04,999 INFO L93 Difference]: Finished difference Result 69451 states and 98228 transitions. [2023-11-23 21:37:04,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69451 states and 98228 transitions. [2023-11-23 21:37:05,262 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 68912 [2023-11-23 21:37:05,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69451 states to 69451 states and 98228 transitions. [2023-11-23 21:37:05,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69451 [2023-11-23 21:37:05,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69451 [2023-11-23 21:37:05,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69451 states and 98228 transitions. [2023-11-23 21:37:05,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:05,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69451 states and 98228 transitions. [2023-11-23 21:37:05,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69451 states and 98228 transitions. [2023-11-23 21:37:06,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69451 to 49009. [2023-11-23 21:37:06,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49009 states, 49009 states have (on average 1.4169030178130548) internal successors, (69441), 49008 states have internal predecessors, (69441), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:06,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49009 states to 49009 states and 69441 transitions. [2023-11-23 21:37:06,631 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49009 states and 69441 transitions. [2023-11-23 21:37:06,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 21:37:06,632 INFO L428 stractBuchiCegarLoop]: Abstraction has 49009 states and 69441 transitions. [2023-11-23 21:37:06,632 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-23 21:37:06,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49009 states and 69441 transitions. [2023-11-23 21:37:06,736 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48592 [2023-11-23 21:37:06,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:06,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:06,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:06,739 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:06,739 INFO L748 eck$LassoCheckResult]: Stem: 562853#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 562854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 563594#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 563595#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 563677#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 563310#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 563311#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 562878#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 562879#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 562803#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 562804#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 563080#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 563050#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 563051#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 563369#L854 assume !(0 == ~M_E~0); 563148#L854-2 assume !(0 == ~T1_E~0); 563149#L859-1 assume !(0 == ~T2_E~0); 562679#L864-1 assume !(0 == ~T3_E~0); 562680#L869-1 assume !(0 == ~T4_E~0); 562792#L874-1 assume !(0 == ~T5_E~0); 563649#L879-1 assume !(0 == ~T6_E~0); 563133#L884-1 assume !(0 == ~T7_E~0); 562541#L889-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 562542#L894-1 assume !(0 == ~E_M~0); 563727#L899-1 assume !(0 == ~E_1~0); 563377#L904-1 assume !(0 == ~E_2~0); 563378#L909-1 assume !(0 == ~E_3~0); 563300#L914-1 assume !(0 == ~E_4~0); 563301#L919-1 assume !(0 == ~E_5~0); 562972#L924-1 assume !(0 == ~E_6~0); 562973#L929-1 assume !(0 == ~E_7~0); 563660#L934-1 assume !(0 == ~E_8~0); 563661#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 563775#L418 assume !(1 == ~m_pc~0); 563694#L418-2 is_master_triggered_~__retres1~0#1 := 0; 563695#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 563772#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 563769#L1061 assume !(0 != activate_threads_~tmp~1#1); 563768#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 563690#L437 assume !(1 == ~t1_pc~0); 563691#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 563511#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 563512#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 562920#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 562921#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 563492#L456 assume !(1 == ~t2_pc~0); 563493#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 563682#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 563683#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 563539#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 563540#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 562674#L475 assume !(1 == ~t3_pc~0); 562675#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 563767#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 562550#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 562551#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 562924#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 562925#L494 assume !(1 == ~t4_pc~0); 562967#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 562968#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 562689#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 562690#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 563325#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 562736#L513 assume !(1 == ~t5_pc~0); 562737#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 562971#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 563527#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 562686#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 562687#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 562640#L532 assume !(1 == ~t6_pc~0); 562641#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 562793#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 562987#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 562988#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 562891#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 562892#L551 assume !(1 == ~t7_pc~0); 563379#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 563331#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 563332#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 563705#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 563714#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 563092#L570 assume !(1 == ~t8_pc~0); 563093#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 563600#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 563450#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 563217#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 562672#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 562673#L952 assume !(1 == ~M_E~0); 563519#L952-2 assume !(1 == ~T1_E~0); 563738#L957-1 assume !(1 == ~T2_E~0); 563737#L962-1 assume !(1 == ~T3_E~0); 563736#L967-1 assume !(1 == ~T4_E~0); 563735#L972-1 assume !(1 == ~T5_E~0); 563734#L977-1 assume !(1 == ~T6_E~0); 563733#L982-1 assume !(1 == ~T7_E~0); 563732#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 562796#L992-1 assume !(1 == ~E_M~0); 562805#L997-1 assume !(1 == ~E_1~0); 563184#L1002-1 assume !(1 == ~E_2~0); 563169#L1007-1 assume !(1 == ~E_3~0); 562544#L1012-1 assume !(1 == ~E_4~0); 562545#L1017-1 assume !(1 == ~E_5~0); 563175#L1022-1 assume !(1 == ~E_6~0); 563176#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 563203#L1032-1 assume !(1 == ~E_8~0); 563359#L1037-1 assume { :end_inline_reset_delta_events } true; 563360#L1303-2 [2023-11-23 21:37:06,740 INFO L750 eck$LassoCheckResult]: Loop: 563360#L1303-2 assume !false; 577218#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 577214#L829-1 assume !false; 577212#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 577200#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 577194#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 577193#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 577189#L712 assume !(0 != eval_~tmp~0#1); 577190#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 578284#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 578279#L854-3 assume !(0 == ~M_E~0); 578275#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 578271#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 578267#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 578263#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 578259#L874-3 assume !(0 == ~T5_E~0); 578255#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 578250#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 570745#L889-3 assume !(0 == ~T8_E~0); 570746#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 584743#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 584741#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 584739#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 584737#L914-3 assume !(0 == ~E_4~0); 584735#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 584732#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 584730#L929-3 assume !(0 == ~E_7~0); 584728#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 584726#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 584724#L418-30 assume !(1 == ~m_pc~0); 584720#L418-32 is_master_triggered_~__retres1~0#1 := 0; 584718#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 584716#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 584714#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 584711#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 584709#L437-30 assume !(1 == ~t1_pc~0); 584707#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 584704#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 584702#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 584700#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 584698#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 584696#L456-30 assume !(1 == ~t2_pc~0); 584693#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 584691#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 584689#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 584687#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 584685#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 584683#L475-30 assume !(1 == ~t3_pc~0); 584681#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 584678#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 584676#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 584674#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 584672#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 584670#L494-30 assume !(1 == ~t4_pc~0); 584667#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 584666#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 584663#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 584661#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 584659#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 584657#L513-30 assume !(1 == ~t5_pc~0); 584655#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 584653#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 584650#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 584648#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 584646#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 584551#L532-30 assume !(1 == ~t6_pc~0); 584542#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 584536#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 584529#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 584523#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 584516#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 584509#L551-30 assume !(1 == ~t7_pc~0); 576454#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 584496#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 584312#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 584310#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 584308#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 584306#L570-30 assume !(1 == ~t8_pc~0); 584304#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 584302#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 584300#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 584298#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 584296#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 584294#L952-3 assume !(1 == ~M_E~0); 584292#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 584291#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 584290#L962-3 assume !(1 == ~T3_E~0); 584280#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 584278#L972-3 assume !(1 == ~T5_E~0); 584276#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 584275#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 570572#L987-3 assume !(1 == ~T8_E~0); 570569#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 570567#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 570565#L1002-3 assume !(1 == ~E_2~0); 570563#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 570561#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 570559#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 570556#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 570554#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 570552#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 570550#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 570545#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 570535#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 570532#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 570529#L1322 assume !(0 == start_simulation_~tmp~3#1); 570530#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 577237#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 577230#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 577228#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 577226#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 577224#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 577222#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 577220#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 563360#L1303-2 [2023-11-23 21:37:06,740 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:06,740 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2023-11-23 21:37:06,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:06,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911075562] [2023-11-23 21:37:06,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:06,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:06,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:06,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:06,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:06,805 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911075562] [2023-11-23 21:37:06,805 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911075562] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:06,805 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:06,805 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:06,805 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084218192] [2023-11-23 21:37:06,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:06,806 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:37:06,806 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:06,807 INFO L85 PathProgramCache]: Analyzing trace with hash 136068460, now seen corresponding path program 1 times [2023-11-23 21:37:06,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:06,807 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [839552678] [2023-11-23 21:37:06,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:06,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:06,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:06,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:06,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:06,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [839552678] [2023-11-23 21:37:06,855 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [839552678] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:06,855 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:06,855 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:06,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915727767] [2023-11-23 21:37:06,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:06,857 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:06,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:06,857 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 21:37:06,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 21:37:06,858 INFO L87 Difference]: Start difference. First operand 49009 states and 69441 transitions. cyclomatic complexity: 20464 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:07,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:07,043 INFO L93 Difference]: Finished difference Result 43649 states and 61584 transitions. [2023-11-23 21:37:07,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43649 states and 61584 transitions. [2023-11-23 21:37:07,696 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2023-11-23 21:37:07,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43649 states to 43649 states and 61584 transitions. [2023-11-23 21:37:07,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43649 [2023-11-23 21:37:07,824 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43649 [2023-11-23 21:37:07,824 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43649 states and 61584 transitions. [2023-11-23 21:37:07,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:07,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61584 transitions. [2023-11-23 21:37:07,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43649 states and 61584 transitions. [2023-11-23 21:37:08,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43649 to 43649. [2023-11-23 21:37:08,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.4108914293569155) internal successors, (61584), 43648 states have internal predecessors, (61584), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:08,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 61584 transitions. [2023-11-23 21:37:08,251 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61584 transitions. [2023-11-23 21:37:08,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 21:37:08,252 INFO L428 stractBuchiCegarLoop]: Abstraction has 43649 states and 61584 transitions. [2023-11-23 21:37:08,253 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-23 21:37:08,253 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 61584 transitions. [2023-11-23 21:37:08,363 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2023-11-23 21:37:08,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:08,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:08,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:08,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:08,365 INFO L748 eck$LassoCheckResult]: Stem: 655517#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 655518#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 656251#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 656252#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 656319#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 655970#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 655971#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 655536#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 655537#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 655466#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 655467#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 655741#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 655712#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 655713#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 656031#L854 assume !(0 == ~M_E~0); 655805#L854-2 assume !(0 == ~T1_E~0); 655806#L859-1 assume !(0 == ~T2_E~0); 655344#L864-1 assume !(0 == ~T3_E~0); 655345#L869-1 assume !(0 == ~T4_E~0); 655456#L874-1 assume !(0 == ~T5_E~0); 656295#L879-1 assume !(0 == ~T6_E~0); 655795#L884-1 assume !(0 == ~T7_E~0); 655208#L889-1 assume !(0 == ~T8_E~0); 655209#L894-1 assume !(0 == ~E_M~0); 655552#L899-1 assume !(0 == ~E_1~0); 656037#L904-1 assume !(0 == ~E_2~0); 655730#L909-1 assume !(0 == ~E_3~0); 655731#L914-1 assume !(0 == ~E_4~0); 655956#L919-1 assume !(0 == ~E_5~0); 655636#L924-1 assume !(0 == ~E_6~0); 655438#L929-1 assume !(0 == ~E_7~0); 655439#L934-1 assume !(0 == ~E_8~0); 655709#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 655225#L418 assume !(1 == ~m_pc~0); 655200#L418-2 is_master_triggered_~__retres1~0#1 := 0; 656225#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 656226#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 656156#L1061 assume !(0 != activate_threads_~tmp~1#1); 656066#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 656067#L437 assume !(1 == ~t1_pc~0); 656283#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 656164#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 655247#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 655248#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 655584#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 656146#L456 assume !(1 == ~t2_pc~0); 655499#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 655498#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 655668#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 655669#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 655848#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 655339#L475 assume !(1 == ~t3_pc~0); 655340#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 655403#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 655216#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 655217#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 655587#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 655588#L494 assume !(1 == ~t4_pc~0); 655630#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 655631#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 655354#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 655355#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 655988#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 655398#L513 assume !(1 == ~t5_pc~0); 655399#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 655632#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 656174#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 655351#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 655352#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 655303#L532 assume !(1 == ~t6_pc~0); 655304#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 655457#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 655649#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 655650#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 655556#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 655557#L551 assume !(1 == ~t7_pc~0); 656038#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 655990#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 655991#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 656344#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 656350#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 655753#L570 assume !(1 == ~t8_pc~0); 655754#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 656256#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 656114#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 655872#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 655333#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 655334#L952 assume !(1 == ~M_E~0); 655272#L952-2 assume !(1 == ~T1_E~0); 655273#L957-1 assume !(1 == ~T2_E~0); 656124#L962-1 assume !(1 == ~T3_E~0); 655892#L967-1 assume !(1 == ~T4_E~0); 655893#L972-1 assume !(1 == ~T5_E~0); 656189#L977-1 assume !(1 == ~T6_E~0); 656190#L982-1 assume !(1 == ~T7_E~0); 655460#L987-1 assume !(1 == ~T8_E~0); 655461#L992-1 assume !(1 == ~E_M~0); 655468#L997-1 assume !(1 == ~E_1~0); 655845#L1002-1 assume !(1 == ~E_2~0); 655828#L1007-1 assume !(1 == ~E_3~0); 655210#L1012-1 assume !(1 == ~E_4~0); 655211#L1017-1 assume !(1 == ~E_5~0); 655831#L1022-1 assume !(1 == ~E_6~0); 655832#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 655862#L1032-1 assume !(1 == ~E_8~0); 656015#L1037-1 assume { :end_inline_reset_delta_events } true; 656016#L1303-2 [2023-11-23 21:37:08,366 INFO L750 eck$LassoCheckResult]: Loop: 656016#L1303-2 assume !false; 661855#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 661850#L829-1 assume !false; 661847#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 661835#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 661829#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 661827#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 661824#L712 assume !(0 != eval_~tmp~0#1); 661825#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 663464#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 663460#L854-3 assume !(0 == ~M_E~0); 663455#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 663451#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 663447#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 663443#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 663439#L874-3 assume !(0 == ~T5_E~0); 663435#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 663429#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 663423#L889-3 assume !(0 == ~T8_E~0); 663419#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 663415#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 663410#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 663407#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 663402#L914-3 assume !(0 == ~E_4~0); 663399#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 663395#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 663391#L929-3 assume !(0 == ~E_7~0); 663387#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 663384#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 663380#L418-30 assume 1 == ~m_pc~0; 663375#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 663369#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 663363#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 663357#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 663352#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 663349#L437-30 assume !(1 == ~t1_pc~0); 663345#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 663340#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 663336#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 663332#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 663327#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 663321#L456-30 assume !(1 == ~t2_pc~0); 663314#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 663307#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 663301#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 663296#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 663288#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 663282#L475-30 assume !(1 == ~t3_pc~0); 663276#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 663270#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 663267#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 663263#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 663259#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 662907#L494-30 assume 1 == ~t4_pc~0; 662790#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 662787#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 662785#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 662783#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 662781#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 662779#L513-30 assume !(1 == ~t5_pc~0); 662777#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 662775#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 662773#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 662770#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 662755#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 662748#L532-30 assume !(1 == ~t6_pc~0); 662740#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 662731#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 662722#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 662716#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 662629#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 661960#L551-30 assume !(1 == ~t7_pc~0); 661959#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 661958#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 661954#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 661952#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 661950#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 661949#L570-30 assume !(1 == ~t8_pc~0); 661946#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 661945#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 661944#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 661941#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 661937#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 661936#L952-3 assume !(1 == ~M_E~0); 661935#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 661934#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 661933#L962-3 assume !(1 == ~T3_E~0); 661931#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 661930#L972-3 assume !(1 == ~T5_E~0); 661929#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 661928#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 661927#L987-3 assume !(1 == ~T8_E~0); 661926#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 661925#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 661924#L1002-3 assume !(1 == ~E_2~0); 661923#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 661922#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 661921#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 661918#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 661916#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 661914#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 661910#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 661906#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 661895#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 661893#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 661890#L1322 assume !(0 == start_simulation_~tmp~3#1); 661888#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 661874#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 661868#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 661866#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 661864#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 661862#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 661860#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 661858#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 656016#L1303-2 [2023-11-23 21:37:08,367 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:08,367 INFO L85 PathProgramCache]: Analyzing trace with hash 1031757063, now seen corresponding path program 1 times [2023-11-23 21:37:08,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:08,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260467968] [2023-11-23 21:37:08,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:08,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:08,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:08,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:08,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:08,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1260467968] [2023-11-23 21:37:08,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1260467968] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:08,442 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:08,442 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:08,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1597904976] [2023-11-23 21:37:08,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:08,443 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:37:08,443 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:08,444 INFO L85 PathProgramCache]: Analyzing trace with hash 1382561000, now seen corresponding path program 1 times [2023-11-23 21:37:08,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:08,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605986999] [2023-11-23 21:37:08,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:08,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:08,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:08,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:08,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:08,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1605986999] [2023-11-23 21:37:08,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1605986999] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:08,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:08,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:08,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2014162779] [2023-11-23 21:37:08,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:08,489 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:08,489 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:08,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 21:37:08,490 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 21:37:08,490 INFO L87 Difference]: Start difference. First operand 43649 states and 61584 transitions. cyclomatic complexity: 17967 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:09,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:09,188 INFO L93 Difference]: Finished difference Result 67715 states and 95298 transitions. [2023-11-23 21:37:09,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67715 states and 95298 transitions. [2023-11-23 21:37:09,408 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 67152 [2023-11-23 21:37:09,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67715 states to 67715 states and 95298 transitions. [2023-11-23 21:37:09,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67715 [2023-11-23 21:37:09,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67715 [2023-11-23 21:37:09,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67715 states and 95298 transitions. [2023-11-23 21:37:09,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:09,607 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67715 states and 95298 transitions. [2023-11-23 21:37:09,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67715 states and 95298 transitions. [2023-11-23 21:37:10,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67715 to 48977. [2023-11-23 21:37:10,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48977 states, 48977 states have (on average 1.4089674745288605) internal successors, (69007), 48976 states have internal predecessors, (69007), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:10,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48977 states to 48977 states and 69007 transitions. [2023-11-23 21:37:10,603 INFO L240 hiAutomatonCegarLoop]: Abstraction has 48977 states and 69007 transitions. [2023-11-23 21:37:10,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 21:37:10,604 INFO L428 stractBuchiCegarLoop]: Abstraction has 48977 states and 69007 transitions. [2023-11-23 21:37:10,605 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-23 21:37:10,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48977 states and 69007 transitions. [2023-11-23 21:37:10,746 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48560 [2023-11-23 21:37:10,746 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:10,746 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:10,748 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:10,748 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:10,749 INFO L748 eck$LassoCheckResult]: Stem: 766894#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 766895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 767658#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 767659#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 767742#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 767356#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 767357#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 766910#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 766911#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 766841#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 766842#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 767117#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 767087#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 767088#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 767418#L854 assume !(0 == ~M_E~0); 767186#L854-2 assume !(0 == ~T1_E~0); 767187#L859-1 assume !(0 == ~T2_E~0); 766716#L864-1 assume !(0 == ~T3_E~0); 766717#L869-1 assume !(0 == ~T4_E~0); 766829#L874-1 assume !(0 == ~T5_E~0); 767713#L879-1 assume !(0 == ~T6_E~0); 767176#L884-1 assume !(0 == ~T7_E~0); 766582#L889-1 assume !(0 == ~T8_E~0); 766583#L894-1 assume !(0 == ~E_M~0); 766924#L899-1 assume !(0 == ~E_1~0); 767424#L904-1 assume !(0 == ~E_2~0); 767105#L909-1 assume !(0 == ~E_3~0); 767106#L914-1 assume !(0 == ~E_4~0); 767342#L919-1 assume !(0 == ~E_5~0); 767008#L924-1 assume !(0 == ~E_6~0); 766810#L929-1 assume 0 == ~E_7~0;~E_7~0 := 1; 766811#L934-1 assume !(0 == ~E_8~0); 767083#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 767084#L418 assume !(1 == ~m_pc~0); 767762#L418-2 is_master_triggered_~__retres1~0#1 := 0; 767763#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 767811#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 767812#L1061 assume !(0 != activate_threads_~tmp~1#1); 767454#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 767455#L437 assume !(1 == ~t1_pc~0); 767698#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 767699#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 766619#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 766620#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 767720#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 767721#L456 assume !(1 == ~t2_pc~0); 766872#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 766871#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 767040#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 767041#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 767228#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 767229#L475 assume !(1 == ~t3_pc~0); 767303#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 767304#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 766590#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 766591#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 766957#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 766958#L494 assume !(1 == ~t4_pc~0); 767001#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 767002#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 766726#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 766727#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 767372#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 767373#L513 assume !(1 == ~t5_pc~0); 767003#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 767004#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 767578#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 767579#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 767757#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 767758#L532 assume !(1 == ~t6_pc~0); 766832#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 766831#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 767022#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 767023#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 766928#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 766929#L551 assume !(1 == ~t7_pc~0); 767822#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 767378#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 767379#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 767821#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 767820#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 767130#L570 assume !(1 == ~t8_pc~0); 767131#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 767662#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 767663#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 767254#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 766705#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 766706#L952 assume !(1 == ~M_E~0); 766645#L952-2 assume !(1 == ~T1_E~0); 766646#L957-1 assume !(1 == ~T2_E~0); 767818#L962-1 assume !(1 == ~T3_E~0); 767273#L967-1 assume !(1 == ~T4_E~0); 767274#L972-1 assume !(1 == ~T5_E~0); 767743#L977-1 assume !(1 == ~T6_E~0); 767816#L982-1 assume !(1 == ~T7_E~0); 767815#L987-1 assume !(1 == ~T8_E~0); 766843#L992-1 assume !(1 == ~E_M~0); 766844#L997-1 assume !(1 == ~E_1~0); 767716#L1002-1 assume !(1 == ~E_2~0); 767717#L1007-1 assume !(1 == ~E_3~0); 766584#L1012-1 assume !(1 == ~E_4~0); 766585#L1017-1 assume !(1 == ~E_5~0); 767213#L1022-1 assume !(1 == ~E_6~0); 767214#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 767245#L1032-1 assume !(1 == ~E_8~0); 767403#L1037-1 assume { :end_inline_reset_delta_events } true; 767404#L1303-2 [2023-11-23 21:37:10,750 INFO L750 eck$LassoCheckResult]: Loop: 767404#L1303-2 assume !false; 779384#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 779380#L829-1 assume !false; 779378#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 779366#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 779361#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 779358#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 779356#L712 assume !(0 != eval_~tmp~0#1); 779357#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 789755#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 789748#L854-3 assume !(0 == ~M_E~0); 789741#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 789734#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 789726#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 789719#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 789712#L874-3 assume !(0 == ~T5_E~0); 789705#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 789698#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 789691#L889-3 assume !(0 == ~T8_E~0); 789683#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 789676#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 789669#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 789662#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 789652#L914-3 assume !(0 == ~E_4~0); 789644#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 789602#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 789595#L929-3 assume !(0 == ~E_7~0); 789596#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 790291#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 790289#L418-30 assume !(1 == ~m_pc~0); 790285#L418-32 is_master_triggered_~__retres1~0#1 := 0; 790283#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 790281#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 790278#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 790275#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 790273#L437-30 assume !(1 == ~t1_pc~0); 790271#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 790269#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 790267#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 790265#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 790263#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 790261#L456-30 assume !(1 == ~t2_pc~0); 790258#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 790256#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 790254#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 790253#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 790252#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 790251#L475-30 assume !(1 == ~t3_pc~0); 790250#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 790248#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 790247#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 790246#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 790245#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 790241#L494-30 assume !(1 == ~t4_pc~0); 790237#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 790235#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 790232#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 790230#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 790228#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 790225#L513-30 assume !(1 == ~t5_pc~0); 790223#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 790221#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 790219#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 790217#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 790215#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 790214#L532-30 assume !(1 == ~t6_pc~0); 790212#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 790209#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 790207#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 790205#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 790203#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 790201#L551-30 assume !(1 == ~t7_pc~0); 787055#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 790197#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 790195#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 789793#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 789787#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 789782#L570-30 assume !(1 == ~t8_pc~0); 789777#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 789771#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 789766#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 789760#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 789753#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 789746#L952-3 assume !(1 == ~M_E~0); 789739#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 789731#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 789724#L962-3 assume !(1 == ~T3_E~0); 789717#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 789710#L972-3 assume !(1 == ~T5_E~0); 789703#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 789696#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 789688#L987-3 assume !(1 == ~T8_E~0); 789681#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 789674#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 789667#L1002-3 assume !(1 == ~E_2~0); 789660#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 789650#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 789641#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 789601#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 789516#L1027-3 assume !(1 == ~E_7~0); 789511#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 789509#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 789361#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 789351#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 789349#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 776449#L1322 assume !(0 == start_simulation_~tmp~3#1); 776450#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 779402#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 779396#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 779394#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 779392#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 779390#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 779388#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 779387#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 767404#L1303-2 [2023-11-23 21:37:10,750 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:10,751 INFO L85 PathProgramCache]: Analyzing trace with hash -1185873335, now seen corresponding path program 1 times [2023-11-23 21:37:10,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:10,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535747342] [2023-11-23 21:37:10,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:10,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:10,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:10,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:10,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:10,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535747342] [2023-11-23 21:37:10,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535747342] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:10,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:10,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:10,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698161235] [2023-11-23 21:37:10,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:10,827 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:37:10,828 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:10,828 INFO L85 PathProgramCache]: Analyzing trace with hash -1143795218, now seen corresponding path program 1 times [2023-11-23 21:37:10,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:10,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783800765] [2023-11-23 21:37:10,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:10,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:10,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:10,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:10,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:10,888 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783800765] [2023-11-23 21:37:10,889 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783800765] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:10,889 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:10,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:10,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965735864] [2023-11-23 21:37:10,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:10,890 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:10,890 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:10,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 21:37:10,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 21:37:10,891 INFO L87 Difference]: Start difference. First operand 48977 states and 69007 transitions. cyclomatic complexity: 20062 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:11,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:11,256 INFO L93 Difference]: Finished difference Result 62017 states and 86974 transitions. [2023-11-23 21:37:11,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62017 states and 86974 transitions. [2023-11-23 21:37:11,526 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 61536 [2023-11-23 21:37:11,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62017 states to 62017 states and 86974 transitions. [2023-11-23 21:37:11,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62017 [2023-11-23 21:37:11,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62017 [2023-11-23 21:37:11,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62017 states and 86974 transitions. [2023-11-23 21:37:11,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:11,772 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62017 states and 86974 transitions. [2023-11-23 21:37:11,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62017 states and 86974 transitions. [2023-11-23 21:37:12,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62017 to 43649. [2023-11-23 21:37:12,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.401681596371051) internal successors, (61182), 43648 states have internal predecessors, (61182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:12,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 61182 transitions. [2023-11-23 21:37:12,945 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61182 transitions. [2023-11-23 21:37:12,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 21:37:12,946 INFO L428 stractBuchiCegarLoop]: Abstraction has 43649 states and 61182 transitions. [2023-11-23 21:37:12,946 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-23 21:37:12,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 61182 transitions. [2023-11-23 21:37:13,049 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2023-11-23 21:37:13,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:13,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:13,051 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:13,052 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:13,055 INFO L748 eck$LassoCheckResult]: Stem: 877897#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 877898#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 878638#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 878639#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 878714#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 878355#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 878356#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 877914#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 877915#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 877845#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 877846#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 878124#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 878093#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 878094#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 878414#L854 assume !(0 == ~M_E~0); 878189#L854-2 assume !(0 == ~T1_E~0); 878190#L859-1 assume !(0 == ~T2_E~0); 877720#L864-1 assume !(0 == ~T3_E~0); 877721#L869-1 assume !(0 == ~T4_E~0); 877836#L874-1 assume !(0 == ~T5_E~0); 878686#L879-1 assume !(0 == ~T6_E~0); 878179#L884-1 assume !(0 == ~T7_E~0); 877586#L889-1 assume !(0 == ~T8_E~0); 877587#L894-1 assume !(0 == ~E_M~0); 877929#L899-1 assume !(0 == ~E_1~0); 878421#L904-1 assume !(0 == ~E_2~0); 878113#L909-1 assume !(0 == ~E_3~0); 878114#L914-1 assume !(0 == ~E_4~0); 878342#L919-1 assume !(0 == ~E_5~0); 878016#L924-1 assume !(0 == ~E_6~0); 877817#L929-1 assume !(0 == ~E_7~0); 877818#L934-1 assume !(0 == ~E_8~0); 878090#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 877602#L418 assume !(1 == ~m_pc~0); 877579#L418-2 is_master_triggered_~__retres1~0#1 := 0; 878618#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 878619#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 878545#L1061 assume !(0 != activate_threads_~tmp~1#1); 878448#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 878449#L437 assume !(1 == ~t1_pc~0); 878673#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 878552#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 877623#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 877624#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 877962#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 878535#L456 assume !(1 == ~t2_pc~0); 877877#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 877876#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 878049#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 878050#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 878230#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 877715#L475 assume !(1 == ~t3_pc~0); 877716#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 877779#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 877594#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 877595#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 877965#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 877966#L494 assume !(1 == ~t4_pc~0); 878010#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 878011#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 877730#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 877731#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 878371#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 877774#L513 assume !(1 == ~t5_pc~0); 877775#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 878012#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 878564#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 877727#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 877728#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 877680#L532 assume !(1 == ~t6_pc~0); 877681#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 877837#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 878030#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 878031#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 877935#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 877936#L551 assume !(1 == ~t7_pc~0); 878422#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 878373#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 878374#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 878739#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 878746#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 878137#L570 assume !(1 == ~t8_pc~0); 878138#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 878645#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 878495#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 878253#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 877709#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 877710#L952 assume !(1 == ~M_E~0); 877649#L952-2 assume !(1 == ~T1_E~0); 877650#L957-1 assume !(1 == ~T2_E~0); 878512#L962-1 assume !(1 == ~T3_E~0); 878272#L967-1 assume !(1 == ~T4_E~0); 878273#L972-1 assume !(1 == ~T5_E~0); 878584#L977-1 assume !(1 == ~T6_E~0); 878585#L982-1 assume !(1 == ~T7_E~0); 877839#L987-1 assume !(1 == ~T8_E~0); 877840#L992-1 assume !(1 == ~E_M~0); 877847#L997-1 assume !(1 == ~E_1~0); 878228#L1002-1 assume !(1 == ~E_2~0); 878212#L1007-1 assume !(1 == ~E_3~0); 877588#L1012-1 assume !(1 == ~E_4~0); 877589#L1017-1 assume !(1 == ~E_5~0); 878215#L1022-1 assume !(1 == ~E_6~0); 878216#L1027-1 assume !(1 == ~E_7~0); 878243#L1032-1 assume !(1 == ~E_8~0); 878401#L1037-1 assume { :end_inline_reset_delta_events } true; 878402#L1303-2 [2023-11-23 21:37:13,055 INFO L750 eck$LassoCheckResult]: Loop: 878402#L1303-2 assume !false; 891878#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 891874#L829-1 assume !false; 891873#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 891867#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 891861#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 891860#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 891856#L712 assume !(0 != eval_~tmp~0#1); 891857#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 896930#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 896926#L854-3 assume !(0 == ~M_E~0); 896921#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 896917#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 896913#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 896909#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 896905#L874-3 assume !(0 == ~T5_E~0); 896901#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 896896#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 896892#L889-3 assume !(0 == ~T8_E~0); 896888#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 896884#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 896881#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 896877#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 896872#L914-3 assume !(0 == ~E_4~0); 896868#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 896864#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 896861#L929-3 assume !(0 == ~E_7~0); 896857#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 896852#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 896848#L418-30 assume !(1 == ~m_pc~0); 896844#L418-32 is_master_triggered_~__retres1~0#1 := 0; 896839#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 896834#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 896829#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 896823#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 896818#L437-30 assume !(1 == ~t1_pc~0); 896814#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 896810#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 896806#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 896802#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 896798#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 896795#L456-30 assume 1 == ~t2_pc~0; 896791#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 896786#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 896782#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 896778#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 896773#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 896769#L475-30 assume !(1 == ~t3_pc~0); 896764#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 896759#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 896754#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 896749#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 896745#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 896741#L494-30 assume 1 == ~t4_pc~0; 896737#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 896732#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 896728#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 896724#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 896719#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 896715#L513-30 assume !(1 == ~t5_pc~0); 896710#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 896706#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 896702#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 896698#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 896694#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 896690#L532-30 assume !(1 == ~t6_pc~0); 896685#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 896681#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 896677#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 896673#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 896669#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 896481#L551-30 assume !(1 == ~t7_pc~0); 896479#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 896477#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 896475#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 896473#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 896471#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 896469#L570-30 assume !(1 == ~t8_pc~0); 896467#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 896465#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 896463#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 896461#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 896459#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 896457#L952-3 assume !(1 == ~M_E~0); 896455#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 896453#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 896451#L962-3 assume !(1 == ~T3_E~0); 896449#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 896447#L972-3 assume !(1 == ~T5_E~0); 896445#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 896443#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 896441#L987-3 assume !(1 == ~T8_E~0); 896439#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 896437#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 896435#L1002-3 assume !(1 == ~E_2~0); 896433#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 896431#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 896429#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 896427#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 896426#L1027-3 assume !(1 == ~E_7~0); 896425#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 896424#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 896381#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 896364#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 896306#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 887996#L1322 assume !(0 == start_simulation_~tmp~3#1); 887997#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 891898#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 891892#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 891890#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 891888#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 891886#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 891885#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 891881#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 878402#L1303-2 [2023-11-23 21:37:13,056 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:13,056 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 1 times [2023-11-23 21:37:13,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:13,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765787196] [2023-11-23 21:37:13,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:13,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:13,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 21:37:13,073 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 21:37:13,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 21:37:13,168 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 21:37:13,169 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:13,169 INFO L85 PathProgramCache]: Analyzing trace with hash -9348116, now seen corresponding path program 1 times [2023-11-23 21:37:13,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:13,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117326326] [2023-11-23 21:37:13,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:13,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:13,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:13,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:13,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:13,214 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117326326] [2023-11-23 21:37:13,214 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117326326] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:13,214 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:13,215 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:13,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413826115] [2023-11-23 21:37:13,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:13,215 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:13,215 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:13,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:37:13,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:37:13,216 INFO L87 Difference]: Start difference. First operand 43649 states and 61182 transitions. cyclomatic complexity: 17565 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:13,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:13,387 INFO L93 Difference]: Finished difference Result 49009 states and 68747 transitions. [2023-11-23 21:37:13,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49009 states and 68747 transitions. [2023-11-23 21:37:13,560 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48592 [2023-11-23 21:37:13,667 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49009 states to 49009 states and 68747 transitions. [2023-11-23 21:37:13,668 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49009 [2023-11-23 21:37:13,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49009 [2023-11-23 21:37:13,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49009 states and 68747 transitions. [2023-11-23 21:37:13,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:13,712 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49009 states and 68747 transitions. [2023-11-23 21:37:13,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49009 states and 68747 transitions. [2023-11-23 21:37:14,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49009 to 49009. [2023-11-23 21:37:14,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49009 states, 49009 states have (on average 1.4027423534452856) internal successors, (68747), 49008 states have internal predecessors, (68747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:14,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49009 states to 49009 states and 68747 transitions. [2023-11-23 21:37:14,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49009 states and 68747 transitions. [2023-11-23 21:37:14,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:37:14,766 INFO L428 stractBuchiCegarLoop]: Abstraction has 49009 states and 68747 transitions. [2023-11-23 21:37:14,766 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-23 21:37:14,766 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49009 states and 68747 transitions. [2023-11-23 21:37:14,886 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48592 [2023-11-23 21:37:14,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:14,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:14,887 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:14,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:14,888 INFO L748 eck$LassoCheckResult]: Stem: 970560#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 970561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 971300#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 971301#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 971379#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 971009#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 971010#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 970578#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 970579#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 970508#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 970509#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 970781#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 970752#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 970753#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 971075#L854 assume !(0 == ~M_E~0); 970845#L854-2 assume !(0 == ~T1_E~0); 970846#L859-1 assume !(0 == ~T2_E~0); 970385#L864-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 970386#L869-1 assume !(0 == ~T4_E~0); 971383#L874-1 assume !(0 == ~T5_E~0); 971384#L879-1 assume !(0 == ~T6_E~0); 970834#L884-1 assume !(0 == ~T7_E~0); 970835#L889-1 assume !(0 == ~T8_E~0); 970592#L894-1 assume !(0 == ~E_M~0); 970593#L899-1 assume !(0 == ~E_1~0); 971465#L904-1 assume !(0 == ~E_2~0); 970770#L909-1 assume !(0 == ~E_3~0); 970771#L914-1 assume !(0 == ~E_4~0); 971028#L919-1 assume !(0 == ~E_5~0); 971029#L924-1 assume !(0 == ~E_6~0); 970481#L929-1 assume !(0 == ~E_7~0); 970482#L934-1 assume !(0 == ~E_8~0); 970749#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 970266#L418 assume !(1 == ~m_pc~0); 970267#L418-2 is_master_triggered_~__retres1~0#1 := 0; 971283#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 971284#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 971210#L1061 assume !(0 != activate_threads_~tmp~1#1); 971211#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 971390#L437 assume !(1 == ~t1_pc~0); 971391#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 971218#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 971219#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 970622#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 970623#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 971198#L456 assume !(1 == ~t2_pc~0); 971199#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 971385#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 971386#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 971240#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 971241#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 970380#L475 assume !(1 == ~t3_pc~0); 970381#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 970445#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 970446#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 971339#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 971340#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 971274#L494 assume !(1 == ~t4_pc~0); 971275#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 970966#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 970967#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 971420#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 971421#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 970440#L513 assume !(1 == ~t5_pc~0); 970441#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 971397#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 971398#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 970393#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 970394#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 970345#L532 assume !(1 == ~t6_pc~0); 970346#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 970500#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 970689#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 970690#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 970597#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 970598#L551 assume !(1 == ~t7_pc~0); 971084#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 971031#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 971032#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 971411#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 971419#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 970793#L570 assume !(1 == ~t8_pc~0); 970794#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 971305#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 971161#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 970909#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 970374#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 970375#L952 assume !(1 == ~M_E~0); 970314#L952-2 assume !(1 == ~T1_E~0); 970315#L957-1 assume !(1 == ~T2_E~0); 971176#L962-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 970929#L967-1 assume !(1 == ~T4_E~0); 970930#L972-1 assume !(1 == ~T5_E~0); 971247#L977-1 assume !(1 == ~T6_E~0); 971248#L982-1 assume !(1 == ~T7_E~0); 970502#L987-1 assume !(1 == ~T8_E~0); 970503#L992-1 assume !(1 == ~E_M~0); 970510#L997-1 assume !(1 == ~E_1~0); 970882#L1002-1 assume !(1 == ~E_2~0); 970867#L1007-1 assume !(1 == ~E_3~0); 970252#L1012-1 assume !(1 == ~E_4~0); 970253#L1017-1 assume !(1 == ~E_5~0); 970870#L1022-1 assume !(1 == ~E_6~0); 970871#L1027-1 assume !(1 == ~E_7~0); 970898#L1032-1 assume !(1 == ~E_8~0); 971061#L1037-1 assume { :end_inline_reset_delta_events } true; 971062#L1303-2 [2023-11-23 21:37:14,888 INFO L750 eck$LassoCheckResult]: Loop: 971062#L1303-2 assume !false; 975485#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 975480#L829-1 assume !false; 975478#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 975466#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 975460#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 975458#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 975454#L712 assume !(0 != eval_~tmp~0#1); 975455#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 975851#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 975850#L854-3 assume !(0 == ~M_E~0); 975849#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 975848#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 975846#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 975847#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 976330#L874-3 assume !(0 == ~T5_E~0); 976319#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 976290#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 976289#L889-3 assume !(0 == ~T8_E~0); 976288#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 976286#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 976284#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 976283#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 976282#L914-3 assume !(0 == ~E_4~0); 976280#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 976277#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 976275#L929-3 assume !(0 == ~E_7~0); 976273#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 976270#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 975695#L418-30 assume 1 == ~m_pc~0; 975693#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 975694#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 975699#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 975684#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 975682#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 975680#L437-30 assume !(1 == ~t1_pc~0); 975678#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 975675#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 975673#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 975671#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 975669#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 975667#L456-30 assume !(1 == ~t2_pc~0); 975664#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 975662#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 975660#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 975658#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 975656#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 975654#L475-30 assume !(1 == ~t3_pc~0); 975652#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 975649#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 975647#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 975645#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 975643#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 975641#L494-30 assume !(1 == ~t4_pc~0); 975638#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 975636#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 975634#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 975632#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 975630#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 975628#L513-30 assume !(1 == ~t5_pc~0); 975626#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 975623#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 975621#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 975619#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 975617#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 975615#L532-30 assume !(1 == ~t6_pc~0); 975612#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 975611#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 975609#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 975607#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 975605#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 975603#L551-30 assume !(1 == ~t7_pc~0); 974937#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 975600#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 975598#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 975596#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 975594#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 975592#L570-30 assume !(1 == ~t8_pc~0); 975591#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 975587#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 975585#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 975583#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 975582#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 975579#L952-3 assume !(1 == ~M_E~0); 975578#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 975577#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 975574#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 975569#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 975565#L972-3 assume !(1 == ~T5_E~0); 975561#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 975560#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 975559#L987-3 assume !(1 == ~T8_E~0); 975558#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 975557#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 975556#L1002-3 assume !(1 == ~E_2~0); 975555#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 975554#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 975553#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 975552#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 975551#L1027-3 assume !(1 == ~E_7~0); 975550#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 975548#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 975536#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 975526#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 975524#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 975521#L1322 assume !(0 == start_simulation_~tmp~3#1); 975519#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 975505#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 975499#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 975497#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 975495#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 975493#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 975491#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 975489#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 971062#L1303-2 [2023-11-23 21:37:14,889 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:14,889 INFO L85 PathProgramCache]: Analyzing trace with hash -1471406391, now seen corresponding path program 1 times [2023-11-23 21:37:14,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:14,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877384221] [2023-11-23 21:37:14,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:14,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:14,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:14,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:14,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:14,949 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877384221] [2023-11-23 21:37:14,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [877384221] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:14,949 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:14,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:14,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884327566] [2023-11-23 21:37:14,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:14,950 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:37:14,951 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:14,951 INFO L85 PathProgramCache]: Analyzing trace with hash 1640702573, now seen corresponding path program 1 times [2023-11-23 21:37:14,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:14,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2045941269] [2023-11-23 21:37:14,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:14,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:14,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:14,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:14,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:14,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2045941269] [2023-11-23 21:37:14,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2045941269] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:14,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:14,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:14,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607991209] [2023-11-23 21:37:14,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:14,996 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:14,996 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:14,996 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 21:37:14,996 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 21:37:14,997 INFO L87 Difference]: Start difference. First operand 49009 states and 68747 transitions. cyclomatic complexity: 19770 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:15,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:15,271 INFO L93 Difference]: Finished difference Result 64096 states and 89671 transitions. [2023-11-23 21:37:15,272 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64096 states and 89671 transitions. [2023-11-23 21:37:15,571 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 63632 [2023-11-23 21:37:15,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64096 states to 64096 states and 89671 transitions. [2023-11-23 21:37:15,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64096 [2023-11-23 21:37:15,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64096 [2023-11-23 21:37:15,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64096 states and 89671 transitions. [2023-11-23 21:37:15,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:15,796 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64096 states and 89671 transitions. [2023-11-23 21:37:15,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64096 states and 89671 transitions. [2023-11-23 21:37:16,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64096 to 43649. [2023-11-23 21:37:16,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.4001924442713465) internal successors, (61117), 43648 states have internal predecessors, (61117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:16,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 61117 transitions. [2023-11-23 21:37:16,742 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61117 transitions. [2023-11-23 21:37:16,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 21:37:16,743 INFO L428 stractBuchiCegarLoop]: Abstraction has 43649 states and 61117 transitions. [2023-11-23 21:37:16,743 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-23 21:37:16,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 61117 transitions. [2023-11-23 21:37:16,842 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2023-11-23 21:37:16,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:16,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:16,843 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:16,843 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:16,844 INFO L748 eck$LassoCheckResult]: Stem: 1083674#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1083675#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1084372#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1084373#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1084430#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1084113#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1084114#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1083697#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1083698#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1083625#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1083626#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1083898#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1083867#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1083868#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1084170#L854 assume !(0 == ~M_E~0); 1083965#L854-2 assume !(0 == ~T1_E~0); 1083966#L859-1 assume !(0 == ~T2_E~0); 1083500#L864-1 assume !(0 == ~T3_E~0); 1083501#L869-1 assume !(0 == ~T4_E~0); 1083614#L874-1 assume !(0 == ~T5_E~0); 1084408#L879-1 assume !(0 == ~T6_E~0); 1083950#L884-1 assume !(0 == ~T7_E~0); 1083366#L889-1 assume !(0 == ~T8_E~0); 1083367#L894-1 assume !(0 == ~E_M~0); 1083708#L899-1 assume !(0 == ~E_1~0); 1084177#L904-1 assume !(0 == ~E_2~0); 1083891#L909-1 assume !(0 == ~E_3~0); 1083892#L914-1 assume !(0 == ~E_4~0); 1084102#L919-1 assume !(0 == ~E_5~0); 1083789#L924-1 assume !(0 == ~E_6~0); 1083600#L929-1 assume !(0 == ~E_7~0); 1083601#L934-1 assume !(0 == ~E_8~0); 1083866#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1083382#L418 assume !(1 == ~m_pc~0); 1083358#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1084357#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1084358#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1084294#L1061 assume !(0 != activate_threads_~tmp~1#1); 1084204#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1084205#L437 assume !(1 == ~t1_pc~0); 1084403#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1084301#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1083406#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1083407#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1083737#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1084287#L456 assume !(1 == ~t2_pc~0); 1083658#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1083657#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1083821#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1083822#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1083999#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1083495#L475 assume !(1 == ~t3_pc~0); 1083496#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1083561#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1083374#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1083375#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1083740#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1083741#L494 assume !(1 == ~t4_pc~0); 1083783#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1083784#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1083510#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1083511#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1084129#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1083557#L513 assume !(1 == ~t5_pc~0); 1083558#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1083788#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1084313#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1083507#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1083508#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1083462#L532 assume !(1 == ~t6_pc~0); 1083463#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1083615#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1083802#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1083803#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1083710#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1083711#L551 assume !(1 == ~t7_pc~0); 1084178#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1084131#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1084132#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1084448#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1084454#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1083912#L570 assume !(1 == ~t8_pc~0); 1083913#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1084377#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1084248#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1084022#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1083493#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1083494#L952 assume !(1 == ~M_E~0); 1083429#L952-2 assume !(1 == ~T1_E~0); 1083430#L957-1 assume !(1 == ~T2_E~0); 1084262#L962-1 assume !(1 == ~T3_E~0); 1084038#L967-1 assume !(1 == ~T4_E~0); 1084039#L972-1 assume !(1 == ~T5_E~0); 1084330#L977-1 assume !(1 == ~T6_E~0); 1084331#L982-1 assume !(1 == ~T7_E~0); 1083617#L987-1 assume !(1 == ~T8_E~0); 1083618#L992-1 assume !(1 == ~E_M~0); 1083627#L997-1 assume !(1 == ~E_1~0); 1083997#L1002-1 assume !(1 == ~E_2~0); 1083982#L1007-1 assume !(1 == ~E_3~0); 1083368#L1012-1 assume !(1 == ~E_4~0); 1083369#L1017-1 assume !(1 == ~E_5~0); 1083988#L1022-1 assume !(1 == ~E_6~0); 1083989#L1027-1 assume !(1 == ~E_7~0); 1084011#L1032-1 assume !(1 == ~E_8~0); 1084158#L1037-1 assume { :end_inline_reset_delta_events } true; 1084159#L1303-2 [2023-11-23 21:37:16,844 INFO L750 eck$LassoCheckResult]: Loop: 1084159#L1303-2 assume !false; 1099680#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1099669#L829-1 assume !false; 1099528#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1099414#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1099403#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1099396#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1099388#L712 assume !(0 != eval_~tmp~0#1); 1099389#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1103506#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1103502#L854-3 assume !(0 == ~M_E~0); 1103498#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1103494#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1103490#L864-3 assume !(0 == ~T3_E~0); 1103486#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1103481#L874-3 assume !(0 == ~T5_E~0); 1103477#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1103472#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1103468#L889-3 assume !(0 == ~T8_E~0); 1103464#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1103460#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1103455#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1103451#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1103447#L914-3 assume !(0 == ~E_4~0); 1103443#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1103439#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1103434#L929-3 assume !(0 == ~E_7~0); 1103428#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1103423#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1103418#L418-30 assume 1 == ~m_pc~0; 1103413#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1103408#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1103403#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1103398#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1103394#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1103390#L437-30 assume !(1 == ~t1_pc~0); 1103386#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1103382#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1103377#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1103372#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1103367#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1103362#L456-30 assume !(1 == ~t2_pc~0); 1103355#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1103349#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1103346#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1103344#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1103342#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1103340#L475-30 assume !(1 == ~t3_pc~0); 1103338#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1103336#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1103333#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1103331#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1103329#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1103315#L494-30 assume !(1 == ~t4_pc~0); 1103309#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1103304#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1103299#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1103294#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1103289#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1103284#L513-30 assume !(1 == ~t5_pc~0); 1103278#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1103270#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1103267#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1103265#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1103264#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1103263#L532-30 assume !(1 == ~t6_pc~0); 1103261#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1103260#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1103243#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1103236#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1103228#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1103220#L551-30 assume !(1 == ~t7_pc~0); 1096306#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1103207#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1103203#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1103198#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 1103194#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1103189#L570-30 assume !(1 == ~t8_pc~0); 1103184#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1103178#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1103173#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1103167#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1103162#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1103157#L952-3 assume !(1 == ~M_E~0); 1103152#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1103147#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1103143#L962-3 assume !(1 == ~T3_E~0); 1103139#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1103135#L972-3 assume !(1 == ~T5_E~0); 1103130#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1103124#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1103117#L987-3 assume !(1 == ~T8_E~0); 1103111#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1103105#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1103099#L1002-3 assume !(1 == ~E_2~0); 1103095#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1103090#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1103086#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1103080#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1103075#L1027-3 assume !(1 == ~E_7~0); 1103071#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1103069#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1102946#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1102931#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1102621#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1090254#L1322 assume !(0 == start_simulation_~tmp~3#1); 1090255#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1099729#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1099723#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1099721#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1099719#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1099717#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1099715#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1099713#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1084159#L1303-2 [2023-11-23 21:37:16,845 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:16,845 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 2 times [2023-11-23 21:37:16,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:16,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769279039] [2023-11-23 21:37:16,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:16,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:16,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 21:37:16,859 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 21:37:16,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 21:37:16,905 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 21:37:16,906 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:16,906 INFO L85 PathProgramCache]: Analyzing trace with hash -175912915, now seen corresponding path program 1 times [2023-11-23 21:37:16,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:16,906 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117915113] [2023-11-23 21:37:16,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:16,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:16,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:16,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:16,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:16,958 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117915113] [2023-11-23 21:37:16,958 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117915113] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:16,958 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:16,958 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:16,958 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1236583710] [2023-11-23 21:37:16,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:16,959 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:16,959 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:16,959 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:37:16,959 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:37:16,960 INFO L87 Difference]: Start difference. First operand 43649 states and 61117 transitions. cyclomatic complexity: 17500 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:17,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:17,230 INFO L93 Difference]: Finished difference Result 81937 states and 113513 transitions. [2023-11-23 21:37:17,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81937 states and 113513 transitions. [2023-11-23 21:37:17,486 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 81296 [2023-11-23 21:37:17,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81937 states to 81937 states and 113513 transitions. [2023-11-23 21:37:17,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81937 [2023-11-23 21:37:17,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81937 [2023-11-23 21:37:17,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81937 states and 113513 transitions. [2023-11-23 21:37:18,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:18,360 INFO L218 hiAutomatonCegarLoop]: Abstraction has 81937 states and 113513 transitions. [2023-11-23 21:37:18,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81937 states and 113513 transitions. [2023-11-23 21:37:19,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81937 to 81905. [2023-11-23 21:37:19,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81905 states, 81905 states have (on average 1.3855198095354373) internal successors, (113481), 81904 states have internal predecessors, (113481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:19,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81905 states to 81905 states and 113481 transitions. [2023-11-23 21:37:19,369 INFO L240 hiAutomatonCegarLoop]: Abstraction has 81905 states and 113481 transitions. [2023-11-23 21:37:19,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:37:19,370 INFO L428 stractBuchiCegarLoop]: Abstraction has 81905 states and 113481 transitions. [2023-11-23 21:37:19,370 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-23 21:37:19,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81905 states and 113481 transitions. [2023-11-23 21:37:19,628 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 81264 [2023-11-23 21:37:19,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:19,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:19,630 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:19,630 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:19,631 INFO L748 eck$LassoCheckResult]: Stem: 1209268#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1209269#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1210055#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1210056#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1210149#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1209732#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1209733#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1209290#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1209291#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1209217#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1209218#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1209499#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1209468#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1209469#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1209803#L854 assume !(0 == ~M_E~0); 1209569#L854-2 assume !(0 == ~T1_E~0); 1209570#L859-1 assume !(0 == ~T2_E~0); 1209092#L864-1 assume !(0 == ~T3_E~0); 1209093#L869-1 assume !(0 == ~T4_E~0); 1209204#L874-1 assume !(0 == ~T5_E~0); 1210116#L879-1 assume !(0 == ~T6_E~0); 1209555#L884-1 assume !(0 == ~T7_E~0); 1208957#L889-1 assume !(0 == ~T8_E~0); 1208958#L894-1 assume !(0 == ~E_M~0); 1209302#L899-1 assume !(0 == ~E_1~0); 1209809#L904-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1209810#L909-1 assume !(0 == ~E_3~0); 1209720#L914-1 assume !(0 == ~E_4~0); 1209721#L919-1 assume !(0 == ~E_5~0); 1209389#L924-1 assume !(0 == ~E_6~0); 1209390#L929-1 assume !(0 == ~E_7~0); 1210129#L934-1 assume !(0 == ~E_8~0); 1210130#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1210247#L418 assume !(1 == ~m_pc~0); 1208949#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1210029#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1210030#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1210241#L1061 assume !(0 != activate_threads_~tmp~1#1); 1209840#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1209841#L437 assume !(1 == ~t1_pc~0); 1210097#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1210098#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1208999#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1209000#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1210118#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1210119#L456 assume !(1 == ~t2_pc~0); 1210243#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1209250#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1210158#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1209982#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1209983#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1209087#L475 assume !(1 == ~t3_pc~0); 1209088#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1209152#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1209153#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1210102#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1210103#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1210021#L494 assume !(1 == ~t4_pc~0); 1210022#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1209685#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1209686#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1210203#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1210204#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1209148#L513 assume !(1 == ~t5_pc~0); 1209149#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1210174#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1210175#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1209099#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1209100#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1209054#L532 assume !(1 == ~t6_pc~0); 1209055#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1209529#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1209530#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1210139#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1210140#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1209987#L551 assume !(1 == ~t7_pc~0); 1209811#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1209812#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1210189#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1210190#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1210233#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1209512#L570 assume !(1 == ~t8_pc~0); 1209513#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1210063#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1210064#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1209627#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1209628#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1209956#L952 assume !(1 == ~M_E~0); 1209957#L952-2 assume !(1 == ~T1_E~0); 1209906#L957-1 assume !(1 == ~T2_E~0); 1209907#L962-1 assume !(1 == ~T3_E~0); 1209646#L967-1 assume !(1 == ~T4_E~0); 1209647#L972-1 assume !(1 == ~T5_E~0); 1209990#L977-1 assume !(1 == ~T6_E~0); 1209991#L982-1 assume !(1 == ~T7_E~0); 1209209#L987-1 assume !(1 == ~T8_E~0); 1209210#L992-1 assume !(1 == ~E_M~0); 1209219#L997-1 assume !(1 == ~E_1~0); 1209599#L1002-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1209584#L1007-1 assume !(1 == ~E_3~0); 1208959#L1012-1 assume !(1 == ~E_4~0); 1208960#L1017-1 assume !(1 == ~E_5~0); 1209590#L1022-1 assume !(1 == ~E_6~0); 1209591#L1027-1 assume !(1 == ~E_7~0); 1209616#L1032-1 assume !(1 == ~E_8~0); 1209787#L1037-1 assume { :end_inline_reset_delta_events } true; 1209788#L1303-2 [2023-11-23 21:37:19,632 INFO L750 eck$LassoCheckResult]: Loop: 1209788#L1303-2 assume !false; 1218114#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1218109#L829-1 assume !false; 1218107#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1218093#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1218087#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1218086#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1218083#L712 assume !(0 != eval_~tmp~0#1); 1218084#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1284318#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1284316#L854-3 assume !(0 == ~M_E~0); 1284314#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1284312#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1284310#L864-3 assume !(0 == ~T3_E~0); 1284308#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1284306#L874-3 assume !(0 == ~T5_E~0); 1284304#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1284302#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1284300#L889-3 assume !(0 == ~T8_E~0); 1284298#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1284296#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1284292#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1284291#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1284290#L914-3 assume !(0 == ~E_4~0); 1284287#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1284285#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1284283#L929-3 assume !(0 == ~E_7~0); 1284279#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1284277#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1284275#L418-30 assume 1 == ~m_pc~0; 1284273#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1284274#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1284320#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1284263#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1284261#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1284259#L437-30 assume !(1 == ~t1_pc~0); 1284257#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1284255#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1284253#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1284250#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1284248#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1284246#L456-30 assume !(1 == ~t2_pc~0); 1284059#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1284057#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1284055#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1284053#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1284051#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1284049#L475-30 assume !(1 == ~t3_pc~0); 1284047#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1284045#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1284043#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1284041#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1284039#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1284037#L494-30 assume 1 == ~t4_pc~0; 1284034#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1284031#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1284029#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1284027#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1284025#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1284023#L513-30 assume !(1 == ~t5_pc~0); 1284020#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1284018#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1284016#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1284014#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1284012#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1284010#L532-30 assume 1 == ~t6_pc~0; 1284007#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1284004#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1284002#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1284000#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1283998#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1218231#L551-30 assume !(1 == ~t7_pc~0); 1218229#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1218227#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1218225#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1218223#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 1218221#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1218219#L570-30 assume !(1 == ~t8_pc~0); 1218217#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1218215#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1218213#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1218211#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1218209#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1218207#L952-3 assume !(1 == ~M_E~0); 1218205#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1218203#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1218201#L962-3 assume !(1 == ~T3_E~0); 1218199#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1218197#L972-3 assume !(1 == ~T5_E~0); 1218195#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1218193#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1218192#L987-3 assume !(1 == ~T8_E~0); 1218191#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1218189#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1218186#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1218183#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1218181#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1218178#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1218176#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1218174#L1027-3 assume !(1 == ~E_7~0); 1218172#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1218170#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1218164#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1218154#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1218152#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1218149#L1322 assume !(0 == start_simulation_~tmp~3#1); 1218147#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1218135#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1218129#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1218126#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1218124#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1218122#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1218120#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1218118#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1209788#L1303-2 [2023-11-23 21:37:19,632 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:19,633 INFO L85 PathProgramCache]: Analyzing trace with hash -1396023607, now seen corresponding path program 1 times [2023-11-23 21:37:19,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:19,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991879612] [2023-11-23 21:37:19,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:19,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:19,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:19,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:19,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:19,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991879612] [2023-11-23 21:37:19,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1991879612] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:19,691 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:19,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 21:37:19,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115973390] [2023-11-23 21:37:19,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:19,692 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 21:37:19,692 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:19,693 INFO L85 PathProgramCache]: Analyzing trace with hash -1854999955, now seen corresponding path program 1 times [2023-11-23 21:37:19,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:19,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264040318] [2023-11-23 21:37:19,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:19,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:19,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:19,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:19,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:19,772 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264040318] [2023-11-23 21:37:19,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1264040318] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:19,773 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:19,773 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 21:37:19,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252788484] [2023-11-23 21:37:19,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:19,774 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:19,774 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:19,775 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:37:19,775 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:37:19,775 INFO L87 Difference]: Start difference. First operand 81905 states and 113481 transitions. cyclomatic complexity: 31608 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:19,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:19,986 INFO L93 Difference]: Finished difference Result 43649 states and 60442 transitions. [2023-11-23 21:37:19,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43649 states and 60442 transitions. [2023-11-23 21:37:20,807 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2023-11-23 21:37:20,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43649 states to 43649 states and 60442 transitions. [2023-11-23 21:37:20,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43649 [2023-11-23 21:37:20,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43649 [2023-11-23 21:37:20,893 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43649 states and 60442 transitions. [2023-11-23 21:37:20,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:20,908 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43649 states and 60442 transitions. [2023-11-23 21:37:20,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43649 states and 60442 transitions. [2023-11-23 21:37:21,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43649 to 43649. [2023-11-23 21:37:21,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.384728172466723) internal successors, (60442), 43648 states have internal predecessors, (60442), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:21,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 60442 transitions. [2023-11-23 21:37:21,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 60442 transitions. [2023-11-23 21:37:21,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:37:21,294 INFO L428 stractBuchiCegarLoop]: Abstraction has 43649 states and 60442 transitions. [2023-11-23 21:37:21,294 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-23 21:37:21,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 60442 transitions. [2023-11-23 21:37:21,393 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2023-11-23 21:37:21,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:21,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:21,395 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:21,395 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:21,395 INFO L748 eck$LassoCheckResult]: Stem: 1334828#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1334829#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1335568#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1335569#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1335651#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1335283#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1335284#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1334851#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1334852#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1334778#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1334779#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1335056#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1335025#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1335026#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1335345#L854 assume !(0 == ~M_E~0); 1335124#L854-2 assume !(0 == ~T1_E~0); 1335125#L859-1 assume !(0 == ~T2_E~0); 1334654#L864-1 assume !(0 == ~T3_E~0); 1334655#L869-1 assume !(0 == ~T4_E~0); 1334767#L874-1 assume !(0 == ~T5_E~0); 1335624#L879-1 assume !(0 == ~T6_E~0); 1335109#L884-1 assume !(0 == ~T7_E~0); 1334520#L889-1 assume !(0 == ~T8_E~0); 1334521#L894-1 assume !(0 == ~E_M~0); 1334862#L899-1 assume !(0 == ~E_1~0); 1335351#L904-1 assume !(0 == ~E_2~0); 1335049#L909-1 assume !(0 == ~E_3~0); 1335050#L914-1 assume !(0 == ~E_4~0); 1335272#L919-1 assume !(0 == ~E_5~0); 1334948#L924-1 assume !(0 == ~E_6~0); 1334753#L929-1 assume !(0 == ~E_7~0); 1334754#L934-1 assume !(0 == ~E_8~0); 1335024#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1334536#L418 assume !(1 == ~m_pc~0); 1334513#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1335548#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1335549#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1335476#L1061 assume !(0 != activate_threads_~tmp~1#1); 1335380#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1335381#L437 assume !(1 == ~t1_pc~0); 1335605#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1335485#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1334560#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1334561#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1334896#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1335468#L456 assume !(1 == ~t2_pc~0); 1334809#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1335268#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1334982#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1334983#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1335159#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1334649#L475 assume !(1 == ~t3_pc~0); 1334650#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1334716#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1334528#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1334529#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1334899#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1334900#L494 assume !(1 == ~t4_pc~0); 1334943#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1334944#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1334664#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1334665#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1335299#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1334712#L513 assume !(1 == ~t5_pc~0); 1334713#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1334947#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1335498#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1334661#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1334662#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1334616#L532 assume !(1 == ~t6_pc~0); 1334617#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1334768#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1334962#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1334963#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1334866#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1334867#L551 assume !(1 == ~t7_pc~0); 1335352#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1335301#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1335302#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1335674#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1335677#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1335069#L570 assume !(1 == ~t8_pc~0); 1335070#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1335577#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1335428#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1335184#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1334647#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1334648#L952 assume !(1 == ~M_E~0); 1334583#L952-2 assume !(1 == ~T1_E~0); 1334584#L957-1 assume !(1 == ~T2_E~0); 1335443#L962-1 assume !(1 == ~T3_E~0); 1335203#L967-1 assume !(1 == ~T4_E~0); 1335204#L972-1 assume !(1 == ~T5_E~0); 1335516#L977-1 assume !(1 == ~T6_E~0); 1335517#L982-1 assume !(1 == ~T7_E~0); 1334770#L987-1 assume !(1 == ~T8_E~0); 1334771#L992-1 assume !(1 == ~E_M~0); 1334780#L997-1 assume !(1 == ~E_1~0); 1335157#L1002-1 assume !(1 == ~E_2~0); 1335140#L1007-1 assume !(1 == ~E_3~0); 1334522#L1012-1 assume !(1 == ~E_4~0); 1334523#L1017-1 assume !(1 == ~E_5~0); 1335146#L1022-1 assume !(1 == ~E_6~0); 1335147#L1027-1 assume !(1 == ~E_7~0); 1335173#L1032-1 assume !(1 == ~E_8~0); 1335331#L1037-1 assume { :end_inline_reset_delta_events } true; 1335332#L1303-2 [2023-11-23 21:37:21,396 INFO L750 eck$LassoCheckResult]: Loop: 1335332#L1303-2 assume !false; 1342933#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1342928#L829-1 assume !false; 1342926#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1342910#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1342904#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1342902#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1342899#L712 assume !(0 != eval_~tmp~0#1); 1342900#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1347733#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1347731#L854-3 assume !(0 == ~M_E~0); 1347728#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1347724#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1347720#L864-3 assume !(0 == ~T3_E~0); 1347716#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1347712#L874-3 assume !(0 == ~T5_E~0); 1347708#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1347704#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1347700#L889-3 assume !(0 == ~T8_E~0); 1347697#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1347694#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1347692#L904-3 assume !(0 == ~E_2~0); 1347690#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1347688#L914-3 assume !(0 == ~E_4~0); 1347686#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1347684#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1347682#L929-3 assume !(0 == ~E_7~0); 1347680#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1347678#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1347676#L418-30 assume !(1 == ~m_pc~0); 1347672#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1347670#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1347668#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1347666#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1347663#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1347661#L437-30 assume !(1 == ~t1_pc~0); 1347659#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1347657#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1347655#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1347653#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1347651#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1347649#L456-30 assume !(1 == ~t2_pc~0); 1347646#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1347644#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1347642#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1347640#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1347638#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1347636#L475-30 assume !(1 == ~t3_pc~0); 1347634#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1347632#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1347630#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1347628#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1347627#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1347626#L494-30 assume !(1 == ~t4_pc~0); 1347624#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1347614#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1347612#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1347610#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1347607#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1347605#L513-30 assume !(1 == ~t5_pc~0); 1347604#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1347603#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1347602#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1347601#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1347600#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1347599#L532-30 assume !(1 == ~t6_pc~0); 1347588#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1347586#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1347584#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1347582#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1347580#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1343186#L551-30 assume !(1 == ~t7_pc~0); 1343184#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1343182#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1343180#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1343177#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 1343175#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1343173#L570-30 assume !(1 == ~t8_pc~0); 1343171#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1343169#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1343167#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1343166#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1343164#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1343162#L952-3 assume !(1 == ~M_E~0); 1343160#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1343158#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1343156#L962-3 assume !(1 == ~T3_E~0); 1343153#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1343151#L972-3 assume !(1 == ~T5_E~0); 1343149#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1343147#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1343145#L987-3 assume !(1 == ~T8_E~0); 1343143#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1343141#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1343139#L1002-3 assume !(1 == ~E_2~0); 1343137#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1343135#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1343133#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1343131#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1343129#L1027-3 assume !(1 == ~E_7~0); 1343127#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1343125#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1343121#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1343111#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1343109#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1343106#L1322 assume !(0 == start_simulation_~tmp~3#1); 1343104#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1342953#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1342947#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1342945#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1342942#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1342940#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1342938#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1342936#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1335332#L1303-2 [2023-11-23 21:37:21,396 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:21,396 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 3 times [2023-11-23 21:37:21,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:21,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538381565] [2023-11-23 21:37:21,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:21,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:21,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 21:37:21,410 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 21:37:21,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 21:37:21,449 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 21:37:21,450 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:21,450 INFO L85 PathProgramCache]: Analyzing trace with hash 960520690, now seen corresponding path program 1 times [2023-11-23 21:37:21,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:21,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413190566] [2023-11-23 21:37:21,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:21,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:21,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:21,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:21,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:21,511 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1413190566] [2023-11-23 21:37:21,511 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1413190566] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:21,512 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:21,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 21:37:21,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1495639803] [2023-11-23 21:37:21,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:21,513 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:21,513 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:21,513 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 21:37:21,513 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 21:37:21,514 INFO L87 Difference]: Start difference. First operand 43649 states and 60442 transitions. cyclomatic complexity: 16825 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:21,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:21,900 INFO L93 Difference]: Finished difference Result 79793 states and 109210 transitions. [2023-11-23 21:37:21,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79793 states and 109210 transitions. [2023-11-23 21:37:22,840 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79232 [2023-11-23 21:37:23,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79793 states to 79793 states and 109210 transitions. [2023-11-23 21:37:23,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79793 [2023-11-23 21:37:23,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79793 [2023-11-23 21:37:23,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79793 states and 109210 transitions. [2023-11-23 21:37:23,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:23,108 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79793 states and 109210 transitions. [2023-11-23 21:37:23,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79793 states and 109210 transitions. [2023-11-23 21:37:23,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79793 to 43841. [2023-11-23 21:37:23,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43841 states, 43841 states have (on average 1.3830432699984032) internal successors, (60634), 43840 states have internal predecessors, (60634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:23,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43841 states to 43841 states and 60634 transitions. [2023-11-23 21:37:23,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43841 states and 60634 transitions. [2023-11-23 21:37:23,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-23 21:37:23,622 INFO L428 stractBuchiCegarLoop]: Abstraction has 43841 states and 60634 transitions. [2023-11-23 21:37:23,622 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-23 21:37:23,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43841 states and 60634 transitions. [2023-11-23 21:37:23,736 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43504 [2023-11-23 21:37:23,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:23,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:23,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:23,738 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:23,739 INFO L748 eck$LassoCheckResult]: Stem: 1458286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1458287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1459052#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1459053#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1459126#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1458746#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1458747#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1458306#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1458307#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1458236#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1458237#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1458516#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1458483#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1458484#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1458820#L854 assume !(0 == ~M_E~0); 1458580#L854-2 assume !(0 == ~T1_E~0); 1458581#L859-1 assume !(0 == ~T2_E~0); 1458112#L864-1 assume !(0 == ~T3_E~0); 1458113#L869-1 assume !(0 == ~T4_E~0); 1458225#L874-1 assume !(0 == ~T5_E~0); 1459104#L879-1 assume !(0 == ~T6_E~0); 1458568#L884-1 assume !(0 == ~T7_E~0); 1457979#L889-1 assume !(0 == ~T8_E~0); 1457980#L894-1 assume !(0 == ~E_M~0); 1458320#L899-1 assume !(0 == ~E_1~0); 1458826#L904-1 assume !(0 == ~E_2~0); 1458506#L909-1 assume !(0 == ~E_3~0); 1458507#L914-1 assume !(0 == ~E_4~0); 1458731#L919-1 assume !(0 == ~E_5~0); 1458403#L924-1 assume !(0 == ~E_6~0); 1458210#L929-1 assume !(0 == ~E_7~0); 1458211#L934-1 assume !(0 == ~E_8~0); 1458482#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1457995#L418 assume !(1 == ~m_pc~0); 1457971#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1459036#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1459037#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1458955#L1061 assume !(0 != activate_threads_~tmp~1#1); 1458853#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1458854#L437 assume !(1 == ~t1_pc~0); 1459090#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1458965#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1458019#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1458020#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1458350#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1458948#L456 assume !(1 == ~t2_pc~0); 1458267#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1458727#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1458437#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1458438#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1458619#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1458107#L475 assume !(1 == ~t3_pc~0); 1458108#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1458173#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1457987#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1457988#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1458353#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1458354#L494 assume !(1 == ~t4_pc~0); 1458397#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1458398#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1458122#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1458123#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1458765#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1458166#L513 assume !(1 == ~t5_pc~0); 1458167#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1458402#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1458977#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1458119#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1458120#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1458074#L532 assume !(1 == ~t6_pc~0); 1458075#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1458226#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1458417#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1458418#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1458322#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1458323#L551 assume !(1 == ~t7_pc~0); 1458827#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1458769#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1458770#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1459150#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1459157#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1458528#L570 assume !(1 == ~t8_pc~0); 1458529#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1459058#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1458908#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1458645#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1458105#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1458106#L952 assume !(1 == ~M_E~0); 1458041#L952-2 assume !(1 == ~T1_E~0); 1458042#L957-1 assume !(1 == ~T2_E~0); 1458923#L962-1 assume !(1 == ~T3_E~0); 1458663#L967-1 assume !(1 == ~T4_E~0); 1458664#L972-1 assume !(1 == ~T5_E~0); 1458995#L977-1 assume !(1 == ~T6_E~0); 1458996#L982-1 assume !(1 == ~T7_E~0); 1458228#L987-1 assume !(1 == ~T8_E~0); 1458229#L992-1 assume !(1 == ~E_M~0); 1458238#L997-1 assume !(1 == ~E_1~0); 1458616#L1002-1 assume !(1 == ~E_2~0); 1458601#L1007-1 assume !(1 == ~E_3~0); 1457981#L1012-1 assume !(1 == ~E_4~0); 1457982#L1017-1 assume !(1 == ~E_5~0); 1458604#L1022-1 assume !(1 == ~E_6~0); 1458605#L1027-1 assume !(1 == ~E_7~0); 1458634#L1032-1 assume !(1 == ~E_8~0); 1458802#L1037-1 assume { :end_inline_reset_delta_events } true; 1458803#L1303-2 [2023-11-23 21:37:23,739 INFO L750 eck$LassoCheckResult]: Loop: 1458803#L1303-2 assume !false; 1498569#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1491135#L829-1 assume !false; 1498566#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1498332#L650 assume !(0 == ~m_st~0); 1498333#L654 assume !(0 == ~t1_st~0); 1498336#L658 assume !(0 == ~t2_st~0); 1498330#L662 assume !(0 == ~t3_st~0); 1498331#L666 assume !(0 == ~t4_st~0); 1498335#L670 assume !(0 == ~t5_st~0); 1498327#L674 assume !(0 == ~t6_st~0); 1498329#L678 assume !(0 == ~t7_st~0); 1498334#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1498315#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1482719#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1482720#L712 assume !(0 != eval_~tmp~0#1); 1501148#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1501147#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1501146#L854-3 assume !(0 == ~M_E~0); 1501145#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1501144#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1501143#L864-3 assume !(0 == ~T3_E~0); 1501142#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1501141#L874-3 assume !(0 == ~T5_E~0); 1501140#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1501139#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1501138#L889-3 assume !(0 == ~T8_E~0); 1501137#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1501136#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1501135#L904-3 assume !(0 == ~E_2~0); 1501134#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1501133#L914-3 assume !(0 == ~E_4~0); 1501132#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1501131#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1501130#L929-3 assume !(0 == ~E_7~0); 1501129#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1501128#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1501127#L418-30 assume !(1 == ~m_pc~0); 1501126#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1501124#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1501122#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1501120#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1501118#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1501117#L437-30 assume !(1 == ~t1_pc~0); 1501116#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1501115#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1501114#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1501113#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1501112#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1501111#L456-30 assume !(1 == ~t2_pc~0); 1501109#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1501108#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1501107#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1501106#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1501105#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1501104#L475-30 assume !(1 == ~t3_pc~0); 1501103#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1501102#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1501101#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1501100#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1501099#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1501098#L494-30 assume !(1 == ~t4_pc~0); 1501096#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1501095#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1501094#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1501093#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1500472#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1500473#L513-30 assume !(1 == ~t5_pc~0); 1501092#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1501091#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1501090#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1501089#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1501088#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1501087#L532-30 assume 1 == ~t6_pc~0; 1501086#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1501084#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1501083#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1501082#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1501081#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1501080#L551-30 assume !(1 == ~t7_pc~0); 1459024#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1458973#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1458859#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1457983#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 1457984#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1458355#L570-30 assume !(1 == ~t8_pc~0); 1501075#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1501074#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1501073#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1501072#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1501071#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1501070#L952-3 assume !(1 == ~M_E~0); 1501069#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1501068#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1501067#L962-3 assume !(1 == ~T3_E~0); 1501066#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1501065#L972-3 assume !(1 == ~T5_E~0); 1501064#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1501063#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1501062#L987-3 assume !(1 == ~T8_E~0); 1501061#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1501060#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1501059#L1002-3 assume !(1 == ~E_2~0); 1501058#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1501057#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1501056#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1501055#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1501054#L1027-3 assume !(1 == ~E_7~0); 1501053#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1501052#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1501051#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1501042#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1501041#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1501039#L1322 assume !(0 == start_simulation_~tmp~3#1); 1501038#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1498590#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1498585#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1498581#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1498579#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1498577#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1498575#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1498572#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1458803#L1303-2 [2023-11-23 21:37:23,740 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:23,740 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 4 times [2023-11-23 21:37:23,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:23,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958933799] [2023-11-23 21:37:23,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:23,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:23,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 21:37:23,756 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 21:37:23,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 21:37:23,799 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 21:37:23,802 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:23,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1606696795, now seen corresponding path program 1 times [2023-11-23 21:37:23,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:23,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3395398] [2023-11-23 21:37:23,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:23,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:23,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:23,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:23,851 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:23,851 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3395398] [2023-11-23 21:37:23,851 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [3395398] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:23,851 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:23,851 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 21:37:23,851 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574112735] [2023-11-23 21:37:23,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:23,852 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:23,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:23,853 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 21:37:23,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 21:37:23,853 INFO L87 Difference]: Start difference. First operand 43841 states and 60634 transitions. cyclomatic complexity: 16825 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:24,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:24,093 INFO L93 Difference]: Finished difference Result 82897 states and 113274 transitions. [2023-11-23 21:37:24,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82897 states and 113274 transitions. [2023-11-23 21:37:24,944 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 82336 [2023-11-23 21:37:25,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82897 states to 82897 states and 113274 transitions. [2023-11-23 21:37:25,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82897 [2023-11-23 21:37:25,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82897 [2023-11-23 21:37:25,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82897 states and 113274 transitions. [2023-11-23 21:37:25,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 21:37:25,172 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82897 states and 113274 transitions. [2023-11-23 21:37:25,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82897 states and 113274 transitions. [2023-11-23 21:37:25,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82897 to 79345. [2023-11-23 21:37:25,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79345 states, 79345 states have (on average 1.368731489066734) internal successors, (108602), 79344 states have internal predecessors, (108602), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:25,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79345 states to 79345 states and 108602 transitions. [2023-11-23 21:37:25,887 INFO L240 hiAutomatonCegarLoop]: Abstraction has 79345 states and 108602 transitions. [2023-11-23 21:37:25,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 21:37:25,887 INFO L428 stractBuchiCegarLoop]: Abstraction has 79345 states and 108602 transitions. [2023-11-23 21:37:25,888 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-23 21:37:25,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79345 states and 108602 transitions. [2023-11-23 21:37:26,554 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78784 [2023-11-23 21:37:26,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 21:37:26,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 21:37:26,556 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:26,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 21:37:26,556 INFO L748 eck$LassoCheckResult]: Stem: 1585029#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1585030#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1585797#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1585798#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1585882#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1585489#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1585490#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1585049#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1585050#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1584981#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1584982#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1585258#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1585225#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1585226#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1585551#L854 assume !(0 == ~M_E~0); 1585324#L854-2 assume !(0 == ~T1_E~0); 1585325#L859-1 assume !(0 == ~T2_E~0); 1584858#L864-1 assume !(0 == ~T3_E~0); 1584859#L869-1 assume !(0 == ~T4_E~0); 1584970#L874-1 assume !(0 == ~T5_E~0); 1585854#L879-1 assume !(0 == ~T6_E~0); 1585311#L884-1 assume !(0 == ~T7_E~0); 1584724#L889-1 assume !(0 == ~T8_E~0); 1584725#L894-1 assume !(0 == ~E_M~0); 1585064#L899-1 assume !(0 == ~E_1~0); 1585557#L904-1 assume !(0 == ~E_2~0); 1585250#L909-1 assume !(0 == ~E_3~0); 1585251#L914-1 assume !(0 == ~E_4~0); 1585478#L919-1 assume !(0 == ~E_5~0); 1585147#L924-1 assume !(0 == ~E_6~0); 1584956#L929-1 assume !(0 == ~E_7~0); 1584957#L934-1 assume !(0 == ~E_8~0); 1585222#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1584740#L418 assume !(1 == ~m_pc~0); 1584716#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1585774#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1585775#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1585686#L1061 assume !(0 != activate_threads_~tmp~1#1); 1585587#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1585588#L437 assume !(1 == ~t1_pc~0); 1585843#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1585695#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1584765#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1584766#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1585095#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1585675#L456 assume !(1 == ~t2_pc~0); 1585011#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1585473#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1585179#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1585180#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1585361#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1584853#L475 assume !(1 == ~t3_pc~0); 1584854#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1584919#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1584732#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1584733#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1585098#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1585099#L494 assume !(1 == ~t4_pc~0); 1585141#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1585142#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1584869#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1584870#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1585508#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1584912#L513 assume !(1 == ~t5_pc~0); 1584913#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1585146#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1585711#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1584865#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1584866#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1584819#L532 assume !(1 == ~t6_pc~0); 1584820#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1584971#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1585160#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1585161#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1585068#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1585069#L551 assume !(1 == ~t7_pc~0); 1585558#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1585511#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1585512#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1585908#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1585912#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1585270#L570 assume !(1 == ~t8_pc~0); 1585271#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1585805#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1585633#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1585388#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1584851#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1584852#L952 assume !(1 == ~M_E~0); 1584788#L952-2 assume !(1 == ~T1_E~0); 1584789#L957-1 assume !(1 == ~T2_E~0); 1585650#L962-1 assume !(1 == ~T3_E~0); 1585406#L967-1 assume !(1 == ~T4_E~0); 1585407#L972-1 assume !(1 == ~T5_E~0); 1585732#L977-1 assume !(1 == ~T6_E~0); 1585733#L982-1 assume !(1 == ~T7_E~0); 1584973#L987-1 assume !(1 == ~T8_E~0); 1584974#L992-1 assume !(1 == ~E_M~0); 1584983#L997-1 assume !(1 == ~E_1~0); 1585359#L1002-1 assume !(1 == ~E_2~0); 1585344#L1007-1 assume !(1 == ~E_3~0); 1584726#L1012-1 assume !(1 == ~E_4~0); 1584727#L1017-1 assume !(1 == ~E_5~0); 1585347#L1022-1 assume !(1 == ~E_6~0); 1585348#L1027-1 assume !(1 == ~E_7~0); 1585376#L1032-1 assume !(1 == ~E_8~0); 1585537#L1037-1 assume { :end_inline_reset_delta_events } true; 1585538#L1303-2 [2023-11-23 21:37:26,557 INFO L750 eck$LassoCheckResult]: Loop: 1585538#L1303-2 assume !false; 1631593#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1631588#L829-1 assume !false; 1631586#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1631583#L650 assume !(0 == ~m_st~0); 1631584#L654 assume !(0 == ~t1_st~0); 1651784#L658 assume !(0 == ~t2_st~0); 1651782#L662 assume !(0 == ~t3_st~0); 1651780#L666 assume !(0 == ~t4_st~0); 1651777#L670 assume !(0 == ~t5_st~0); 1651775#L674 assume !(0 == ~t6_st~0); 1651773#L678 assume !(0 == ~t7_st~0); 1651770#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1651768#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1651766#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1651764#L712 assume !(0 != eval_~tmp~0#1); 1651761#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1651759#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1651757#L854-3 assume !(0 == ~M_E~0); 1651755#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1651753#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1651752#L864-3 assume !(0 == ~T3_E~0); 1651749#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1651748#L874-3 assume !(0 == ~T5_E~0); 1651746#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1651744#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1651743#L889-3 assume !(0 == ~T8_E~0); 1651742#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1651741#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1651740#L904-3 assume !(0 == ~E_2~0); 1651739#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1651738#L914-3 assume !(0 == ~E_4~0); 1651736#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1651734#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1651732#L929-3 assume !(0 == ~E_7~0); 1651730#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1651728#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1651725#L418-30 assume 1 == ~m_pc~0; 1651722#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1651720#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1651718#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1651716#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1651714#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1651712#L437-30 assume !(1 == ~t1_pc~0); 1651710#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1651708#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1651706#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1651704#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1651702#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1651699#L456-30 assume !(1 == ~t2_pc~0); 1651696#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1651694#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1651692#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1651690#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1651689#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1651688#L475-30 assume !(1 == ~t3_pc~0); 1651687#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1651686#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1651685#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1651684#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1651682#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1651680#L494-30 assume !(1 == ~t4_pc~0); 1651677#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1651676#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1651674#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1651671#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1651669#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1651667#L513-30 assume !(1 == ~t5_pc~0); 1651665#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1651663#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1651660#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1651658#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1651656#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1651654#L532-30 assume !(1 == ~t6_pc~0); 1651651#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1651649#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1651647#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1651645#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1651643#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1631688#L551-30 assume !(1 == ~t7_pc~0); 1631687#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1631686#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1631685#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1631684#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 1631683#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1631681#L570-30 assume !(1 == ~t8_pc~0); 1631679#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1631677#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1631674#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1631672#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1631669#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1631666#L952-3 assume !(1 == ~M_E~0); 1631664#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1631661#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1631659#L962-3 assume !(1 == ~T3_E~0); 1631655#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1631653#L972-3 assume !(1 == ~T5_E~0); 1631651#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1631649#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1631645#L987-3 assume !(1 == ~T8_E~0); 1631643#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1631641#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1631638#L1002-3 assume !(1 == ~E_2~0); 1631636#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1631634#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1631632#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1631630#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1631628#L1027-3 assume !(1 == ~E_7~0); 1631625#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1631623#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1631620#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1631618#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1631616#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1631614#L1322 assume !(0 == start_simulation_~tmp~3#1); 1631612#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1631609#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1631607#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1631605#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1631603#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1631601#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1631598#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1631596#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1585538#L1303-2 [2023-11-23 21:37:26,557 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:26,557 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 5 times [2023-11-23 21:37:26,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:26,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110591406] [2023-11-23 21:37:26,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:26,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:26,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 21:37:26,576 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 21:37:26,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 21:37:26,623 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 21:37:26,624 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 21:37:26,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1054957529, now seen corresponding path program 1 times [2023-11-23 21:37:26,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 21:37:26,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998253178] [2023-11-23 21:37:26,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 21:37:26,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 21:37:26,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 21:37:26,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 21:37:26,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 21:37:26,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [998253178] [2023-11-23 21:37:26,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [998253178] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 21:37:26,729 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 21:37:26,729 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 21:37:26,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120007429] [2023-11-23 21:37:26,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 21:37:26,730 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 21:37:26,730 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 21:37:26,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 21:37:26,731 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 21:37:26,731 INFO L87 Difference]: Start difference. First operand 79345 states and 108602 transitions. cyclomatic complexity: 29289 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 21:37:27,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 21:37:27,517 INFO L93 Difference]: Finished difference Result 144497 states and 195625 transitions. [2023-11-23 21:37:27,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144497 states and 195625 transitions.