./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 30e01a73 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b --- Real Ultimate output --- This is Ultimate 0.2.3-dev-30e01a7 [2023-11-23 22:34:21,596 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-23 22:34:21,711 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-23 22:34:21,715 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-23 22:34:21,716 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-23 22:34:21,757 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-23 22:34:21,759 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-23 22:34:21,760 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-23 22:34:21,761 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-23 22:34:21,766 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-23 22:34:21,767 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-23 22:34:21,768 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-23 22:34:21,768 INFO L153 SettingsManager]: * Use SBE=true [2023-11-23 22:34:21,771 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-23 22:34:21,771 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-23 22:34:21,772 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-23 22:34:21,772 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-23 22:34:21,773 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-23 22:34:21,773 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-23 22:34:21,774 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-23 22:34:21,774 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-23 22:34:21,775 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-23 22:34:21,775 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-23 22:34:21,776 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-23 22:34:21,776 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-23 22:34:21,777 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-23 22:34:21,777 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-23 22:34:21,778 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-23 22:34:21,778 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-23 22:34:21,778 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-23 22:34:21,780 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-23 22:34:21,780 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-23 22:34:21,781 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-23 22:34:21,781 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-23 22:34:21,781 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-23 22:34:21,782 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-23 22:34:21,782 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-23 22:34:21,783 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-23 22:34:21,783 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b [2023-11-23 22:34:22,138 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-23 22:34:22,180 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-23 22:34:22,182 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-23 22:34:22,184 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-23 22:34:22,185 INFO L274 PluginConnector]: CDTParser initialized [2023-11-23 22:34:22,186 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2023-11-23 22:34:25,360 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-23 22:34:25,673 INFO L384 CDTParser]: Found 1 translation units. [2023-11-23 22:34:25,673 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2023-11-23 22:34:25,690 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/data/dcd699ded/1bd0864ecbd843e39816d5802755a63d/FLAG39e657759 [2023-11-23 22:34:25,707 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/data/dcd699ded/1bd0864ecbd843e39816d5802755a63d [2023-11-23 22:34:25,712 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-23 22:34:25,715 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-23 22:34:25,718 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-23 22:34:25,718 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-23 22:34:25,724 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-23 22:34:25,725 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:34:25" (1/1) ... [2023-11-23 22:34:25,726 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3b4c49f7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:25, skipping insertion in model container [2023-11-23 22:34:25,726 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:34:25" (1/1) ... [2023-11-23 22:34:25,800 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-23 22:34:26,082 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-23 22:34:26,097 INFO L202 MainTranslator]: Completed pre-run [2023-11-23 22:34:26,169 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-23 22:34:26,202 INFO L206 MainTranslator]: Completed translation [2023-11-23 22:34:26,203 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26 WrapperNode [2023-11-23 22:34:26,203 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-23 22:34:26,204 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-23 22:34:26,204 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-23 22:34:26,205 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-23 22:34:26,212 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,225 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,315 INFO L138 Inliner]: procedures = 42, calls = 54, calls flagged for inlining = 49, calls inlined = 137, statements flattened = 2020 [2023-11-23 22:34:26,316 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-23 22:34:26,317 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-23 22:34:26,317 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-23 22:34:26,317 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-23 22:34:26,337 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,338 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,354 INFO L184 PluginConnector]: Executing the observer HeapSplitter from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,390 INFO L189 HeapSplitter]: Split 2 memory accesses to 1 slices as follows [2] [2023-11-23 22:34:26,390 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,390 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,424 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,448 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,452 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,460 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,471 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-23 22:34:26,472 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-23 22:34:26,473 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-23 22:34:26,473 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-23 22:34:26,474 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (1/1) ... [2023-11-23 22:34:26,479 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-23 22:34:26,532 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/z3 [2023-11-23 22:34:26,551 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-23 22:34:26,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a0f74a4-7902-4252-9ea2-edc00bfbdf3d/bin/uautomizer-verify-zZY32mL2XJ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-23 22:34:26,654 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-23 22:34:26,654 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-23 22:34:26,654 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-23 22:34:26,655 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-23 22:34:26,794 INFO L241 CfgBuilder]: Building ICFG [2023-11-23 22:34:26,796 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-23 22:34:28,101 INFO L282 CfgBuilder]: Performing block encoding [2023-11-23 22:34:28,138 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-23 22:34:28,138 INFO L309 CfgBuilder]: Removed 10 assume(true) statements. [2023-11-23 22:34:28,140 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:34:28 BoogieIcfgContainer [2023-11-23 22:34:28,140 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-23 22:34:28,142 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-23 22:34:28,142 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-23 22:34:28,146 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-23 22:34:28,146 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-23 22:34:28,146 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 10:34:25" (1/3) ... [2023-11-23 22:34:28,166 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1152359c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 10:34:28, skipping insertion in model container [2023-11-23 22:34:28,166 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-23 22:34:28,167 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:34:26" (2/3) ... [2023-11-23 22:34:28,167 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1152359c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 10:34:28, skipping insertion in model container [2023-11-23 22:34:28,167 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-23 22:34:28,167 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:34:28" (3/3) ... [2023-11-23 22:34:28,168 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-2.c [2023-11-23 22:34:28,242 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-23 22:34:28,242 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-23 22:34:28,242 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-23 22:34:28,242 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-23 22:34:28,242 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-23 22:34:28,243 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-23 22:34:28,243 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-23 22:34:28,243 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-23 22:34:28,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:28,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2023-11-23 22:34:28,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:28,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:28,340 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:28,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:28,341 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-23 22:34:28,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:28,357 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2023-11-23 22:34:28,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:28,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:28,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:28,363 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:28,373 INFO L748 eck$LassoCheckResult]: Stem: 127#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 784#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 622#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 782#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 807#L548true assume !(1 == ~m_i~0);~m_st~0 := 2; 213#L548-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 401#L553-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 295#L558-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 760#L563-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 153#L568-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 41#L573-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 791#L578-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 130#L583-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 505#L781true assume !(0 == ~M_E~0); 822#L781-2true assume !(0 == ~T1_E~0); 846#L786-1true assume !(0 == ~T2_E~0); 21#L791-1true assume !(0 == ~T3_E~0); 385#L796-1true assume !(0 == ~T4_E~0); 355#L801-1true assume !(0 == ~T5_E~0); 387#L806-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 766#L811-1true assume !(0 == ~T7_E~0); 134#L816-1true assume !(0 == ~E_M~0); 626#L821-1true assume !(0 == ~E_1~0); 37#L826-1true assume !(0 == ~E_2~0); 353#L831-1true assume !(0 == ~E_3~0); 210#L836-1true assume !(0 == ~E_4~0); 507#L841-1true assume !(0 == ~E_5~0); 107#L846-1true assume 0 == ~E_6~0;~E_6~0 := 1; 799#L851-1true assume !(0 == ~E_7~0); 119#L856-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 651#L388true assume !(1 == ~m_pc~0); 116#L388-2true is_master_triggered_~__retres1~0#1 := 0; 478#L399true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 545#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44#L967true assume !(0 != activate_threads_~tmp~1#1); 767#L967-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11#L407true assume 1 == ~t1_pc~0; 414#L408true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13#L418true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 618#L975true assume !(0 != activate_threads_~tmp___0~0#1); 644#L975-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 184#L426true assume !(1 == ~t2_pc~0); 662#L426-2true is_transmit2_triggered_~__retres1~2#1 := 0; 753#L437true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 745#L983true assume !(0 != activate_threads_~tmp___1~0#1); 847#L983-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 241#L445true assume 1 == ~t3_pc~0; 838#L446true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 517#L456true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 441#L991true assume !(0 != activate_threads_~tmp___2~0#1); 512#L991-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 415#L464true assume !(1 == ~t4_pc~0); 121#L464-2true is_transmit4_triggered_~__retres1~4#1 := 0; 52#L475true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 845#L999true assume !(0 != activate_threads_~tmp___3~0#1); 227#L999-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410#L483true assume 1 == ~t5_pc~0; 737#L484true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 593#L494true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 548#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 701#L1007true assume !(0 != activate_threads_~tmp___4~0#1); 175#L1007-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 461#L502true assume 1 == ~t6_pc~0; 383#L503true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73#L513true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 322#L1015true assume !(0 != activate_threads_~tmp___5~0#1); 560#L1015-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 711#L521true assume !(1 == ~t7_pc~0); 666#L521-2true is_transmit7_triggered_~__retres1~7#1 := 0; 42#L532true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 800#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 607#L1023true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 569#L1023-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 469#L869true assume !(1 == ~M_E~0); 223#L869-2true assume !(1 == ~T1_E~0); 738#L874-1true assume !(1 == ~T2_E~0); 686#L879-1true assume !(1 == ~T3_E~0); 272#L884-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 5#L889-1true assume !(1 == ~T5_E~0); 139#L894-1true assume !(1 == ~T6_E~0); 836#L899-1true assume !(1 == ~T7_E~0); 431#L904-1true assume !(1 == ~E_M~0); 239#L909-1true assume !(1 == ~E_1~0); 371#L914-1true assume !(1 == ~E_2~0); 394#L919-1true assume !(1 == ~E_3~0); 183#L924-1true assume 1 == ~E_4~0;~E_4~0 := 2; 90#L929-1true assume !(1 == ~E_5~0); 705#L934-1true assume !(1 == ~E_6~0); 225#L939-1true assume !(1 == ~E_7~0); 559#L944-1true assume { :end_inline_reset_delta_events } true; 555#L1190-2true [2023-11-23 22:34:28,376 INFO L750 eck$LassoCheckResult]: Loop: 555#L1190-2true assume !false; 135#L1191true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 136#L756-1true assume false; 491#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 302#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 398#L781-3true assume 0 == ~M_E~0;~M_E~0 := 1; 59#L781-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 253#L786-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 308#L791-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 34#L796-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 632#L801-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 176#L806-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 303#L811-3true assume !(0 == ~T7_E~0); 497#L816-3true assume 0 == ~E_M~0;~E_M~0 := 1; 663#L821-3true assume 0 == ~E_1~0;~E_1~0 := 1; 777#L826-3true assume 0 == ~E_2~0;~E_2~0 := 1; 437#L831-3true assume 0 == ~E_3~0;~E_3~0 := 1; 679#L836-3true assume 0 == ~E_4~0;~E_4~0 := 1; 112#L841-3true assume 0 == ~E_5~0;~E_5~0 := 1; 606#L846-3true assume 0 == ~E_6~0;~E_6~0 := 1; 321#L851-3true assume !(0 == ~E_7~0); 55#L856-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 759#L388-27true assume 1 == ~m_pc~0; 608#L389-9true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 773#L399-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 458#is_master_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 709#L967-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155#L967-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 459#L407-27true assume 1 == ~t1_pc~0; 442#L408-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 540#L418-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 482#L975-27true assume !(0 != activate_threads_~tmp___0~0#1); 337#L975-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108#L426-27true assume !(1 == ~t2_pc~0); 851#L426-29true is_transmit2_triggered_~__retres1~2#1 := 0; 113#L437-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 438#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 707#L983-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 602#L983-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 298#L445-27true assume 1 == ~t3_pc~0; 278#L446-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32#L456-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 854#L991-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 376#L991-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171#L464-27true assume 1 == ~t4_pc~0; 483#L465-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65#L475-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304#L999-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 104#L999-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 796#L483-27true assume !(1 == ~t5_pc~0); 587#L483-29true is_transmit5_triggered_~__retres1~5#1 := 0; 56#L494-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 563#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552#L1007-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 824#L1007-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 717#L502-27true assume !(1 == ~t6_pc~0); 317#L502-29true is_transmit6_triggered_~__retres1~6#1 := 0; 706#L513-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 690#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 464#L1015-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 750#L1015-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6#L521-27true assume 1 == ~t7_pc~0; 193#L522-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 785#L532-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 162#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30#L1023-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 328#L1023-29true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 678#L869-3true assume 1 == ~M_E~0;~M_E~0 := 2; 462#L869-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 252#L874-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 291#L879-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 320#L884-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 284#L889-3true assume !(1 == ~T5_E~0); 85#L894-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 425#L899-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 97#L904-3true assume 1 == ~E_M~0;~E_M~0 := 2; 269#L909-3true assume 1 == ~E_1~0;~E_1~0 := 2; 74#L914-3true assume 1 == ~E_2~0;~E_2~0 := 2; 94#L919-3true assume 1 == ~E_3~0;~E_3~0 := 2; 619#L924-3true assume 1 == ~E_4~0;~E_4~0 := 2; 448#L929-3true assume !(1 == ~E_5~0); 374#L934-3true assume 1 == ~E_6~0;~E_6~0 := 2; 565#L939-3true assume 1 == ~E_7~0;~E_7~0 := 2; 100#L944-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 601#L596-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 674#L638-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 169#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 790#L1209true assume !(0 == start_simulation_~tmp~3#1); 314#L1209-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 301#L596-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 544#L638-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 609#L1164true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 25#L1171true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 315#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 128#L1222true assume !(0 != start_simulation_~tmp___0~1#1); 555#L1190-2true [2023-11-23 22:34:28,383 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:28,384 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2023-11-23 22:34:28,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:28,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751052699] [2023-11-23 22:34:28,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:28,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:28,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:28,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:28,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:28,750 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [751052699] [2023-11-23 22:34:28,751 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [751052699] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:28,751 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:28,751 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:28,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644180245] [2023-11-23 22:34:28,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:28,758 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:28,758 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:28,759 INFO L85 PathProgramCache]: Analyzing trace with hash -41697262, now seen corresponding path program 1 times [2023-11-23 22:34:28,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:28,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1252675219] [2023-11-23 22:34:28,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:28,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:28,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:28,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:28,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:28,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1252675219] [2023-11-23 22:34:28,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1252675219] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:28,820 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:28,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:34:28,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2125342427] [2023-11-23 22:34:28,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:28,821 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:28,822 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:28,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:28,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:28,860 INFO L87 Difference]: Start difference. First operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:28,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:28,953 INFO L93 Difference]: Finished difference Result 849 states and 1263 transitions. [2023-11-23 22:34:28,955 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 849 states and 1263 transitions. [2023-11-23 22:34:28,968 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:28,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 849 states to 843 states and 1257 transitions. [2023-11-23 22:34:28,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-23 22:34:28,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-23 22:34:28,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1257 transitions. [2023-11-23 22:34:28,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:28,999 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1257 transitions. [2023-11-23 22:34:29,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1257 transitions. [2023-11-23 22:34:29,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-23 22:34:29,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.491103202846975) internal successors, (1257), 842 states have internal predecessors, (1257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:29,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1257 transitions. [2023-11-23 22:34:29,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1257 transitions. [2023-11-23 22:34:29,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:29,103 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1257 transitions. [2023-11-23 22:34:29,103 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-23 22:34:29,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1257 transitions. [2023-11-23 22:34:29,112 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:29,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:29,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:29,121 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:29,121 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:29,122 INFO L748 eck$LassoCheckResult]: Stem: 1961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2509#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2510#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2549#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2104#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2105#L553-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2227#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2228#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2005#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1796#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1797#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1966#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1967#L781 assume !(0 == ~M_E~0); 2444#L781-2 assume !(0 == ~T1_E~0); 2552#L786-1 assume !(0 == ~T2_E~0); 1756#L791-1 assume !(0 == ~T3_E~0); 1757#L796-1 assume !(0 == ~T4_E~0); 2296#L801-1 assume !(0 == ~T5_E~0); 2297#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2327#L811-1 assume !(0 == ~T7_E~0); 1973#L816-1 assume !(0 == ~E_M~0); 1974#L821-1 assume !(0 == ~E_1~0); 1787#L826-1 assume !(0 == ~E_2~0); 1788#L831-1 assume !(0 == ~E_3~0); 2099#L836-1 assume !(0 == ~E_4~0); 2100#L841-1 assume !(0 == ~E_5~0); 1924#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1925#L851-1 assume !(0 == ~E_7~0); 1948#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1949#L388 assume !(1 == ~m_pc~0); 1942#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1943#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2422#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1802#L967 assume !(0 != activate_threads_~tmp~1#1); 1803#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1732#L407 assume 1 == ~t1_pc~0; 1733#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1737#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1773#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2507#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2059#L426 assume !(1 == ~t2_pc~0); 2060#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2524#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2081#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2082#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2545#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2145#L445 assume 1 == ~t3_pc~0; 2146#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2450#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1730#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1731#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2386#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2354#L464 assume !(1 == ~t4_pc~0); 1952#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1822#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1823#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1834#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2124#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2125#L483 assume 1 == ~t5_pc~0; 2350#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2490#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2463#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2464#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2042#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2043#L502 assume 1 == ~t6_pc~0; 2324#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1862#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1863#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2067#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2264#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2473#L521 assume !(1 == ~t7_pc~0); 2504#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1798#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1799#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2498#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2477#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2413#L869 assume !(1 == ~M_E~0); 2118#L869-2 assume !(1 == ~T1_E~0); 2119#L874-1 assume !(1 == ~T2_E~0); 2532#L879-1 assume !(1 == ~T3_E~0); 2193#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1718#L889-1 assume !(1 == ~T5_E~0); 1719#L894-1 assume !(1 == ~T6_E~0); 1981#L899-1 assume !(1 == ~T7_E~0); 2375#L904-1 assume !(1 == ~E_M~0); 2142#L909-1 assume !(1 == ~E_1~0); 2143#L914-1 assume !(1 == ~E_2~0); 2312#L919-1 assume !(1 == ~E_3~0); 2058#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1895#L929-1 assume !(1 == ~E_5~0); 1896#L934-1 assume !(1 == ~E_6~0); 2120#L939-1 assume !(1 == ~E_7~0); 2121#L944-1 assume { :end_inline_reset_delta_events } true; 1964#L1190-2 [2023-11-23 22:34:29,123 INFO L750 eck$LassoCheckResult]: Loop: 1964#L1190-2 assume !false; 1975#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1976#L756-1 assume !false; 1977#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2550#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1815#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2106#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2107#L653 assume !(0 != eval_~tmp~0#1); 2158#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2237#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2238#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1835#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1836#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2164#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1781#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1782#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2044#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2045#L811-3 assume !(0 == ~T7_E~0); 2239#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2436#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2525#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2379#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2380#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1935#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1936#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2263#L851-3 assume !(0 == ~E_7~0); 1829#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1830#L388-27 assume 1 == ~m_pc~0; 2499#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2500#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2403#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2404#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2008#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2009#L407-27 assume 1 == ~t1_pc~0; 2387#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2388#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2306#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2307#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 2280#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1926#L426-27 assume 1 == ~t2_pc~0; 1927#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1940#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1941#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2381#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2496#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2231#L445-27 assume 1 == ~t3_pc~0; 2205#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1778#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1779#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2232#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2317#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2034#L464-27 assume !(1 == ~t4_pc~0); 1776#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1777#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1848#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2161#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1919#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1920#L483-27 assume 1 == ~t5_pc~0; 2455#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1831#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1832#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2468#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2469#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2536#L502-27 assume !(1 == ~t6_pc~0); 2257#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2258#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2533#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2409#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2410#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1720#L521-27 assume 1 == ~t7_pc~0; 1721#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2072#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2020#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1774#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1775#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2270#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2406#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2162#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2163#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2223#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2216#L889-3 assume !(1 == ~T5_E~0); 1885#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1886#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1906#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1907#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1864#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1865#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1901#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2393#L929-3 assume !(1 == ~E_5~0); 2314#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2315#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1911#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1912#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1740#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2031#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2032#L1209 assume !(0 == start_simulation_~tmp~3#1); 2253#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2236#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1879#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1770#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1765#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1766#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1963#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1964#L1190-2 [2023-11-23 22:34:29,123 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:29,124 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2023-11-23 22:34:29,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:29,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969417133] [2023-11-23 22:34:29,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:29,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:29,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:29,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:29,278 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:29,278 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969417133] [2023-11-23 22:34:29,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969417133] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:29,279 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:29,279 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:29,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583454491] [2023-11-23 22:34:29,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:29,281 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:29,283 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:29,285 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 1 times [2023-11-23 22:34:29,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:29,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815254648] [2023-11-23 22:34:29,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:29,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:29,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:29,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:29,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:29,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815254648] [2023-11-23 22:34:29,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815254648] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:29,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:29,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:29,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249645881] [2023-11-23 22:34:29,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:29,398 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:29,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:29,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:29,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:29,399 INFO L87 Difference]: Start difference. First operand 843 states and 1257 transitions. cyclomatic complexity: 415 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:29,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:29,424 INFO L93 Difference]: Finished difference Result 843 states and 1256 transitions. [2023-11-23 22:34:29,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1256 transitions. [2023-11-23 22:34:29,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:29,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1256 transitions. [2023-11-23 22:34:29,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-23 22:34:29,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-23 22:34:29,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1256 transitions. [2023-11-23 22:34:29,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:29,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1256 transitions. [2023-11-23 22:34:29,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1256 transitions. [2023-11-23 22:34:29,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-23 22:34:29,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4899169632265719) internal successors, (1256), 842 states have internal predecessors, (1256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:29,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1256 transitions. [2023-11-23 22:34:29,513 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1256 transitions. [2023-11-23 22:34:29,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:29,515 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1256 transitions. [2023-11-23 22:34:29,515 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-23 22:34:29,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1256 transitions. [2023-11-23 22:34:29,527 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:29,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:29,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:29,531 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:29,531 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:29,533 INFO L748 eck$LassoCheckResult]: Stem: 3654#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4202#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4203#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4242#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3797#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3798#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3920#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3921#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3698#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3489#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3490#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3659#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3660#L781 assume !(0 == ~M_E~0); 4137#L781-2 assume !(0 == ~T1_E~0); 4245#L786-1 assume !(0 == ~T2_E~0); 3449#L791-1 assume !(0 == ~T3_E~0); 3450#L796-1 assume !(0 == ~T4_E~0); 3989#L801-1 assume !(0 == ~T5_E~0); 3990#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4020#L811-1 assume !(0 == ~T7_E~0); 3666#L816-1 assume !(0 == ~E_M~0); 3667#L821-1 assume !(0 == ~E_1~0); 3480#L826-1 assume !(0 == ~E_2~0); 3481#L831-1 assume !(0 == ~E_3~0); 3792#L836-1 assume !(0 == ~E_4~0); 3793#L841-1 assume !(0 == ~E_5~0); 3617#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3618#L851-1 assume !(0 == ~E_7~0); 3641#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3642#L388 assume !(1 == ~m_pc~0); 3635#L388-2 is_master_triggered_~__retres1~0#1 := 0; 3636#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4115#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3495#L967 assume !(0 != activate_threads_~tmp~1#1); 3496#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3425#L407 assume 1 == ~t1_pc~0; 3426#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3430#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3431#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3466#L975 assume !(0 != activate_threads_~tmp___0~0#1); 4200#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3752#L426 assume !(1 == ~t2_pc~0); 3753#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4217#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3774#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3775#L983 assume !(0 != activate_threads_~tmp___1~0#1); 4238#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3838#L445 assume 1 == ~t3_pc~0; 3839#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4143#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3424#L991 assume !(0 != activate_threads_~tmp___2~0#1); 4079#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4047#L464 assume !(1 == ~t4_pc~0); 3645#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3515#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3516#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3527#L999 assume !(0 != activate_threads_~tmp___3~0#1); 3817#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3818#L483 assume 1 == ~t5_pc~0; 4043#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4183#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4156#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4157#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 3735#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3736#L502 assume 1 == ~t6_pc~0; 4017#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3555#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3556#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3760#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 3957#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4166#L521 assume !(1 == ~t7_pc~0); 4197#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3491#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3492#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4191#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4170#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4106#L869 assume !(1 == ~M_E~0); 3811#L869-2 assume !(1 == ~T1_E~0); 3812#L874-1 assume !(1 == ~T2_E~0); 4225#L879-1 assume !(1 == ~T3_E~0); 3886#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3411#L889-1 assume !(1 == ~T5_E~0); 3412#L894-1 assume !(1 == ~T6_E~0); 3674#L899-1 assume !(1 == ~T7_E~0); 4068#L904-1 assume !(1 == ~E_M~0); 3835#L909-1 assume !(1 == ~E_1~0); 3836#L914-1 assume !(1 == ~E_2~0); 4005#L919-1 assume !(1 == ~E_3~0); 3751#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3588#L929-1 assume !(1 == ~E_5~0); 3589#L934-1 assume !(1 == ~E_6~0); 3813#L939-1 assume !(1 == ~E_7~0); 3814#L944-1 assume { :end_inline_reset_delta_events } true; 3657#L1190-2 [2023-11-23 22:34:29,535 INFO L750 eck$LassoCheckResult]: Loop: 3657#L1190-2 assume !false; 3668#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3669#L756-1 assume !false; 3670#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4243#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3508#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3799#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3800#L653 assume !(0 != eval_~tmp~0#1); 3851#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3930#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3931#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3528#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3529#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3857#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3474#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3475#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3737#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3738#L811-3 assume !(0 == ~T7_E~0); 3932#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4129#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4218#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4072#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4073#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3628#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3629#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3956#L851-3 assume !(0 == ~E_7~0); 3522#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3523#L388-27 assume 1 == ~m_pc~0; 4192#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4193#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4096#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4097#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3701#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3702#L407-27 assume 1 == ~t1_pc~0; 4080#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4081#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3999#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4000#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 3973#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3619#L426-27 assume 1 == ~t2_pc~0; 3620#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3633#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3634#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4074#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4189#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3924#L445-27 assume 1 == ~t3_pc~0; 3898#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3471#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3472#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3925#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4010#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3727#L464-27 assume 1 == ~t4_pc~0; 3728#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3470#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3541#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3854#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3612#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3613#L483-27 assume 1 == ~t5_pc~0; 4148#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3524#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3525#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4161#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4162#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4229#L502-27 assume 1 == ~t6_pc~0; 4230#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3951#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4226#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4102#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4103#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3413#L521-27 assume 1 == ~t7_pc~0; 3414#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3765#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3713#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3467#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3468#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3963#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4099#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3855#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3856#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3916#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3909#L889-3 assume !(1 == ~T5_E~0); 3578#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3579#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3599#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3600#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3557#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3558#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3594#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4086#L929-3 assume !(1 == ~E_5~0); 4007#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4008#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3604#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3605#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3433#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3724#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3725#L1209 assume !(0 == start_simulation_~tmp~3#1); 3946#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3929#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3572#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3462#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3463#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3458#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3459#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3656#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 3657#L1190-2 [2023-11-23 22:34:29,538 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:29,539 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2023-11-23 22:34:29,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:29,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038981702] [2023-11-23 22:34:29,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:29,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:29,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:29,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:29,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:29,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2038981702] [2023-11-23 22:34:29,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2038981702] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:29,640 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:29,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:29,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [706631290] [2023-11-23 22:34:29,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:29,641 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:29,641 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:29,642 INFO L85 PathProgramCache]: Analyzing trace with hash -2135531812, now seen corresponding path program 1 times [2023-11-23 22:34:29,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:29,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246820088] [2023-11-23 22:34:29,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:29,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:29,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:29,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:29,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:29,756 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246820088] [2023-11-23 22:34:29,757 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246820088] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:29,757 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:29,757 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:29,757 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139226558] [2023-11-23 22:34:29,759 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:29,760 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:29,760 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:29,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:29,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:29,761 INFO L87 Difference]: Start difference. First operand 843 states and 1256 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:29,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:29,787 INFO L93 Difference]: Finished difference Result 843 states and 1255 transitions. [2023-11-23 22:34:29,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1255 transitions. [2023-11-23 22:34:29,795 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:29,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1255 transitions. [2023-11-23 22:34:29,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-23 22:34:29,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-23 22:34:29,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1255 transitions. [2023-11-23 22:34:29,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:29,807 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1255 transitions. [2023-11-23 22:34:29,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1255 transitions. [2023-11-23 22:34:29,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-23 22:34:29,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4887307236061684) internal successors, (1255), 842 states have internal predecessors, (1255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:29,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1255 transitions. [2023-11-23 22:34:29,827 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1255 transitions. [2023-11-23 22:34:29,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:29,830 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1255 transitions. [2023-11-23 22:34:29,830 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-23 22:34:29,830 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1255 transitions. [2023-11-23 22:34:29,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:29,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:29,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:29,845 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:29,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:29,846 INFO L748 eck$LassoCheckResult]: Stem: 5347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5895#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5896#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5935#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5490#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5491#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5613#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5614#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5391#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5182#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5183#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5352#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5353#L781 assume !(0 == ~M_E~0); 5830#L781-2 assume !(0 == ~T1_E~0); 5938#L786-1 assume !(0 == ~T2_E~0); 5142#L791-1 assume !(0 == ~T3_E~0); 5143#L796-1 assume !(0 == ~T4_E~0); 5682#L801-1 assume !(0 == ~T5_E~0); 5683#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5713#L811-1 assume !(0 == ~T7_E~0); 5359#L816-1 assume !(0 == ~E_M~0); 5360#L821-1 assume !(0 == ~E_1~0); 5173#L826-1 assume !(0 == ~E_2~0); 5174#L831-1 assume !(0 == ~E_3~0); 5485#L836-1 assume !(0 == ~E_4~0); 5486#L841-1 assume !(0 == ~E_5~0); 5310#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5311#L851-1 assume !(0 == ~E_7~0); 5334#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5335#L388 assume !(1 == ~m_pc~0); 5328#L388-2 is_master_triggered_~__retres1~0#1 := 0; 5329#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5808#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5188#L967 assume !(0 != activate_threads_~tmp~1#1); 5189#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5118#L407 assume 1 == ~t1_pc~0; 5119#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5123#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5159#L975 assume !(0 != activate_threads_~tmp___0~0#1); 5893#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5445#L426 assume !(1 == ~t2_pc~0); 5446#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5910#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5467#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5468#L983 assume !(0 != activate_threads_~tmp___1~0#1); 5931#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5531#L445 assume 1 == ~t3_pc~0; 5532#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5836#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5117#L991 assume !(0 != activate_threads_~tmp___2~0#1); 5772#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5740#L464 assume !(1 == ~t4_pc~0); 5338#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5208#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5209#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5220#L999 assume !(0 != activate_threads_~tmp___3~0#1); 5510#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5511#L483 assume 1 == ~t5_pc~0; 5736#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5876#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5849#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5850#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 5428#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5429#L502 assume 1 == ~t6_pc~0; 5710#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5248#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5453#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 5650#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5859#L521 assume !(1 == ~t7_pc~0); 5890#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5184#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5185#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5884#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5863#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5799#L869 assume !(1 == ~M_E~0); 5504#L869-2 assume !(1 == ~T1_E~0); 5505#L874-1 assume !(1 == ~T2_E~0); 5918#L879-1 assume !(1 == ~T3_E~0); 5579#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5104#L889-1 assume !(1 == ~T5_E~0); 5105#L894-1 assume !(1 == ~T6_E~0); 5367#L899-1 assume !(1 == ~T7_E~0); 5761#L904-1 assume !(1 == ~E_M~0); 5528#L909-1 assume !(1 == ~E_1~0); 5529#L914-1 assume !(1 == ~E_2~0); 5698#L919-1 assume !(1 == ~E_3~0); 5444#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5281#L929-1 assume !(1 == ~E_5~0); 5282#L934-1 assume !(1 == ~E_6~0); 5506#L939-1 assume !(1 == ~E_7~0); 5507#L944-1 assume { :end_inline_reset_delta_events } true; 5350#L1190-2 [2023-11-23 22:34:29,846 INFO L750 eck$LassoCheckResult]: Loop: 5350#L1190-2 assume !false; 5361#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5362#L756-1 assume !false; 5363#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5936#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5201#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5492#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5493#L653 assume !(0 != eval_~tmp~0#1); 5544#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5624#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5221#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5222#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5550#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5167#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5168#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5430#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5431#L811-3 assume !(0 == ~T7_E~0); 5625#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5822#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5911#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5765#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5766#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5321#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5322#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5649#L851-3 assume !(0 == ~E_7~0); 5215#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5216#L388-27 assume 1 == ~m_pc~0; 5885#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5886#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5789#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5790#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5394#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5395#L407-27 assume 1 == ~t1_pc~0; 5773#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5774#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5692#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5693#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 5666#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5312#L426-27 assume 1 == ~t2_pc~0; 5313#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5326#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5327#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5767#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5882#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5617#L445-27 assume 1 == ~t3_pc~0; 5591#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5164#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5165#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5618#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5703#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5420#L464-27 assume !(1 == ~t4_pc~0); 5162#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5163#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5234#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5547#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5305#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5306#L483-27 assume 1 == ~t5_pc~0; 5841#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5217#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5218#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5854#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5855#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5922#L502-27 assume 1 == ~t6_pc~0; 5923#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5644#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5919#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5795#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5796#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5106#L521-27 assume 1 == ~t7_pc~0; 5107#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5458#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5406#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5160#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5161#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5656#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5792#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5548#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5549#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5609#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5602#L889-3 assume !(1 == ~T5_E~0); 5271#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5272#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5292#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5293#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5250#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5251#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5287#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5779#L929-3 assume !(1 == ~E_5~0); 5700#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5701#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5297#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5298#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5126#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5417#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5418#L1209 assume !(0 == start_simulation_~tmp~3#1); 5639#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5622#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5265#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5156#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5151#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5152#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 5349#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 5350#L1190-2 [2023-11-23 22:34:29,847 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:29,847 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2023-11-23 22:34:29,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:29,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485991987] [2023-11-23 22:34:29,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:29,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:29,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:29,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:29,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:29,940 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485991987] [2023-11-23 22:34:29,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485991987] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:29,941 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:29,941 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:29,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794199334] [2023-11-23 22:34:29,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:29,942 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:29,942 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:29,942 INFO L85 PathProgramCache]: Analyzing trace with hash 1885656989, now seen corresponding path program 1 times [2023-11-23 22:34:29,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:29,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175525235] [2023-11-23 22:34:29,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:29,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:29,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:30,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:30,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:30,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175525235] [2023-11-23 22:34:30,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [175525235] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:30,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:30,033 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:30,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275390760] [2023-11-23 22:34:30,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:30,034 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:30,034 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:30,034 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:30,034 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:30,035 INFO L87 Difference]: Start difference. First operand 843 states and 1255 transitions. cyclomatic complexity: 413 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:30,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:30,058 INFO L93 Difference]: Finished difference Result 843 states and 1254 transitions. [2023-11-23 22:34:30,058 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1254 transitions. [2023-11-23 22:34:30,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:30,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1254 transitions. [2023-11-23 22:34:30,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-23 22:34:30,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-23 22:34:30,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1254 transitions. [2023-11-23 22:34:30,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:30,077 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1254 transitions. [2023-11-23 22:34:30,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1254 transitions. [2023-11-23 22:34:30,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-23 22:34:30,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4875444839857652) internal successors, (1254), 842 states have internal predecessors, (1254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:30,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1254 transitions. [2023-11-23 22:34:30,102 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1254 transitions. [2023-11-23 22:34:30,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:30,104 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1254 transitions. [2023-11-23 22:34:30,104 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-23 22:34:30,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1254 transitions. [2023-11-23 22:34:30,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:30,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:30,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:30,114 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:30,114 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:30,115 INFO L748 eck$LassoCheckResult]: Stem: 7040#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7588#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7589#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7628#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 7183#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7184#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7306#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7307#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7084#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6875#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6876#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7048#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7049#L781 assume !(0 == ~M_E~0); 7523#L781-2 assume !(0 == ~T1_E~0); 7631#L786-1 assume !(0 == ~T2_E~0); 6838#L791-1 assume !(0 == ~T3_E~0); 6839#L796-1 assume !(0 == ~T4_E~0); 7375#L801-1 assume !(0 == ~T5_E~0); 7376#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7406#L811-1 assume !(0 == ~T7_E~0); 7052#L816-1 assume !(0 == ~E_M~0); 7053#L821-1 assume !(0 == ~E_1~0); 6866#L826-1 assume !(0 == ~E_2~0); 6867#L831-1 assume !(0 == ~E_3~0); 7178#L836-1 assume !(0 == ~E_4~0); 7179#L841-1 assume !(0 == ~E_5~0); 7003#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7004#L851-1 assume !(0 == ~E_7~0); 7027#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7028#L388 assume !(1 == ~m_pc~0); 7021#L388-2 is_master_triggered_~__retres1~0#1 := 0; 7022#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7501#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6881#L967 assume !(0 != activate_threads_~tmp~1#1); 6882#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6811#L407 assume 1 == ~t1_pc~0; 6812#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6819#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6820#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6854#L975 assume !(0 != activate_threads_~tmp___0~0#1); 7586#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7138#L426 assume !(1 == ~t2_pc~0); 7139#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7603#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7160#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7161#L983 assume !(0 != activate_threads_~tmp___1~0#1); 7624#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7224#L445 assume 1 == ~t3_pc~0; 7225#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7529#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6809#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6810#L991 assume !(0 != activate_threads_~tmp___2~0#1); 7465#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7433#L464 assume !(1 == ~t4_pc~0); 7031#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6901#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6902#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6913#L999 assume !(0 != activate_threads_~tmp___3~0#1); 7203#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7204#L483 assume 1 == ~t5_pc~0; 7429#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7569#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7543#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 7123#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7124#L502 assume 1 == ~t6_pc~0; 7404#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6941#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6942#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7148#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 7343#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7552#L521 assume !(1 == ~t7_pc~0); 7583#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6877#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6878#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7577#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7556#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7494#L869 assume !(1 == ~M_E~0); 7197#L869-2 assume !(1 == ~T1_E~0); 7198#L874-1 assume !(1 == ~T2_E~0); 7611#L879-1 assume !(1 == ~T3_E~0); 7272#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6797#L889-1 assume !(1 == ~T5_E~0); 6798#L894-1 assume !(1 == ~T6_E~0); 7063#L899-1 assume !(1 == ~T7_E~0); 7455#L904-1 assume !(1 == ~E_M~0); 7221#L909-1 assume !(1 == ~E_1~0); 7222#L914-1 assume !(1 == ~E_2~0); 7392#L919-1 assume !(1 == ~E_3~0); 7137#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6974#L929-1 assume !(1 == ~E_5~0); 6975#L934-1 assume !(1 == ~E_6~0); 7201#L939-1 assume !(1 == ~E_7~0); 7202#L944-1 assume { :end_inline_reset_delta_events } true; 7043#L1190-2 [2023-11-23 22:34:30,115 INFO L750 eck$LassoCheckResult]: Loop: 7043#L1190-2 assume !false; 7054#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7055#L756-1 assume !false; 7056#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7629#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6896#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7186#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7187#L653 assume !(0 != eval_~tmp~0#1); 7240#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7318#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6914#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6915#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7243#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6860#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6861#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7121#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7122#L811-3 assume !(0 == ~T7_E~0); 7316#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7515#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7604#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7458#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7459#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7014#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7015#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7342#L851-3 assume !(0 == ~E_7~0); 6908#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6909#L388-27 assume 1 == ~m_pc~0; 7578#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7579#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7482#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7483#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7087#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7088#L407-27 assume 1 == ~t1_pc~0; 7466#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7467#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7385#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7386#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 7359#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7005#L426-27 assume 1 == ~t2_pc~0; 7006#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7019#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7020#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7460#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7575#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7310#L445-27 assume 1 == ~t3_pc~0; 7282#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6857#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6858#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7311#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7395#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7113#L464-27 assume !(1 == ~t4_pc~0); 6855#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 6856#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6927#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7238#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6998#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6999#L483-27 assume 1 == ~t5_pc~0; 7534#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6910#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6911#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7547#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7548#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7615#L502-27 assume 1 == ~t6_pc~0; 7616#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7337#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7612#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7488#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7489#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6799#L521-27 assume 1 == ~t7_pc~0; 6800#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7151#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7099#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6852#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6853#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7349#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7485#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7241#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7242#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7302#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7295#L889-3 assume !(1 == ~T5_E~0); 6964#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6965#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6985#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6986#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6943#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6944#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6980#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7472#L929-3 assume !(1 == ~E_5~0); 7393#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7394#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6990#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6991#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6817#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7110#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7111#L1209 assume !(0 == start_simulation_~tmp~3#1); 7332#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7315#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6958#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6848#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6849#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 6844#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6845#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 7042#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 7043#L1190-2 [2023-11-23 22:34:30,116 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:30,116 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2023-11-23 22:34:30,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:30,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217865742] [2023-11-23 22:34:30,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:30,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:30,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:30,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:30,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:30,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217865742] [2023-11-23 22:34:30,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1217865742] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:30,170 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:30,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:30,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732499778] [2023-11-23 22:34:30,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:30,172 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:30,172 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:30,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1885656989, now seen corresponding path program 2 times [2023-11-23 22:34:30,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:30,173 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142443385] [2023-11-23 22:34:30,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:30,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:30,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:30,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:30,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:30,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [142443385] [2023-11-23 22:34:30,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [142443385] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:30,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:30,292 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:30,292 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677662643] [2023-11-23 22:34:30,292 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:30,292 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:30,292 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:30,293 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:30,293 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:30,293 INFO L87 Difference]: Start difference. First operand 843 states and 1254 transitions. cyclomatic complexity: 412 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:30,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:30,321 INFO L93 Difference]: Finished difference Result 843 states and 1253 transitions. [2023-11-23 22:34:30,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1253 transitions. [2023-11-23 22:34:30,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:30,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1253 transitions. [2023-11-23 22:34:30,336 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-23 22:34:30,337 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-23 22:34:30,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1253 transitions. [2023-11-23 22:34:30,339 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:30,339 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1253 transitions. [2023-11-23 22:34:30,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1253 transitions. [2023-11-23 22:34:30,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-23 22:34:30,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4863582443653618) internal successors, (1253), 842 states have internal predecessors, (1253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:30,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1253 transitions. [2023-11-23 22:34:30,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1253 transitions. [2023-11-23 22:34:30,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:30,363 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1253 transitions. [2023-11-23 22:34:30,363 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-23 22:34:30,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1253 transitions. [2023-11-23 22:34:30,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:30,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:30,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:30,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:30,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:30,371 INFO L748 eck$LassoCheckResult]: Stem: 8733#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9281#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9282#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9321#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 8876#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8877#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8999#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9000#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8777#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8568#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8569#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8741#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8742#L781 assume !(0 == ~M_E~0); 9216#L781-2 assume !(0 == ~T1_E~0); 9324#L786-1 assume !(0 == ~T2_E~0); 8528#L791-1 assume !(0 == ~T3_E~0); 8529#L796-1 assume !(0 == ~T4_E~0); 9068#L801-1 assume !(0 == ~T5_E~0); 9069#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9099#L811-1 assume !(0 == ~T7_E~0); 8745#L816-1 assume !(0 == ~E_M~0); 8746#L821-1 assume !(0 == ~E_1~0); 8559#L826-1 assume !(0 == ~E_2~0); 8560#L831-1 assume !(0 == ~E_3~0); 8871#L836-1 assume !(0 == ~E_4~0); 8872#L841-1 assume !(0 == ~E_5~0); 8696#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8697#L851-1 assume !(0 == ~E_7~0); 8720#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8721#L388 assume !(1 == ~m_pc~0); 8714#L388-2 is_master_triggered_~__retres1~0#1 := 0; 8715#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9194#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8574#L967 assume !(0 != activate_threads_~tmp~1#1); 8575#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8504#L407 assume 1 == ~t1_pc~0; 8505#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8512#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8513#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8547#L975 assume !(0 != activate_threads_~tmp___0~0#1); 9279#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8831#L426 assume !(1 == ~t2_pc~0); 8832#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9296#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8853#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8854#L983 assume !(0 != activate_threads_~tmp___1~0#1); 9317#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8917#L445 assume 1 == ~t3_pc~0; 8918#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9222#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8502#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8503#L991 assume !(0 != activate_threads_~tmp___2~0#1); 9158#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9126#L464 assume !(1 == ~t4_pc~0); 8724#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8594#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8595#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8606#L999 assume !(0 != activate_threads_~tmp___3~0#1); 8896#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8897#L483 assume 1 == ~t5_pc~0; 9122#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9262#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9235#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9236#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 8814#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8815#L502 assume 1 == ~t6_pc~0; 9097#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8634#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8635#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8839#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 9036#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9245#L521 assume !(1 == ~t7_pc~0); 9276#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8570#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8571#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9270#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9249#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9185#L869 assume !(1 == ~M_E~0); 8890#L869-2 assume !(1 == ~T1_E~0); 8891#L874-1 assume !(1 == ~T2_E~0); 9304#L879-1 assume !(1 == ~T3_E~0); 8965#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8490#L889-1 assume !(1 == ~T5_E~0); 8491#L894-1 assume !(1 == ~T6_E~0); 8753#L899-1 assume !(1 == ~T7_E~0); 9148#L904-1 assume !(1 == ~E_M~0); 8914#L909-1 assume !(1 == ~E_1~0); 8915#L914-1 assume !(1 == ~E_2~0); 9084#L919-1 assume !(1 == ~E_3~0); 8830#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8667#L929-1 assume !(1 == ~E_5~0); 8668#L934-1 assume !(1 == ~E_6~0); 8892#L939-1 assume !(1 == ~E_7~0); 8893#L944-1 assume { :end_inline_reset_delta_events } true; 8736#L1190-2 [2023-11-23 22:34:30,372 INFO L750 eck$LassoCheckResult]: Loop: 8736#L1190-2 assume !false; 8747#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8748#L756-1 assume !false; 8749#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9322#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8589#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8878#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8879#L653 assume !(0 != eval_~tmp~0#1); 8931#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9009#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9010#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8607#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8608#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8936#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8553#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8554#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8816#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8817#L811-3 assume !(0 == ~T7_E~0); 9011#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9208#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9297#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9151#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9152#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8707#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8708#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9035#L851-3 assume !(0 == ~E_7~0); 8601#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8602#L388-27 assume 1 == ~m_pc~0; 9271#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9272#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9175#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9176#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8780#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8781#L407-27 assume 1 == ~t1_pc~0; 9159#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9160#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9078#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9079#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 9052#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8698#L426-27 assume 1 == ~t2_pc~0; 8699#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8712#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8713#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9153#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9268#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9003#L445-27 assume 1 == ~t3_pc~0; 8977#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8550#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8551#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9004#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9088#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8806#L464-27 assume !(1 == ~t4_pc~0); 8548#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 8549#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8618#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8929#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8691#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8692#L483-27 assume 1 == ~t5_pc~0; 9227#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8603#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8604#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9240#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9241#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9308#L502-27 assume !(1 == ~t6_pc~0); 9029#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 9030#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9305#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9181#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9182#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8492#L521-27 assume 1 == ~t7_pc~0; 8493#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8844#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8792#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8545#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8546#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9040#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9178#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8934#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8935#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8995#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8988#L889-3 assume !(1 == ~T5_E~0); 8657#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8658#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8678#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8679#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8636#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8637#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8673#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9165#L929-3 assume !(1 == ~E_5~0); 9086#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9087#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8683#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8684#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8510#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8804#L1209 assume !(0 == start_simulation_~tmp~3#1); 9025#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9008#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8651#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8541#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8542#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 8537#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8538#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8735#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 8736#L1190-2 [2023-11-23 22:34:30,372 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:30,373 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2023-11-23 22:34:30,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:30,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167921730] [2023-11-23 22:34:30,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:30,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:30,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:30,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:30,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:30,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1167921730] [2023-11-23 22:34:30,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1167921730] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:30,427 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:30,427 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:30,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181962339] [2023-11-23 22:34:30,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:30,433 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:30,433 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:30,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 2 times [2023-11-23 22:34:30,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:30,434 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041641675] [2023-11-23 22:34:30,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:30,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:30,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:30,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:30,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:30,490 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041641675] [2023-11-23 22:34:30,490 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2041641675] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:30,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:30,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:30,491 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766896063] [2023-11-23 22:34:30,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:30,492 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:30,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:30,492 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:30,493 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:30,493 INFO L87 Difference]: Start difference. First operand 843 states and 1253 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:30,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:30,515 INFO L93 Difference]: Finished difference Result 843 states and 1252 transitions. [2023-11-23 22:34:30,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1252 transitions. [2023-11-23 22:34:30,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:30,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1252 transitions. [2023-11-23 22:34:30,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-23 22:34:30,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-23 22:34:30,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1252 transitions. [2023-11-23 22:34:30,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:30,534 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1252 transitions. [2023-11-23 22:34:30,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1252 transitions. [2023-11-23 22:34:30,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-23 22:34:30,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4851720047449586) internal successors, (1252), 842 states have internal predecessors, (1252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:30,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1252 transitions. [2023-11-23 22:34:30,555 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1252 transitions. [2023-11-23 22:34:30,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:30,557 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1252 transitions. [2023-11-23 22:34:30,557 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-23 22:34:30,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1252 transitions. [2023-11-23 22:34:30,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:30,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:30,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:30,566 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:30,566 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:30,566 INFO L748 eck$LassoCheckResult]: Stem: 10426#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11014#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 10569#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10570#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10692#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10693#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10470#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10261#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10262#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10431#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10432#L781 assume !(0 == ~M_E~0); 10909#L781-2 assume !(0 == ~T1_E~0); 11017#L786-1 assume !(0 == ~T2_E~0); 10221#L791-1 assume !(0 == ~T3_E~0); 10222#L796-1 assume !(0 == ~T4_E~0); 10761#L801-1 assume !(0 == ~T5_E~0); 10762#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10792#L811-1 assume !(0 == ~T7_E~0); 10438#L816-1 assume !(0 == ~E_M~0); 10439#L821-1 assume !(0 == ~E_1~0); 10252#L826-1 assume !(0 == ~E_2~0); 10253#L831-1 assume !(0 == ~E_3~0); 10564#L836-1 assume !(0 == ~E_4~0); 10565#L841-1 assume !(0 == ~E_5~0); 10389#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10390#L851-1 assume !(0 == ~E_7~0); 10413#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10414#L388 assume !(1 == ~m_pc~0); 10407#L388-2 is_master_triggered_~__retres1~0#1 := 0; 10408#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10887#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10267#L967 assume !(0 != activate_threads_~tmp~1#1); 10268#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10197#L407 assume 1 == ~t1_pc~0; 10198#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10202#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10238#L975 assume !(0 != activate_threads_~tmp___0~0#1); 10972#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10524#L426 assume !(1 == ~t2_pc~0); 10525#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10989#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10546#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10547#L983 assume !(0 != activate_threads_~tmp___1~0#1); 11010#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10610#L445 assume 1 == ~t3_pc~0; 10611#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10915#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10195#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10196#L991 assume !(0 != activate_threads_~tmp___2~0#1); 10851#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10819#L464 assume !(1 == ~t4_pc~0); 10417#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10287#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10288#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10299#L999 assume !(0 != activate_threads_~tmp___3~0#1); 10589#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10590#L483 assume 1 == ~t5_pc~0; 10815#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10955#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10929#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 10507#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10508#L502 assume 1 == ~t6_pc~0; 10789#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10327#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10328#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10532#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 10729#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10938#L521 assume !(1 == ~t7_pc~0); 10969#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10263#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10264#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10963#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10942#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10878#L869 assume !(1 == ~M_E~0); 10583#L869-2 assume !(1 == ~T1_E~0); 10584#L874-1 assume !(1 == ~T2_E~0); 10997#L879-1 assume !(1 == ~T3_E~0); 10658#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10183#L889-1 assume !(1 == ~T5_E~0); 10184#L894-1 assume !(1 == ~T6_E~0); 10446#L899-1 assume !(1 == ~T7_E~0); 10840#L904-1 assume !(1 == ~E_M~0); 10607#L909-1 assume !(1 == ~E_1~0); 10608#L914-1 assume !(1 == ~E_2~0); 10777#L919-1 assume !(1 == ~E_3~0); 10523#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10360#L929-1 assume !(1 == ~E_5~0); 10361#L934-1 assume !(1 == ~E_6~0); 10585#L939-1 assume !(1 == ~E_7~0); 10586#L944-1 assume { :end_inline_reset_delta_events } true; 10429#L1190-2 [2023-11-23 22:34:30,567 INFO L750 eck$LassoCheckResult]: Loop: 10429#L1190-2 assume !false; 10440#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10441#L756-1 assume !false; 10442#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11015#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10280#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10571#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10572#L653 assume !(0 != eval_~tmp~0#1); 10623#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10703#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10300#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10301#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10629#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10246#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10247#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10509#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10510#L811-3 assume !(0 == ~T7_E~0); 10704#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10901#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10990#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10844#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10845#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10400#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10401#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10728#L851-3 assume !(0 == ~E_7~0); 10294#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10295#L388-27 assume 1 == ~m_pc~0; 10964#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10965#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10868#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10869#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10473#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10474#L407-27 assume 1 == ~t1_pc~0; 10852#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10853#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10771#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10772#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 10745#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10391#L426-27 assume 1 == ~t2_pc~0; 10392#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10405#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10406#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10846#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10961#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10696#L445-27 assume 1 == ~t3_pc~0; 10670#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10243#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10244#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10697#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10782#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10499#L464-27 assume !(1 == ~t4_pc~0); 10241#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 10242#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10313#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10626#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10384#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10385#L483-27 assume 1 == ~t5_pc~0; 10920#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10296#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10297#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10933#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10934#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11001#L502-27 assume !(1 == ~t6_pc~0); 10722#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 10723#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10998#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10874#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10875#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10185#L521-27 assume 1 == ~t7_pc~0; 10186#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10537#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10485#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10239#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10240#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10735#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10871#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10627#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10628#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10688#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10681#L889-3 assume !(1 == ~T5_E~0); 10350#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10351#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10371#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10372#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10329#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10330#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10366#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10858#L929-3 assume !(1 == ~E_5~0); 10779#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10780#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10376#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10377#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10205#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10497#L1209 assume !(0 == start_simulation_~tmp~3#1); 10718#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10701#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10344#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10234#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10235#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 10230#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10231#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10428#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 10429#L1190-2 [2023-11-23 22:34:30,568 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:30,568 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2023-11-23 22:34:30,568 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:30,568 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508318158] [2023-11-23 22:34:30,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:30,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:30,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:30,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:30,608 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:30,609 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [508318158] [2023-11-23 22:34:30,609 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [508318158] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:30,609 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:30,609 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:30,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673569067] [2023-11-23 22:34:30,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:30,610 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:30,610 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:30,610 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 3 times [2023-11-23 22:34:30,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:30,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54120157] [2023-11-23 22:34:30,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:30,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:30,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:30,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:30,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:30,671 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54120157] [2023-11-23 22:34:30,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54120157] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:30,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:30,672 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:30,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557856627] [2023-11-23 22:34:30,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:30,672 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:30,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:30,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:30,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:30,673 INFO L87 Difference]: Start difference. First operand 843 states and 1252 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:30,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:30,703 INFO L93 Difference]: Finished difference Result 843 states and 1251 transitions. [2023-11-23 22:34:30,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1251 transitions. [2023-11-23 22:34:30,711 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:30,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1251 transitions. [2023-11-23 22:34:30,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-23 22:34:30,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-23 22:34:30,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1251 transitions. [2023-11-23 22:34:30,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:30,722 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1251 transitions. [2023-11-23 22:34:30,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1251 transitions. [2023-11-23 22:34:30,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-23 22:34:30,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4839857651245552) internal successors, (1251), 842 states have internal predecessors, (1251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:30,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1251 transitions. [2023-11-23 22:34:30,741 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1251 transitions. [2023-11-23 22:34:30,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:30,743 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1251 transitions. [2023-11-23 22:34:30,744 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-23 22:34:30,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1251 transitions. [2023-11-23 22:34:30,749 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-23 22:34:30,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:30,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:30,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:30,752 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:30,752 INFO L748 eck$LassoCheckResult]: Stem: 12119#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12120#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12667#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12668#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12707#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 12262#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12263#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12385#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12386#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12163#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11954#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11955#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12124#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12125#L781 assume !(0 == ~M_E~0); 12602#L781-2 assume !(0 == ~T1_E~0); 12710#L786-1 assume !(0 == ~T2_E~0); 11914#L791-1 assume !(0 == ~T3_E~0); 11915#L796-1 assume !(0 == ~T4_E~0); 12454#L801-1 assume !(0 == ~T5_E~0); 12455#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12485#L811-1 assume !(0 == ~T7_E~0); 12131#L816-1 assume !(0 == ~E_M~0); 12132#L821-1 assume !(0 == ~E_1~0); 11945#L826-1 assume !(0 == ~E_2~0); 11946#L831-1 assume !(0 == ~E_3~0); 12257#L836-1 assume !(0 == ~E_4~0); 12258#L841-1 assume !(0 == ~E_5~0); 12082#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 12083#L851-1 assume !(0 == ~E_7~0); 12106#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12107#L388 assume !(1 == ~m_pc~0); 12100#L388-2 is_master_triggered_~__retres1~0#1 := 0; 12101#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12580#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11960#L967 assume !(0 != activate_threads_~tmp~1#1); 11961#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11890#L407 assume 1 == ~t1_pc~0; 11891#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11895#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11896#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11931#L975 assume !(0 != activate_threads_~tmp___0~0#1); 12665#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12217#L426 assume !(1 == ~t2_pc~0); 12218#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12682#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12240#L983 assume !(0 != activate_threads_~tmp___1~0#1); 12703#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12303#L445 assume 1 == ~t3_pc~0; 12304#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12608#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11888#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11889#L991 assume !(0 != activate_threads_~tmp___2~0#1); 12544#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12512#L464 assume !(1 == ~t4_pc~0); 12110#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11980#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11981#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11992#L999 assume !(0 != activate_threads_~tmp___3~0#1); 12282#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12283#L483 assume 1 == ~t5_pc~0; 12508#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12648#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12621#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12622#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 12200#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12201#L502 assume 1 == ~t6_pc~0; 12482#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12020#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12021#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12225#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 12422#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12631#L521 assume !(1 == ~t7_pc~0); 12662#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11956#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11957#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12656#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12635#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12571#L869 assume !(1 == ~M_E~0); 12276#L869-2 assume !(1 == ~T1_E~0); 12277#L874-1 assume !(1 == ~T2_E~0); 12690#L879-1 assume !(1 == ~T3_E~0); 12351#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11876#L889-1 assume !(1 == ~T5_E~0); 11877#L894-1 assume !(1 == ~T6_E~0); 12139#L899-1 assume !(1 == ~T7_E~0); 12533#L904-1 assume !(1 == ~E_M~0); 12300#L909-1 assume !(1 == ~E_1~0); 12301#L914-1 assume !(1 == ~E_2~0); 12470#L919-1 assume !(1 == ~E_3~0); 12216#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12053#L929-1 assume !(1 == ~E_5~0); 12054#L934-1 assume !(1 == ~E_6~0); 12278#L939-1 assume !(1 == ~E_7~0); 12279#L944-1 assume { :end_inline_reset_delta_events } true; 12122#L1190-2 [2023-11-23 22:34:30,753 INFO L750 eck$LassoCheckResult]: Loop: 12122#L1190-2 assume !false; 12133#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12134#L756-1 assume !false; 12135#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12708#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11973#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12264#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12265#L653 assume !(0 != eval_~tmp~0#1); 12316#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12395#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12396#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11993#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11994#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12322#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11939#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11940#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12202#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12203#L811-3 assume !(0 == ~T7_E~0); 12397#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12594#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12683#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12537#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12538#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12093#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12094#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12421#L851-3 assume !(0 == ~E_7~0); 11987#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11988#L388-27 assume 1 == ~m_pc~0; 12657#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12658#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12561#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12562#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12166#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12167#L407-27 assume 1 == ~t1_pc~0; 12545#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12546#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12464#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12465#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 12438#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12084#L426-27 assume 1 == ~t2_pc~0; 12085#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12098#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12099#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12539#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12654#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12389#L445-27 assume 1 == ~t3_pc~0; 12363#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11936#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11937#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12390#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12475#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12192#L464-27 assume 1 == ~t4_pc~0; 12193#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11935#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12006#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12319#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12077#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12078#L483-27 assume 1 == ~t5_pc~0; 12613#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11989#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11990#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12626#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12627#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12694#L502-27 assume 1 == ~t6_pc~0; 12695#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12416#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12691#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12567#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12568#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11878#L521-27 assume 1 == ~t7_pc~0; 11879#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12230#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12178#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11932#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11933#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12428#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12564#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12320#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12321#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12381#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12374#L889-3 assume !(1 == ~T5_E~0); 12043#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12044#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12064#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12065#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12022#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12023#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12059#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12551#L929-3 assume !(1 == ~E_5~0); 12472#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12473#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12069#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12070#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11898#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12189#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 12190#L1209 assume !(0 == start_simulation_~tmp~3#1); 12411#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12394#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 12037#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11927#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11928#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11923#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11924#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12121#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 12122#L1190-2 [2023-11-23 22:34:30,753 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:30,754 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2023-11-23 22:34:30,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:30,754 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305366924] [2023-11-23 22:34:30,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:30,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:30,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:30,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:30,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:30,882 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305366924] [2023-11-23 22:34:30,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1305366924] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:30,883 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:30,883 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:30,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18320137] [2023-11-23 22:34:30,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:30,884 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:30,884 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:30,884 INFO L85 PathProgramCache]: Analyzing trace with hash -2135531812, now seen corresponding path program 2 times [2023-11-23 22:34:30,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:30,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005843447] [2023-11-23 22:34:30,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:30,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:30,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:30,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:30,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:30,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005843447] [2023-11-23 22:34:30,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005843447] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:30,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:30,949 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:30,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094310066] [2023-11-23 22:34:30,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:30,949 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:30,950 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:30,950 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:34:30,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:34:30,950 INFO L87 Difference]: Start difference. First operand 843 states and 1251 transitions. cyclomatic complexity: 409 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:31,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:31,107 INFO L93 Difference]: Finished difference Result 1525 states and 2254 transitions. [2023-11-23 22:34:31,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1525 states and 2254 transitions. [2023-11-23 22:34:31,123 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1406 [2023-11-23 22:34:31,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1525 states to 1525 states and 2254 transitions. [2023-11-23 22:34:31,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1525 [2023-11-23 22:34:31,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1525 [2023-11-23 22:34:31,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1525 states and 2254 transitions. [2023-11-23 22:34:31,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:31,147 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2023-11-23 22:34:31,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1525 states and 2254 transitions. [2023-11-23 22:34:31,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1525 to 1525. [2023-11-23 22:34:31,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1525 states, 1525 states have (on average 1.4780327868852459) internal successors, (2254), 1524 states have internal predecessors, (2254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:31,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1525 states to 1525 states and 2254 transitions. [2023-11-23 22:34:31,202 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2023-11-23 22:34:31,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:34:31,205 INFO L428 stractBuchiCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2023-11-23 22:34:31,205 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-23 22:34:31,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1525 states and 2254 transitions. [2023-11-23 22:34:31,217 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1406 [2023-11-23 22:34:31,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:31,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:31,219 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:31,220 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:31,220 INFO L748 eck$LassoCheckResult]: Stem: 14498#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15072#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15073#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15121#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 14642#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14643#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14769#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14770#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14542#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14332#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14333#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14503#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14504#L781 assume !(0 == ~M_E~0); 15005#L781-2 assume !(0 == ~T1_E~0); 15127#L786-1 assume !(0 == ~T2_E~0); 14292#L791-1 assume !(0 == ~T3_E~0); 14293#L796-1 assume !(0 == ~T4_E~0); 14843#L801-1 assume !(0 == ~T5_E~0); 14844#L806-1 assume !(0 == ~T6_E~0); 14876#L811-1 assume !(0 == ~T7_E~0); 14510#L816-1 assume !(0 == ~E_M~0); 14511#L821-1 assume !(0 == ~E_1~0); 14323#L826-1 assume !(0 == ~E_2~0); 14324#L831-1 assume !(0 == ~E_3~0); 14637#L836-1 assume !(0 == ~E_4~0); 14638#L841-1 assume !(0 == ~E_5~0); 14460#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14461#L851-1 assume !(0 == ~E_7~0); 14484#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14485#L388 assume !(1 == ~m_pc~0); 14478#L388-2 is_master_triggered_~__retres1~0#1 := 0; 14479#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14981#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14338#L967 assume !(0 != activate_threads_~tmp~1#1); 14339#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14268#L407 assume 1 == ~t1_pc~0; 14269#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14273#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14274#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14309#L975 assume !(0 != activate_threads_~tmp___0~0#1); 15070#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14596#L426 assume !(1 == ~t2_pc~0); 14597#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15089#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14619#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14620#L983 assume !(0 != activate_threads_~tmp___1~0#1); 15116#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14684#L445 assume 1 == ~t3_pc~0; 14685#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15011#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14267#L991 assume !(0 != activate_threads_~tmp___2~0#1); 14942#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14908#L464 assume !(1 == ~t4_pc~0); 14488#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14358#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14359#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14370#L999 assume !(0 != activate_threads_~tmp___3~0#1); 14662#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14663#L483 assume 1 == ~t5_pc~0; 14904#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15053#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15024#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15025#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 14579#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14580#L502 assume 1 == ~t6_pc~0; 14873#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14398#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14399#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14605#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 14809#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15036#L521 assume !(1 == ~t7_pc~0); 15067#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14334#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14335#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15061#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15040#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14970#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 14656#L869-2 assume !(1 == ~T1_E~0); 14657#L874-1 assume !(1 == ~T2_E~0); 15101#L879-1 assume !(1 == ~T3_E~0); 14734#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14254#L889-1 assume !(1 == ~T5_E~0); 14255#L894-1 assume !(1 == ~T6_E~0); 14518#L899-1 assume !(1 == ~T7_E~0); 14930#L904-1 assume !(1 == ~E_M~0); 14681#L909-1 assume !(1 == ~E_1~0); 14682#L914-1 assume !(1 == ~E_2~0); 14860#L919-1 assume !(1 == ~E_3~0); 14595#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14431#L929-1 assume !(1 == ~E_5~0); 14432#L934-1 assume !(1 == ~E_6~0); 15105#L939-1 assume !(1 == ~E_7~0); 15035#L944-1 assume { :end_inline_reset_delta_events } true; 14501#L1190-2 [2023-11-23 22:34:31,221 INFO L750 eck$LassoCheckResult]: Loop: 14501#L1190-2 assume !false; 15139#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15138#L756-1 assume !false; 15137#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15136#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14899#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14900#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14696#L653 assume !(0 != eval_~tmp~0#1); 14698#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14780#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14781#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14371#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14372#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14704#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14317#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14318#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14581#L806-3 assume !(0 == ~T6_E~0); 14582#L811-3 assume !(0 == ~T7_E~0); 14782#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14997#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15090#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14935#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14936#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14471#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14472#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14808#L851-3 assume !(0 == ~E_7~0); 14365#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14366#L388-27 assume 1 == ~m_pc~0; 15062#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15063#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14959#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14960#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14545#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14546#L407-27 assume !(1 == ~t1_pc~0); 14945#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 14944#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14854#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14855#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 14826#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14462#L426-27 assume !(1 == ~t2_pc~0); 14464#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 14476#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14477#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14937#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15059#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14774#L445-27 assume 1 == ~t3_pc~0; 14746#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14314#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14315#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14775#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14866#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14571#L464-27 assume !(1 == ~t4_pc~0); 14312#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 14313#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14384#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14701#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14455#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14456#L483-27 assume 1 == ~t5_pc~0; 15016#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14367#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14368#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15029#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15030#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15107#L502-27 assume !(1 == ~t6_pc~0); 14802#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 14803#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15102#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14965#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14966#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14256#L521-27 assume 1 == ~t7_pc~0; 14257#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14610#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14557#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14310#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14311#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14816#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14962#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14702#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14703#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14764#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14757#L889-3 assume !(1 == ~T5_E~0); 14421#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14422#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14442#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14443#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14400#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14401#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14437#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14949#L929-3 assume !(1 == ~E_5~0); 14863#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14864#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14447#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14448#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14276#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15211#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15209#L1209 assume !(0 == start_simulation_~tmp~3#1); 14796#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14797#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15146#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15145#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15144#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 15143#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15142#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14500#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 14501#L1190-2 [2023-11-23 22:34:31,222 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:31,222 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2023-11-23 22:34:31,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:31,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033594015] [2023-11-23 22:34:31,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:31,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:31,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:31,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:31,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:31,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033594015] [2023-11-23 22:34:31,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1033594015] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:31,312 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:31,312 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:31,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315778123] [2023-11-23 22:34:31,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:31,313 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:31,314 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:31,314 INFO L85 PathProgramCache]: Analyzing trace with hash -1171889826, now seen corresponding path program 1 times [2023-11-23 22:34:31,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:31,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799327059] [2023-11-23 22:34:31,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:31,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:31,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:31,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:31,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:31,372 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1799327059] [2023-11-23 22:34:31,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1799327059] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:31,372 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:31,372 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:31,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1081475411] [2023-11-23 22:34:31,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:31,373 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:31,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:31,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:34:31,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:34:31,374 INFO L87 Difference]: Start difference. First operand 1525 states and 2254 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:31,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:31,546 INFO L93 Difference]: Finished difference Result 2755 states and 4059 transitions. [2023-11-23 22:34:31,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2755 states and 4059 transitions. [2023-11-23 22:34:31,573 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2622 [2023-11-23 22:34:31,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2755 states to 2755 states and 4059 transitions. [2023-11-23 22:34:31,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2755 [2023-11-23 22:34:31,602 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2755 [2023-11-23 22:34:31,603 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2755 states and 4059 transitions. [2023-11-23 22:34:31,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:31,607 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2755 states and 4059 transitions. [2023-11-23 22:34:31,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2755 states and 4059 transitions. [2023-11-23 22:34:31,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2755 to 2753. [2023-11-23 22:34:31,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2753 states, 2753 states have (on average 1.473665092626226) internal successors, (4057), 2752 states have internal predecessors, (4057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:31,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2753 states to 2753 states and 4057 transitions. [2023-11-23 22:34:31,681 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2753 states and 4057 transitions. [2023-11-23 22:34:31,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:34:31,683 INFO L428 stractBuchiCegarLoop]: Abstraction has 2753 states and 4057 transitions. [2023-11-23 22:34:31,684 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-23 22:34:31,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2753 states and 4057 transitions. [2023-11-23 22:34:31,700 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2622 [2023-11-23 22:34:31,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:31,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:31,702 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:31,702 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:31,703 INFO L748 eck$LassoCheckResult]: Stem: 18788#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19366#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19415#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 18933#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18934#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19061#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19062#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18833#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18622#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18623#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18796#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18797#L781 assume !(0 == ~M_E~0); 19290#L781-2 assume !(0 == ~T1_E~0); 19420#L786-1 assume !(0 == ~T2_E~0); 18585#L791-1 assume !(0 == ~T3_E~0); 18586#L796-1 assume !(0 == ~T4_E~0); 19135#L801-1 assume !(0 == ~T5_E~0); 19136#L806-1 assume !(0 == ~T6_E~0); 19167#L811-1 assume !(0 == ~T7_E~0); 18800#L816-1 assume !(0 == ~E_M~0); 18801#L821-1 assume !(0 == ~E_1~0); 18613#L826-1 assume !(0 == ~E_2~0); 18614#L831-1 assume !(0 == ~E_3~0); 18928#L836-1 assume !(0 == ~E_4~0); 18929#L841-1 assume !(0 == ~E_5~0); 18751#L846-1 assume !(0 == ~E_6~0); 18752#L851-1 assume !(0 == ~E_7~0); 18775#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18776#L388 assume !(1 == ~m_pc~0); 18769#L388-2 is_master_triggered_~__retres1~0#1 := 0; 18770#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19265#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18628#L967 assume !(0 != activate_threads_~tmp~1#1); 18629#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18558#L407 assume 1 == ~t1_pc~0; 18559#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18566#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18567#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18601#L975 assume !(0 != activate_threads_~tmp___0~0#1); 19363#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18888#L426 assume !(1 == ~t2_pc~0); 18889#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19385#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18910#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18911#L983 assume !(0 != activate_threads_~tmp___1~0#1); 19410#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18977#L445 assume 1 == ~t3_pc~0; 18978#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19300#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18557#L991 assume !(0 != activate_threads_~tmp___2~0#1); 19228#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19195#L464 assume !(1 == ~t4_pc~0); 18779#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18648#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18649#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18660#L999 assume !(0 != activate_threads_~tmp___3~0#1); 18955#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18956#L483 assume 1 == ~t5_pc~0; 19191#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19345#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19315#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19316#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 18871#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18872#L502 assume 1 == ~t6_pc~0; 19165#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18688#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18689#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18898#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 19102#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19325#L521 assume !(1 == ~t7_pc~0); 19360#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18624#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19354#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19332#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19257#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 19258#L869-2 assume !(1 == ~T1_E~0); 19591#L874-1 assume !(1 == ~T2_E~0); 19590#L879-1 assume !(1 == ~T3_E~0); 19589#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19588#L889-1 assume !(1 == ~T5_E~0); 19587#L894-1 assume !(1 == ~T6_E~0); 19585#L899-1 assume !(1 == ~T7_E~0); 19583#L904-1 assume !(1 == ~E_M~0); 19582#L909-1 assume !(1 == ~E_1~0); 19581#L914-1 assume !(1 == ~E_2~0); 19580#L919-1 assume !(1 == ~E_3~0); 19543#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19541#L929-1 assume !(1 == ~E_5~0); 19540#L934-1 assume !(1 == ~E_6~0); 19537#L939-1 assume !(1 == ~E_7~0); 19450#L944-1 assume { :end_inline_reset_delta_events } true; 19444#L1190-2 [2023-11-23 22:34:31,703 INFO L750 eck$LassoCheckResult]: Loop: 19444#L1190-2 assume !false; 19440#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19439#L756-1 assume !false; 19438#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19437#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19429#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19428#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19426#L653 assume !(0 != eval_~tmp~0#1); 19425#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19424#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19422#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19423#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19997#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19996#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19995#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19994#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19993#L806-3 assume !(0 == ~T6_E~0); 19941#L811-3 assume !(0 == ~T7_E~0); 19939#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19937#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19935#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19934#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19932#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19930#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19928#L846-3 assume !(0 == ~E_6~0); 19927#L851-3 assume !(0 == ~E_7~0); 19926#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19925#L388-27 assume !(1 == ~m_pc~0); 19922#L388-29 is_master_triggered_~__retres1~0#1 := 0; 19920#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19918#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19916#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19915#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19913#L407-27 assume 1 == ~t1_pc~0; 19910#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19908#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19905#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19862#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 19859#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19857#L426-27 assume 1 == ~t2_pc~0; 19854#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19851#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19849#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19847#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19845#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19843#L445-27 assume !(1 == ~t3_pc~0); 19815#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 19813#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19770#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19768#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19766#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19764#L464-27 assume 1 == ~t4_pc~0; 19760#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19758#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19756#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19754#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19752#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19750#L483-27 assume !(1 == ~t5_pc~0); 19723#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 19721#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19719#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19717#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19715#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19714#L502-27 assume 1 == ~t6_pc~0; 19712#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19711#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19664#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19663#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19636#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19633#L521-27 assume !(1 == ~t7_pc~0); 19630#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19628#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19626#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19607#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19593#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19550#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19390#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19546#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19544#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19529#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19526#L889-3 assume !(1 == ~T5_E~0); 19524#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18712#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19518#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19515#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19511#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19508#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19505#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19502#L929-3 assume !(1 == ~E_5~0); 19499#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19495#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19492#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19486#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19480#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19476#L1209 assume !(0 == start_simulation_~tmp~3#1); 19103#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19469#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19463#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 19459#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 19455#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19453#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 19451#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 19444#L1190-2 [2023-11-23 22:34:31,704 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:31,704 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2023-11-23 22:34:31,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:31,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020249159] [2023-11-23 22:34:31,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:31,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:31,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:31,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:31,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:31,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020249159] [2023-11-23 22:34:31,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1020249159] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:31,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:31,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:34:31,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136317539] [2023-11-23 22:34:31,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:31,778 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:31,778 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:31,778 INFO L85 PathProgramCache]: Analyzing trace with hash 601568924, now seen corresponding path program 1 times [2023-11-23 22:34:31,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:31,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1551829393] [2023-11-23 22:34:31,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:31,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:31,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:31,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:31,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:31,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1551829393] [2023-11-23 22:34:31,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1551829393] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:31,883 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:31,883 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:31,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771188835] [2023-11-23 22:34:31,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:31,884 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:31,884 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:31,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:31,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:31,885 INFO L87 Difference]: Start difference. First operand 2753 states and 4057 transitions. cyclomatic complexity: 1308 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:31,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:31,996 INFO L93 Difference]: Finished difference Result 5107 states and 7472 transitions. [2023-11-23 22:34:31,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5107 states and 7472 transitions. [2023-11-23 22:34:32,036 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4969 [2023-11-23 22:34:32,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5107 states to 5107 states and 7472 transitions. [2023-11-23 22:34:32,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5107 [2023-11-23 22:34:32,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5107 [2023-11-23 22:34:32,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5107 states and 7472 transitions. [2023-11-23 22:34:32,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:32,095 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5107 states and 7472 transitions. [2023-11-23 22:34:32,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5107 states and 7472 transitions. [2023-11-23 22:34:32,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5107 to 5099. [2023-11-23 22:34:32,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5099 states, 5099 states have (on average 1.4638164345950186) internal successors, (7464), 5098 states have internal predecessors, (7464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:32,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5099 states to 5099 states and 7464 transitions. [2023-11-23 22:34:32,222 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5099 states and 7464 transitions. [2023-11-23 22:34:32,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:32,223 INFO L428 stractBuchiCegarLoop]: Abstraction has 5099 states and 7464 transitions. [2023-11-23 22:34:32,223 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-23 22:34:32,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5099 states and 7464 transitions. [2023-11-23 22:34:32,247 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4961 [2023-11-23 22:34:32,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:32,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:32,249 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:32,249 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:32,250 INFO L748 eck$LassoCheckResult]: Stem: 26658#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 26659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 27304#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27305#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27400#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 26808#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26809#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26945#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26946#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26705#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26488#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26489#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26666#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26667#L781 assume !(0 == ~M_E~0); 27209#L781-2 assume !(0 == ~T1_E~0); 27416#L786-1 assume !(0 == ~T2_E~0); 26448#L791-1 assume !(0 == ~T3_E~0); 26449#L796-1 assume !(0 == ~T4_E~0); 27023#L801-1 assume !(0 == ~T5_E~0); 27024#L806-1 assume !(0 == ~T6_E~0); 27061#L811-1 assume !(0 == ~T7_E~0); 26671#L816-1 assume !(0 == ~E_M~0); 26672#L821-1 assume !(0 == ~E_1~0); 26479#L826-1 assume !(0 == ~E_2~0); 26480#L831-1 assume !(0 == ~E_3~0); 26803#L836-1 assume !(0 == ~E_4~0); 26804#L841-1 assume !(0 == ~E_5~0); 26620#L846-1 assume !(0 == ~E_6~0); 26621#L851-1 assume !(0 == ~E_7~0); 26644#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26645#L388 assume !(1 == ~m_pc~0); 26638#L388-2 is_master_triggered_~__retres1~0#1 := 0; 26639#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27177#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26494#L967 assume !(0 != activate_threads_~tmp~1#1); 26495#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26425#L407 assume !(1 == ~t1_pc~0); 26426#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26432#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26467#L975 assume !(0 != activate_threads_~tmp___0~0#1); 27302#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26763#L426 assume !(1 == ~t2_pc~0); 26764#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27333#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26785#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26786#L983 assume !(0 != activate_threads_~tmp___1~0#1); 27384#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26855#L445 assume 1 == ~t3_pc~0; 26856#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27218#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26424#L991 assume !(0 != activate_threads_~tmp___2~0#1); 27131#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27092#L464 assume !(1 == ~t4_pc~0); 26648#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26514#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26515#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26526#L999 assume !(0 != activate_threads_~tmp___3~0#1); 26833#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26834#L483 assume 1 == ~t5_pc~0; 27087#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27282#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27240#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27241#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 26744#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26745#L502 assume 1 == ~t6_pc~0; 27059#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26554#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26555#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26771#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 26982#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27254#L521 assume !(1 == ~t7_pc~0); 27299#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26490#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26491#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27293#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27262#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27165#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 27166#L869-2 assume !(1 == ~T1_E~0); 28230#L874-1 assume !(1 == ~T2_E~0); 27348#L879-1 assume !(1 == ~T3_E~0); 27349#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28193#L889-1 assume !(1 == ~T5_E~0); 28191#L894-1 assume !(1 == ~T6_E~0); 28190#L899-1 assume !(1 == ~T7_E~0); 28160#L904-1 assume !(1 == ~E_M~0); 28139#L909-1 assume !(1 == ~E_1~0); 28137#L914-1 assume !(1 == ~E_2~0); 28135#L919-1 assume !(1 == ~E_3~0); 28134#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26589#L929-1 assume !(1 == ~E_5~0); 26590#L934-1 assume !(1 == ~E_6~0); 28111#L939-1 assume !(1 == ~E_7~0); 28103#L944-1 assume { :end_inline_reset_delta_events } true; 28097#L1190-2 [2023-11-23 22:34:32,250 INFO L750 eck$LassoCheckResult]: Loop: 28097#L1190-2 assume !false; 28093#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28092#L756-1 assume !false; 28091#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28090#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28082#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28081#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28079#L653 assume !(0 != eval_~tmp~0#1); 28078#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28077#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28074#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28075#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29633#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29632#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29631#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29630#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29629#L806-3 assume !(0 == ~T6_E~0); 29628#L811-3 assume !(0 == ~T7_E~0); 29627#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29625#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29623#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29621#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29619#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29617#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29615#L846-3 assume !(0 == ~E_6~0); 29613#L851-3 assume !(0 == ~E_7~0); 29611#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29609#L388-27 assume !(1 == ~m_pc~0); 29605#L388-29 is_master_triggered_~__retres1~0#1 := 0; 29603#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29601#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29599#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29597#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29595#L407-27 assume !(1 == ~t1_pc~0); 29593#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 29591#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29589#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29586#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 29584#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29582#L426-27 assume 1 == ~t2_pc~0; 29579#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29577#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29575#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29573#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29571#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29569#L445-27 assume !(1 == ~t3_pc~0); 29566#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 29564#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29562#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29559#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29557#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29555#L464-27 assume 1 == ~t4_pc~0; 29552#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29550#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29548#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29545#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29543#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29541#L483-27 assume !(1 == ~t5_pc~0); 29538#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 29536#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29534#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29531#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29529#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29527#L502-27 assume 1 == ~t6_pc~0; 29524#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29522#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29520#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29517#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29515#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29513#L521-27 assume !(1 == ~t7_pc~0); 27954#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 27951#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27948#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27945#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27943#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27939#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27936#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27933#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27929#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27930#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28364#L889-3 assume !(1 == ~T5_E~0); 28346#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28269#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28267#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28266#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28265#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28263#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28261#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28259#L929-3 assume !(1 == ~E_5~0); 28229#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28226#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28196#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28172#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28167#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28166#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 28165#L1209 assume !(0 == start_simulation_~tmp~3#1); 27788#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28148#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28140#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28138#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 28125#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 28121#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28112#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 28104#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 28097#L1190-2 [2023-11-23 22:34:32,251 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:32,251 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2023-11-23 22:34:32,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:32,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433523768] [2023-11-23 22:34:32,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:32,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:32,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:32,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:32,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:32,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433523768] [2023-11-23 22:34:32,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433523768] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:32,326 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:32,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:34:32,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [87513677] [2023-11-23 22:34:32,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:32,327 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:32,328 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:32,328 INFO L85 PathProgramCache]: Analyzing trace with hash -1353752291, now seen corresponding path program 1 times [2023-11-23 22:34:32,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:32,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [650201052] [2023-11-23 22:34:32,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:32,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:32,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:32,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:32,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:32,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [650201052] [2023-11-23 22:34:32,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [650201052] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:32,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:32,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:32,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949095145] [2023-11-23 22:34:32,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:32,390 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:32,390 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:32,391 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:32,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:32,391 INFO L87 Difference]: Start difference. First operand 5099 states and 7464 transitions. cyclomatic complexity: 2373 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:32,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:32,512 INFO L93 Difference]: Finished difference Result 9533 states and 13868 transitions. [2023-11-23 22:34:32,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9533 states and 13868 transitions. [2023-11-23 22:34:32,572 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9380 [2023-11-23 22:34:32,709 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9533 states to 9533 states and 13868 transitions. [2023-11-23 22:34:32,710 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9533 [2023-11-23 22:34:32,722 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9533 [2023-11-23 22:34:32,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9533 states and 13868 transitions. [2023-11-23 22:34:32,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:32,735 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9533 states and 13868 transitions. [2023-11-23 22:34:32,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9533 states and 13868 transitions. [2023-11-23 22:34:32,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9533 to 9517. [2023-11-23 22:34:32,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9517 states, 9517 states have (on average 1.4555006829883366) internal successors, (13852), 9516 states have internal predecessors, (13852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:32,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9517 states to 9517 states and 13852 transitions. [2023-11-23 22:34:32,949 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9517 states and 13852 transitions. [2023-11-23 22:34:32,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:32,950 INFO L428 stractBuchiCegarLoop]: Abstraction has 9517 states and 13852 transitions. [2023-11-23 22:34:32,950 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-23 22:34:32,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9517 states and 13852 transitions. [2023-11-23 22:34:32,993 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9364 [2023-11-23 22:34:32,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:32,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:32,996 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:32,996 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:32,997 INFO L748 eck$LassoCheckResult]: Stem: 41298#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 41299#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 41920#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41921#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42009#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 41448#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41449#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41580#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41581#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41344#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41126#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41127#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41306#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41307#L781 assume !(0 == ~M_E~0); 41839#L781-2 assume !(0 == ~T1_E~0); 42025#L786-1 assume !(0 == ~T2_E~0); 41089#L791-1 assume !(0 == ~T3_E~0); 41090#L796-1 assume !(0 == ~T4_E~0); 41660#L801-1 assume !(0 == ~T5_E~0); 41661#L806-1 assume !(0 == ~T6_E~0); 41697#L811-1 assume !(0 == ~T7_E~0); 41311#L816-1 assume !(0 == ~E_M~0); 41312#L821-1 assume !(0 == ~E_1~0); 41117#L826-1 assume !(0 == ~E_2~0); 41118#L831-1 assume !(0 == ~E_3~0); 41443#L836-1 assume !(0 == ~E_4~0); 41444#L841-1 assume !(0 == ~E_5~0); 41261#L846-1 assume !(0 == ~E_6~0); 41262#L851-1 assume !(0 == ~E_7~0); 41285#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41286#L388 assume !(1 == ~m_pc~0); 41279#L388-2 is_master_triggered_~__retres1~0#1 := 0; 41280#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41811#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41132#L967 assume !(0 != activate_threads_~tmp~1#1); 41133#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41064#L407 assume !(1 == ~t1_pc~0); 41065#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41071#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41072#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41105#L975 assume !(0 != activate_threads_~tmp___0~0#1); 41918#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41401#L426 assume !(1 == ~t2_pc~0); 41402#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41948#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41424#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41425#L983 assume !(0 != activate_threads_~tmp___1~0#1); 41993#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41491#L445 assume !(1 == ~t3_pc~0); 41492#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41847#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41062#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41063#L991 assume !(0 != activate_threads_~tmp___2~0#1); 41768#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41732#L464 assume !(1 == ~t4_pc~0); 41289#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41152#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41153#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41168#L999 assume !(0 != activate_threads_~tmp___3~0#1); 41469#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41470#L483 assume 1 == ~t5_pc~0; 41728#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41895#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41863#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41864#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 41385#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41386#L502 assume 1 == ~t6_pc~0; 41695#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41194#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41195#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41411#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 41620#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41877#L521 assume !(1 == ~t7_pc~0); 41912#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41128#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41129#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41906#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41882#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41802#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 41803#L869-2 assume !(1 == ~T1_E~0); 43992#L874-1 assume !(1 == ~T2_E~0); 43991#L879-1 assume !(1 == ~T3_E~0); 43990#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43989#L889-1 assume !(1 == ~T5_E~0); 43988#L894-1 assume !(1 == ~T6_E~0); 43987#L899-1 assume !(1 == ~T7_E~0); 43986#L904-1 assume !(1 == ~E_M~0); 43985#L909-1 assume !(1 == ~E_1~0); 43984#L914-1 assume !(1 == ~E_2~0); 41708#L919-1 assume !(1 == ~E_3~0); 41709#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43799#L929-1 assume !(1 == ~E_5~0); 43798#L934-1 assume !(1 == ~E_6~0); 43795#L939-1 assume !(1 == ~E_7~0); 43794#L944-1 assume { :end_inline_reset_delta_events } true; 43793#L1190-2 [2023-11-23 22:34:32,997 INFO L750 eck$LassoCheckResult]: Loop: 43793#L1190-2 assume !false; 43767#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43737#L756-1 assume !false; 43735#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43707#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43672#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43670#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43644#L653 assume !(0 != eval_~tmp~0#1); 43645#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46454#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46452#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46450#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46448#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46446#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46444#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46442#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46440#L806-3 assume !(0 == ~T6_E~0); 46438#L811-3 assume !(0 == ~T7_E~0); 46436#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46434#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46432#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46430#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46428#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46426#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46424#L846-3 assume !(0 == ~E_6~0); 46422#L851-3 assume !(0 == ~E_7~0); 46420#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46418#L388-27 assume !(1 == ~m_pc~0); 46414#L388-29 is_master_triggered_~__retres1~0#1 := 0; 46412#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46410#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46408#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46406#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46404#L407-27 assume !(1 == ~t1_pc~0); 46402#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 46400#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46398#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46396#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 46394#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46392#L426-27 assume 1 == ~t2_pc~0; 46388#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46386#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46384#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46382#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46380#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46378#L445-27 assume !(1 == ~t3_pc~0); 46376#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 46374#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46372#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46370#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46368#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46366#L464-27 assume 1 == ~t4_pc~0; 46362#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46360#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46358#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46356#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46354#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46352#L483-27 assume !(1 == ~t5_pc~0); 46348#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 46346#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46344#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46341#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46338#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46335#L502-27 assume 1 == ~t6_pc~0; 46330#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46327#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46325#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46322#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46319#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46315#L521-27 assume !(1 == ~t7_pc~0); 46308#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 46305#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46302#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46196#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46195#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46148#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44800#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46143#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46141#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46138#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46136#L889-3 assume !(1 == ~T5_E~0); 46134#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44786#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46131#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46129#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46127#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46125#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46123#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46057#L929-3 assume !(1 == ~E_5~0); 46058#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46053#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46054#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42170#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42166#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 42155#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 42156#L1209 assume !(0 == start_simulation_~tmp~3#1); 43171#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43172#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43160#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43161#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 43156#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 43157#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43146#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 43147#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 43793#L1190-2 [2023-11-23 22:34:32,998 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:32,998 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2023-11-23 22:34:32,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:33,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999053987] [2023-11-23 22:34:33,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:33,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:33,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:33,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:33,070 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:33,071 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [999053987] [2023-11-23 22:34:33,071 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [999053987] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:33,071 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:33,071 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:34:33,071 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643186172] [2023-11-23 22:34:33,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:33,072 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:33,072 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:33,073 INFO L85 PathProgramCache]: Analyzing trace with hash -1353752291, now seen corresponding path program 2 times [2023-11-23 22:34:33,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:33,073 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335780380] [2023-11-23 22:34:33,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:33,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:33,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:33,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:33,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:33,134 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335780380] [2023-11-23 22:34:33,135 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335780380] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:33,135 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:33,135 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:33,135 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852934201] [2023-11-23 22:34:33,135 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:33,136 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:33,136 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:33,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:33,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:33,137 INFO L87 Difference]: Start difference. First operand 9517 states and 13852 transitions. cyclomatic complexity: 4351 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:33,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:33,302 INFO L93 Difference]: Finished difference Result 18316 states and 26485 transitions. [2023-11-23 22:34:33,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18316 states and 26485 transitions. [2023-11-23 22:34:33,554 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18108 [2023-11-23 22:34:33,621 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18316 states to 18316 states and 26485 transitions. [2023-11-23 22:34:33,621 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18316 [2023-11-23 22:34:33,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18316 [2023-11-23 22:34:33,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18316 states and 26485 transitions. [2023-11-23 22:34:33,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:33,661 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18316 states and 26485 transitions. [2023-11-23 22:34:33,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18316 states and 26485 transitions. [2023-11-23 22:34:34,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18316 to 18284. [2023-11-23 22:34:34,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18284 states, 18284 states have (on average 1.4467840735068913) internal successors, (26453), 18283 states have internal predecessors, (26453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:34,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18284 states to 18284 states and 26453 transitions. [2023-11-23 22:34:34,153 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18284 states and 26453 transitions. [2023-11-23 22:34:34,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:34,154 INFO L428 stractBuchiCegarLoop]: Abstraction has 18284 states and 26453 transitions. [2023-11-23 22:34:34,154 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-23 22:34:34,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18284 states and 26453 transitions. [2023-11-23 22:34:34,243 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18076 [2023-11-23 22:34:34,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:34,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:34,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:34,245 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:34,246 INFO L748 eck$LassoCheckResult]: Stem: 69133#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 69134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 69745#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69746#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69824#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 69280#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69281#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69413#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69414#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69180#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68965#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68966#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69141#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69142#L781 assume !(0 == ~M_E~0); 69660#L781-2 assume !(0 == ~T1_E~0); 69843#L786-1 assume !(0 == ~T2_E~0); 68926#L791-1 assume !(0 == ~T3_E~0); 68927#L796-1 assume !(0 == ~T4_E~0); 69491#L801-1 assume !(0 == ~T5_E~0); 69492#L806-1 assume !(0 == ~T6_E~0); 69527#L811-1 assume !(0 == ~T7_E~0); 69146#L816-1 assume !(0 == ~E_M~0); 69147#L821-1 assume !(0 == ~E_1~0); 68957#L826-1 assume !(0 == ~E_2~0); 68958#L831-1 assume !(0 == ~E_3~0); 69275#L836-1 assume !(0 == ~E_4~0); 69276#L841-1 assume !(0 == ~E_5~0); 69095#L846-1 assume !(0 == ~E_6~0); 69096#L851-1 assume !(0 == ~E_7~0); 69119#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69120#L388 assume !(1 == ~m_pc~0); 69113#L388-2 is_master_triggered_~__retres1~0#1 := 0; 69114#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69633#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68971#L967 assume !(0 != activate_threads_~tmp~1#1); 68972#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68904#L407 assume !(1 == ~t1_pc~0); 68905#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68911#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68912#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68945#L975 assume !(0 != activate_threads_~tmp___0~0#1); 69742#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69234#L426 assume !(1 == ~t2_pc~0); 69235#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69770#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69256#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 69257#L983 assume !(0 != activate_threads_~tmp___1~0#1); 69814#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69325#L445 assume !(1 == ~t3_pc~0); 69326#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69667#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68902#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68903#L991 assume !(0 != activate_threads_~tmp___2~0#1); 69591#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69557#L464 assume !(1 == ~t4_pc~0); 69123#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68991#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68992#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69003#L999 assume !(0 != activate_threads_~tmp___3~0#1); 69303#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69304#L483 assume !(1 == ~t5_pc~0); 69554#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69724#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69687#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69688#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 69217#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69218#L502 assume 1 == ~t6_pc~0; 69525#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69031#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69032#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69242#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 69454#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69699#L521 assume !(1 == ~t7_pc~0); 69738#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68967#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68968#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69732#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69706#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69622#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 69297#L869-2 assume !(1 == ~T1_E~0); 69298#L874-1 assume !(1 == ~T2_E~0); 69809#L879-1 assume !(1 == ~T3_E~0); 69375#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69376#L889-1 assume !(1 == ~T5_E~0); 69154#L894-1 assume !(1 == ~T6_E~0); 69155#L899-1 assume !(1 == ~T7_E~0); 69581#L904-1 assume !(1 == ~E_M~0); 69322#L909-1 assume !(1 == ~E_1~0); 69323#L914-1 assume !(1 == ~E_2~0); 69510#L919-1 assume !(1 == ~E_3~0); 69536#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69065#L929-1 assume !(1 == ~E_5~0); 69066#L934-1 assume !(1 == ~E_6~0); 73409#L939-1 assume !(1 == ~E_7~0); 73399#L944-1 assume { :end_inline_reset_delta_events } true; 73392#L1190-2 [2023-11-23 22:34:34,247 INFO L750 eck$LassoCheckResult]: Loop: 73392#L1190-2 assume !false; 73387#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 73385#L756-1 assume !false; 73383#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 73381#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73373#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73370#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 73368#L653 assume !(0 != eval_~tmp~0#1); 73369#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 73982#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 73979#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 73976#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 73973#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73970#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 73967#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 73964#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 73961#L806-3 assume !(0 == ~T6_E~0); 73958#L811-3 assume !(0 == ~T7_E~0); 73955#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 73952#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 73949#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 73946#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 73943#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 73940#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 73937#L846-3 assume !(0 == ~E_6~0); 73934#L851-3 assume !(0 == ~E_7~0); 73931#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73928#L388-27 assume !(1 == ~m_pc~0); 73923#L388-29 is_master_triggered_~__retres1~0#1 := 0; 73919#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73916#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 73913#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 73910#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73907#L407-27 assume !(1 == ~t1_pc~0); 73904#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 73901#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73898#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 73895#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 73892#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73889#L426-27 assume !(1 == ~t2_pc~0); 73885#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 73880#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73877#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 73874#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 73871#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73868#L445-27 assume !(1 == ~t3_pc~0); 73865#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 73862#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73859#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73855#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 73851#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73847#L464-27 assume 1 == ~t4_pc~0; 73841#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73836#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73832#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73828#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 73823#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73819#L483-27 assume !(1 == ~t5_pc~0); 73815#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 73811#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73807#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73803#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 73799#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73795#L502-27 assume 1 == ~t6_pc~0; 73789#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73784#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73780#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73776#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73771#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73766#L521-27 assume 1 == ~t7_pc~0; 73759#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 73752#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73747#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73742#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 73736#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73731#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 69775#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73720#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73710#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73704#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73698#L889-3 assume !(1 == ~T5_E~0); 73693#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69055#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 73680#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 73675#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 73670#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 73665#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 73660#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73655#L929-3 assume !(1 == ~E_5~0); 73650#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 73644#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 73642#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 73590#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73582#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73579#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 73575#L1209 assume !(0 == start_simulation_~tmp~3#1); 73573#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 73457#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73443#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73433#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 73428#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 73419#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73410#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 73400#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 73392#L1190-2 [2023-11-23 22:34:34,247 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:34,248 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2023-11-23 22:34:34,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:34,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128046555] [2023-11-23 22:34:34,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:34,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:34,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:34,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:34,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:34,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128046555] [2023-11-23 22:34:34,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2128046555] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:34,322 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:34,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:34:34,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [273520000] [2023-11-23 22:34:34,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:34,324 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:34,325 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:34,325 INFO L85 PathProgramCache]: Analyzing trace with hash -2027558563, now seen corresponding path program 1 times [2023-11-23 22:34:34,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:34,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999564834] [2023-11-23 22:34:34,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:34,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:34,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:34,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:34,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:34,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999564834] [2023-11-23 22:34:34,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999564834] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:34,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:34,386 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:34,386 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262194017] [2023-11-23 22:34:34,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:34,387 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:34,387 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:34,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:34,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:34,389 INFO L87 Difference]: Start difference. First operand 18284 states and 26453 transitions. cyclomatic complexity: 8201 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:34,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:34,786 INFO L93 Difference]: Finished difference Result 34391 states and 49534 transitions. [2023-11-23 22:34:34,786 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34391 states and 49534 transitions. [2023-11-23 22:34:34,954 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 34040 [2023-11-23 22:34:35,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34391 states to 34391 states and 49534 transitions. [2023-11-23 22:34:35,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34391 [2023-11-23 22:34:35,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34391 [2023-11-23 22:34:35,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34391 states and 49534 transitions. [2023-11-23 22:34:35,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:35,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34391 states and 49534 transitions. [2023-11-23 22:34:35,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34391 states and 49534 transitions. [2023-11-23 22:34:35,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34391 to 34327. [2023-11-23 22:34:35,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34327 states, 34327 states have (on average 1.4411396276983133) internal successors, (49470), 34326 states have internal predecessors, (49470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:36,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34327 states to 34327 states and 49470 transitions. [2023-11-23 22:34:36,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34327 states and 49470 transitions. [2023-11-23 22:34:36,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:36,198 INFO L428 stractBuchiCegarLoop]: Abstraction has 34327 states and 49470 transitions. [2023-11-23 22:34:36,198 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-23 22:34:36,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34327 states and 49470 transitions. [2023-11-23 22:34:36,416 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 33976 [2023-11-23 22:34:36,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:36,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:36,418 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:36,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:36,419 INFO L748 eck$LassoCheckResult]: Stem: 121814#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 121815#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 122417#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122418#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122502#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 121960#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121961#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122090#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122091#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121861#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 121647#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 121648#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 121819#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 121820#L781 assume !(0 == ~M_E~0); 122333#L781-2 assume !(0 == ~T1_E~0); 122511#L786-1 assume !(0 == ~T2_E~0); 121608#L791-1 assume !(0 == ~T3_E~0); 121609#L796-1 assume !(0 == ~T4_E~0); 122164#L801-1 assume !(0 == ~T5_E~0); 122165#L806-1 assume !(0 == ~T6_E~0); 122197#L811-1 assume !(0 == ~T7_E~0); 121827#L816-1 assume !(0 == ~E_M~0); 121828#L821-1 assume !(0 == ~E_1~0); 121639#L826-1 assume !(0 == ~E_2~0); 121640#L831-1 assume !(0 == ~E_3~0); 121955#L836-1 assume !(0 == ~E_4~0); 121956#L841-1 assume !(0 == ~E_5~0); 121777#L846-1 assume !(0 == ~E_6~0); 121778#L851-1 assume !(0 == ~E_7~0); 121800#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121801#L388 assume !(1 == ~m_pc~0); 121794#L388-2 is_master_triggered_~__retres1~0#1 := 0; 121795#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122307#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 121653#L967 assume !(0 != activate_threads_~tmp~1#1); 121654#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121586#L407 assume !(1 == ~t1_pc~0); 121587#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 121590#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121591#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 121625#L975 assume !(0 != activate_threads_~tmp___0~0#1); 122414#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121916#L426 assume !(1 == ~t2_pc~0); 121917#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 122445#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121938#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121939#L983 assume !(0 != activate_threads_~tmp___1~0#1); 122492#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122001#L445 assume !(1 == ~t3_pc~0); 122002#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 122342#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121584#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 121585#L991 assume !(0 != activate_threads_~tmp___2~0#1); 122266#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122230#L464 assume !(1 == ~t4_pc~0); 121804#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 121673#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121674#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121685#L999 assume !(0 != activate_threads_~tmp___3~0#1); 121981#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121982#L483 assume !(1 == ~t5_pc~0); 122227#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122392#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122361#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122362#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 121898#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121899#L502 assume !(1 == ~t6_pc~0); 121755#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 121713#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121714#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 121924#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 122128#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122373#L521 assume !(1 == ~t7_pc~0); 122409#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 121649#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 121650#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 122403#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 122378#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122297#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 122298#L869-2 assume !(1 == ~T1_E~0); 122487#L874-1 assume !(1 == ~T2_E~0); 122457#L879-1 assume !(1 == ~T3_E~0); 122458#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123702#L889-1 assume !(1 == ~T5_E~0); 123700#L894-1 assume !(1 == ~T6_E~0); 123698#L899-1 assume !(1 == ~T7_E~0); 123697#L904-1 assume !(1 == ~E_M~0); 123696#L909-1 assume !(1 == ~E_1~0); 123695#L914-1 assume !(1 == ~E_2~0); 122206#L919-1 assume !(1 == ~E_3~0); 121915#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 121747#L929-1 assume !(1 == ~E_5~0); 121748#L934-1 assume !(1 == ~E_6~0); 123590#L939-1 assume !(1 == ~E_7~0); 123585#L944-1 assume { :end_inline_reset_delta_events } true; 123576#L1190-2 [2023-11-23 22:34:36,420 INFO L750 eck$LassoCheckResult]: Loop: 123576#L1190-2 assume !false; 123545#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 123543#L756-1 assume !false; 123489#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 123487#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 123479#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 123469#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 123459#L653 assume !(0 != eval_~tmp~0#1); 123460#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 124177#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 124176#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 124175#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 124174#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 124173#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 124172#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 124171#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 124170#L806-3 assume !(0 == ~T6_E~0); 124169#L811-3 assume !(0 == ~T7_E~0); 124167#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 124166#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 124165#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 124164#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 124163#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 124162#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 124153#L846-3 assume !(0 == ~E_6~0); 124151#L851-3 assume !(0 == ~E_7~0); 124149#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124147#L388-27 assume !(1 == ~m_pc~0); 124109#L388-29 is_master_triggered_~__retres1~0#1 := 0; 124107#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124105#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 124103#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 124101#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124099#L407-27 assume !(1 == ~t1_pc~0); 124097#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 124095#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 124093#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 124091#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 124089#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124087#L426-27 assume 1 == ~t2_pc~0; 124083#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 124081#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124079#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124077#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 124075#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124073#L445-27 assume !(1 == ~t3_pc~0); 124071#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 124069#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124067#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124065#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 124063#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124061#L464-27 assume 1 == ~t4_pc~0; 124057#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 124055#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124053#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 124051#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124049#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124047#L483-27 assume !(1 == ~t5_pc~0); 124045#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 124043#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124041#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124039#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 124037#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124035#L502-27 assume !(1 == ~t6_pc~0); 124033#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 124031#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124029#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 124027#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 124025#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124023#L521-27 assume !(1 == ~t7_pc~0); 124019#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 124017#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 124015#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124013#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 124011#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124009#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 124005#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 124003#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 124001#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123999#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123997#L889-3 assume !(1 == ~T5_E~0); 123993#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 123989#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 123987#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 123985#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 123983#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 123981#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 123979#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 123977#L929-3 assume !(1 == ~E_5~0); 123976#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 123973#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 123972#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 123968#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 123963#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 123954#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 123951#L1209 assume !(0 == start_simulation_~tmp~3#1); 123949#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 123852#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 123822#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 123802#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 123795#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 123689#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123688#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 123586#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 123576#L1190-2 [2023-11-23 22:34:36,420 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:36,421 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2023-11-23 22:34:36,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:36,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531312492] [2023-11-23 22:34:36,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:36,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:36,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:36,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:36,493 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:36,493 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [531312492] [2023-11-23 22:34:36,494 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [531312492] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:36,494 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:36,494 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:34:36,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1956654550] [2023-11-23 22:34:36,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:36,497 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:36,498 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:36,498 INFO L85 PathProgramCache]: Analyzing trace with hash -1838927010, now seen corresponding path program 1 times [2023-11-23 22:34:36,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:36,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236223709] [2023-11-23 22:34:36,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:36,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:36,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:36,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:36,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:36,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236223709] [2023-11-23 22:34:36,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236223709] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:36,548 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:36,548 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:36,549 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545439480] [2023-11-23 22:34:36,549 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:36,549 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:36,549 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:36,550 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 22:34:36,550 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 22:34:36,551 INFO L87 Difference]: Start difference. First operand 34327 states and 49470 transitions. cyclomatic complexity: 15207 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:37,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:37,367 INFO L93 Difference]: Finished difference Result 67681 states and 96593 transitions. [2023-11-23 22:34:37,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67681 states and 96593 transitions. [2023-11-23 22:34:37,961 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 67056 [2023-11-23 22:34:38,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67681 states to 67681 states and 96593 transitions. [2023-11-23 22:34:38,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67681 [2023-11-23 22:34:38,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67681 [2023-11-23 22:34:38,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67681 states and 96593 transitions. [2023-11-23 22:34:38,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:38,552 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67681 states and 96593 transitions. [2023-11-23 22:34:38,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67681 states and 96593 transitions. [2023-11-23 22:34:39,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67681 to 35674. [2023-11-23 22:34:39,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35674 states, 35674 states have (on average 1.4244828166171442) internal successors, (50817), 35673 states have internal predecessors, (50817), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:39,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35674 states to 35674 states and 50817 transitions. [2023-11-23 22:34:39,438 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2023-11-23 22:34:39,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-23 22:34:39,440 INFO L428 stractBuchiCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2023-11-23 22:34:39,440 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-23 22:34:39,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35674 states and 50817 transitions. [2023-11-23 22:34:39,543 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35320 [2023-11-23 22:34:39,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:39,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:39,545 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:39,545 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:39,545 INFO L748 eck$LassoCheckResult]: Stem: 223840#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 223841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 224473#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 224474#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 224567#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 223986#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 223987#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224121#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 224122#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 223886#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 223669#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 223670#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 223845#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 223846#L781 assume !(0 == ~M_E~0); 224382#L781-2 assume !(0 == ~T1_E~0); 224586#L786-1 assume !(0 == ~T2_E~0); 223629#L791-1 assume !(0 == ~T3_E~0); 223630#L796-1 assume !(0 == ~T4_E~0); 224202#L801-1 assume !(0 == ~T5_E~0); 224203#L806-1 assume !(0 == ~T6_E~0); 224239#L811-1 assume !(0 == ~T7_E~0); 223852#L816-1 assume !(0 == ~E_M~0); 223853#L821-1 assume !(0 == ~E_1~0); 223660#L826-1 assume !(0 == ~E_2~0); 223661#L831-1 assume !(0 == ~E_3~0); 223981#L836-1 assume !(0 == ~E_4~0); 223982#L841-1 assume !(0 == ~E_5~0); 223802#L846-1 assume !(0 == ~E_6~0); 223803#L851-1 assume !(0 == ~E_7~0); 223826#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 223827#L388 assume !(1 == ~m_pc~0); 223820#L388-2 is_master_triggered_~__retres1~0#1 := 0; 223821#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 224354#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 223675#L967 assume !(0 != activate_threads_~tmp~1#1); 223676#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 223607#L407 assume !(1 == ~t1_pc~0); 223608#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 223611#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 223612#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 223646#L975 assume !(0 != activate_threads_~tmp___0~0#1); 224471#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223942#L426 assume !(1 == ~t2_pc~0); 223943#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 224500#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 223965#L983 assume !(0 != activate_threads_~tmp___1~0#1); 224550#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224031#L445 assume !(1 == ~t3_pc~0); 224032#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 224391#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 223605#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 223606#L991 assume !(0 != activate_threads_~tmp___2~0#1); 224310#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 224269#L464 assume !(1 == ~t4_pc~0); 223830#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 223695#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223696#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 223707#L999 assume !(0 != activate_threads_~tmp___3~0#1); 224008#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224009#L483 assume !(1 == ~t5_pc~0); 224266#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 224451#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 224409#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 224410#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 223925#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 223926#L502 assume !(1 == ~t6_pc~0); 223778#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 223735#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223736#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 223950#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 224161#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 224425#L521 assume !(1 == ~t7_pc~0); 224468#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 223671#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 223672#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 224461#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 224432#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 224343#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 224000#L869-2 assume !(1 == ~T1_E~0); 224001#L874-1 assume !(1 == ~T2_E~0); 224516#L879-1 assume !(1 == ~T3_E~0); 224517#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 229542#L889-1 assume !(1 == ~T5_E~0); 223860#L894-1 assume !(1 == ~T6_E~0); 223861#L899-1 assume !(1 == ~T7_E~0); 224295#L904-1 assume !(1 == ~E_M~0); 224028#L909-1 assume !(1 == ~E_1~0); 224029#L914-1 assume !(1 == ~E_2~0); 224224#L919-1 assume !(1 == ~E_3~0); 223941#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 223771#L929-1 assume !(1 == ~E_5~0); 223772#L934-1 assume !(1 == ~E_6~0); 224524#L939-1 assume !(1 == ~E_7~0); 235747#L944-1 assume { :end_inline_reset_delta_events } true; 235739#L1190-2 [2023-11-23 22:34:39,546 INFO L750 eck$LassoCheckResult]: Loop: 235739#L1190-2 assume !false; 235733#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 235730#L756-1 assume !false; 235727#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 235704#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 235694#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 235690#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 235685#L653 assume !(0 != eval_~tmp~0#1); 235686#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 236456#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 236447#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 236445#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 236443#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 236440#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 236436#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 236420#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 236411#L806-3 assume !(0 == ~T6_E~0); 236409#L811-3 assume !(0 == ~T7_E~0); 236407#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 236404#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 236400#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 236397#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 236384#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 236383#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 236382#L846-3 assume !(0 == ~E_6~0); 236381#L851-3 assume !(0 == ~E_7~0); 236380#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 236378#L388-27 assume !(1 == ~m_pc~0); 236375#L388-29 is_master_triggered_~__retres1~0#1 := 0; 236373#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 236370#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 236368#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 236366#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 236364#L407-27 assume !(1 == ~t1_pc~0); 236362#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 236360#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 236357#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 236355#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 236353#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 236351#L426-27 assume !(1 == ~t2_pc~0); 236349#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 236346#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 236343#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 236341#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 236339#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 236337#L445-27 assume !(1 == ~t3_pc~0); 236335#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 236333#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 236331#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 236329#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 236327#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 236325#L464-27 assume !(1 == ~t4_pc~0); 236323#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 236320#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 236317#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 236315#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 236313#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 236311#L483-27 assume !(1 == ~t5_pc~0); 236308#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 236305#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 236303#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 236301#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 236299#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 236297#L502-27 assume !(1 == ~t6_pc~0); 236295#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 236293#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 236291#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 236289#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 236287#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 236286#L521-27 assume !(1 == ~t7_pc~0); 236285#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 236283#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 236281#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 236279#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 235909#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 235907#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 229733#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 235902#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 235899#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 235896#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 235893#L889-3 assume !(1 == ~T5_E~0); 235890#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 235885#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 235882#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 235879#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 235876#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 235873#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 235870#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 235867#L929-3 assume !(1 == ~E_5~0); 235864#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 229715#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 235860#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 235842#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 235833#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 235824#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 235819#L1209 assume !(0 == start_simulation_~tmp~3#1); 235816#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 235805#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 235795#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 235788#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 235787#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 235764#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 235756#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 235748#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 235739#L1190-2 [2023-11-23 22:34:39,547 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:39,547 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2023-11-23 22:34:39,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:39,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370775779] [2023-11-23 22:34:39,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:39,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:39,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:39,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:39,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:39,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370775779] [2023-11-23 22:34:39,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370775779] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:39,624 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:39,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:34:39,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117616815] [2023-11-23 22:34:39,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:39,625 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:39,625 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:39,626 INFO L85 PathProgramCache]: Analyzing trace with hash -1033462814, now seen corresponding path program 1 times [2023-11-23 22:34:39,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:39,626 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715789903] [2023-11-23 22:34:39,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:39,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:39,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:39,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:39,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:39,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715789903] [2023-11-23 22:34:39,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715789903] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:39,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:39,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:39,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [580385607] [2023-11-23 22:34:39,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:39,682 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:39,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:39,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:39,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:39,683 INFO L87 Difference]: Start difference. First operand 35674 states and 50817 transitions. cyclomatic complexity: 15207 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:40,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:40,131 INFO L93 Difference]: Finished difference Result 44740 states and 63748 transitions. [2023-11-23 22:34:40,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44740 states and 63748 transitions. [2023-11-23 22:34:40,356 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 44344 [2023-11-23 22:34:40,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44740 states to 44740 states and 63748 transitions. [2023-11-23 22:34:40,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44740 [2023-11-23 22:34:40,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44740 [2023-11-23 22:34:40,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44740 states and 63748 transitions. [2023-11-23 22:34:40,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:40,621 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44740 states and 63748 transitions. [2023-11-23 22:34:40,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44740 states and 63748 transitions. [2023-11-23 22:34:41,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44740 to 19206. [2023-11-23 22:34:41,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.4305425387899615) internal successors, (27475), 19205 states have internal predecessors, (27475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:41,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27475 transitions. [2023-11-23 22:34:41,422 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27475 transitions. [2023-11-23 22:34:41,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:41,423 INFO L428 stractBuchiCegarLoop]: Abstraction has 19206 states and 27475 transitions. [2023-11-23 22:34:41,423 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-23 22:34:41,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27475 transitions. [2023-11-23 22:34:41,481 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2023-11-23 22:34:41,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:41,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:41,483 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:41,483 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:41,483 INFO L748 eck$LassoCheckResult]: Stem: 304256#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 304257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 304849#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 304850#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 304922#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 304403#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 304404#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 304531#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 304532#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 304302#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 304091#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 304092#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 304264#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 304265#L781 assume !(0 == ~M_E~0); 304770#L781-2 assume !(0 == ~T1_E~0); 304932#L786-1 assume !(0 == ~T2_E~0); 304054#L791-1 assume !(0 == ~T3_E~0); 304055#L796-1 assume !(0 == ~T4_E~0); 304605#L801-1 assume !(0 == ~T5_E~0); 304606#L806-1 assume !(0 == ~T6_E~0); 304637#L811-1 assume !(0 == ~T7_E~0); 304268#L816-1 assume !(0 == ~E_M~0); 304269#L821-1 assume !(0 == ~E_1~0); 304082#L826-1 assume !(0 == ~E_2~0); 304083#L831-1 assume !(0 == ~E_3~0); 304398#L836-1 assume !(0 == ~E_4~0); 304399#L841-1 assume !(0 == ~E_5~0); 304219#L846-1 assume !(0 == ~E_6~0); 304220#L851-1 assume !(0 == ~E_7~0); 304243#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 304244#L388 assume !(1 == ~m_pc~0); 304237#L388-2 is_master_triggered_~__retres1~0#1 := 0; 304238#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 304744#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 304097#L967 assume !(0 != activate_threads_~tmp~1#1); 304098#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 304028#L407 assume !(1 == ~t1_pc~0); 304029#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 304035#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 304036#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 304070#L975 assume !(0 != activate_threads_~tmp___0~0#1); 304847#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 304357#L426 assume !(1 == ~t2_pc~0); 304358#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 304873#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 304379#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 304380#L983 assume !(0 != activate_threads_~tmp___1~0#1); 304915#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 304447#L445 assume !(1 == ~t3_pc~0); 304448#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 304777#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 304026#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 304027#L991 assume !(0 != activate_threads_~tmp___2~0#1); 304702#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 304665#L464 assume !(1 == ~t4_pc~0); 304249#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 304117#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 304118#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304131#L999 assume !(0 != activate_threads_~tmp___3~0#1); 304427#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 304428#L483 assume !(1 == ~t5_pc~0); 304662#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 304828#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 304795#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 304796#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 304342#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 304343#L502 assume !(1 == ~t6_pc~0); 304197#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 304157#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 304158#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 304367#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 304567#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 304809#L521 assume !(1 == ~t7_pc~0); 304844#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 304875#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 304934#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 304838#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 304813#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 304736#L869 assume !(1 == ~M_E~0); 304420#L869-2 assume !(1 == ~T1_E~0); 304421#L874-1 assume !(1 == ~T2_E~0); 304887#L879-1 assume !(1 == ~T3_E~0); 304496#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 304014#L889-1 assume !(1 == ~T5_E~0); 304015#L894-1 assume !(1 == ~T6_E~0); 304279#L899-1 assume !(1 == ~T7_E~0); 304692#L904-1 assume !(1 == ~E_M~0); 304444#L909-1 assume !(1 == ~E_1~0); 304445#L914-1 assume !(1 == ~E_2~0); 304624#L919-1 assume !(1 == ~E_3~0); 304356#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 304190#L929-1 assume !(1 == ~E_5~0); 304191#L934-1 assume !(1 == ~E_6~0); 304425#L939-1 assume !(1 == ~E_7~0); 304426#L944-1 assume { :end_inline_reset_delta_events } true; 304808#L1190-2 [2023-11-23 22:34:41,484 INFO L750 eck$LassoCheckResult]: Loop: 304808#L1190-2 assume !false; 310563#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 310374#L756-1 assume !false; 309229#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 308560#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 308551#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 308549#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 308546#L653 assume !(0 != eval_~tmp~0#1); 308543#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 308541#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 308539#L781-3 assume !(0 == ~M_E~0); 308538#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 308535#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 308534#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 308531#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 308527#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 308523#L806-3 assume !(0 == ~T6_E~0); 308519#L811-3 assume !(0 == ~T7_E~0); 308515#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 308511#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 308507#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 308502#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 308500#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 308498#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 308489#L846-3 assume !(0 == ~E_6~0); 308487#L851-3 assume !(0 == ~E_7~0); 308065#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 307924#L388-27 assume !(1 == ~m_pc~0); 307913#L388-29 is_master_triggered_~__retres1~0#1 := 0; 307904#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 307894#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 307887#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 307883#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 307875#L407-27 assume !(1 == ~t1_pc~0); 307864#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 307860#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 307856#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 307851#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 307847#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 307841#L426-27 assume 1 == ~t2_pc~0; 307836#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 307832#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 307828#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 307824#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 307820#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307815#L445-27 assume !(1 == ~t3_pc~0); 307811#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 307807#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 307803#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 307799#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 307795#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 307790#L464-27 assume 1 == ~t4_pc~0; 307785#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 307781#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 307777#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 307773#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 307769#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 307763#L483-27 assume !(1 == ~t5_pc~0); 307758#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 307754#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 307750#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 307746#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 307742#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 307738#L502-27 assume !(1 == ~t6_pc~0); 307733#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 307729#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 307725#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 307721#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 307717#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 307712#L521-27 assume 1 == ~t7_pc~0; 307705#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 307699#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 307693#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 307688#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 307684#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 307680#L869-3 assume !(1 == ~M_E~0); 306862#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 307671#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 307666#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 307662#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 307658#L889-3 assume !(1 == ~T5_E~0); 307655#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 307650#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 307646#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 307642#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 307638#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 307634#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 307630#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 307625#L929-3 assume !(1 == ~E_5~0); 307621#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 307617#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 307615#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 307592#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 307575#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 307547#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 307045#L1209 assume !(0 == start_simulation_~tmp~3#1); 307046#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 310601#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 310593#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 310589#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 310586#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 310580#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 310577#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 310573#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 304808#L1190-2 [2023-11-23 22:34:41,485 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:41,485 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2023-11-23 22:34:41,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:41,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238849348] [2023-11-23 22:34:41,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:41,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:41,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:41,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:41,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:41,563 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238849348] [2023-11-23 22:34:41,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1238849348] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:41,563 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:41,563 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:41,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64135800] [2023-11-23 22:34:41,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:41,564 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:41,564 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:41,564 INFO L85 PathProgramCache]: Analyzing trace with hash 1171819677, now seen corresponding path program 1 times [2023-11-23 22:34:41,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:41,565 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258643583] [2023-11-23 22:34:41,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:41,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:41,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:41,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:41,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:41,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [258643583] [2023-11-23 22:34:41,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [258643583] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:41,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:41,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:41,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997687160] [2023-11-23 22:34:41,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:41,628 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:41,629 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:41,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:34:41,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:34:41,629 INFO L87 Difference]: Start difference. First operand 19206 states and 27475 transitions. cyclomatic complexity: 8285 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:41,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:41,833 INFO L93 Difference]: Finished difference Result 30482 states and 43470 transitions. [2023-11-23 22:34:41,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30482 states and 43470 transitions. [2023-11-23 22:34:41,967 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 30128 [2023-11-23 22:34:42,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30482 states to 30482 states and 43470 transitions. [2023-11-23 22:34:42,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30482 [2023-11-23 22:34:42,085 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30482 [2023-11-23 22:34:42,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30482 states and 43470 transitions. [2023-11-23 22:34:42,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:42,111 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30482 states and 43470 transitions. [2023-11-23 22:34:42,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30482 states and 43470 transitions. [2023-11-23 22:34:42,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30482 to 21646. [2023-11-23 22:34:42,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4298715698050448) internal successors, (30951), 21645 states have internal predecessors, (30951), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:42,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30951 transitions. [2023-11-23 22:34:42,778 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30951 transitions. [2023-11-23 22:34:42,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:34:42,780 INFO L428 stractBuchiCegarLoop]: Abstraction has 21646 states and 30951 transitions. [2023-11-23 22:34:42,780 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-23 22:34:42,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30951 transitions. [2023-11-23 22:34:42,844 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2023-11-23 22:34:42,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:42,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:42,846 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:42,847 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:42,847 INFO L748 eck$LassoCheckResult]: Stem: 353957#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 353958#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 354583#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 354584#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 354685#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 354102#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 354103#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 354231#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 354232#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 354003#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 353789#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 353790#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 353965#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 353966#L781 assume !(0 == ~M_E~0); 354485#L781-2 assume !(0 == ~T1_E~0); 354699#L786-1 assume !(0 == ~T2_E~0); 353751#L791-1 assume !(0 == ~T3_E~0); 353752#L796-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 354312#L801-1 assume !(0 == ~T5_E~0); 354313#L806-1 assume !(0 == ~T6_E~0); 354671#L811-1 assume !(0 == ~T7_E~0); 354672#L816-1 assume !(0 == ~E_M~0); 354587#L821-1 assume !(0 == ~E_1~0); 354588#L826-1 assume !(0 == ~E_2~0); 354309#L831-1 assume !(0 == ~E_3~0); 354310#L836-1 assume !(0 == ~E_4~0); 354731#L841-1 assume !(0 == ~E_5~0); 353919#L846-1 assume !(0 == ~E_6~0); 353920#L851-1 assume !(0 == ~E_7~0); 354730#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 354610#L388 assume !(1 == ~m_pc~0); 354611#L388-2 is_master_triggered_~__retres1~0#1 := 0; 354729#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 354509#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 354510#L967 assume !(0 != activate_threads_~tmp~1#1); 354673#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 354674#L407 assume !(1 == ~t1_pc~0); 354684#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 353733#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 353734#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 353767#L975 assume !(0 != activate_threads_~tmp___0~0#1); 354605#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 354606#L426 assume !(1 == ~t2_pc~0); 354618#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 354619#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 354080#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 354081#L983 assume !(0 != activate_threads_~tmp___1~0#1); 354726#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 354725#L445 assume !(1 == ~t3_pc~0); 354700#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 354496#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 354497#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 354723#L991 assume !(0 != activate_threads_~tmp___2~0#1); 354722#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 354378#L464 assume !(1 == ~t4_pc~0); 353949#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 353950#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 354719#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 354718#L999 assume !(0 != activate_threads_~tmp___3~0#1); 354717#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 354374#L483 assume !(1 == ~t5_pc~0); 354375#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 354554#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 354555#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 354634#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 354635#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 354716#L502 assume !(1 == ~t6_pc~0); 353896#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 353897#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 354067#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 354068#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 354530#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 354531#L521 assume !(1 == ~t7_pc~0); 354573#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 353791#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 353792#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 354708#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 354535#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 354454#L869 assume !(1 == ~M_E~0); 354117#L869-2 assume !(1 == ~T1_E~0); 354118#L874-1 assume !(1 == ~T2_E~0); 354630#L879-1 assume !(1 == ~T3_E~0); 354631#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 353712#L889-1 assume !(1 == ~T5_E~0); 353713#L894-1 assume !(1 == ~T6_E~0); 353981#L899-1 assume !(1 == ~T7_E~0); 354405#L904-1 assume !(1 == ~E_M~0); 354142#L909-1 assume !(1 == ~E_1~0); 354143#L914-1 assume !(1 == ~E_2~0); 354334#L919-1 assume !(1 == ~E_3~0); 354056#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 353889#L929-1 assume !(1 == ~E_5~0); 353890#L934-1 assume !(1 == ~E_6~0); 354122#L939-1 assume !(1 == ~E_7~0); 354123#L944-1 assume { :end_inline_reset_delta_events } true; 354529#L1190-2 [2023-11-23 22:34:42,847 INFO L750 eck$LassoCheckResult]: Loop: 354529#L1190-2 assume !false; 367314#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 367310#L756-1 assume !false; 367306#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 367213#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 367199#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 367194#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 367186#L653 assume !(0 != eval_~tmp~0#1); 367187#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 371086#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 371084#L781-3 assume !(0 == ~M_E~0); 371083#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 371082#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 371081#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 371079#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 371078#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 371077#L806-3 assume !(0 == ~T6_E~0); 371076#L811-3 assume !(0 == ~T7_E~0); 371075#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 371074#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 371073#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 371072#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 371071#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 371070#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 371069#L846-3 assume !(0 == ~E_6~0); 371068#L851-3 assume !(0 == ~E_7~0); 371067#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371066#L388-27 assume 1 == ~m_pc~0; 371065#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 371063#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 371062#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 371061#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 371060#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 371059#L407-27 assume !(1 == ~t1_pc~0); 371058#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 371057#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 371056#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 371055#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 371054#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 371053#L426-27 assume !(1 == ~t2_pc~0); 371052#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 371050#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 371049#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 371048#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 371047#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 371046#L445-27 assume !(1 == ~t3_pc~0); 371045#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 371044#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 371043#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 371042#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 371041#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 371040#L464-27 assume !(1 == ~t4_pc~0); 371039#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 371037#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 371036#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 371035#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 371034#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 371033#L483-27 assume !(1 == ~t5_pc~0); 371032#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 371031#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 371030#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 371029#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 371028#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 371027#L502-27 assume !(1 == ~t6_pc~0); 371026#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 371025#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 371024#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 371023#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 371022#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 371021#L521-27 assume !(1 == ~t7_pc~0); 371020#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 371018#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 371016#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 371014#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 371012#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 371011#L869-3 assume !(1 == ~M_E~0); 361250#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 371010#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 371009#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 371007#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 371005#L889-3 assume !(1 == ~T5_E~0); 371002#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 371000#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 370998#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 370996#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 370994#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 370990#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 370988#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 370986#L929-3 assume !(1 == ~E_5~0); 370984#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 370981#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 370979#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 370972#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 370852#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 370666#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 361144#L1209 assume !(0 == start_simulation_~tmp~3#1); 361145#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 367367#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 367354#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 367349#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 367344#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 367336#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 367330#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 367325#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 354529#L1190-2 [2023-11-23 22:34:42,848 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:42,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2023-11-23 22:34:42,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:42,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482219192] [2023-11-23 22:34:42,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:42,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:42,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:42,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:42,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:42,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482219192] [2023-11-23 22:34:42,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [482219192] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:42,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:42,908 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:42,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830774997] [2023-11-23 22:34:42,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:42,908 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:42,909 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:42,909 INFO L85 PathProgramCache]: Analyzing trace with hash 576079457, now seen corresponding path program 1 times [2023-11-23 22:34:42,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:42,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975492755] [2023-11-23 22:34:42,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:42,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:42,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:42,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:42,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:42,952 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [975492755] [2023-11-23 22:34:42,953 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [975492755] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:42,953 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:42,953 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:42,953 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [126299380] [2023-11-23 22:34:42,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:42,954 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:42,954 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:42,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:34:42,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:34:42,955 INFO L87 Difference]: Start difference. First operand 21646 states and 30951 transitions. cyclomatic complexity: 9321 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:43,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:43,142 INFO L93 Difference]: Finished difference Result 28030 states and 39857 transitions. [2023-11-23 22:34:43,142 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28030 states and 39857 transitions. [2023-11-23 22:34:43,274 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27760 [2023-11-23 22:34:43,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28030 states to 28030 states and 39857 transitions. [2023-11-23 22:34:43,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28030 [2023-11-23 22:34:43,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28030 [2023-11-23 22:34:43,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28030 states and 39857 transitions. [2023-11-23 22:34:43,674 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:43,674 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28030 states and 39857 transitions. [2023-11-23 22:34:43,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28030 states and 39857 transitions. [2023-11-23 22:34:43,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28030 to 19206. [2023-11-23 22:34:43,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.42543996667708) internal successors, (27377), 19205 states have internal predecessors, (27377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:43,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27377 transitions. [2023-11-23 22:34:43,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27377 transitions. [2023-11-23 22:34:43,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:34:43,948 INFO L428 stractBuchiCegarLoop]: Abstraction has 19206 states and 27377 transitions. [2023-11-23 22:34:43,949 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-23 22:34:43,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27377 transitions. [2023-11-23 22:34:44,004 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2023-11-23 22:34:44,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:44,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:44,007 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:44,007 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:44,007 INFO L748 eck$LassoCheckResult]: Stem: 403643#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 403644#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 404243#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 404244#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 404315#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 403788#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 403789#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 403917#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 403918#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 403689#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 403473#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 403474#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 403648#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 403649#L781 assume !(0 == ~M_E~0); 404159#L781-2 assume !(0 == ~T1_E~0); 404333#L786-1 assume !(0 == ~T2_E~0); 403437#L791-1 assume !(0 == ~T3_E~0); 403438#L796-1 assume !(0 == ~T4_E~0); 403994#L801-1 assume !(0 == ~T5_E~0); 403995#L806-1 assume !(0 == ~T6_E~0); 404027#L811-1 assume !(0 == ~T7_E~0); 403655#L816-1 assume !(0 == ~E_M~0); 403656#L821-1 assume !(0 == ~E_1~0); 403465#L826-1 assume !(0 == ~E_2~0); 403466#L831-1 assume !(0 == ~E_3~0); 403783#L836-1 assume !(0 == ~E_4~0); 403784#L841-1 assume !(0 == ~E_5~0); 403605#L846-1 assume !(0 == ~E_6~0); 403606#L851-1 assume !(0 == ~E_7~0); 403629#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 403630#L388 assume !(1 == ~m_pc~0); 403623#L388-2 is_master_triggered_~__retres1~0#1 := 0; 403624#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 404134#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 403479#L967 assume !(0 != activate_threads_~tmp~1#1); 403480#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 403412#L407 assume !(1 == ~t1_pc~0); 403413#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 403419#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 403420#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 403453#L975 assume !(0 != activate_threads_~tmp___0~0#1); 404241#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 403743#L426 assume !(1 == ~t2_pc~0); 403744#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 404262#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 403766#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 403767#L983 assume !(0 != activate_threads_~tmp___1~0#1); 404301#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 403830#L445 assume !(1 == ~t3_pc~0); 403831#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 404167#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 403410#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 403411#L991 assume !(0 != activate_threads_~tmp___2~0#1); 404092#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 404055#L464 assume !(1 == ~t4_pc~0); 403633#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 403499#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 403500#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 403511#L999 assume !(0 != activate_threads_~tmp___3~0#1); 403810#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 403811#L483 assume !(1 == ~t5_pc~0); 404052#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 404219#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 404186#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 404187#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 403726#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 403727#L502 assume !(1 == ~t6_pc~0); 403581#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 403539#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 403540#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 403754#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 403957#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 404197#L521 assume !(1 == ~t7_pc~0); 404238#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 403475#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 403476#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 404230#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 404203#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 404126#L869 assume !(1 == ~M_E~0); 403804#L869-2 assume !(1 == ~T1_E~0); 403805#L874-1 assume !(1 == ~T2_E~0); 404273#L879-1 assume !(1 == ~T3_E~0); 403882#L884-1 assume !(1 == ~T4_E~0); 403398#L889-1 assume !(1 == ~T5_E~0); 403399#L894-1 assume !(1 == ~T6_E~0); 403666#L899-1 assume !(1 == ~T7_E~0); 404078#L904-1 assume !(1 == ~E_M~0); 403827#L909-1 assume !(1 == ~E_1~0); 403828#L914-1 assume !(1 == ~E_2~0); 404014#L919-1 assume !(1 == ~E_3~0); 403742#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 403574#L929-1 assume !(1 == ~E_5~0); 403575#L934-1 assume !(1 == ~E_6~0); 403808#L939-1 assume !(1 == ~E_7~0); 403809#L944-1 assume { :end_inline_reset_delta_events } true; 404196#L1190-2 [2023-11-23 22:34:44,008 INFO L750 eck$LassoCheckResult]: Loop: 404196#L1190-2 assume !false; 416789#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 416787#L756-1 assume !false; 416785#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 416783#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 416773#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 416771#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 416768#L653 assume !(0 != eval_~tmp~0#1); 416769#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 422049#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 422048#L781-3 assume !(0 == ~M_E~0); 422046#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 422044#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 422042#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 422039#L796-3 assume !(0 == ~T4_E~0); 422035#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 422032#L806-3 assume !(0 == ~T6_E~0); 422029#L811-3 assume !(0 == ~T7_E~0); 422026#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 422023#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 422020#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 422016#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 422013#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 422010#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 422007#L846-3 assume !(0 == ~E_6~0); 422004#L851-3 assume !(0 == ~E_7~0); 422001#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 421998#L388-27 assume !(1 == ~m_pc~0); 421994#L388-29 is_master_triggered_~__retres1~0#1 := 0; 421991#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 421988#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 421985#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 421982#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 421977#L407-27 assume !(1 == ~t1_pc~0); 421974#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 421971#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 421968#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 421965#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 421962#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 421958#L426-27 assume 1 == ~t2_pc~0; 421954#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 421951#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 421948#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 421945#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 421942#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 421938#L445-27 assume !(1 == ~t3_pc~0); 421935#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 421932#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 421929#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 421926#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 421923#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 421919#L464-27 assume 1 == ~t4_pc~0; 421914#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 421910#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 421906#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 421903#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 421900#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 421897#L483-27 assume !(1 == ~t5_pc~0); 421894#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 421891#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 421888#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 421885#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 421882#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 421878#L502-27 assume !(1 == ~t6_pc~0); 421875#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 421872#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 421869#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 421866#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 421863#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 421859#L521-27 assume 1 == ~t7_pc~0; 421854#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 421850#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 421848#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 421845#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 421843#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 421839#L869-3 assume !(1 == ~M_E~0); 411235#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 421826#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 421823#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 421821#L884-3 assume !(1 == ~T4_E~0); 421819#L889-3 assume !(1 == ~T5_E~0); 421818#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 421816#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 421814#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 421812#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 421810#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 421808#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 421806#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 421804#L929-3 assume !(1 == ~E_5~0); 421802#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 421800#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 421798#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 421791#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 421785#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 421782#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 411354#L1209 assume !(0 == start_simulation_~tmp~3#1); 411355#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 416875#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 416869#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 416867#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 416865#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 416863#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 416861#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 416859#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 404196#L1190-2 [2023-11-23 22:34:44,008 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:44,009 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2023-11-23 22:34:44,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:44,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82207652] [2023-11-23 22:34:44,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:44,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:44,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:44,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:44,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:44,076 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82207652] [2023-11-23 22:34:44,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [82207652] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:44,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:44,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:44,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [469858196] [2023-11-23 22:34:44,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:44,077 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:44,078 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:44,078 INFO L85 PathProgramCache]: Analyzing trace with hash -1105535779, now seen corresponding path program 1 times [2023-11-23 22:34:44,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:44,078 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827987284] [2023-11-23 22:34:44,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:44,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:44,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:44,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:44,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:44,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827987284] [2023-11-23 22:34:44,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [827987284] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:44,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:44,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:44,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1974862639] [2023-11-23 22:34:44,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:44,126 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:44,127 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:44,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:34:44,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:34:44,127 INFO L87 Difference]: Start difference. First operand 19206 states and 27377 transitions. cyclomatic complexity: 8187 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:44,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:44,382 INFO L93 Difference]: Finished difference Result 30510 states and 43007 transitions. [2023-11-23 22:34:44,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30510 states and 43007 transitions. [2023-11-23 22:34:44,856 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 30116 [2023-11-23 22:34:44,961 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30510 states to 30510 states and 43007 transitions. [2023-11-23 22:34:44,962 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30510 [2023-11-23 22:34:44,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30510 [2023-11-23 22:34:44,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30510 states and 43007 transitions. [2023-11-23 22:34:45,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:45,013 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30510 states and 43007 transitions. [2023-11-23 22:34:45,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30510 states and 43007 transitions. [2023-11-23 22:34:45,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30510 to 21646. [2023-11-23 22:34:45,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4149496442760787) internal successors, (30628), 21645 states have internal predecessors, (30628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:45,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30628 transitions. [2023-11-23 22:34:45,428 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30628 transitions. [2023-11-23 22:34:45,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:34:45,429 INFO L428 stractBuchiCegarLoop]: Abstraction has 21646 states and 30628 transitions. [2023-11-23 22:34:45,429 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-23 22:34:45,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30628 transitions. [2023-11-23 22:34:45,511 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2023-11-23 22:34:45,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:45,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:45,514 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:45,514 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:45,515 INFO L748 eck$LassoCheckResult]: Stem: 453366#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 453367#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 453976#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 453977#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 454075#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 453512#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 453513#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 453639#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 453640#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 453412#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 453200#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 453201#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 453371#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 453372#L781 assume !(0 == ~M_E~0); 453885#L781-2 assume !(0 == ~T1_E~0); 454090#L786-1 assume !(0 == ~T2_E~0); 453160#L791-1 assume !(0 == ~T3_E~0); 453161#L796-1 assume !(0 == ~T4_E~0); 453716#L801-1 assume !(0 == ~T5_E~0); 453717#L806-1 assume !(0 == ~T6_E~0); 453750#L811-1 assume !(0 == ~T7_E~0); 453377#L816-1 assume !(0 == ~E_M~0); 453378#L821-1 assume !(0 == ~E_1~0); 453191#L826-1 assume !(0 == ~E_2~0); 453192#L831-1 assume !(0 == ~E_3~0); 453506#L836-1 assume 0 == ~E_4~0;~E_4~0 := 1; 453507#L841-1 assume !(0 == ~E_5~0); 453330#L846-1 assume !(0 == ~E_6~0); 453331#L851-1 assume !(0 == ~E_7~0); 454151#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 453997#L388 assume !(1 == ~m_pc~0); 453998#L388-2 is_master_triggered_~__retres1~0#1 := 0; 454150#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 453910#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 453911#L967 assume !(0 != activate_threads_~tmp~1#1); 454065#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 454066#L407 assume !(1 == ~t1_pc~0); 454074#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 453142#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 453143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 453177#L975 assume !(0 != activate_threads_~tmp___0~0#1); 453993#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 453994#L426 assume !(1 == ~t2_pc~0); 454006#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 454007#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453488#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 453489#L983 assume !(0 != activate_threads_~tmp___1~0#1); 454147#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 454146#L445 assume !(1 == ~t3_pc~0); 454145#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 454144#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 453136#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 453137#L991 assume !(0 != activate_threads_~tmp___2~0#1); 453816#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 453890#L464 assume !(1 == ~t4_pc~0); 454140#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 454139#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 454138#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 454137#L999 assume !(0 != activate_threads_~tmp___3~0#1); 454136#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 454135#L483 assume !(1 == ~t5_pc~0); 454134#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 454133#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 454132#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 454131#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 454130#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 454129#L502 assume !(1 == ~t6_pc~0); 454128#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 454127#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 454126#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 454125#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 454124#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 454123#L521 assume !(1 == ~t7_pc~0); 454121#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 454119#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 454117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 454115#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 454114#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 454113#L869 assume !(1 == ~M_E~0); 454112#L869-2 assume !(1 == ~T1_E~0); 454111#L874-1 assume !(1 == ~T2_E~0); 454110#L879-1 assume !(1 == ~T3_E~0); 454109#L884-1 assume !(1 == ~T4_E~0); 454108#L889-1 assume !(1 == ~T5_E~0); 454107#L894-1 assume !(1 == ~T6_E~0); 454106#L899-1 assume !(1 == ~T7_E~0); 454105#L904-1 assume !(1 == ~E_M~0); 454104#L909-1 assume !(1 == ~E_1~0); 454103#L914-1 assume !(1 == ~E_2~0); 454102#L919-1 assume !(1 == ~E_3~0); 454101#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 453298#L929-1 assume !(1 == ~E_5~0); 453299#L934-1 assume !(1 == ~E_6~0); 453529#L939-1 assume !(1 == ~E_7~0); 453530#L944-1 assume { :end_inline_reset_delta_events } true; 453929#L1190-2 [2023-11-23 22:34:45,515 INFO L750 eck$LassoCheckResult]: Loop: 453929#L1190-2 assume !false; 459854#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 459852#L756-1 assume !false; 459850#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 459848#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 459839#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 459837#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 459834#L653 assume !(0 != eval_~tmp~0#1); 459832#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 459830#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 459828#L781-3 assume !(0 == ~M_E~0); 459826#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 459824#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 459822#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 459820#L796-3 assume !(0 == ~T4_E~0); 459818#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 459816#L806-3 assume !(0 == ~T6_E~0); 459812#L811-3 assume !(0 == ~T7_E~0); 459810#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 459808#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 459806#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 459803#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 459800#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 459799#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 459798#L846-3 assume !(0 == ~E_6~0); 459797#L851-3 assume !(0 == ~E_7~0); 459796#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 459795#L388-27 assume 1 == ~m_pc~0; 459794#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 459792#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 459791#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 459790#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 459789#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 459788#L407-27 assume !(1 == ~t1_pc~0); 459787#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 459786#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 459785#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 459784#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 459783#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 459782#L426-27 assume !(1 == ~t2_pc~0); 459781#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 459779#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 459778#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 459777#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 459776#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 459775#L445-27 assume !(1 == ~t3_pc~0); 459774#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 459773#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 459772#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 459771#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 459770#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 459769#L464-27 assume 1 == ~t4_pc~0; 459766#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 459765#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 459764#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 459763#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 459762#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 459761#L483-27 assume !(1 == ~t5_pc~0); 459760#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 459759#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 459758#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 459757#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 459756#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 459755#L502-27 assume !(1 == ~t6_pc~0); 459754#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 459753#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 459752#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 459751#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 459750#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 459749#L521-27 assume !(1 == ~t7_pc~0); 459748#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 459746#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 459744#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 459742#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 459740#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 459739#L869-3 assume !(1 == ~M_E~0); 457862#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 459738#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 459737#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 459736#L884-3 assume !(1 == ~T4_E~0); 459735#L889-3 assume !(1 == ~T5_E~0); 459734#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 459733#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 459732#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 459731#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 459730#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 459729#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 459727#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 459725#L929-3 assume !(1 == ~E_5~0); 459723#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 459721#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 459719#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 459709#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 459703#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 459153#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 458325#L1209 assume !(0 == start_simulation_~tmp~3#1); 458326#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 460145#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 460140#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 460139#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 460138#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 460137#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 460136#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 460135#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 453929#L1190-2 [2023-11-23 22:34:45,516 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:45,516 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2023-11-23 22:34:45,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:45,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256994586] [2023-11-23 22:34:45,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:45,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:45,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:45,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:45,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:45,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256994586] [2023-11-23 22:34:45,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1256994586] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:45,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:45,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:45,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [728214544] [2023-11-23 22:34:45,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:45,593 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:45,593 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:45,593 INFO L85 PathProgramCache]: Analyzing trace with hash -1427497504, now seen corresponding path program 1 times [2023-11-23 22:34:45,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:45,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675088019] [2023-11-23 22:34:45,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:45,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:45,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:45,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:45,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:45,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675088019] [2023-11-23 22:34:45,660 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [675088019] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:45,661 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:45,661 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:45,661 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1293420532] [2023-11-23 22:34:45,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:45,663 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:45,663 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:45,664 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:34:45,664 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:34:45,664 INFO L87 Difference]: Start difference. First operand 21646 states and 30628 transitions. cyclomatic complexity: 8998 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:45,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:45,921 INFO L93 Difference]: Finished difference Result 27562 states and 38762 transitions. [2023-11-23 22:34:45,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27562 states and 38762 transitions. [2023-11-23 22:34:46,075 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27284 [2023-11-23 22:34:46,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27562 states to 27562 states and 38762 transitions. [2023-11-23 22:34:46,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27562 [2023-11-23 22:34:46,194 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27562 [2023-11-23 22:34:46,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27562 states and 38762 transitions. [2023-11-23 22:34:46,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:46,216 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27562 states and 38762 transitions. [2023-11-23 22:34:46,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27562 states and 38762 transitions. [2023-11-23 22:34:46,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27562 to 19206. [2023-11-23 22:34:46,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.408622305529522) internal successors, (27054), 19205 states have internal predecessors, (27054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:46,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27054 transitions. [2023-11-23 22:34:46,820 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27054 transitions. [2023-11-23 22:34:46,824 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:34:46,825 INFO L428 stractBuchiCegarLoop]: Abstraction has 19206 states and 27054 transitions. [2023-11-23 22:34:46,825 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-23 22:34:46,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27054 transitions. [2023-11-23 22:34:46,883 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2023-11-23 22:34:46,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:46,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:46,886 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:46,886 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:46,886 INFO L748 eck$LassoCheckResult]: Stem: 502584#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 502585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 503202#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 503203#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 503280#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 502729#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 502730#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 502855#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 502856#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 502629#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 502419#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 502420#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 502589#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 502590#L781 assume !(0 == ~M_E~0); 503107#L781-2 assume !(0 == ~T1_E~0); 503292#L786-1 assume !(0 == ~T2_E~0); 502379#L791-1 assume !(0 == ~T3_E~0); 502380#L796-1 assume !(0 == ~T4_E~0); 502935#L801-1 assume !(0 == ~T5_E~0); 502936#L806-1 assume !(0 == ~T6_E~0); 502968#L811-1 assume !(0 == ~T7_E~0); 502595#L816-1 assume !(0 == ~E_M~0); 502596#L821-1 assume !(0 == ~E_1~0); 502410#L826-1 assume !(0 == ~E_2~0); 502411#L831-1 assume !(0 == ~E_3~0); 502724#L836-1 assume !(0 == ~E_4~0); 502725#L841-1 assume !(0 == ~E_5~0); 502548#L846-1 assume !(0 == ~E_6~0); 502549#L851-1 assume !(0 == ~E_7~0); 502571#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 502572#L388 assume !(1 == ~m_pc~0); 502565#L388-2 is_master_triggered_~__retres1~0#1 := 0; 502566#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 503081#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 502425#L967 assume !(0 != activate_threads_~tmp~1#1); 502426#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 502356#L407 assume !(1 == ~t1_pc~0); 502357#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 502360#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 502361#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 502396#L975 assume !(0 != activate_threads_~tmp___0~0#1); 503200#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 502682#L426 assume !(1 == ~t2_pc~0); 502683#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 503226#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 502706#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 502707#L983 assume !(0 != activate_threads_~tmp___1~0#1); 503267#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 502769#L445 assume !(1 == ~t3_pc~0); 502770#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 503116#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 502354#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 502355#L991 assume !(0 != activate_threads_~tmp___2~0#1); 503035#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 502996#L464 assume !(1 == ~t4_pc~0); 502575#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 502445#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 502446#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 502457#L999 assume !(0 != activate_threads_~tmp___3~0#1); 502749#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 502750#L483 assume !(1 == ~t5_pc~0); 502993#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 503176#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 503138#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 503139#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 502667#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 502668#L502 assume !(1 == ~t6_pc~0); 502525#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 502484#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 502485#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 502693#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 502893#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 503153#L521 assume !(1 == ~t7_pc~0); 503197#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 502421#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 502422#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 503190#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 503157#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 503068#L869 assume !(1 == ~M_E~0); 502743#L869-2 assume !(1 == ~T1_E~0); 502744#L874-1 assume !(1 == ~T2_E~0); 503239#L879-1 assume !(1 == ~T3_E~0); 502819#L884-1 assume !(1 == ~T4_E~0); 502342#L889-1 assume !(1 == ~T5_E~0); 502343#L894-1 assume !(1 == ~T6_E~0); 502603#L899-1 assume !(1 == ~T7_E~0); 503023#L904-1 assume !(1 == ~E_M~0); 502766#L909-1 assume !(1 == ~E_1~0); 502767#L914-1 assume !(1 == ~E_2~0); 502954#L919-1 assume !(1 == ~E_3~0); 502681#L924-1 assume !(1 == ~E_4~0); 502518#L929-1 assume !(1 == ~E_5~0); 502519#L934-1 assume !(1 == ~E_6~0); 502745#L939-1 assume !(1 == ~E_7~0); 502746#L944-1 assume { :end_inline_reset_delta_events } true; 503152#L1190-2 [2023-11-23 22:34:46,887 INFO L750 eck$LassoCheckResult]: Loop: 503152#L1190-2 assume !false; 509116#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 509114#L756-1 assume !false; 509112#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 509109#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 509100#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 509098#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 509095#L653 assume !(0 != eval_~tmp~0#1); 509093#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 509091#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 509089#L781-3 assume !(0 == ~M_E~0); 509087#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 509085#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 509083#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 509028#L796-3 assume !(0 == ~T4_E~0); 509023#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 509018#L806-3 assume !(0 == ~T6_E~0); 509012#L811-3 assume !(0 == ~T7_E~0); 509007#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 509002#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 508997#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 508991#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 508985#L836-3 assume !(0 == ~E_4~0); 508980#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 508975#L846-3 assume !(0 == ~E_6~0); 508969#L851-3 assume !(0 == ~E_7~0); 508964#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 508959#L388-27 assume 1 == ~m_pc~0; 508954#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 508948#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 508943#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 508937#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 508932#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 508926#L407-27 assume !(1 == ~t1_pc~0); 508920#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 508915#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 508910#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 508904#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 508898#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508893#L426-27 assume 1 == ~t2_pc~0; 508887#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 508882#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 508877#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 508872#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 508865#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 508859#L445-27 assume !(1 == ~t3_pc~0); 508854#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 508849#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508843#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 508838#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 508832#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 508826#L464-27 assume !(1 == ~t4_pc~0); 508820#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 508815#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 508810#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 508804#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 508799#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 508794#L483-27 assume !(1 == ~t5_pc~0); 508788#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 508783#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 508778#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 508772#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 508767#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508761#L502-27 assume !(1 == ~t6_pc~0); 508754#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 508747#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 508740#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 508733#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 508727#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 508722#L521-27 assume !(1 == ~t7_pc~0); 508717#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 508711#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 508705#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 508700#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 508694#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508689#L869-3 assume !(1 == ~M_E~0); 508418#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 508680#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 508675#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 508670#L884-3 assume !(1 == ~T4_E~0); 508664#L889-3 assume !(1 == ~T5_E~0); 508658#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 508653#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 508648#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 508644#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 508565#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 508564#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 508563#L924-3 assume !(1 == ~E_4~0); 508562#L929-3 assume !(1 == ~E_5~0); 508561#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 508560#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 508559#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 508529#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 508521#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 508519#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 508473#L1209 assume !(0 == start_simulation_~tmp~3#1); 508474#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 509153#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 509140#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 509138#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 509136#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 509134#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 509132#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 509130#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 503152#L1190-2 [2023-11-23 22:34:46,888 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:46,888 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2023-11-23 22:34:46,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:46,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229216169] [2023-11-23 22:34:46,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:46,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:46,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:46,903 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:34:46,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:46,968 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:34:46,969 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:46,969 INFO L85 PathProgramCache]: Analyzing trace with hash -2100508768, now seen corresponding path program 1 times [2023-11-23 22:34:46,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:46,969 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063076634] [2023-11-23 22:34:46,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:46,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:46,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:47,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:47,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:47,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1063076634] [2023-11-23 22:34:47,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1063076634] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:47,011 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:47,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:47,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809668695] [2023-11-23 22:34:47,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:47,012 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:47,012 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:47,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:47,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:47,013 INFO L87 Difference]: Start difference. First operand 19206 states and 27054 transitions. cyclomatic complexity: 7864 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:47,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:47,127 INFO L93 Difference]: Finished difference Result 21646 states and 30463 transitions. [2023-11-23 22:34:47,128 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21646 states and 30463 transitions. [2023-11-23 22:34:47,218 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2023-11-23 22:34:47,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21646 states to 21646 states and 30463 transitions. [2023-11-23 22:34:47,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21646 [2023-11-23 22:34:47,274 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21646 [2023-11-23 22:34:47,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21646 states and 30463 transitions. [2023-11-23 22:34:47,287 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:47,287 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30463 transitions. [2023-11-23 22:34:47,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21646 states and 30463 transitions. [2023-11-23 22:34:47,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21646 to 21646. [2023-11-23 22:34:47,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4073269888201054) internal successors, (30463), 21645 states have internal predecessors, (30463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:47,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30463 transitions. [2023-11-23 22:34:47,566 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30463 transitions. [2023-11-23 22:34:47,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:47,567 INFO L428 stractBuchiCegarLoop]: Abstraction has 21646 states and 30463 transitions. [2023-11-23 22:34:47,567 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-23 22:34:47,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30463 transitions. [2023-11-23 22:34:47,631 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2023-11-23 22:34:47,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:47,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:47,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:47,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:47,635 INFO L748 eck$LassoCheckResult]: Stem: 543444#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 543445#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 544078#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 544079#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 544177#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 543593#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 543594#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 543723#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 543724#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 543492#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 543276#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 543277#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 543452#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 543453#L781 assume !(0 == ~M_E~0); 543981#L781-2 assume !(0 == ~T1_E~0); 544196#L786-1 assume !(0 == ~T2_E~0); 543239#L791-1 assume !(0 == ~T3_E~0); 543240#L796-1 assume !(0 == ~T4_E~0); 543807#L801-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 543808#L806-1 assume !(0 == ~T6_E~0); 543841#L811-1 assume !(0 == ~T7_E~0); 543456#L816-1 assume !(0 == ~E_M~0); 543457#L821-1 assume !(0 == ~E_1~0); 543267#L826-1 assume !(0 == ~E_2~0); 543268#L831-1 assume !(0 == ~E_3~0); 544237#L836-1 assume !(0 == ~E_4~0); 544236#L841-1 assume !(0 == ~E_5~0); 544235#L846-1 assume !(0 == ~E_6~0); 544186#L851-1 assume !(0 == ~E_7~0); 543429#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 543430#L388 assume !(1 == ~m_pc~0); 543423#L388-2 is_master_triggered_~__retres1~0#1 := 0; 543424#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 543956#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 543282#L967 assume !(0 != activate_threads_~tmp~1#1); 543283#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 543214#L407 assume !(1 == ~t1_pc~0); 543215#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 544232#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 544231#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 544073#L975 assume !(0 != activate_threads_~tmp___0~0#1); 544074#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 543545#L426 assume !(1 == ~t2_pc~0); 543546#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 544161#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 543569#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 543570#L983 assume !(0 != activate_threads_~tmp___1~0#1); 544229#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 544228#L445 assume !(1 == ~t3_pc~0); 544227#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 544226#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 543212#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 543213#L991 assume !(0 != activate_threads_~tmp___2~0#1); 543909#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 543988#L464 assume !(1 == ~t4_pc~0); 544222#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 543302#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 543303#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 543318#L999 assume !(0 != activate_threads_~tmp___3~0#1); 543613#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 543614#L483 assume !(1 == ~t5_pc~0); 543868#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 544048#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 544049#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 544136#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 544137#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 544217#L502 assume !(1 == ~t6_pc~0); 543383#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 543384#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 544215#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 544214#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 544213#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 544212#L521 assume !(1 == ~t7_pc~0); 544118#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 544119#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 544216#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 544207#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 544206#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 544205#L869 assume !(1 == ~M_E~0); 544204#L869-2 assume !(1 == ~T1_E~0); 544203#L874-1 assume !(1 == ~T2_E~0); 544202#L879-1 assume !(1 == ~T3_E~0); 544201#L884-1 assume !(1 == ~T4_E~0); 543200#L889-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 543201#L894-1 assume !(1 == ~T6_E~0); 543468#L899-1 assume !(1 == ~T7_E~0); 543899#L904-1 assume !(1 == ~E_M~0); 543632#L909-1 assume !(1 == ~E_1~0); 543633#L914-1 assume !(1 == ~E_2~0); 543828#L919-1 assume !(1 == ~E_3~0); 543544#L924-1 assume !(1 == ~E_4~0); 543376#L929-1 assume !(1 == ~E_5~0); 543377#L934-1 assume !(1 == ~E_6~0); 543611#L939-1 assume !(1 == ~E_7~0); 543612#L944-1 assume { :end_inline_reset_delta_events } true; 544027#L1190-2 [2023-11-23 22:34:47,635 INFO L750 eck$LassoCheckResult]: Loop: 544027#L1190-2 assume !false; 547920#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 547918#L756-1 assume !false; 547916#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 547914#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 547905#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 547902#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 547899#L653 assume !(0 != eval_~tmp~0#1); 547900#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 548908#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 548907#L781-3 assume !(0 == ~M_E~0); 548906#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 548905#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 548904#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 548902#L796-3 assume !(0 == ~T4_E~0); 548898#L801-3 assume !(0 == ~T5_E~0); 548896#L806-3 assume !(0 == ~T6_E~0); 548894#L811-3 assume !(0 == ~T7_E~0); 548892#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 548890#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 548888#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 548886#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 548884#L836-3 assume !(0 == ~E_4~0); 548882#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 548880#L846-3 assume !(0 == ~E_6~0); 548878#L851-3 assume !(0 == ~E_7~0); 548876#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 548873#L388-27 assume !(1 == ~m_pc~0); 548870#L388-29 is_master_triggered_~__retres1~0#1 := 0; 548868#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 548866#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 548864#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 548862#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 548860#L407-27 assume !(1 == ~t1_pc~0); 548858#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 548856#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 548854#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 548852#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 548849#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 548847#L426-27 assume 1 == ~t2_pc~0; 548844#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 548842#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 548840#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 548838#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 548836#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 548833#L445-27 assume !(1 == ~t3_pc~0); 548831#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 548829#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 548827#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 548825#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 548823#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 548821#L464-27 assume !(1 == ~t4_pc~0); 548818#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 548816#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 548814#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 548812#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 548808#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 548806#L483-27 assume !(1 == ~t5_pc~0); 548804#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 548802#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 548799#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 548797#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 548796#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 548792#L502-27 assume !(1 == ~t6_pc~0); 548790#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 548788#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 548787#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 548784#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 548783#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 548782#L521-27 assume !(1 == ~t7_pc~0); 548779#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 548777#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 548776#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 548775#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 548773#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 548772#L869-3 assume !(1 == ~M_E~0); 548230#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 548770#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 548769#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 548768#L884-3 assume !(1 == ~T4_E~0); 548523#L889-3 assume !(1 == ~T5_E~0); 548521#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 548519#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 548517#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 548515#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 548512#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 548510#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 548508#L924-3 assume !(1 == ~E_4~0); 548506#L929-3 assume !(1 == ~E_5~0); 548504#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 548502#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 548500#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 548487#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 548481#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 548478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 548475#L1209 assume !(0 == start_simulation_~tmp~3#1); 548476#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 548600#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 548594#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 548592#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 548590#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 548588#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 548585#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 548583#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 544027#L1190-2 [2023-11-23 22:34:47,636 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:47,636 INFO L85 PathProgramCache]: Analyzing trace with hash 1343517957, now seen corresponding path program 1 times [2023-11-23 22:34:47,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:47,636 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156919296] [2023-11-23 22:34:47,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:47,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:47,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:47,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:47,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:47,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156919296] [2023-11-23 22:34:47,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156919296] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:47,702 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:47,702 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:47,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906067829] [2023-11-23 22:34:47,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:47,703 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:47,703 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:47,703 INFO L85 PathProgramCache]: Analyzing trace with hash -418588829, now seen corresponding path program 1 times [2023-11-23 22:34:47,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:47,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003531394] [2023-11-23 22:34:47,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:47,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:47,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:47,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:47,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:47,762 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003531394] [2023-11-23 22:34:47,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1003531394] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:47,763 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:47,763 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:47,763 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694199617] [2023-11-23 22:34:47,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:47,764 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:47,764 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:47,764 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:34:47,764 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:34:47,765 INFO L87 Difference]: Start difference. First operand 21646 states and 30463 transitions. cyclomatic complexity: 8833 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:47,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:47,943 INFO L93 Difference]: Finished difference Result 28041 states and 39369 transitions. [2023-11-23 22:34:47,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28041 states and 39369 transitions. [2023-11-23 22:34:48,356 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27760 [2023-11-23 22:34:48,456 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28041 states to 28041 states and 39369 transitions. [2023-11-23 22:34:48,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28041 [2023-11-23 22:34:48,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28041 [2023-11-23 22:34:48,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28041 states and 39369 transitions. [2023-11-23 22:34:48,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:48,486 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28041 states and 39369 transitions. [2023-11-23 22:34:48,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28041 states and 39369 transitions. [2023-11-23 22:34:48,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28041 to 19206. [2023-11-23 22:34:48,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.4069040924711027) internal successors, (27021), 19205 states have internal predecessors, (27021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:48,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27021 transitions. [2023-11-23 22:34:48,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27021 transitions. [2023-11-23 22:34:48,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:34:48,746 INFO L428 stractBuchiCegarLoop]: Abstraction has 19206 states and 27021 transitions. [2023-11-23 22:34:48,746 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-23 22:34:48,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27021 transitions. [2023-11-23 22:34:48,808 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2023-11-23 22:34:48,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:48,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:48,812 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:48,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:48,812 INFO L748 eck$LassoCheckResult]: Stem: 593136#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 593137#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 593723#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 593724#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 593798#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 593279#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 593280#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 593411#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 593412#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 593182#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 592973#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 592974#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 593141#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 593142#L781 assume !(0 == ~M_E~0); 593647#L781-2 assume !(0 == ~T1_E~0); 593813#L786-1 assume !(0 == ~T2_E~0); 592934#L791-1 assume !(0 == ~T3_E~0); 592935#L796-1 assume !(0 == ~T4_E~0); 593485#L801-1 assume !(0 == ~T5_E~0); 593486#L806-1 assume !(0 == ~T6_E~0); 593516#L811-1 assume !(0 == ~T7_E~0); 593147#L816-1 assume !(0 == ~E_M~0); 593148#L821-1 assume !(0 == ~E_1~0); 592965#L826-1 assume !(0 == ~E_2~0); 592966#L831-1 assume !(0 == ~E_3~0); 593274#L836-1 assume !(0 == ~E_4~0); 593275#L841-1 assume !(0 == ~E_5~0); 593100#L846-1 assume !(0 == ~E_6~0); 593101#L851-1 assume !(0 == ~E_7~0); 593123#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 593124#L388 assume !(1 == ~m_pc~0); 593117#L388-2 is_master_triggered_~__retres1~0#1 := 0; 593118#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 593621#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 592979#L967 assume !(0 != activate_threads_~tmp~1#1); 592980#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 592911#L407 assume !(1 == ~t1_pc~0); 592912#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 592918#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 592919#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 592953#L975 assume !(0 != activate_threads_~tmp___0~0#1); 593721#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 593236#L426 assume !(1 == ~t2_pc~0); 593237#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 593746#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 593257#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 593258#L983 assume !(0 != activate_threads_~tmp___1~0#1); 593789#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 593323#L445 assume !(1 == ~t3_pc~0); 593324#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 593653#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 592909#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 592910#L991 assume !(0 != activate_threads_~tmp___2~0#1); 593579#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 593544#L464 assume !(1 == ~t4_pc~0); 593127#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 592999#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 593000#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 593011#L999 assume !(0 != activate_threads_~tmp___3~0#1); 593302#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 593303#L483 assume !(1 == ~t5_pc~0); 593541#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 593701#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 593669#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 593670#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 593219#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 593220#L502 assume !(1 == ~t6_pc~0); 593078#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 593038#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 593039#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 593244#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 593451#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 593680#L521 assume !(1 == ~t7_pc~0); 593718#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 593749#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 593819#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 593712#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 593684#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 593611#L869 assume !(1 == ~M_E~0); 593295#L869-2 assume !(1 == ~T1_E~0); 593296#L874-1 assume !(1 == ~T2_E~0); 593758#L879-1 assume !(1 == ~T3_E~0); 593376#L884-1 assume !(1 == ~T4_E~0); 592897#L889-1 assume !(1 == ~T5_E~0); 592898#L894-1 assume !(1 == ~T6_E~0); 593158#L899-1 assume !(1 == ~T7_E~0); 593566#L904-1 assume !(1 == ~E_M~0); 593320#L909-1 assume !(1 == ~E_1~0); 593321#L914-1 assume !(1 == ~E_2~0); 593503#L919-1 assume !(1 == ~E_3~0); 593235#L924-1 assume !(1 == ~E_4~0); 593071#L929-1 assume !(1 == ~E_5~0); 593072#L934-1 assume !(1 == ~E_6~0); 593300#L939-1 assume !(1 == ~E_7~0); 593301#L944-1 assume { :end_inline_reset_delta_events } true; 593679#L1190-2 [2023-11-23 22:34:48,813 INFO L750 eck$LassoCheckResult]: Loop: 593679#L1190-2 assume !false; 602943#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 602941#L756-1 assume !false; 602940#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 602376#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 599719#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 599716#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 599713#L653 assume !(0 != eval_~tmp~0#1); 599711#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 599709#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 599707#L781-3 assume !(0 == ~M_E~0); 599705#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 599702#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 599700#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 599698#L796-3 assume !(0 == ~T4_E~0); 599696#L801-3 assume !(0 == ~T5_E~0); 599694#L806-3 assume !(0 == ~T6_E~0); 599691#L811-3 assume !(0 == ~T7_E~0); 599689#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 599687#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 599685#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 599683#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 599681#L836-3 assume !(0 == ~E_4~0); 599679#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 599676#L846-3 assume !(0 == ~E_6~0); 599674#L851-3 assume !(0 == ~E_7~0); 599672#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 599670#L388-27 assume !(1 == ~m_pc~0); 599667#L388-29 is_master_triggered_~__retres1~0#1 := 0; 599665#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 599663#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 599661#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 599659#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 599657#L407-27 assume !(1 == ~t1_pc~0); 599655#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 599653#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 599650#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 599648#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 599646#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 599645#L426-27 assume 1 == ~t2_pc~0; 599643#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 599642#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 599640#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 599639#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 599638#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 599634#L445-27 assume !(1 == ~t3_pc~0); 599632#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 599630#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 599628#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 599047#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 599038#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 599036#L464-27 assume !(1 == ~t4_pc~0); 599033#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 599030#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 599028#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 599026#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 599024#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 599022#L483-27 assume !(1 == ~t5_pc~0); 599020#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 599018#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 599016#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 599014#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 599012#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 599010#L502-27 assume !(1 == ~t6_pc~0); 599008#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 599006#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 599004#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 599002#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 599000#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 598998#L521-27 assume !(1 == ~t7_pc~0); 598994#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 598992#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 598990#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 598988#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 598984#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 598982#L869-3 assume !(1 == ~M_E~0); 596138#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 598979#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 598977#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 598975#L884-3 assume !(1 == ~T4_E~0); 598973#L889-3 assume !(1 == ~T5_E~0); 598971#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 598969#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 598967#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 598965#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 598963#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 598755#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 598740#L924-3 assume !(1 == ~E_4~0); 598733#L929-3 assume !(1 == ~E_5~0); 598728#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 598665#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 598661#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 598648#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 598639#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 598634#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 596241#L1209 assume !(0 == start_simulation_~tmp~3#1); 596242#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 603169#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 603163#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 603161#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 603159#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 603156#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 603154#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 603150#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 593679#L1190-2 [2023-11-23 22:34:48,813 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:48,813 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2023-11-23 22:34:48,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:48,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495420536] [2023-11-23 22:34:48,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:48,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:48,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:48,829 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:34:48,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:48,888 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:34:48,889 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:48,889 INFO L85 PathProgramCache]: Analyzing trace with hash -418588829, now seen corresponding path program 2 times [2023-11-23 22:34:48,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:48,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718336113] [2023-11-23 22:34:48,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:48,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:48,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:48,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:48,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:48,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718336113] [2023-11-23 22:34:48,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1718336113] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:48,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:48,936 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:48,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [616211252] [2023-11-23 22:34:48,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:48,937 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:48,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:48,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:48,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:48,938 INFO L87 Difference]: Start difference. First operand 19206 states and 27021 transitions. cyclomatic complexity: 7831 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:49,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:49,128 INFO L93 Difference]: Finished difference Result 28778 states and 40307 transitions. [2023-11-23 22:34:49,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28778 states and 40307 transitions. [2023-11-23 22:34:49,251 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28452 [2023-11-23 22:34:49,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28778 states to 28778 states and 40307 transitions. [2023-11-23 22:34:49,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28778 [2023-11-23 22:34:49,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28778 [2023-11-23 22:34:49,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28778 states and 40307 transitions. [2023-11-23 22:34:49,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:49,350 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28778 states and 40307 transitions. [2023-11-23 22:34:49,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28778 states and 40307 transitions. [2023-11-23 22:34:49,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28778 to 28762. [2023-11-23 22:34:49,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28762 states, 28762 states have (on average 1.400841387942424) internal successors, (40291), 28761 states have internal predecessors, (40291), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:50,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28762 states to 28762 states and 40291 transitions. [2023-11-23 22:34:50,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28762 states and 40291 transitions. [2023-11-23 22:34:50,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:50,026 INFO L428 stractBuchiCegarLoop]: Abstraction has 28762 states and 40291 transitions. [2023-11-23 22:34:50,026 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-23 22:34:50,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28762 states and 40291 transitions. [2023-11-23 22:34:50,096 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28436 [2023-11-23 22:34:50,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:50,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:50,098 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:50,098 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:50,098 INFO L748 eck$LassoCheckResult]: Stem: 641131#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 641132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 641768#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 641769#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 641860#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 641277#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 641278#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 641413#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 641414#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 641177#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 640964#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 640965#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 641136#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 641137#L781 assume !(0 == ~M_E~0); 641671#L781-2 assume !(0 == ~T1_E~0); 641874#L786-1 assume !(0 == ~T2_E~0); 640924#L791-1 assume !(0 == ~T3_E~0); 640925#L796-1 assume !(0 == ~T4_E~0); 641497#L801-1 assume !(0 == ~T5_E~0); 641498#L806-1 assume !(0 == ~T6_E~0); 641529#L811-1 assume !(0 == ~T7_E~0); 641142#L816-1 assume !(0 == ~E_M~0); 641143#L821-1 assume !(0 == ~E_1~0); 640955#L826-1 assume !(0 == ~E_2~0); 640956#L831-1 assume !(0 == ~E_3~0); 641272#L836-1 assume !(0 == ~E_4~0); 641273#L841-1 assume 0 == ~E_5~0;~E_5~0 := 1; 641094#L846-1 assume !(0 == ~E_6~0); 641095#L851-1 assume !(0 == ~E_7~0); 641917#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 641793#L388 assume !(1 == ~m_pc~0); 641794#L388-2 is_master_triggered_~__retres1~0#1 := 0; 641916#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 641697#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 641698#L967 assume !(0 != activate_threads_~tmp~1#1); 641854#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 641855#L407 assume !(1 == ~t1_pc~0); 641859#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 640905#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 640906#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 640941#L975 assume !(0 != activate_threads_~tmp___0~0#1); 641788#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 641789#L426 assume !(1 == ~t2_pc~0); 641799#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 641800#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 641913#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 641847#L983 assume !(0 != activate_threads_~tmp___1~0#1); 641848#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 641320#L445 assume !(1 == ~t3_pc~0); 641321#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 641910#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 640899#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 640900#L991 assume !(0 != activate_threads_~tmp___2~0#1); 641597#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 641561#L464 assume !(1 == ~t4_pc~0); 641122#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 641123#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 641904#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 641903#L999 assume !(0 != activate_threads_~tmp___3~0#1); 641902#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 641557#L483 assume !(1 == ~t5_pc~0); 641558#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 641740#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 641741#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 641822#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 641823#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 641901#L502 assume !(1 == ~t6_pc~0); 641071#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 641072#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 641241#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 641242#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 641717#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 641718#L521 assume !(1 == ~t7_pc~0); 641762#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 640966#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 640967#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 641753#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 641754#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 641899#L869 assume !(1 == ~M_E~0); 641898#L869-2 assume !(1 == ~T1_E~0); 641843#L874-1 assume !(1 == ~T2_E~0); 641844#L879-1 assume !(1 == ~T3_E~0); 641375#L884-1 assume !(1 == ~T4_E~0); 641376#L889-1 assume !(1 == ~T5_E~0); 641151#L894-1 assume !(1 == ~T6_E~0); 641152#L899-1 assume !(1 == ~T7_E~0); 641585#L904-1 assume !(1 == ~E_M~0); 641317#L909-1 assume !(1 == ~E_1~0); 641318#L914-1 assume !(1 == ~E_2~0); 641538#L919-1 assume !(1 == ~E_3~0); 641232#L924-1 assume !(1 == ~E_4~0); 641064#L929-1 assume 1 == ~E_5~0;~E_5~0 := 2; 641065#L934-1 assume !(1 == ~E_6~0); 641295#L939-1 assume !(1 == ~E_7~0); 641296#L944-1 assume { :end_inline_reset_delta_events } true; 641716#L1190-2 [2023-11-23 22:34:50,099 INFO L750 eck$LassoCheckResult]: Loop: 641716#L1190-2 assume !false; 656419#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 656411#L756-1 assume !false; 656405#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 656235#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 656226#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 656224#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 656222#L653 assume !(0 != eval_~tmp~0#1); 656221#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 656220#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 656218#L781-3 assume !(0 == ~M_E~0); 656216#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 656214#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 656211#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 656209#L796-3 assume !(0 == ~T4_E~0); 656207#L801-3 assume !(0 == ~T5_E~0); 656205#L806-3 assume !(0 == ~T6_E~0); 656203#L811-3 assume !(0 == ~T7_E~0); 656201#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 656129#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 656114#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 656106#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 656097#L836-3 assume !(0 == ~E_4~0); 656088#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 656089#L846-3 assume !(0 == ~E_6~0); 656219#L851-3 assume !(0 == ~E_7~0); 656217#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 656215#L388-27 assume !(1 == ~m_pc~0); 656212#L388-29 is_master_triggered_~__retres1~0#1 := 0; 656210#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 656208#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 656206#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 656204#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 656202#L407-27 assume !(1 == ~t1_pc~0); 656200#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 656128#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 656113#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 656105#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 656096#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 656087#L426-27 assume 1 == ~t2_pc~0; 656078#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 656071#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 656063#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 656056#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 656048#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 656041#L445-27 assume !(1 == ~t3_pc~0); 656034#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 656027#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 656020#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 656014#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 656009#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 656000#L464-27 assume !(1 == ~t4_pc~0); 655997#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 655995#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 655993#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 655991#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 655988#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 655986#L483-27 assume !(1 == ~t5_pc~0); 655984#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 655982#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 655980#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 655978#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 655976#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 655974#L502-27 assume !(1 == ~t6_pc~0); 655972#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 655970#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 655968#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 655965#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 655963#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 655961#L521-27 assume !(1 == ~t7_pc~0); 655950#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 655945#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 655790#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 655665#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 655661#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 655659#L869-3 assume !(1 == ~M_E~0); 655196#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 655657#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 655655#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 655653#L884-3 assume !(1 == ~T4_E~0); 655651#L889-3 assume !(1 == ~T5_E~0); 655649#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 655638#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 655629#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 655619#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 655612#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 655605#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 655599#L924-3 assume !(1 == ~E_4~0); 655592#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 655586#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 655581#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 655578#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 655532#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 655523#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 655517#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 655508#L1209 assume !(0 == start_simulation_~tmp~3#1); 655509#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 656795#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 656786#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 656780#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 656521#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 656517#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 656515#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 656513#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 641716#L1190-2 [2023-11-23 22:34:50,099 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:50,100 INFO L85 PathProgramCache]: Analyzing trace with hash 2121315589, now seen corresponding path program 1 times [2023-11-23 22:34:50,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:50,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200031875] [2023-11-23 22:34:50,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:50,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:50,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:50,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:50,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:50,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [200031875] [2023-11-23 22:34:50,154 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [200031875] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:50,154 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:50,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:50,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994127229] [2023-11-23 22:34:50,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:50,155 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:34:50,155 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:50,156 INFO L85 PathProgramCache]: Analyzing trace with hash 602479525, now seen corresponding path program 1 times [2023-11-23 22:34:50,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:50,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665926630] [2023-11-23 22:34:50,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:50,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:50,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:50,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:50,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:50,217 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665926630] [2023-11-23 22:34:50,217 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665926630] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:50,217 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:50,217 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:34:50,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [225620844] [2023-11-23 22:34:50,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:50,218 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:50,218 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:50,218 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:34:50,218 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:34:50,219 INFO L87 Difference]: Start difference. First operand 28762 states and 40291 transitions. cyclomatic complexity: 11545 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:50,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:50,487 INFO L93 Difference]: Finished difference Result 39377 states and 55061 transitions. [2023-11-23 22:34:50,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39377 states and 55061 transitions. [2023-11-23 22:34:50,654 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 38304 [2023-11-23 22:34:50,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39377 states to 39377 states and 55061 transitions. [2023-11-23 22:34:50,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39377 [2023-11-23 22:34:50,785 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39377 [2023-11-23 22:34:50,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39377 states and 55061 transitions. [2023-11-23 22:34:50,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:50,801 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39377 states and 55061 transitions. [2023-11-23 22:34:50,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39377 states and 55061 transitions. [2023-11-23 22:34:51,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39377 to 27514. [2023-11-23 22:34:51,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27514 states, 27514 states have (on average 1.3997237769862616) internal successors, (38512), 27513 states have internal predecessors, (38512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:51,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27514 states to 27514 states and 38512 transitions. [2023-11-23 22:34:51,078 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27514 states and 38512 transitions. [2023-11-23 22:34:51,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:34:51,079 INFO L428 stractBuchiCegarLoop]: Abstraction has 27514 states and 38512 transitions. [2023-11-23 22:34:51,079 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-23 22:34:51,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27514 states and 38512 transitions. [2023-11-23 22:34:51,429 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27260 [2023-11-23 22:34:51,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:51,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:51,431 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:51,432 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:51,432 INFO L748 eck$LassoCheckResult]: Stem: 709278#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 709279#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 709911#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 709912#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 710003#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 709425#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 709426#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 709559#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 709560#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 709322#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 709114#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 709115#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 709283#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 709284#L781 assume !(0 == ~M_E~0); 709814#L781-2 assume !(0 == ~T1_E~0); 710027#L786-1 assume !(0 == ~T2_E~0); 709074#L791-1 assume !(0 == ~T3_E~0); 709075#L796-1 assume !(0 == ~T4_E~0); 709635#L801-1 assume !(0 == ~T5_E~0); 709636#L806-1 assume !(0 == ~T6_E~0); 709674#L811-1 assume !(0 == ~T7_E~0); 709289#L816-1 assume !(0 == ~E_M~0); 709290#L821-1 assume !(0 == ~E_1~0); 709106#L826-1 assume !(0 == ~E_2~0); 709107#L831-1 assume !(0 == ~E_3~0); 709420#L836-1 assume !(0 == ~E_4~0); 709421#L841-1 assume !(0 == ~E_5~0); 709243#L846-1 assume !(0 == ~E_6~0); 709244#L851-1 assume !(0 == ~E_7~0); 709266#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 709267#L388 assume !(1 == ~m_pc~0); 709260#L388-2 is_master_triggered_~__retres1~0#1 := 0; 709261#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 709788#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 709120#L967 assume !(0 != activate_threads_~tmp~1#1); 709121#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 709052#L407 assume !(1 == ~t1_pc~0); 709053#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 709056#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 709057#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 709091#L975 assume !(0 != activate_threads_~tmp___0~0#1); 709908#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 709377#L426 assume !(1 == ~t2_pc~0); 709378#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 709935#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 709401#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 709402#L983 assume !(0 != activate_threads_~tmp___1~0#1); 709988#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 709472#L445 assume !(1 == ~t3_pc~0); 709473#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 709826#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 709050#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 709051#L991 assume !(0 != activate_threads_~tmp___2~0#1); 709738#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 709701#L464 assume !(1 == ~t4_pc~0); 709270#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 709140#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 709141#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 709152#L999 assume !(0 != activate_threads_~tmp___3~0#1); 709450#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 709451#L483 assume !(1 == ~t5_pc~0); 709698#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 709884#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 709843#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 709844#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 709361#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 709362#L502 assume !(1 == ~t6_pc~0); 709220#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 709179#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 709180#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 709388#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 709596#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 709859#L521 assume !(1 == ~t7_pc~0); 709904#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 709116#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 709117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 709897#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 709864#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 709775#L869 assume !(1 == ~M_E~0); 709443#L869-2 assume !(1 == ~T1_E~0); 709444#L874-1 assume !(1 == ~T2_E~0); 709946#L879-1 assume !(1 == ~T3_E~0); 709522#L884-1 assume !(1 == ~T4_E~0); 709038#L889-1 assume !(1 == ~T5_E~0); 709039#L894-1 assume !(1 == ~T6_E~0); 709297#L899-1 assume !(1 == ~T7_E~0); 709725#L904-1 assume !(1 == ~E_M~0); 709469#L909-1 assume !(1 == ~E_1~0); 709470#L914-1 assume !(1 == ~E_2~0); 709658#L919-1 assume !(1 == ~E_3~0); 709376#L924-1 assume !(1 == ~E_4~0); 709213#L929-1 assume !(1 == ~E_5~0); 709214#L934-1 assume !(1 == ~E_6~0); 709446#L939-1 assume !(1 == ~E_7~0); 709447#L944-1 assume { :end_inline_reset_delta_events } true; 709858#L1190-2 [2023-11-23 22:34:51,433 INFO L750 eck$LassoCheckResult]: Loop: 709858#L1190-2 assume !false; 713189#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 713180#L756-1 assume !false; 712791#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 712765#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 712755#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 712752#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 712748#L653 assume !(0 != eval_~tmp~0#1); 712745#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 712742#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 712739#L781-3 assume !(0 == ~M_E~0); 712736#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 712733#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 712730#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 712727#L796-3 assume !(0 == ~T4_E~0); 712724#L801-3 assume !(0 == ~T5_E~0); 712721#L806-3 assume !(0 == ~T6_E~0); 712718#L811-3 assume !(0 == ~T7_E~0); 712715#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 712712#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 712709#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 712706#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 712703#L836-3 assume !(0 == ~E_4~0); 712700#L841-3 assume !(0 == ~E_5~0); 712696#L846-3 assume !(0 == ~E_6~0); 712692#L851-3 assume !(0 == ~E_7~0); 712689#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 712686#L388-27 assume !(1 == ~m_pc~0); 712682#L388-29 is_master_triggered_~__retres1~0#1 := 0; 712679#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 712676#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 712673#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 712670#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 712667#L407-27 assume !(1 == ~t1_pc~0); 712664#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 712661#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 712657#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 712653#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 712650#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 712647#L426-27 assume 1 == ~t2_pc~0; 712643#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 712640#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 712636#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 712633#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 712630#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 712627#L445-27 assume !(1 == ~t3_pc~0); 712624#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 712620#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 712616#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 712613#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 712610#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 712606#L464-27 assume !(1 == ~t4_pc~0); 712602#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 712599#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 712596#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 712593#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 712590#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 712587#L483-27 assume !(1 == ~t5_pc~0); 712584#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 712579#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 712575#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 712570#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 712566#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 712562#L502-27 assume !(1 == ~t6_pc~0); 712558#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 712553#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 712548#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 712542#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 712536#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 712530#L521-27 assume !(1 == ~t7_pc~0); 712522#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 712521#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 712520#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 712513#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 712510#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 712509#L869-3 assume !(1 == ~M_E~0); 712260#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 712506#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 712504#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 712502#L884-3 assume !(1 == ~T4_E~0); 712500#L889-3 assume !(1 == ~T5_E~0); 712498#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 712496#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 712494#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 712492#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 712490#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 712488#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 712486#L924-3 assume !(1 == ~E_4~0); 712484#L929-3 assume !(1 == ~E_5~0); 712482#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 712476#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 712475#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 712456#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 712442#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 712439#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 712414#L1209 assume !(0 == start_simulation_~tmp~3#1); 712415#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 713223#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 713217#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 713215#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 713213#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 713211#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 713209#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 713207#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 709858#L1190-2 [2023-11-23 22:34:51,433 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:51,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2023-11-23 22:34:51,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:51,434 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1546559386] [2023-11-23 22:34:51,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:51,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:51,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:51,450 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:34:51,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:51,492 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:34:51,492 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:51,493 INFO L85 PathProgramCache]: Analyzing trace with hash -1476426907, now seen corresponding path program 1 times [2023-11-23 22:34:51,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:51,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571304345] [2023-11-23 22:34:51,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:51,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:51,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:51,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:51,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:51,564 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [571304345] [2023-11-23 22:34:51,565 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [571304345] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:51,565 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:51,565 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:34:51,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110973139] [2023-11-23 22:34:51,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:51,566 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:51,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:51,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 22:34:51,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 22:34:51,567 INFO L87 Difference]: Start difference. First operand 27514 states and 38512 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:51,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:51,976 INFO L93 Difference]: Finished difference Result 50246 states and 69676 transitions. [2023-11-23 22:34:51,976 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50246 states and 69676 transitions. [2023-11-23 22:34:52,234 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 49840 [2023-11-23 22:34:52,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50246 states to 50246 states and 69676 transitions. [2023-11-23 22:34:52,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50246 [2023-11-23 22:34:52,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50246 [2023-11-23 22:34:52,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50246 states and 69676 transitions. [2023-11-23 22:34:52,419 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:52,419 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50246 states and 69676 transitions. [2023-11-23 22:34:52,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50246 states and 69676 transitions. [2023-11-23 22:34:52,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50246 to 27658. [2023-11-23 22:34:52,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27658 states, 27658 states have (on average 1.3976426350423024) internal successors, (38656), 27657 states have internal predecessors, (38656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:52,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27658 states to 27658 states and 38656 transitions. [2023-11-23 22:34:52,849 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27658 states and 38656 transitions. [2023-11-23 22:34:52,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-23 22:34:52,850 INFO L428 stractBuchiCegarLoop]: Abstraction has 27658 states and 38656 transitions. [2023-11-23 22:34:52,850 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-23 22:34:52,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27658 states and 38656 transitions. [2023-11-23 22:34:52,936 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27404 [2023-11-23 22:34:52,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:52,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:52,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:52,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:52,939 INFO L748 eck$LassoCheckResult]: Stem: 787054#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 787055#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 787678#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 787679#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 787744#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 787199#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 787200#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 787334#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 787335#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 787100#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 786891#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 786892#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 787060#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 787061#L781 assume !(0 == ~M_E~0); 787589#L781-2 assume !(0 == ~T1_E~0); 787763#L786-1 assume !(0 == ~T2_E~0); 786851#L791-1 assume !(0 == ~T3_E~0); 786852#L796-1 assume !(0 == ~T4_E~0); 787412#L801-1 assume !(0 == ~T5_E~0); 787413#L806-1 assume !(0 == ~T6_E~0); 787449#L811-1 assume !(0 == ~T7_E~0); 787066#L816-1 assume !(0 == ~E_M~0); 787067#L821-1 assume !(0 == ~E_1~0); 786882#L826-1 assume !(0 == ~E_2~0); 786883#L831-1 assume !(0 == ~E_3~0); 787194#L836-1 assume !(0 == ~E_4~0); 787195#L841-1 assume !(0 == ~E_5~0); 787019#L846-1 assume !(0 == ~E_6~0); 787020#L851-1 assume !(0 == ~E_7~0); 787042#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 787043#L388 assume !(1 == ~m_pc~0); 787036#L388-2 is_master_triggered_~__retres1~0#1 := 0; 787037#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 787563#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 786897#L967 assume !(0 != activate_threads_~tmp~1#1); 786898#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 786829#L407 assume !(1 == ~t1_pc~0); 786830#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 786836#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 786837#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 786868#L975 assume !(0 != activate_threads_~tmp___0~0#1); 787673#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 787153#L426 assume !(1 == ~t2_pc~0); 787154#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 787700#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 787176#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 787177#L983 assume !(0 != activate_threads_~tmp___1~0#1); 787735#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 787243#L445 assume !(1 == ~t3_pc~0); 787244#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 787598#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 786827#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 786828#L991 assume !(0 != activate_threads_~tmp___2~0#1); 787515#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 787476#L464 assume !(1 == ~t4_pc~0); 787046#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 786917#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 786918#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 786929#L999 assume !(0 != activate_threads_~tmp___3~0#1); 787221#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 787222#L483 assume !(1 == ~t5_pc~0); 787473#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 787653#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 787616#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 787617#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 787138#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 787139#L502 assume !(1 == ~t6_pc~0); 786997#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 786956#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 786957#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 787163#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 787374#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 787632#L521 assume !(1 == ~t7_pc~0); 787670#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 786893#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 786894#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 787663#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 787637#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 787552#L869 assume !(1 == ~M_E~0); 787215#L869-2 assume !(1 == ~T1_E~0); 787216#L874-1 assume !(1 == ~T2_E~0); 787711#L879-1 assume !(1 == ~T3_E~0); 787294#L884-1 assume !(1 == ~T4_E~0); 786815#L889-1 assume !(1 == ~T5_E~0); 786816#L894-1 assume !(1 == ~T6_E~0); 787076#L899-1 assume !(1 == ~T7_E~0); 787503#L904-1 assume !(1 == ~E_M~0); 787240#L909-1 assume !(1 == ~E_1~0); 787241#L914-1 assume !(1 == ~E_2~0); 787436#L919-1 assume !(1 == ~E_3~0); 787152#L924-1 assume !(1 == ~E_4~0); 786989#L929-1 assume !(1 == ~E_5~0); 786990#L934-1 assume !(1 == ~E_6~0); 787219#L939-1 assume !(1 == ~E_7~0); 787220#L944-1 assume { :end_inline_reset_delta_events } true; 787631#L1190-2 [2023-11-23 22:34:52,940 INFO L750 eck$LassoCheckResult]: Loop: 787631#L1190-2 assume !false; 808402#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 808397#L756-1 assume !false; 807966#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 807252#L596 assume !(0 == ~m_st~0); 807248#L600 assume !(0 == ~t1_st~0); 807249#L604 assume !(0 == ~t2_st~0); 807251#L608 assume !(0 == ~t3_st~0); 807246#L612 assume !(0 == ~t4_st~0); 807247#L616 assume !(0 == ~t5_st~0); 807250#L620 assume !(0 == ~t6_st~0); 807244#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 807242#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 800202#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 800203#L653 assume !(0 != eval_~tmp~0#1); 808832#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 808830#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 808828#L781-3 assume !(0 == ~M_E~0); 808826#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 808824#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 808822#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 808820#L796-3 assume !(0 == ~T4_E~0); 808818#L801-3 assume !(0 == ~T5_E~0); 808816#L806-3 assume !(0 == ~T6_E~0); 808814#L811-3 assume !(0 == ~T7_E~0); 808812#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 808810#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 808808#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 808806#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 808804#L836-3 assume !(0 == ~E_4~0); 808802#L841-3 assume !(0 == ~E_5~0); 808800#L846-3 assume !(0 == ~E_6~0); 808798#L851-3 assume !(0 == ~E_7~0); 808796#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 808794#L388-27 assume 1 == ~m_pc~0; 808792#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 808788#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 808786#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 808784#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 808782#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 808780#L407-27 assume !(1 == ~t1_pc~0); 808778#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 808776#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 808774#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 808772#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 808770#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 808768#L426-27 assume 1 == ~t2_pc~0; 808765#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 808762#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 808760#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 808758#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 808756#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 808754#L445-27 assume !(1 == ~t3_pc~0); 808752#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 808750#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 808748#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 808746#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 808744#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 808742#L464-27 assume !(1 == ~t4_pc~0); 808738#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 808736#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 808734#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 808732#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 808730#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 808728#L483-27 assume !(1 == ~t5_pc~0); 808726#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 808724#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 808722#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 808720#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 808718#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 808716#L502-27 assume !(1 == ~t6_pc~0); 808714#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 808712#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 808710#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 808708#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 808706#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 808704#L521-27 assume 1 == ~t7_pc~0; 808701#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 808697#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 808693#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 808689#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 808686#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 808684#L869-3 assume !(1 == ~M_E~0); 808681#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 808680#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 808679#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 808678#L884-3 assume !(1 == ~T4_E~0); 808677#L889-3 assume !(1 == ~T5_E~0); 808676#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 808675#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 808674#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 808673#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 808672#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 808671#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 808670#L924-3 assume !(1 == ~E_4~0); 808669#L929-3 assume !(1 == ~E_5~0); 808668#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 808667#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 808666#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 808662#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 808657#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 808655#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 808651#L1209 assume !(0 == start_simulation_~tmp~3#1); 808437#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 808433#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 808427#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 808424#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 808422#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 808418#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 808416#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 808414#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 787631#L1190-2 [2023-11-23 22:34:52,940 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:52,941 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2023-11-23 22:34:52,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:52,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596240295] [2023-11-23 22:34:52,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:52,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:52,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:52,958 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:34:52,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:52,996 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:34:52,997 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:52,997 INFO L85 PathProgramCache]: Analyzing trace with hash 1520718769, now seen corresponding path program 1 times [2023-11-23 22:34:52,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:52,997 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43845224] [2023-11-23 22:34:52,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:52,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:53,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:53,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:53,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:53,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [43845224] [2023-11-23 22:34:53,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [43845224] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:53,075 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:53,076 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:34:53,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868772926] [2023-11-23 22:34:53,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:53,076 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:53,077 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:53,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 22:34:53,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 22:34:53,077 INFO L87 Difference]: Start difference. First operand 27658 states and 38656 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:53,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:53,641 INFO L93 Difference]: Finished difference Result 49606 states and 68620 transitions. [2023-11-23 22:34:53,641 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49606 states and 68620 transitions. [2023-11-23 22:34:53,865 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 49200 [2023-11-23 22:34:53,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49606 states to 49606 states and 68620 transitions. [2023-11-23 22:34:53,975 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49606 [2023-11-23 22:34:53,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49606 [2023-11-23 22:34:53,998 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49606 states and 68620 transitions. [2023-11-23 22:34:54,017 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:54,017 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49606 states and 68620 transitions. [2023-11-23 22:34:54,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49606 states and 68620 transitions. [2023-11-23 22:34:54,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49606 to 27754. [2023-11-23 22:34:54,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27754 states, 27754 states have (on average 1.3962672047272464) internal successors, (38752), 27753 states have internal predecessors, (38752), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:54,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27754 states to 27754 states and 38752 transitions. [2023-11-23 22:34:54,344 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27754 states and 38752 transitions. [2023-11-23 22:34:54,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-23 22:34:54,345 INFO L428 stractBuchiCegarLoop]: Abstraction has 27754 states and 38752 transitions. [2023-11-23 22:34:54,345 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-23 22:34:54,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27754 states and 38752 transitions. [2023-11-23 22:34:54,415 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27500 [2023-11-23 22:34:54,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:54,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:54,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:54,418 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:54,418 INFO L748 eck$LassoCheckResult]: Stem: 864331#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 864332#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 864945#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 864946#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 865028#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 864478#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 864479#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 864608#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 864609#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 864376#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 864167#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 864168#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 864336#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 864337#L781 assume !(0 == ~M_E~0); 864855#L781-2 assume !(0 == ~T1_E~0); 865048#L786-1 assume !(0 == ~T2_E~0); 864128#L791-1 assume !(0 == ~T3_E~0); 864129#L796-1 assume !(0 == ~T4_E~0); 864685#L801-1 assume !(0 == ~T5_E~0); 864686#L806-1 assume !(0 == ~T6_E~0); 864720#L811-1 assume !(0 == ~T7_E~0); 864342#L816-1 assume !(0 == ~E_M~0); 864343#L821-1 assume !(0 == ~E_1~0); 864159#L826-1 assume !(0 == ~E_2~0); 864160#L831-1 assume !(0 == ~E_3~0); 864473#L836-1 assume !(0 == ~E_4~0); 864474#L841-1 assume !(0 == ~E_5~0); 864295#L846-1 assume !(0 == ~E_6~0); 864296#L851-1 assume !(0 == ~E_7~0); 864318#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 864319#L388 assume !(1 == ~m_pc~0); 864312#L388-2 is_master_triggered_~__retres1~0#1 := 0; 864313#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 864832#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 864173#L967 assume !(0 != activate_threads_~tmp~1#1); 864174#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 864106#L407 assume !(1 == ~t1_pc~0); 864107#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 864110#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 864111#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 864145#L975 assume !(0 != activate_threads_~tmp___0~0#1); 864941#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 864430#L426 assume !(1 == ~t2_pc~0); 864431#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 864975#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 864456#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 864457#L983 assume !(0 != activate_threads_~tmp___1~0#1); 865013#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 864521#L445 assume !(1 == ~t3_pc~0); 864522#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 864863#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 864104#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 864105#L991 assume !(0 != activate_threads_~tmp___2~0#1); 864785#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 864748#L464 assume !(1 == ~t4_pc~0); 864322#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 864193#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 864194#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 864205#L999 assume !(0 != activate_threads_~tmp___3~0#1); 864501#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 864502#L483 assume !(1 == ~t5_pc~0); 864745#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 864918#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 864883#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 864884#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 864414#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 864415#L502 assume !(1 == ~t6_pc~0); 864273#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 864233#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 864234#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 864441#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 864646#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 864895#L521 assume !(1 == ~t7_pc~0); 864938#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 864169#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 864170#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 864931#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 864901#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 864818#L869 assume !(1 == ~M_E~0); 864495#L869-2 assume !(1 == ~T1_E~0); 864496#L874-1 assume !(1 == ~T2_E~0); 864986#L879-1 assume !(1 == ~T3_E~0); 864571#L884-1 assume !(1 == ~T4_E~0); 864092#L889-1 assume !(1 == ~T5_E~0); 864093#L894-1 assume !(1 == ~T6_E~0); 864350#L899-1 assume !(1 == ~T7_E~0); 864773#L904-1 assume !(1 == ~E_M~0); 864518#L909-1 assume !(1 == ~E_1~0); 864519#L914-1 assume !(1 == ~E_2~0); 864703#L919-1 assume !(1 == ~E_3~0); 864429#L924-1 assume !(1 == ~E_4~0); 864266#L929-1 assume !(1 == ~E_5~0); 864267#L934-1 assume !(1 == ~E_6~0); 864497#L939-1 assume !(1 == ~E_7~0); 864498#L944-1 assume { :end_inline_reset_delta_events } true; 864894#L1190-2 [2023-11-23 22:34:54,419 INFO L750 eck$LassoCheckResult]: Loop: 864894#L1190-2 assume !false; 877414#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 877412#L756-1 assume !false; 877410#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 877409#L596 assume !(0 == ~m_st~0); 877408#L600 assume !(0 == ~t1_st~0); 877407#L604 assume !(0 == ~t2_st~0); 877406#L608 assume !(0 == ~t3_st~0); 877405#L612 assume !(0 == ~t4_st~0); 877404#L616 assume !(0 == ~t5_st~0); 877403#L620 assume !(0 == ~t6_st~0); 877401#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 877400#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 877399#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 877397#L653 assume !(0 != eval_~tmp~0#1); 877396#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 877395#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 877394#L781-3 assume !(0 == ~M_E~0); 877393#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 877392#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 877391#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 877390#L796-3 assume !(0 == ~T4_E~0); 877389#L801-3 assume !(0 == ~T5_E~0); 877388#L806-3 assume !(0 == ~T6_E~0); 877387#L811-3 assume !(0 == ~T7_E~0); 877386#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 877385#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 877384#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 877383#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 877382#L836-3 assume !(0 == ~E_4~0); 877381#L841-3 assume !(0 == ~E_5~0); 877380#L846-3 assume !(0 == ~E_6~0); 877379#L851-3 assume !(0 == ~E_7~0); 877378#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 877377#L388-27 assume !(1 == ~m_pc~0); 877375#L388-29 is_master_triggered_~__retres1~0#1 := 0; 877374#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 877373#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 877372#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 877371#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 877370#L407-27 assume !(1 == ~t1_pc~0); 877369#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 877368#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 877367#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 877366#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 877365#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 877364#L426-27 assume !(1 == ~t2_pc~0); 877363#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 877361#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 877360#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 877359#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 877358#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 877357#L445-27 assume !(1 == ~t3_pc~0); 877356#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 877355#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 877354#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 877353#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 877352#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 877351#L464-27 assume !(1 == ~t4_pc~0); 877349#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 877348#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 877347#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 877346#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 877345#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 877344#L483-27 assume !(1 == ~t5_pc~0); 877343#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 877342#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 877341#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 877340#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 877339#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 877338#L502-27 assume !(1 == ~t6_pc~0); 877337#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 877336#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 877335#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 877334#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 877333#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 877332#L521-27 assume !(1 == ~t7_pc~0); 877331#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 877329#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 877327#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 877325#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 877323#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 877322#L869-3 assume !(1 == ~M_E~0); 877087#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 877321#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 877320#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 877319#L884-3 assume !(1 == ~T4_E~0); 877318#L889-3 assume !(1 == ~T5_E~0); 877317#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 877316#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 877315#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 877314#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 877313#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 877312#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 877311#L924-3 assume !(1 == ~E_4~0); 877310#L929-3 assume !(1 == ~E_5~0); 877309#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 877308#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 877307#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 877303#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 877297#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 877296#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 877294#L1209 assume !(0 == start_simulation_~tmp~3#1); 877295#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 877586#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 877581#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 877579#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 877577#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 877572#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 877570#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 877568#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 864894#L1190-2 [2023-11-23 22:34:54,419 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:54,420 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 5 times [2023-11-23 22:34:54,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:54,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410481540] [2023-11-23 22:34:54,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:54,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:54,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:54,434 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:34:54,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:54,467 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:34:54,467 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:54,467 INFO L85 PathProgramCache]: Analyzing trace with hash 1809037176, now seen corresponding path program 1 times [2023-11-23 22:34:54,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:54,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577122240] [2023-11-23 22:34:54,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:54,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:54,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:54,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:54,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:54,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577122240] [2023-11-23 22:34:54,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [577122240] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:54,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:54,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:34:54,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1361289121] [2023-11-23 22:34:54,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:54,554 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:54,555 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:54,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 22:34:54,556 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 22:34:54,556 INFO L87 Difference]: Start difference. First operand 27754 states and 38752 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:54,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:54,998 INFO L93 Difference]: Finished difference Result 72296 states and 98907 transitions. [2023-11-23 22:34:54,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72296 states and 98907 transitions. [2023-11-23 22:34:55,448 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 71772 [2023-11-23 22:34:55,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72296 states to 72296 states and 98907 transitions. [2023-11-23 22:34:55,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72296 [2023-11-23 22:34:55,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72296 [2023-11-23 22:34:55,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72296 states and 98907 transitions. [2023-11-23 22:34:55,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:55,630 INFO L218 hiAutomatonCegarLoop]: Abstraction has 72296 states and 98907 transitions. [2023-11-23 22:34:55,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72296 states and 98907 transitions. [2023-11-23 22:34:55,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72296 to 28789. [2023-11-23 22:34:55,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28789 states, 28789 states have (on average 1.382020910764528) internal successors, (39787), 28788 states have internal predecessors, (39787), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:55,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28789 states to 28789 states and 39787 transitions. [2023-11-23 22:34:55,980 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28789 states and 39787 transitions. [2023-11-23 22:34:55,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-23 22:34:55,981 INFO L428 stractBuchiCegarLoop]: Abstraction has 28789 states and 39787 transitions. [2023-11-23 22:34:55,981 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-23 22:34:55,981 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28789 states and 39787 transitions. [2023-11-23 22:34:56,042 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28532 [2023-11-23 22:34:56,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:56,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:56,044 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:56,044 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:56,044 INFO L748 eck$LassoCheckResult]: Stem: 964394#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 964395#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 965047#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 965048#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 965153#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 964541#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 964542#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 964679#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 964680#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 964440#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 964229#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 964230#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 964401#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 964402#L781 assume !(0 == ~M_E~0); 964940#L781-2 assume !(0 == ~T1_E~0); 965171#L786-1 assume !(0 == ~T2_E~0); 964193#L791-1 assume !(0 == ~T3_E~0); 964194#L796-1 assume !(0 == ~T4_E~0); 964760#L801-1 assume !(0 == ~T5_E~0); 964761#L806-1 assume !(0 == ~T6_E~0); 964798#L811-1 assume !(0 == ~T7_E~0); 964405#L816-1 assume !(0 == ~E_M~0); 964406#L821-1 assume !(0 == ~E_1~0); 964221#L826-1 assume !(0 == ~E_2~0); 964222#L831-1 assume !(0 == ~E_3~0); 964536#L836-1 assume !(0 == ~E_4~0); 964537#L841-1 assume !(0 == ~E_5~0); 964359#L846-1 assume !(0 == ~E_6~0); 964360#L851-1 assume !(0 == ~E_7~0); 964382#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 964383#L388 assume !(1 == ~m_pc~0); 964376#L388-2 is_master_triggered_~__retres1~0#1 := 0; 964377#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 964911#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 964235#L967 assume !(0 != activate_threads_~tmp~1#1); 964236#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 964168#L407 assume !(1 == ~t1_pc~0); 964169#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 964175#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 964176#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 964209#L975 assume !(0 != activate_threads_~tmp___0~0#1); 965043#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 964494#L426 assume !(1 == ~t2_pc~0); 964495#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 965081#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 964518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 964519#L983 assume !(0 != activate_threads_~tmp___1~0#1); 965132#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 964587#L445 assume !(1 == ~t3_pc~0); 964588#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 964950#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 964166#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 964167#L991 assume !(0 != activate_threads_~tmp___2~0#1); 964865#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 964830#L464 assume !(1 == ~t4_pc~0); 964388#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 964255#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 964256#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 964269#L999 assume !(0 != activate_threads_~tmp___3~0#1); 964565#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 964566#L483 assume !(1 == ~t5_pc~0); 964826#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 965022#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 964976#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 964977#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 964480#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 964481#L502 assume !(1 == ~t6_pc~0); 964336#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 964294#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 964295#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 964507#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 964722#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 964995#L521 assume !(1 == ~t7_pc~0); 965039#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 964231#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 964232#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 965032#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 965002#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 964902#L869 assume !(1 == ~M_E~0); 964559#L869-2 assume !(1 == ~T1_E~0); 964560#L874-1 assume !(1 == ~T2_E~0); 965100#L879-1 assume !(1 == ~T3_E~0); 964639#L884-1 assume !(1 == ~T4_E~0); 964154#L889-1 assume !(1 == ~T5_E~0); 964155#L894-1 assume !(1 == ~T6_E~0); 964416#L899-1 assume !(1 == ~T7_E~0); 964855#L904-1 assume !(1 == ~E_M~0); 964584#L909-1 assume !(1 == ~E_1~0); 964585#L914-1 assume !(1 == ~E_2~0); 964783#L919-1 assume !(1 == ~E_3~0); 964493#L924-1 assume !(1 == ~E_4~0); 964328#L929-1 assume !(1 == ~E_5~0); 964329#L934-1 assume !(1 == ~E_6~0); 964563#L939-1 assume !(1 == ~E_7~0); 964564#L944-1 assume { :end_inline_reset_delta_events } true; 964994#L1190-2 [2023-11-23 22:34:56,045 INFO L750 eck$LassoCheckResult]: Loop: 964994#L1190-2 assume !false; 988467#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 988465#L756-1 assume !false; 988463#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 988461#L596 assume !(0 == ~m_st~0); 988446#L600 assume !(0 == ~t1_st~0); 988445#L604 assume !(0 == ~t2_st~0); 988444#L608 assume !(0 == ~t3_st~0); 988443#L612 assume !(0 == ~t4_st~0); 988442#L616 assume !(0 == ~t5_st~0); 988440#L620 assume !(0 == ~t6_st~0); 988438#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 988437#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 988435#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 988432#L653 assume !(0 != eval_~tmp~0#1); 988430#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 988428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 988426#L781-3 assume !(0 == ~M_E~0); 988424#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 988422#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 988420#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 988417#L796-3 assume !(0 == ~T4_E~0); 988415#L801-3 assume !(0 == ~T5_E~0); 988413#L806-3 assume !(0 == ~T6_E~0); 988411#L811-3 assume !(0 == ~T7_E~0); 988407#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 988405#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 988403#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 988401#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 988398#L836-3 assume !(0 == ~E_4~0); 988396#L841-3 assume !(0 == ~E_5~0); 988394#L846-3 assume !(0 == ~E_6~0); 988392#L851-3 assume !(0 == ~E_7~0); 988390#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 988388#L388-27 assume !(1 == ~m_pc~0); 988386#L388-29 is_master_triggered_~__retres1~0#1 := 0; 989706#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 989703#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 988377#L967-27 assume !(0 != activate_threads_~tmp~1#1); 988374#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 988372#L407-27 assume !(1 == ~t1_pc~0); 988370#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 988368#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 988367#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 988366#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 988363#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 988361#L426-27 assume !(1 == ~t2_pc~0); 988359#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 988315#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 988302#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 988298#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 988294#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 988289#L445-27 assume !(1 == ~t3_pc~0); 988285#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 988280#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 988276#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 988272#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 988268#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 988263#L464-27 assume !(1 == ~t4_pc~0); 988258#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 988254#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 988250#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 988246#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 988241#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 988237#L483-27 assume !(1 == ~t5_pc~0); 988232#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 988228#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 988215#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 988210#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 988204#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 988197#L502-27 assume !(1 == ~t6_pc~0); 988193#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 988187#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 988183#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 988178#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 988173#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 988165#L521-27 assume 1 == ~t7_pc~0; 988159#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 988152#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 988145#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 988138#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 988133#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 988132#L869-3 assume !(1 == ~M_E~0); 986667#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 988131#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 988130#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 988129#L884-3 assume !(1 == ~T4_E~0); 988128#L889-3 assume !(1 == ~T5_E~0); 988127#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 988126#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 988125#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 988124#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 988123#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 988122#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 988121#L924-3 assume !(1 == ~E_4~0); 988120#L929-3 assume !(1 == ~E_5~0); 988119#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 988118#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 988117#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 988113#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 988108#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 988107#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 988105#L1209 assume !(0 == start_simulation_~tmp~3#1); 988106#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 988568#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 988557#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 988565#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 988489#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 988485#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 988483#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 988479#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 964994#L1190-2 [2023-11-23 22:34:56,045 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:56,045 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 6 times [2023-11-23 22:34:56,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:56,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118179666] [2023-11-23 22:34:56,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:56,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:56,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:56,059 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:34:56,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:56,089 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:34:56,090 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:56,090 INFO L85 PathProgramCache]: Analyzing trace with hash -1855054345, now seen corresponding path program 1 times [2023-11-23 22:34:56,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:56,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725056027] [2023-11-23 22:34:56,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:56,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:56,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:56,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:56,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:56,130 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725056027] [2023-11-23 22:34:56,130 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [725056027] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:56,131 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:56,131 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:34:56,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905894105] [2023-11-23 22:34:56,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:56,131 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:56,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:56,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:34:56,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:34:56,132 INFO L87 Difference]: Start difference. First operand 28789 states and 39787 transitions. cyclomatic complexity: 11014 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:56,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:56,318 INFO L93 Difference]: Finished difference Result 54097 states and 73951 transitions. [2023-11-23 22:34:56,318 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54097 states and 73951 transitions. [2023-11-23 22:34:56,789 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53688 [2023-11-23 22:34:56,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54097 states to 54097 states and 73951 transitions. [2023-11-23 22:34:56,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54097 [2023-11-23 22:34:56,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54097 [2023-11-23 22:34:56,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54097 states and 73951 transitions. [2023-11-23 22:34:56,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:56,946 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54097 states and 73951 transitions. [2023-11-23 22:34:56,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54097 states and 73951 transitions. [2023-11-23 22:34:57,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54097 to 51593. [2023-11-23 22:34:57,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51593 states, 51593 states have (on average 1.3699339057624096) internal successors, (70679), 51592 states have internal predecessors, (70679), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:57,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51593 states to 51593 states and 70679 transitions. [2023-11-23 22:34:57,421 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51593 states and 70679 transitions. [2023-11-23 22:34:57,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:34:57,422 INFO L428 stractBuchiCegarLoop]: Abstraction has 51593 states and 70679 transitions. [2023-11-23 22:34:57,422 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-23 22:34:57,422 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51593 states and 70679 transitions. [2023-11-23 22:34:57,551 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51184 [2023-11-23 22:34:57,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:34:57,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:34:57,552 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:57,552 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:34:57,553 INFO L748 eck$LassoCheckResult]: Stem: 1047287#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1047288#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1047943#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1047944#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1048041#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1047442#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1047443#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1047576#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1047577#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1047334#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1047121#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1047122#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1047293#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1047294#L781 assume !(0 == ~M_E~0); 1047849#L781-2 assume !(0 == ~T1_E~0); 1048068#L786-1 assume !(0 == ~T2_E~0); 1047082#L791-1 assume !(0 == ~T3_E~0); 1047083#L796-1 assume !(0 == ~T4_E~0); 1047655#L801-1 assume !(0 == ~T5_E~0); 1047656#L806-1 assume !(0 == ~T6_E~0); 1047696#L811-1 assume !(0 == ~T7_E~0); 1047299#L816-1 assume !(0 == ~E_M~0); 1047300#L821-1 assume !(0 == ~E_1~0); 1047113#L826-1 assume !(0 == ~E_2~0); 1047114#L831-1 assume !(0 == ~E_3~0); 1047435#L836-1 assume !(0 == ~E_4~0); 1047436#L841-1 assume !(0 == ~E_5~0); 1047250#L846-1 assume !(0 == ~E_6~0); 1047251#L851-1 assume !(0 == ~E_7~0); 1047274#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1047275#L388 assume !(1 == ~m_pc~0); 1047268#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1047269#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1047877#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1047127#L967 assume !(0 != activate_threads_~tmp~1#1); 1047128#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1047060#L407 assume !(1 == ~t1_pc~0); 1047061#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1047064#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1047065#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1047099#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1047939#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1047391#L426 assume !(1 == ~t2_pc~0); 1047392#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1047971#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1047415#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1047416#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1048018#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1047488#L445 assume !(1 == ~t3_pc~0); 1047489#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1047860#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1047058#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1047059#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1047766#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1047730#L464 assume !(1 == ~t4_pc~0); 1047278#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1047147#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1047148#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1047159#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1047465#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1047466#L483 assume !(1 == ~t5_pc~0); 1047726#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1047918#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1047881#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1047882#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1047374#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1047375#L502 assume !(1 == ~t6_pc~0); 1047228#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1047186#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1047187#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1047401#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1047618#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1047894#L521 assume !(1 == ~t7_pc~0); 1047936#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1047123#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1047124#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1047929#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1047902#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1047804#L869 assume !(1 == ~M_E~0); 1047459#L869-2 assume !(1 == ~T1_E~0); 1047460#L874-1 assume !(1 == ~T2_E~0); 1047987#L879-1 assume !(1 == ~T3_E~0); 1047538#L884-1 assume !(1 == ~T4_E~0); 1047046#L889-1 assume !(1 == ~T5_E~0); 1047047#L894-1 assume !(1 == ~T6_E~0); 1047308#L899-1 assume !(1 == ~T7_E~0); 1047754#L904-1 assume !(1 == ~E_M~0); 1047485#L909-1 assume !(1 == ~E_1~0); 1047486#L914-1 assume !(1 == ~E_2~0); 1047677#L919-1 assume !(1 == ~E_3~0); 1047390#L924-1 assume !(1 == ~E_4~0); 1047221#L929-1 assume !(1 == ~E_5~0); 1047222#L934-1 assume !(1 == ~E_6~0); 1047461#L939-1 assume !(1 == ~E_7~0); 1047462#L944-1 assume { :end_inline_reset_delta_events } true; 1047893#L1190-2 [2023-11-23 22:34:57,553 INFO L750 eck$LassoCheckResult]: Loop: 1047893#L1190-2 assume !false; 1065704#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1065702#L756-1 assume !false; 1065700#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1065698#L596 assume !(0 == ~m_st~0); 1060942#L600 assume !(0 == ~t1_st~0); 1060940#L604 assume !(0 == ~t2_st~0); 1060936#L608 assume !(0 == ~t3_st~0); 1060934#L612 assume !(0 == ~t4_st~0); 1060932#L616 assume !(0 == ~t5_st~0); 1060930#L620 assume !(0 == ~t6_st~0); 1060926#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1060924#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1060919#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1060916#L653 assume !(0 != eval_~tmp~0#1); 1060914#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1060913#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1060912#L781-3 assume !(0 == ~M_E~0); 1060911#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1060874#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1060858#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1060849#L796-3 assume !(0 == ~T4_E~0); 1060831#L801-3 assume !(0 == ~T5_E~0); 1059040#L806-3 assume !(0 == ~T6_E~0); 1059037#L811-3 assume !(0 == ~T7_E~0); 1059035#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1059033#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1057725#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1057723#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1057721#L836-3 assume !(0 == ~E_4~0); 1057717#L841-3 assume !(0 == ~E_5~0); 1057715#L846-3 assume !(0 == ~E_6~0); 1057713#L851-3 assume !(0 == ~E_7~0); 1057711#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1057708#L388-27 assume 1 == ~m_pc~0; 1057705#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1057703#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1057702#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1057700#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1057698#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1057696#L407-27 assume !(1 == ~t1_pc~0); 1057694#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1057692#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1057690#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1057688#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1057686#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1057684#L426-27 assume 1 == ~t2_pc~0; 1057681#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1057679#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1057677#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1057675#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1057673#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1057671#L445-27 assume !(1 == ~t3_pc~0); 1056919#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1056866#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1056860#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1056855#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1056849#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1056844#L464-27 assume !(1 == ~t4_pc~0); 1056838#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1056833#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1056828#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1056823#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1056817#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1056812#L483-27 assume !(1 == ~t5_pc~0); 1056807#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1056802#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1056797#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1056792#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1056786#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1056781#L502-27 assume !(1 == ~t6_pc~0); 1056776#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1056771#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1056765#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1056757#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1056750#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1056742#L521-27 assume 1 == ~t7_pc~0; 1056734#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1056727#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1056721#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1056716#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1056710#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1056704#L869-3 assume !(1 == ~M_E~0); 1055607#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1056698#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1056695#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1056687#L884-3 assume !(1 == ~T4_E~0); 1056681#L889-3 assume !(1 == ~T5_E~0); 1056664#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1056652#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1056646#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1056639#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1056630#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1056625#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1056619#L924-3 assume !(1 == ~E_4~0); 1056611#L929-3 assume !(1 == ~E_5~0); 1056604#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1056597#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1056587#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1056581#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1056576#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1056570#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1056564#L1209 assume !(0 == start_simulation_~tmp~3#1); 1056565#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1066290#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1066288#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1066285#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1066283#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1066279#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1066277#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1066275#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1047893#L1190-2 [2023-11-23 22:34:57,553 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:57,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 7 times [2023-11-23 22:34:57,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:57,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760488915] [2023-11-23 22:34:57,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:57,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:57,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:57,566 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:34:57,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:34:57,597 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:34:57,597 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:34:57,598 INFO L85 PathProgramCache]: Analyzing trace with hash 1520659187, now seen corresponding path program 1 times [2023-11-23 22:34:57,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:34:57,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541721669] [2023-11-23 22:34:57,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:34:57,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:34:57,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:34:57,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:34:57,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:34:57,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541721669] [2023-11-23 22:34:57,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541721669] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:34:57,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:34:57,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:34:57,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416630036] [2023-11-23 22:34:57,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:34:57,677 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:34:57,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:34:57,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 22:34:57,678 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 22:34:57,678 INFO L87 Difference]: Start difference. First operand 51593 states and 70679 transitions. cyclomatic complexity: 19102 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:34:58,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:34:58,574 INFO L93 Difference]: Finished difference Result 88953 states and 120298 transitions. [2023-11-23 22:34:58,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88953 states and 120298 transitions. [2023-11-23 22:34:58,933 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 88416 [2023-11-23 22:34:59,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88953 states to 88953 states and 120298 transitions. [2023-11-23 22:34:59,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88953 [2023-11-23 22:34:59,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88953 [2023-11-23 22:34:59,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88953 states and 120298 transitions. [2023-11-23 22:34:59,233 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:34:59,233 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88953 states and 120298 transitions. [2023-11-23 22:34:59,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88953 states and 120298 transitions. [2023-11-23 22:34:59,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88953 to 52625. [2023-11-23 22:34:59,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52625 states, 52625 states have (on average 1.3570356294536816) internal successors, (71414), 52624 states have internal predecessors, (71414), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:35:00,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52625 states to 52625 states and 71414 transitions. [2023-11-23 22:35:00,678 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52625 states and 71414 transitions. [2023-11-23 22:35:00,678 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-23 22:35:00,685 INFO L428 stractBuchiCegarLoop]: Abstraction has 52625 states and 71414 transitions. [2023-11-23 22:35:00,685 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-23 22:35:00,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52625 states and 71414 transitions. [2023-11-23 22:35:00,804 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 52216 [2023-11-23 22:35:00,804 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:35:00,804 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:35:00,805 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:35:00,806 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:35:00,806 INFO L748 eck$LassoCheckResult]: Stem: 1187844#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1187845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1188498#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1188499#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1188604#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1187994#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1187995#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1188125#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1188126#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1187891#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1187679#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1187680#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1187850#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1187851#L781 assume !(0 == ~M_E~0); 1188395#L781-2 assume !(0 == ~T1_E~0); 1188629#L786-1 assume !(0 == ~T2_E~0); 1187643#L791-1 assume !(0 == ~T3_E~0); 1187644#L796-1 assume !(0 == ~T4_E~0); 1188207#L801-1 assume !(0 == ~T5_E~0); 1188208#L806-1 assume !(0 == ~T6_E~0); 1188248#L811-1 assume !(0 == ~T7_E~0); 1187856#L816-1 assume !(0 == ~E_M~0); 1187857#L821-1 assume !(0 == ~E_1~0); 1187671#L826-1 assume !(0 == ~E_2~0); 1187672#L831-1 assume !(0 == ~E_3~0); 1187989#L836-1 assume !(0 == ~E_4~0); 1187990#L841-1 assume !(0 == ~E_5~0); 1187808#L846-1 assume !(0 == ~E_6~0); 1187809#L851-1 assume !(0 == ~E_7~0); 1187831#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1187832#L388 assume !(1 == ~m_pc~0); 1187825#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1187826#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1188424#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1187685#L967 assume !(0 != activate_threads_~tmp~1#1); 1187686#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1187618#L407 assume !(1 == ~t1_pc~0); 1187619#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1187625#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1187626#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1187659#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1188494#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1187945#L426 assume !(1 == ~t2_pc~0); 1187946#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1188530#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1187969#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1187970#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1188582#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1188039#L445 assume !(1 == ~t3_pc~0); 1188040#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1188404#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1187616#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1187617#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1188321#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1188281#L464 assume !(1 == ~t4_pc~0); 1187837#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1187705#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1187706#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1187719#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1188018#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1188019#L483 assume !(1 == ~t5_pc~0); 1188278#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1188470#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1188428#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1188429#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1187931#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1187932#L502 assume !(1 == ~t6_pc~0); 1187785#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1187744#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1187745#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1187958#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1188166#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1188441#L521 assume !(1 == ~t7_pc~0); 1188490#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1187681#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1187682#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1188482#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1188450#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1188357#L869 assume !(1 == ~M_E~0); 1188012#L869-2 assume !(1 == ~T1_E~0); 1188013#L874-1 assume !(1 == ~T2_E~0); 1188547#L879-1 assume !(1 == ~T3_E~0); 1188088#L884-1 assume !(1 == ~T4_E~0); 1187604#L889-1 assume !(1 == ~T5_E~0); 1187605#L894-1 assume !(1 == ~T6_E~0); 1187866#L899-1 assume !(1 == ~T7_E~0); 1188307#L904-1 assume !(1 == ~E_M~0); 1188036#L909-1 assume !(1 == ~E_1~0); 1188037#L914-1 assume !(1 == ~E_2~0); 1188230#L919-1 assume !(1 == ~E_3~0); 1187944#L924-1 assume !(1 == ~E_4~0); 1187778#L929-1 assume !(1 == ~E_5~0); 1187779#L934-1 assume !(1 == ~E_6~0); 1188016#L939-1 assume !(1 == ~E_7~0); 1188017#L944-1 assume { :end_inline_reset_delta_events } true; 1188440#L1190-2 [2023-11-23 22:35:00,807 INFO L750 eck$LassoCheckResult]: Loop: 1188440#L1190-2 assume !false; 1198505#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1198502#L756-1 assume !false; 1198500#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1198497#L596 assume !(0 == ~m_st~0); 1198498#L600 assume !(0 == ~t1_st~0); 1203617#L604 assume !(0 == ~t2_st~0); 1203609#L608 assume !(0 == ~t3_st~0); 1203591#L612 assume !(0 == ~t4_st~0); 1203584#L616 assume !(0 == ~t5_st~0); 1203577#L620 assume !(0 == ~t6_st~0); 1203569#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1203563#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1203557#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1203551#L653 assume !(0 != eval_~tmp~0#1); 1203547#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1200657#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1200656#L781-3 assume !(0 == ~M_E~0); 1200655#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1200654#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1200653#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1200652#L796-3 assume !(0 == ~T4_E~0); 1200651#L801-3 assume !(0 == ~T5_E~0); 1200650#L806-3 assume !(0 == ~T6_E~0); 1200648#L811-3 assume !(0 == ~T7_E~0); 1200647#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1200646#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1200645#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1200644#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1200643#L836-3 assume !(0 == ~E_4~0); 1200642#L841-3 assume !(0 == ~E_5~0); 1200640#L846-3 assume !(0 == ~E_6~0); 1200638#L851-3 assume !(0 == ~E_7~0); 1200636#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1200634#L388-27 assume 1 == ~m_pc~0; 1200631#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1200628#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1200626#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1200623#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1200621#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1200619#L407-27 assume !(1 == ~t1_pc~0); 1200615#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1200613#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1200611#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1200609#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1200606#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1200604#L426-27 assume !(1 == ~t2_pc~0); 1200602#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1200599#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1200598#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1200597#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1200595#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1200593#L445-27 assume !(1 == ~t3_pc~0); 1200591#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1200590#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1200587#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1200585#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1200582#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1200580#L464-27 assume !(1 == ~t4_pc~0); 1200577#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1200574#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1200572#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1200570#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1200569#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1200568#L483-27 assume !(1 == ~t5_pc~0); 1200567#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1200566#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1200565#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1200564#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1200563#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1200562#L502-27 assume !(1 == ~t6_pc~0); 1200561#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1200560#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1200559#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1200558#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1200556#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1200555#L521-27 assume 1 == ~t7_pc~0; 1200554#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1200552#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1200550#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1200547#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1200546#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1200545#L869-3 assume !(1 == ~M_E~0); 1194141#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1200543#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1200542#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1200541#L884-3 assume !(1 == ~T4_E~0); 1200540#L889-3 assume !(1 == ~T5_E~0); 1200539#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1200538#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1200537#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1200535#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1200533#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1200532#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1200531#L924-3 assume !(1 == ~E_4~0); 1200530#L929-3 assume !(1 == ~E_5~0); 1200529#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1200528#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1200527#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1200526#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1200525#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1200524#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1198543#L1209 assume !(0 == start_simulation_~tmp~3#1); 1198540#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1198535#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1198533#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1198531#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1198529#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1198526#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1198524#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1198520#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1188440#L1190-2 [2023-11-23 22:35:00,807 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:35:00,808 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 8 times [2023-11-23 22:35:00,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:35:00,808 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621755308] [2023-11-23 22:35:00,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:35:00,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:35:00,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:35:00,821 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:35:00,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:35:00,853 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:35:00,853 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:35:00,854 INFO L85 PathProgramCache]: Analyzing trace with hash -1009879882, now seen corresponding path program 1 times [2023-11-23 22:35:00,854 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:35:00,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100662710] [2023-11-23 22:35:00,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:35:00,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:35:00,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:35:00,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:35:00,929 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:35:00,929 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [100662710] [2023-11-23 22:35:00,929 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [100662710] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:35:00,929 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:35:00,929 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:35:00,930 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502980928] [2023-11-23 22:35:00,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:35:00,930 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:35:00,930 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:35:00,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 22:35:00,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 22:35:00,931 INFO L87 Difference]: Start difference. First operand 52625 states and 71414 transitions. cyclomatic complexity: 18805 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:35:01,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:35:01,514 INFO L93 Difference]: Finished difference Result 128837 states and 171469 transitions. [2023-11-23 22:35:01,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128837 states and 171469 transitions. [2023-11-23 22:35:01,942 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 128032 [2023-11-23 22:35:02,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128837 states to 128837 states and 171469 transitions. [2023-11-23 22:35:02,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128837 [2023-11-23 22:35:02,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128837 [2023-11-23 22:35:02,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128837 states and 171469 transitions. [2023-11-23 22:35:03,007 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:35:03,007 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128837 states and 171469 transitions. [2023-11-23 22:35:03,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128837 states and 171469 transitions. [2023-11-23 22:35:03,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128837 to 54548. [2023-11-23 22:35:03,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54548 states, 54548 states have (on average 1.3444489257168) internal successors, (73337), 54547 states have internal predecessors, (73337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:35:03,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54548 states to 54548 states and 73337 transitions. [2023-11-23 22:35:03,656 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54548 states and 73337 transitions. [2023-11-23 22:35:03,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-23 22:35:03,657 INFO L428 stractBuchiCegarLoop]: Abstraction has 54548 states and 73337 transitions. [2023-11-23 22:35:03,657 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-23 22:35:03,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54548 states and 73337 transitions. [2023-11-23 22:35:03,798 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54136 [2023-11-23 22:35:03,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:35:03,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:35:03,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:35:03,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:35:03,800 INFO L748 eck$LassoCheckResult]: Stem: 1369318#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1369319#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1369959#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1369960#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1370063#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1369464#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1369465#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1369592#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1369593#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1369364#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1369154#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1369155#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1369323#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1369324#L781 assume !(0 == ~M_E~0); 1369863#L781-2 assume !(0 == ~T1_E~0); 1370085#L786-1 assume !(0 == ~T2_E~0); 1369118#L791-1 assume !(0 == ~T3_E~0); 1369119#L796-1 assume !(0 == ~T4_E~0); 1369681#L801-1 assume !(0 == ~T5_E~0); 1369682#L806-1 assume !(0 == ~T6_E~0); 1369720#L811-1 assume !(0 == ~T7_E~0); 1369329#L816-1 assume !(0 == ~E_M~0); 1369330#L821-1 assume !(0 == ~E_1~0); 1369146#L826-1 assume !(0 == ~E_2~0); 1369147#L831-1 assume !(0 == ~E_3~0); 1369459#L836-1 assume !(0 == ~E_4~0); 1369460#L841-1 assume !(0 == ~E_5~0); 1369282#L846-1 assume !(0 == ~E_6~0); 1369283#L851-1 assume !(0 == ~E_7~0); 1369305#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1369306#L388 assume !(1 == ~m_pc~0); 1369299#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1369300#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1369835#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1369160#L967 assume !(0 != activate_threads_~tmp~1#1); 1369161#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1369092#L407 assume !(1 == ~t1_pc~0); 1369093#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1369099#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1369100#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1369134#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1369953#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1369417#L426 assume !(1 == ~t2_pc~0); 1369418#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1369984#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1370045#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1370041#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1370042#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1369507#L445 assume !(1 == ~t3_pc~0); 1369508#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1369874#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1369090#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1369091#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1369788#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1369749#L464 assume !(1 == ~t4_pc~0); 1369311#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1369180#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1369181#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1369194#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1369486#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1369487#L483 assume !(1 == ~t5_pc~0); 1369746#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1369932#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1369892#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1369893#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1369403#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1369404#L502 assume !(1 == ~t6_pc~0); 1369260#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1369219#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1369220#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1369427#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1369634#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1369907#L521 assume !(1 == ~t7_pc~0); 1369950#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1369988#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1370104#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1369944#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1369915#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1369823#L869 assume !(1 == ~M_E~0); 1369480#L869-2 assume !(1 == ~T1_E~0); 1369481#L874-1 assume !(1 == ~T2_E~0); 1370000#L879-1 assume !(1 == ~T3_E~0); 1369554#L884-1 assume !(1 == ~T4_E~0); 1369078#L889-1 assume !(1 == ~T5_E~0); 1369079#L894-1 assume !(1 == ~T6_E~0); 1369340#L899-1 assume !(1 == ~T7_E~0); 1369775#L904-1 assume !(1 == ~E_M~0); 1369504#L909-1 assume !(1 == ~E_1~0); 1369505#L914-1 assume !(1 == ~E_2~0); 1369705#L919-1 assume !(1 == ~E_3~0); 1369416#L924-1 assume !(1 == ~E_4~0); 1369253#L929-1 assume !(1 == ~E_5~0); 1369254#L934-1 assume !(1 == ~E_6~0); 1369484#L939-1 assume !(1 == ~E_7~0); 1369485#L944-1 assume { :end_inline_reset_delta_events } true; 1369906#L1190-2 [2023-11-23 22:35:03,800 INFO L750 eck$LassoCheckResult]: Loop: 1369906#L1190-2 assume !false; 1376942#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1376940#L756-1 assume !false; 1376938#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1376935#L596 assume !(0 == ~m_st~0); 1376936#L600 assume !(0 == ~t1_st~0); 1379073#L604 assume !(0 == ~t2_st~0); 1379072#L608 assume !(0 == ~t3_st~0); 1379071#L612 assume !(0 == ~t4_st~0); 1379070#L616 assume !(0 == ~t5_st~0); 1379069#L620 assume !(0 == ~t6_st~0); 1379067#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1379066#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1379065#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1379064#L653 assume !(0 != eval_~tmp~0#1); 1379063#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1379062#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1379061#L781-3 assume !(0 == ~M_E~0); 1379060#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1379059#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1379058#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1379057#L796-3 assume !(0 == ~T4_E~0); 1379056#L801-3 assume !(0 == ~T5_E~0); 1379055#L806-3 assume !(0 == ~T6_E~0); 1379054#L811-3 assume !(0 == ~T7_E~0); 1379053#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1379052#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1379051#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1379050#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1379049#L836-3 assume !(0 == ~E_4~0); 1379048#L841-3 assume !(0 == ~E_5~0); 1379047#L846-3 assume !(0 == ~E_6~0); 1379046#L851-3 assume !(0 == ~E_7~0); 1379045#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1379044#L388-27 assume 1 == ~m_pc~0; 1379042#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1379041#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1379040#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1379038#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1379037#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1379036#L407-27 assume !(1 == ~t1_pc~0); 1379035#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1379034#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1379033#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1379032#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1379031#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1379030#L426-27 assume !(1 == ~t2_pc~0); 1379029#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1379027#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1379025#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1379023#L983-27 assume !(0 != activate_threads_~tmp___1~0#1); 1379015#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1379007#L445-27 assume !(1 == ~t3_pc~0); 1379000#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1378974#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1378968#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1378961#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1378920#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1378912#L464-27 assume !(1 == ~t4_pc~0); 1378909#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1378907#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1378905#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1378903#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1378901#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1378899#L483-27 assume !(1 == ~t5_pc~0); 1378896#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1378894#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1378892#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1378890#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1378888#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1378886#L502-27 assume !(1 == ~t6_pc~0); 1378859#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1378833#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1378825#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1378808#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1378765#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1378763#L521-27 assume !(1 == ~t7_pc~0); 1378759#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1378757#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1378755#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1377657#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1377179#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1377172#L869-3 assume !(1 == ~M_E~0); 1377163#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1377158#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1377152#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1377141#L884-3 assume !(1 == ~T4_E~0); 1377128#L889-3 assume !(1 == ~T5_E~0); 1377122#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1377042#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1377038#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1377036#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1377033#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1377031#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1377029#L924-3 assume !(1 == ~E_4~0); 1377027#L929-3 assume !(1 == ~E_5~0); 1377025#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1377023#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1377021#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1377018#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1377014#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1377012#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1377009#L1209 assume !(0 == start_simulation_~tmp~3#1); 1377006#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1377003#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1377001#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1376999#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1376997#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1376995#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1376993#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1376991#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1369906#L1190-2 [2023-11-23 22:35:03,801 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:35:03,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 9 times [2023-11-23 22:35:03,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:35:03,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223639036] [2023-11-23 22:35:03,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:35:03,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:35:03,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:35:03,817 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:35:03,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:35:03,856 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:35:03,856 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:35:03,856 INFO L85 PathProgramCache]: Analyzing trace with hash -1590223557, now seen corresponding path program 1 times [2023-11-23 22:35:03,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:35:03,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279689803] [2023-11-23 22:35:03,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:35:03,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:35:03,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:35:03,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:35:03,937 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:35:03,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [279689803] [2023-11-23 22:35:03,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [279689803] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:35:03,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:35:03,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:35:03,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806217590] [2023-11-23 22:35:03,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:35:03,938 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:35:03,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:35:03,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 22:35:03,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 22:35:03,939 INFO L87 Difference]: Start difference. First operand 54548 states and 73337 transitions. cyclomatic complexity: 18805 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:35:04,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:35:04,940 INFO L93 Difference]: Finished difference Result 72900 states and 97244 transitions. [2023-11-23 22:35:04,940 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72900 states and 97244 transitions. [2023-11-23 22:35:05,177 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 72360 [2023-11-23 22:35:05,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72900 states to 72900 states and 97244 transitions. [2023-11-23 22:35:05,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72900 [2023-11-23 22:35:05,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72900 [2023-11-23 22:35:05,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72900 states and 97244 transitions. [2023-11-23 22:35:05,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:35:05,381 INFO L218 hiAutomatonCegarLoop]: Abstraction has 72900 states and 97244 transitions. [2023-11-23 22:35:05,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72900 states and 97244 transitions. [2023-11-23 22:35:05,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72900 to 54692. [2023-11-23 22:35:05,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54692 states, 54692 states have (on average 1.332699480728443) internal successors, (72888), 54691 states have internal predecessors, (72888), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:35:05,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54692 states to 54692 states and 72888 transitions. [2023-11-23 22:35:05,973 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54692 states and 72888 transitions. [2023-11-23 22:35:05,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-23 22:35:05,974 INFO L428 stractBuchiCegarLoop]: Abstraction has 54692 states and 72888 transitions. [2023-11-23 22:35:05,974 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-23 22:35:05,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54692 states and 72888 transitions. [2023-11-23 22:35:06,116 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54280 [2023-11-23 22:35:06,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:35:06,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:35:06,118 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:35:06,118 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:35:06,119 INFO L748 eck$LassoCheckResult]: Stem: 1496782#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1496783#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1497435#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1497436#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1497540#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1496931#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1496932#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1497061#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1497062#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1496829#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1496615#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1496616#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1496789#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1496790#L781 assume !(0 == ~M_E~0); 1497328#L781-2 assume !(0 == ~T1_E~0); 1497561#L786-1 assume !(0 == ~T2_E~0); 1496578#L791-1 assume !(0 == ~T3_E~0); 1496579#L796-1 assume !(0 == ~T4_E~0); 1497143#L801-1 assume !(0 == ~T5_E~0); 1497144#L806-1 assume !(0 == ~T6_E~0); 1497180#L811-1 assume !(0 == ~T7_E~0); 1496793#L816-1 assume !(0 == ~E_M~0); 1496794#L821-1 assume !(0 == ~E_1~0); 1496606#L826-1 assume !(0 == ~E_2~0); 1496607#L831-1 assume !(0 == ~E_3~0); 1496926#L836-1 assume !(0 == ~E_4~0); 1496927#L841-1 assume !(0 == ~E_5~0); 1496745#L846-1 assume !(0 == ~E_6~0); 1496746#L851-1 assume !(0 == ~E_7~0); 1496769#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1496770#L388 assume !(1 == ~m_pc~0); 1496763#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1496764#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1497354#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1496621#L967 assume !(0 != activate_threads_~tmp~1#1); 1496622#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1496552#L407 assume !(1 == ~t1_pc~0); 1496553#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1496559#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1496560#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1496594#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1497431#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1496886#L426 assume !(1 == ~t2_pc~0); 1496887#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1497465#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1497577#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1497523#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1497524#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1496975#L445 assume !(1 == ~t3_pc~0); 1496976#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1497336#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1496550#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1496551#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1497252#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1497214#L464 assume !(1 == ~t4_pc~0); 1496775#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1496641#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1496642#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1496655#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1496954#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1496955#L483 assume !(1 == ~t5_pc~0); 1497209#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1497403#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1497360#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1497361#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1496871#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1496872#L502 assume !(1 == ~t6_pc~0); 1496723#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1496680#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1496681#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1496896#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1497102#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1497374#L521 assume !(1 == ~t7_pc~0); 1497426#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1496617#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1496618#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1497419#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1497382#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1497289#L869 assume !(1 == ~M_E~0); 1496948#L869-2 assume !(1 == ~T1_E~0); 1496949#L874-1 assume !(1 == ~T2_E~0); 1497487#L879-1 assume !(1 == ~T3_E~0); 1497024#L884-1 assume !(1 == ~T4_E~0); 1496538#L889-1 assume !(1 == ~T5_E~0); 1496539#L894-1 assume !(1 == ~T6_E~0); 1496804#L899-1 assume !(1 == ~T7_E~0); 1497241#L904-1 assume !(1 == ~E_M~0); 1496972#L909-1 assume !(1 == ~E_1~0); 1496973#L914-1 assume !(1 == ~E_2~0); 1497165#L919-1 assume !(1 == ~E_3~0); 1496885#L924-1 assume !(1 == ~E_4~0); 1496715#L929-1 assume !(1 == ~E_5~0); 1496716#L934-1 assume !(1 == ~E_6~0); 1496952#L939-1 assume !(1 == ~E_7~0); 1496953#L944-1 assume { :end_inline_reset_delta_events } true; 1497373#L1190-2 [2023-11-23 22:35:06,119 INFO L750 eck$LassoCheckResult]: Loop: 1497373#L1190-2 assume !false; 1501943#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1501944#L756-1 assume !false; 1501932#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1501933#L596 assume !(0 == ~m_st~0); 1500980#L600 assume !(0 == ~t1_st~0); 1500979#L604 assume !(0 == ~t2_st~0); 1500978#L608 assume !(0 == ~t3_st~0); 1500976#L612 assume !(0 == ~t4_st~0); 1500975#L616 assume !(0 == ~t5_st~0); 1500974#L620 assume !(0 == ~t6_st~0); 1500971#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1500969#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1500967#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1500965#L653 assume !(0 != eval_~tmp~0#1); 1500962#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1500960#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1500958#L781-3 assume !(0 == ~M_E~0); 1500956#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1500954#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1500950#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1500948#L796-3 assume !(0 == ~T4_E~0); 1500946#L801-3 assume !(0 == ~T5_E~0); 1500944#L806-3 assume !(0 == ~T6_E~0); 1500941#L811-3 assume !(0 == ~T7_E~0); 1500939#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1500937#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1500935#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1500933#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1500931#L836-3 assume !(0 == ~E_4~0); 1500929#L841-3 assume !(0 == ~E_5~0); 1500927#L846-3 assume !(0 == ~E_6~0); 1500924#L851-3 assume !(0 == ~E_7~0); 1500922#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1500920#L388-27 assume 1 == ~m_pc~0; 1500917#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1500915#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1500913#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1500910#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1500908#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1500906#L407-27 assume !(1 == ~t1_pc~0); 1500904#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1500902#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1500900#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1500898#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1500896#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1500894#L426-27 assume !(1 == ~t2_pc~0); 1500892#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1500874#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1500871#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1500869#L983-27 assume !(0 != activate_threads_~tmp___1~0#1); 1500864#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1500862#L445-27 assume !(1 == ~t3_pc~0); 1500860#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1500858#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1500856#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1500854#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1500852#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1500850#L464-27 assume !(1 == ~t4_pc~0); 1500847#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1500845#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1500843#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1500841#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 1500839#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1500837#L483-27 assume !(1 == ~t5_pc~0); 1500835#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1500833#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1500831#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1500829#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1500828#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1500827#L502-27 assume !(1 == ~t6_pc~0); 1500820#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1500818#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1500816#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1500813#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1500812#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1500808#L521-27 assume 1 == ~t7_pc~0; 1500806#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1500807#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1501000#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1500797#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1500796#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1500794#L869-3 assume !(1 == ~M_E~0); 1500789#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1500787#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1500785#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1500783#L884-3 assume !(1 == ~T4_E~0); 1500781#L889-3 assume !(1 == ~T5_E~0); 1500777#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1500775#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1500773#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1500771#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1500768#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1500766#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1500764#L924-3 assume !(1 == ~E_4~0); 1500762#L929-3 assume !(1 == ~E_5~0); 1500760#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1500758#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1500756#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1500753#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1500750#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1500748#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1500745#L1209 assume !(0 == start_simulation_~tmp~3#1); 1500746#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1502023#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1502025#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1502112#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1502111#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1502110#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1502109#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1502108#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1497373#L1190-2 [2023-11-23 22:35:06,120 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:35:06,120 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 10 times [2023-11-23 22:35:06,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:35:06,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033829390] [2023-11-23 22:35:06,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:35:06,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:35:06,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:35:06,135 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:35:06,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:35:06,575 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:35:06,575 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:35:06,576 INFO L85 PathProgramCache]: Analyzing trace with hash 936176058, now seen corresponding path program 1 times [2023-11-23 22:35:06,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:35:06,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891734272] [2023-11-23 22:35:06,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:35:06,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:35:06,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:35:06,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:35:06,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:35:06,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891734272] [2023-11-23 22:35:06,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891734272] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:35:06,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:35:06,682 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:35:06,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435139906] [2023-11-23 22:35:06,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:35:06,682 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:35:06,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:35:06,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 22:35:06,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 22:35:06,684 INFO L87 Difference]: Start difference. First operand 54692 states and 72888 transitions. cyclomatic complexity: 18212 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:35:07,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:35:07,311 INFO L93 Difference]: Finished difference Result 88260 states and 116255 transitions. [2023-11-23 22:35:07,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88260 states and 116255 transitions. [2023-11-23 22:35:07,713 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 87688 [2023-11-23 22:35:07,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88260 states to 88260 states and 116255 transitions. [2023-11-23 22:35:07,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88260 [2023-11-23 22:35:08,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88260 [2023-11-23 22:35:08,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88260 states and 116255 transitions. [2023-11-23 22:35:08,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:35:08,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88260 states and 116255 transitions. [2023-11-23 22:35:08,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88260 states and 116255 transitions. [2023-11-23 22:35:09,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88260 to 55364. [2023-11-23 22:35:09,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55364 states, 55364 states have (on average 1.3211292536666426) internal successors, (73143), 55363 states have internal predecessors, (73143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:35:09,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55364 states to 55364 states and 73143 transitions. [2023-11-23 22:35:09,579 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55364 states and 73143 transitions. [2023-11-23 22:35:09,580 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-23 22:35:09,580 INFO L428 stractBuchiCegarLoop]: Abstraction has 55364 states and 73143 transitions. [2023-11-23 22:35:09,580 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-23 22:35:09,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55364 states and 73143 transitions.