./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.11.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 30e01a73 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.11.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-30e01a7 [2023-11-23 22:37:46,645 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-23 22:37:46,769 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-23 22:37:46,776 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-23 22:37:46,776 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-23 22:37:46,805 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-23 22:37:46,806 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-23 22:37:46,807 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-23 22:37:46,808 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-23 22:37:46,809 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-23 22:37:46,810 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-23 22:37:46,810 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-23 22:37:46,811 INFO L153 SettingsManager]: * Use SBE=true [2023-11-23 22:37:46,812 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-23 22:37:46,813 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-23 22:37:46,813 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-23 22:37:46,814 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-23 22:37:46,815 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-23 22:37:46,815 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-23 22:37:46,816 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-23 22:37:46,817 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-23 22:37:46,823 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-23 22:37:46,824 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-23 22:37:46,824 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-23 22:37:46,824 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-23 22:37:46,825 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-23 22:37:46,825 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-23 22:37:46,826 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-23 22:37:46,826 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-23 22:37:46,827 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-23 22:37:46,827 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-23 22:37:46,828 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-23 22:37:46,828 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-23 22:37:46,828 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-23 22:37:46,829 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-23 22:37:46,829 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-23 22:37:46,829 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-23 22:37:46,830 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-23 22:37:46,830 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 [2023-11-23 22:37:47,244 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-23 22:37:47,289 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-23 22:37:47,293 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-23 22:37:47,294 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-23 22:37:47,297 INFO L274 PluginConnector]: CDTParser initialized [2023-11-23 22:37:47,299 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/../../sv-benchmarks/c/systemc/transmitter.11.cil.c [2023-11-23 22:37:51,024 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-23 22:37:51,376 INFO L384 CDTParser]: Found 1 translation units. [2023-11-23 22:37:51,377 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/sv-benchmarks/c/systemc/transmitter.11.cil.c [2023-11-23 22:37:51,405 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/data/08d9064e8/d7e47c2a9cf6423483661a641fa58459/FLAG5ff171819 [2023-11-23 22:37:51,426 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/data/08d9064e8/d7e47c2a9cf6423483661a641fa58459 [2023-11-23 22:37:51,435 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-23 22:37:51,440 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-23 22:37:51,443 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-23 22:37:51,444 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-23 22:37:51,450 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-23 22:37:51,451 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:51,452 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@784fb594 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51, skipping insertion in model container [2023-11-23 22:37:51,453 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:51,540 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-23 22:37:51,843 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-23 22:37:51,866 INFO L202 MainTranslator]: Completed pre-run [2023-11-23 22:37:51,971 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-23 22:37:51,996 INFO L206 MainTranslator]: Completed translation [2023-11-23 22:37:51,996 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51 WrapperNode [2023-11-23 22:37:51,997 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-23 22:37:51,998 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-23 22:37:51,998 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-23 22:37:51,998 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-23 22:37:52,009 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,026 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,154 INFO L138 Inliner]: procedures = 50, calls = 64, calls flagged for inlining = 59, calls inlined = 225, statements flattened = 3461 [2023-11-23 22:37:52,154 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-23 22:37:52,155 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-23 22:37:52,156 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-23 22:37:52,156 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-23 22:37:52,169 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,169 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,180 INFO L184 PluginConnector]: Executing the observer HeapSplitter from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,230 INFO L189 HeapSplitter]: Split 2 memory accesses to 1 slices as follows [2] [2023-11-23 22:37:52,231 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,231 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,284 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,331 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,340 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,353 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,363 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-23 22:37:52,364 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-23 22:37:52,364 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-23 22:37:52,364 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-23 22:37:52,365 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (1/1) ... [2023-11-23 22:37:52,371 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-23 22:37:52,382 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/z3 [2023-11-23 22:37:52,395 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-23 22:37:52,415 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_901fe07f-112f-4c1b-8058-3091f560a6a6/bin/uautomizer-verify-zZY32mL2XJ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-23 22:37:52,502 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-23 22:37:52,503 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-23 22:37:52,503 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-23 22:37:52,503 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-23 22:37:52,715 INFO L241 CfgBuilder]: Building ICFG [2023-11-23 22:37:52,717 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-23 22:37:54,981 INFO L282 CfgBuilder]: Performing block encoding [2023-11-23 22:37:55,037 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-23 22:37:55,037 INFO L309 CfgBuilder]: Removed 15 assume(true) statements. [2023-11-23 22:37:55,040 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:37:55 BoogieIcfgContainer [2023-11-23 22:37:55,040 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-23 22:37:55,042 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-23 22:37:55,042 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-23 22:37:55,047 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-23 22:37:55,048 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-23 22:37:55,048 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 10:37:51" (1/3) ... [2023-11-23 22:37:55,049 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@375de1ff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 10:37:55, skipping insertion in model container [2023-11-23 22:37:55,049 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-23 22:37:55,051 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:37:51" (2/3) ... [2023-11-23 22:37:55,054 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@375de1ff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 10:37:55, skipping insertion in model container [2023-11-23 22:37:55,054 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-23 22:37:55,054 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:37:55" (3/3) ... [2023-11-23 22:37:55,055 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.11.cil.c [2023-11-23 22:37:55,178 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-23 22:37:55,179 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-23 22:37:55,179 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-23 22:37:55,179 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-23 22:37:55,179 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-23 22:37:55,179 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-23 22:37:55,179 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-23 22:37:55,180 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-23 22:37:55,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:55,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1343 [2023-11-23 22:37:55,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:55,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:55,323 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:55,323 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:55,323 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-23 22:37:55,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:55,349 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1343 [2023-11-23 22:37:55,349 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:55,349 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:55,356 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:55,357 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:55,369 INFO L748 eck$LassoCheckResult]: Stem: 227#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1380#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1124#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1376#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 510#L761true assume !(1 == ~m_i~0);~m_st~0 := 2; 528#L761-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 424#L766-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 355#L771-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 197#L776-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18#L781-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1480#L786-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 39#L791-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 657#L796-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 621#L801-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 665#L806-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1359#L811-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 255#L816-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1175#L1090true assume !(0 == ~M_E~0); 280#L1090-2true assume !(0 == ~T1_E~0); 1333#L1095-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 801#L1100-1true assume !(0 == ~T3_E~0); 828#L1105-1true assume !(0 == ~T4_E~0); 151#L1110-1true assume !(0 == ~T5_E~0); 375#L1115-1true assume !(0 == ~T6_E~0); 601#L1120-1true assume !(0 == ~T7_E~0); 1368#L1125-1true assume !(0 == ~T8_E~0); 1360#L1130-1true assume !(0 == ~T9_E~0); 826#L1135-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 258#L1140-1true assume !(0 == ~T11_E~0); 757#L1145-1true assume !(0 == ~E_1~0); 796#L1150-1true assume !(0 == ~E_2~0); 364#L1155-1true assume !(0 == ~E_3~0); 1344#L1160-1true assume !(0 == ~E_4~0); 429#L1165-1true assume !(0 == ~E_5~0); 1097#L1170-1true assume !(0 == ~E_6~0); 1285#L1175-1true assume 0 == ~E_7~0;~E_7~0 := 1; 481#L1180-1true assume !(0 == ~E_8~0); 914#L1185-1true assume !(0 == ~E_9~0); 256#L1190-1true assume !(0 == ~E_10~0); 491#L1195-1true assume !(0 == ~E_11~0); 1041#L1200-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371#L525true assume !(1 == ~m_pc~0); 60#L525-2true is_master_triggered_~__retres1~0#1 := 0; 1035#L536true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 925#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 894#L1350true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 248#L1350-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 532#L544true assume 1 == ~t1_pc~0; 410#L545true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 754#L555true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163#L1358true assume !(0 != activate_threads_~tmp___0~0#1); 578#L1358-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1030#L563true assume !(1 == ~t2_pc~0); 744#L563-2true is_transmit2_triggered_~__retres1~2#1 := 0; 69#L574true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 362#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 295#L1366true assume !(0 != activate_threads_~tmp___1~0#1); 643#L1366-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 755#L582true assume 1 == ~t3_pc~0; 136#L583true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1246#L593true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1108#L1374true assume !(0 != activate_threads_~tmp___2~0#1); 103#L1374-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1404#L601true assume !(1 == ~t4_pc~0); 847#L601-2true is_transmit4_triggered_~__retres1~4#1 := 0; 376#L612true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 765#L1382true assume !(0 != activate_threads_~tmp___3~0#1); 1411#L1382-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1218#L620true assume 1 == ~t5_pc~0; 83#L621true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 662#L631true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 932#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1479#L1390true assume !(0 != activate_threads_~tmp___4~0#1); 1274#L1390-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1372#L639true assume !(1 == ~t6_pc~0); 599#L639-2true is_transmit6_triggered_~__retres1~6#1 := 0; 315#L650true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 347#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1269#L1398true assume !(0 != activate_threads_~tmp___5~0#1); 379#L1398-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 961#L658true assume 1 == ~t7_pc~0; 600#L659true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1293#L669true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1396#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 704#L1406true assume !(0 != activate_threads_~tmp___6~0#1); 251#L1406-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 383#L677true assume 1 == ~t8_pc~0; 883#L678true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 143#L688true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 849#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 292#L1414true assume !(0 != activate_threads_~tmp___7~0#1); 884#L1414-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 996#L696true assume !(1 == ~t9_pc~0); 588#L696-2true is_transmit9_triggered_~__retres1~9#1 := 0; 672#L707true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 416#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 605#L1422true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 805#L1422-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1152#L715true assume 1 == ~t10_pc~0; 814#L716true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 690#L726true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 520#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 781#L1430true assume !(0 != activate_threads_~tmp___9~0#1); 477#L1430-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 141#L734true assume !(1 == ~t11_pc~0); 430#L734-2true is_transmit11_triggered_~__retres1~11#1 := 0; 483#L745true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 711#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12#L1438true assume !(0 != activate_threads_~tmp___10~0#1); 663#L1438-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1214#L1213true assume !(1 == ~M_E~0); 475#L1213-2true assume !(1 == ~T1_E~0); 981#L1218-1true assume !(1 == ~T2_E~0); 29#L1223-1true assume !(1 == ~T3_E~0); 459#L1228-1true assume !(1 == ~T4_E~0); 1275#L1233-1true assume !(1 == ~T5_E~0); 1460#L1238-1true assume !(1 == ~T6_E~0); 764#L1243-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1418#L1248-1true assume !(1 == ~T8_E~0); 811#L1253-1true assume !(1 == ~T9_E~0); 1112#L1258-1true assume !(1 == ~T10_E~0); 789#L1263-1true assume !(1 == ~T11_E~0); 1160#L1268-1true assume !(1 == ~E_1~0); 617#L1273-1true assume !(1 == ~E_2~0); 1256#L1278-1true assume !(1 == ~E_3~0); 314#L1283-1true assume 1 == ~E_4~0;~E_4~0 := 2; 1306#L1288-1true assume !(1 == ~E_5~0); 939#L1293-1true assume !(1 == ~E_6~0); 890#L1298-1true assume !(1 == ~E_7~0); 647#L1303-1true assume !(1 == ~E_8~0); 321#L1308-1true assume !(1 == ~E_9~0); 260#L1313-1true assume !(1 == ~E_10~0); 1385#L1318-1true assume !(1 == ~E_11~0); 265#L1323-1true assume { :end_inline_reset_delta_events } true; 1165#L1644-2true [2023-11-23 22:37:55,373 INFO L750 eck$LassoCheckResult]: Loop: 1165#L1644-2true assume !false; 702#L1645true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 208#L1065-1true assume !true; 857#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 543#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 966#L1090-3true assume !(0 == ~M_E~0); 1054#L1090-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1388#L1095-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 999#L1100-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1267#L1105-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 193#L1110-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1102#L1115-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 356#L1120-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 762#L1125-3true assume !(0 == ~T8_E~0); 1140#L1130-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1305#L1135-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 308#L1140-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 43#L1145-3true assume 0 == ~E_1~0;~E_1~0 := 1; 497#L1150-3true assume 0 == ~E_2~0;~E_2~0 := 1; 104#L1155-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1440#L1160-3true assume 0 == ~E_4~0;~E_4~0 := 1; 299#L1165-3true assume !(0 == ~E_5~0); 1494#L1170-3true assume 0 == ~E_6~0;~E_6~0 := 1; 573#L1175-3true assume 0 == ~E_7~0;~E_7~0 := 1; 250#L1180-3true assume 0 == ~E_8~0;~E_8~0 := 1; 117#L1185-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1308#L1190-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1117#L1195-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1492#L1200-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446#L525-36true assume 1 == ~m_pc~0; 1121#L526-12true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 168#L536-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1127#is_master_triggered_returnLabel#13true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 329#L1350-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 572#L1350-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282#L544-36true assume !(1 == ~t1_pc~0); 936#L544-38true is_transmit1_triggered_~__retres1~1#1 := 0; 679#L555-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1125#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1286#L1358-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1093#L1358-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 927#L563-36true assume !(1 == ~t2_pc~0); 974#L563-38true is_transmit2_triggered_~__retres1~2#1 := 0; 41#L574-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 904#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1284#L1366-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 457#L1366-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1387#L582-36true assume 1 == ~t3_pc~0; 350#L583-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 509#L593-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 411#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 670#L1374-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 482#L1374-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 443#L601-36true assume 1 == ~t4_pc~0; 368#L602-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1475#L612-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 557#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1064#L1382-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1208#L1382-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 911#L620-36true assume !(1 == ~t5_pc~0); 1472#L620-38true is_transmit5_triggered_~__retres1~5#1 := 0; 747#L631-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1075#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 382#L1390-36true assume !(0 != activate_threads_~tmp___4~0#1); 174#L1390-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65#L639-36true assume !(1 == ~t6_pc~0); 1429#L639-38true is_transmit6_triggered_~__retres1~6#1 := 0; 85#L650-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 387#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 203#L1398-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 603#L1398-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1207#L658-36true assume 1 == ~t7_pc~0; 123#L659-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1032#L669-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1038#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61#L1406-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 733#L1406-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 950#L677-36true assume 1 == ~t8_pc~0; 1110#L678-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 644#L688-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 645#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1205#L1414-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 558#L1414-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1114#L696-36true assume !(1 == ~t9_pc~0); 1330#L696-38true is_transmit9_triggered_~__retres1~9#1 := 0; 846#L707-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 436#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1033#L1422-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 574#L1422-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1281#L715-36true assume !(1 == ~t10_pc~0); 545#L715-38true is_transmit10_triggered_~__retres1~10#1 := 0; 13#L726-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 320#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2#L1430-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1079#L1430-38true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 200#L734-36true assume !(1 == ~t11_pc~0); 49#L734-38true is_transmit11_triggered_~__retres1~11#1 := 0; 209#L745-12true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1331#is_transmit11_triggered_returnLabel#13true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9#L1438-36true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 625#L1438-38true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1119#L1213-3true assume 1 == ~M_E~0;~M_E~0 := 2; 361#L1213-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 730#L1218-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 225#L1223-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 770#L1228-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 332#L1233-3true assume !(1 == ~T5_E~0); 1295#L1238-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 507#L1243-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1063#L1248-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1423#L1253-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1070#L1258-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 216#L1263-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1015#L1268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1040#L1273-3true assume !(1 == ~E_2~0); 1473#L1278-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1043#L1283-3true assume 1 == ~E_4~0;~E_4~0 := 2; 428#L1288-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1316#L1293-3true assume 1 == ~E_6~0;~E_6~0 := 2; 328#L1298-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1167#L1303-3true assume 1 == ~E_8~0;~E_8~0 := 2; 699#L1308-3true assume 1 == ~E_9~0;~E_9~0 := 2; 326#L1313-3true assume !(1 == ~E_10~0); 1066#L1318-3true assume 1 == ~E_11~0;~E_11~0 := 2; 217#L1323-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1450#L829-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 439#L891-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 316#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1451#L1663true assume !(0 == start_simulation_~tmp~3#1); 1355#L1663-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 602#L829-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 526#L891-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 76#L1618true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 254#L1625true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 560#stop_simulation_returnLabel#1true start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1194#L1676true assume !(0 != start_simulation_~tmp___0~1#1); 1165#L1644-2true [2023-11-23 22:37:55,382 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:55,382 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 1 times [2023-11-23 22:37:55,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:55,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [98157211] [2023-11-23 22:37:55,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:55,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:55,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:55,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:55,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:55,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [98157211] [2023-11-23 22:37:55,809 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [98157211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:55,809 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:55,810 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:55,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2010480100] [2023-11-23 22:37:55,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:55,817 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:55,818 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:55,818 INFO L85 PathProgramCache]: Analyzing trace with hash -1163004199, now seen corresponding path program 1 times [2023-11-23 22:37:55,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:55,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510150136] [2023-11-23 22:37:55,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:55,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:55,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:55,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:55,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:55,894 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510150136] [2023-11-23 22:37:55,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [510150136] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:55,895 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:55,895 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:37:55,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864652862] [2023-11-23 22:37:55,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:55,897 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:55,898 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:55,933 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-23 22:37:55,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-23 22:37:55,940 INFO L87 Difference]: Start difference. First operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 68.5) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:56,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:56,015 INFO L93 Difference]: Finished difference Result 1494 states and 2211 transitions. [2023-11-23 22:37:56,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1494 states and 2211 transitions. [2023-11-23 22:37:56,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:56,063 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1494 states to 1488 states and 2205 transitions. [2023-11-23 22:37:56,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:56,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:56,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2205 transitions. [2023-11-23 22:37:56,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:56,081 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2023-11-23 22:37:56,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2205 transitions. [2023-11-23 22:37:56,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:56,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4818548387096775) internal successors, (2205), 1487 states have internal predecessors, (2205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:56,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2205 transitions. [2023-11-23 22:37:56,211 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2023-11-23 22:37:56,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-23 22:37:56,221 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2023-11-23 22:37:56,222 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-23 22:37:56,222 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2205 transitions. [2023-11-23 22:37:56,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:56,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:56,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:56,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:56,244 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:56,246 INFO L748 eck$LassoCheckResult]: Stem: 3441#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 3442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3891#L761 assume !(1 == ~m_i~0);~m_st~0 := 2; 3892#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3763#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3656#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3385#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3033#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3034#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3078#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3079#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4023#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4024#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4066#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3482#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3483#L1090 assume !(0 == ~M_E~0); 3528#L1090-2 assume !(0 == ~T1_E~0); 3529#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4214#L1100-1 assume !(0 == ~T3_E~0); 4215#L1105-1 assume !(0 == ~T4_E~0); 3306#L1110-1 assume !(0 == ~T5_E~0); 3307#L1115-1 assume !(0 == ~T6_E~0); 3692#L1120-1 assume !(0 == ~T7_E~0); 4000#L1125-1 assume !(0 == ~T8_E~0); 4472#L1130-1 assume !(0 == ~T9_E~0); 4235#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3487#L1140-1 assume !(0 == ~T11_E~0); 3488#L1145-1 assume !(0 == ~E_1~0); 4169#L1150-1 assume !(0 == ~E_2~0); 3669#L1155-1 assume !(0 == ~E_3~0); 3670#L1160-1 assume !(0 == ~E_4~0); 3768#L1165-1 assume !(0 == ~E_5~0); 3769#L1170-1 assume !(0 == ~E_6~0); 4407#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3849#L1180-1 assume !(0 == ~E_8~0); 3850#L1185-1 assume !(0 == ~E_9~0); 3484#L1190-1 assume !(0 == ~E_10~0); 3485#L1195-1 assume !(0 == ~E_11~0); 3865#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3689#L525 assume !(1 == ~m_pc~0); 3123#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3124#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4309#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4284#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3474#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3475#L544 assume 1 == ~t1_pc~0; 3744#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3691#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3103#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3329#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3969#L563 assume !(1 == ~t2_pc~0); 4155#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3142#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3143#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3556#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3557#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4047#L582 assume 1 == ~t3_pc~0; 3275#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3276#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3025#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3026#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3211#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3212#L601 assume !(1 == ~t4_pc~0); 4181#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3693#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3225#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3226#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4176#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4448#L620 assume 1 == ~t5_pc~0; 3174#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3175#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4063#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4315#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4457#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4458#L639 assume !(1 == ~t6_pc~0); 3998#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3593#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3594#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3642#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3699#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3700#L658 assume 1 == ~t7_pc~0; 3999#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3916#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4463#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4116#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3477#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3478#L677 assume 1 == ~t8_pc~0; 3707#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3288#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3289#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3549#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3550#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4276#L696 assume !(1 == ~t9_pc~0); 3983#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3984#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3754#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3755#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4005#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4218#L715 assume 1 == ~t10_pc~0; 4225#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4097#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3903#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3904#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3843#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3282#L734 assume !(1 == ~t11_pc~0); 3283#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3770#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3854#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3023#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3024#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4064#L1213 assume !(1 == ~M_E~0); 3841#L1213-2 assume !(1 == ~T1_E~0); 3842#L1218-1 assume !(1 == ~T2_E~0); 3056#L1223-1 assume !(1 == ~T3_E~0); 3057#L1228-1 assume !(1 == ~T4_E~0); 3816#L1233-1 assume !(1 == ~T5_E~0); 4459#L1238-1 assume !(1 == ~T6_E~0); 4174#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4175#L1248-1 assume !(1 == ~T8_E~0); 4221#L1253-1 assume !(1 == ~T9_E~0); 4222#L1258-1 assume !(1 == ~T10_E~0); 4197#L1263-1 assume !(1 == ~T11_E~0); 4198#L1268-1 assume !(1 == ~E_1~0); 4018#L1273-1 assume !(1 == ~E_2~0); 4019#L1278-1 assume !(1 == ~E_3~0); 3589#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3590#L1288-1 assume !(1 == ~E_5~0); 4320#L1293-1 assume !(1 == ~E_6~0); 4280#L1298-1 assume !(1 == ~E_7~0); 4051#L1303-1 assume !(1 == ~E_8~0); 3599#L1308-1 assume !(1 == ~E_9~0); 3491#L1313-1 assume !(1 == ~E_10~0); 3492#L1318-1 assume !(1 == ~E_11~0); 3502#L1323-1 assume { :end_inline_reset_delta_events } true; 3503#L1644-2 [2023-11-23 22:37:56,251 INFO L750 eck$LassoCheckResult]: Loop: 3503#L1644-2 assume !false; 4113#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3407#L1065-1 assume !false; 3408#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4455#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3138#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3715#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3604#L906 assume !(0 != eval_~tmp~0#1); 3606#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3926#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3927#L1090-3 assume !(0 == ~M_E~0); 4335#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4392#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4357#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4358#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3380#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3381#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3657#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3658#L1125-3 assume !(0 == ~T8_E~0); 4173#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4430#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3581#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3090#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3091#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3214#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3215#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3562#L1165-3 assume !(0 == ~E_5~0); 3563#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3962#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3476#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3240#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3241#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4418#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4419#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3797#L525-36 assume !(1 == ~m_pc~0); 3798#L525-38 is_master_triggered_~__retres1~0#1 := 0; 3338#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3339#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3614#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3525#L544-36 assume 1 == ~t1_pc~0; 3526#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4085#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4086#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4423#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4405#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4310#L563-36 assume !(1 == ~t2_pc~0); 3328#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3086#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3087#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4291#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3813#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3814#L582-36 assume !(1 == ~t3_pc~0); 3648#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3647#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3745#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3746#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3851#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3791#L601-36 assume 1 == ~t4_pc~0; 3677#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3678#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3943#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3944#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4396#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4297#L620-36 assume 1 == ~t5_pc~0; 3728#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3729#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4158#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3704#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 3347#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3134#L639-36 assume !(1 == ~t6_pc~0); 3136#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3172#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3173#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3397#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3398#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4003#L658-36 assume !(1 == ~t7_pc~0); 3147#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3148#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4382#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3125#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3126#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4147#L677-36 assume 1 == ~t8_pc~0; 4324#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3919#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4048#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4049#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3945#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3946#L696-36 assume 1 == ~t9_pc~0; 3837#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3838#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3779#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3780#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3963#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3964#L715-36 assume !(1 == ~t10_pc~0); 3925#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3021#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3022#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2999#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3000#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3390#L734-36 assume !(1 == ~t11_pc~0); 3100#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 3101#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3406#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3015#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3016#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4027#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3663#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3664#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3438#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3439#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3618#L1233-3 assume !(1 == ~T5_E~0); 3619#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3888#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3889#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4395#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4397#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3420#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3421#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4370#L1273-3 assume !(1 == ~E_2~0); 4385#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4387#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3766#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3767#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3612#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3613#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4109#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3609#L1313-3 assume !(1 == ~E_10~0); 3610#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3422#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3423#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3365#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3591#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3592#L1663 assume !(0 == start_simulation_~tmp~3#1); 3263#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4001#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3209#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3092#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3093#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3158#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3481#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3947#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3503#L1644-2 [2023-11-23 22:37:56,252 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:56,253 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 2 times [2023-11-23 22:37:56,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:56,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [653114848] [2023-11-23 22:37:56,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:56,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:56,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:56,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:56,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:56,362 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [653114848] [2023-11-23 22:37:56,362 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [653114848] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:56,362 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:56,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:56,363 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59782155] [2023-11-23 22:37:56,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:56,364 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:56,364 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:56,365 INFO L85 PathProgramCache]: Analyzing trace with hash -825746646, now seen corresponding path program 1 times [2023-11-23 22:37:56,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:56,365 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456761884] [2023-11-23 22:37:56,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:56,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:56,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:56,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:56,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:56,625 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456761884] [2023-11-23 22:37:56,625 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456761884] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:56,625 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:56,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:56,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [826847772] [2023-11-23 22:37:56,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:56,626 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:56,627 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:56,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:56,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:56,628 INFO L87 Difference]: Start difference. First operand 1488 states and 2205 transitions. cyclomatic complexity: 718 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:56,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:56,698 INFO L93 Difference]: Finished difference Result 1488 states and 2204 transitions. [2023-11-23 22:37:56,699 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2204 transitions. [2023-11-23 22:37:56,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:56,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2204 transitions. [2023-11-23 22:37:56,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:56,734 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:56,735 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2204 transitions. [2023-11-23 22:37:56,738 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:56,739 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2023-11-23 22:37:56,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2204 transitions. [2023-11-23 22:37:56,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:56,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4811827956989247) internal successors, (2204), 1487 states have internal predecessors, (2204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:56,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2204 transitions. [2023-11-23 22:37:56,782 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2023-11-23 22:37:56,782 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:37:56,784 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2023-11-23 22:37:56,784 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-23 22:37:56,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2204 transitions. [2023-11-23 22:37:56,801 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:56,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:56,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:56,811 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:56,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:56,812 INFO L748 eck$LassoCheckResult]: Stem: 6424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 6425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7406#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7407#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6874#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 6875#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6746#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6639#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6368#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6016#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6017#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6061#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6062#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7004#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7005#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7049#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6465#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6466#L1090 assume !(0 == ~M_E~0); 6508#L1090-2 assume !(0 == ~T1_E~0); 6509#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7196#L1100-1 assume !(0 == ~T3_E~0); 7197#L1105-1 assume !(0 == ~T4_E~0); 6288#L1110-1 assume !(0 == ~T5_E~0); 6289#L1115-1 assume !(0 == ~T6_E~0); 6675#L1120-1 assume !(0 == ~T7_E~0); 6983#L1125-1 assume !(0 == ~T8_E~0); 7455#L1130-1 assume !(0 == ~T9_E~0); 7218#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6470#L1140-1 assume !(0 == ~T11_E~0); 6471#L1145-1 assume !(0 == ~E_1~0); 7152#L1150-1 assume !(0 == ~E_2~0); 6652#L1155-1 assume !(0 == ~E_3~0); 6653#L1160-1 assume !(0 == ~E_4~0); 6751#L1165-1 assume !(0 == ~E_5~0); 6752#L1170-1 assume !(0 == ~E_6~0); 7390#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6832#L1180-1 assume !(0 == ~E_8~0); 6833#L1185-1 assume !(0 == ~E_9~0); 6467#L1190-1 assume !(0 == ~E_10~0); 6468#L1195-1 assume !(0 == ~E_11~0); 6848#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6667#L525 assume !(1 == ~m_pc~0); 6106#L525-2 is_master_triggered_~__retres1~0#1 := 0; 6107#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7292#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7265#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6457#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6458#L544 assume 1 == ~t1_pc~0; 6727#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6674#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6080#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6081#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 6312#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6952#L563 assume !(1 == ~t2_pc~0); 7138#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6125#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6126#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6536#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 6537#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7030#L582 assume 1 == ~t3_pc~0; 6256#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6257#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6009#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 6194#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6195#L601 assume !(1 == ~t4_pc~0); 7164#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6676#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6205#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 7159#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7431#L620 assume 1 == ~t5_pc~0; 6153#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6154#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7046#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7297#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 7440#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7441#L639 assume !(1 == ~t6_pc~0); 6981#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6574#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6575#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6625#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 6682#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6683#L658 assume 1 == ~t7_pc~0; 6982#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6898#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7446#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7098#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 6460#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6461#L677 assume 1 == ~t8_pc~0; 6688#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6271#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6272#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6532#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 6533#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7259#L696 assume !(1 == ~t9_pc~0); 6964#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6965#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6737#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6738#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6988#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7201#L715 assume 1 == ~t10_pc~0; 7208#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7080#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6886#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6887#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 6826#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6265#L734 assume !(1 == ~t11_pc~0); 6266#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 6753#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6835#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6004#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 6005#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7047#L1213 assume !(1 == ~M_E~0); 6823#L1213-2 assume !(1 == ~T1_E~0); 6824#L1218-1 assume !(1 == ~T2_E~0); 6039#L1223-1 assume !(1 == ~T3_E~0); 6040#L1228-1 assume !(1 == ~T4_E~0); 6799#L1233-1 assume !(1 == ~T5_E~0); 7442#L1238-1 assume !(1 == ~T6_E~0); 7157#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7158#L1248-1 assume !(1 == ~T8_E~0); 7204#L1253-1 assume !(1 == ~T9_E~0); 7205#L1258-1 assume !(1 == ~T10_E~0); 7180#L1263-1 assume !(1 == ~T11_E~0); 7181#L1268-1 assume !(1 == ~E_1~0); 7001#L1273-1 assume !(1 == ~E_2~0); 7002#L1278-1 assume !(1 == ~E_3~0); 6572#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6573#L1288-1 assume !(1 == ~E_5~0); 7303#L1293-1 assume !(1 == ~E_6~0); 7263#L1298-1 assume !(1 == ~E_7~0); 7034#L1303-1 assume !(1 == ~E_8~0); 6582#L1308-1 assume !(1 == ~E_9~0); 6474#L1313-1 assume !(1 == ~E_10~0); 6475#L1318-1 assume !(1 == ~E_11~0); 6482#L1323-1 assume { :end_inline_reset_delta_events } true; 6483#L1644-2 [2023-11-23 22:37:56,813 INFO L750 eck$LassoCheckResult]: Loop: 6483#L1644-2 assume !false; 7096#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6389#L1065-1 assume !false; 6390#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7438#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6121#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6698#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6587#L906 assume !(0 != eval_~tmp~0#1); 6589#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6908#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6909#L1090-3 assume !(0 == ~M_E~0); 7318#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7375#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7340#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7341#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6363#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6364#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6640#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6641#L1125-3 assume !(0 == ~T8_E~0); 7156#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7413#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6562#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 6071#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6072#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6196#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6197#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6545#L1165-3 assume !(0 == ~E_5~0); 6546#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6945#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6459#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6220#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6221#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7401#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7402#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6780#L525-36 assume !(1 == ~m_pc~0); 6781#L525-38 is_master_triggered_~__retres1~0#1 := 0; 6321#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6322#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6597#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6598#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6511#L544-36 assume 1 == ~t1_pc~0; 6512#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7068#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7069#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7408#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7388#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7293#L563-36 assume 1 == ~t2_pc~0; 6310#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6069#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6070#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7274#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6796#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6797#L582-36 assume 1 == ~t3_pc~0; 6629#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6630#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6728#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6729#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6834#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6774#L601-36 assume 1 == ~t4_pc~0; 6660#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6661#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6926#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6927#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7379#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7280#L620-36 assume 1 == ~t5_pc~0; 6713#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6714#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7141#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6687#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 6330#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6117#L639-36 assume 1 == ~t6_pc~0; 6118#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6158#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6159#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6380#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6381#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6986#L658-36 assume !(1 == ~t7_pc~0); 6130#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 6131#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7365#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6108#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6109#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7130#L677-36 assume !(1 == ~t8_pc~0); 6901#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6902#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7031#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7032#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6928#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6929#L696-36 assume 1 == ~t9_pc~0; 6820#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6821#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6762#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6763#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6946#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6947#L715-36 assume 1 == ~t10_pc~0; 7091#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6006#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6007#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5982#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5983#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6373#L734-36 assume !(1 == ~t11_pc~0); 6085#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 6086#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6391#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5998#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5999#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7010#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6648#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6649#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6421#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6422#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6601#L1233-3 assume !(1 == ~T5_E~0); 6602#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6871#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6872#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7378#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7380#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6404#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6405#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7353#L1273-3 assume !(1 == ~E_2~0); 7368#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7370#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6749#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6750#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6595#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6596#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7092#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6592#L1313-3 assume !(1 == ~E_10~0); 6593#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 6406#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6407#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6348#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6576#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6577#L1663 assume !(0 == start_simulation_~tmp~3#1); 6246#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6984#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6192#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6078#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 6079#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6141#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6464#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6930#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 6483#L1644-2 [2023-11-23 22:37:56,816 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:56,817 INFO L85 PathProgramCache]: Analyzing trace with hash -456355416, now seen corresponding path program 1 times [2023-11-23 22:37:56,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:56,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109779293] [2023-11-23 22:37:56,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:56,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:56,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:56,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:56,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:56,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [109779293] [2023-11-23 22:37:56,897 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [109779293] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:56,897 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:56,897 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:56,897 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141801767] [2023-11-23 22:37:56,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:56,898 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:56,899 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:56,899 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 1 times [2023-11-23 22:37:56,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:56,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864362715] [2023-11-23 22:37:56,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:56,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:56,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:57,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:57,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:57,001 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864362715] [2023-11-23 22:37:57,001 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864362715] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:57,001 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:57,001 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:57,002 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [271937976] [2023-11-23 22:37:57,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:57,002 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:57,003 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:57,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:57,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:57,003 INFO L87 Difference]: Start difference. First operand 1488 states and 2204 transitions. cyclomatic complexity: 717 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:57,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:57,050 INFO L93 Difference]: Finished difference Result 1488 states and 2203 transitions. [2023-11-23 22:37:57,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2203 transitions. [2023-11-23 22:37:57,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:57,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2203 transitions. [2023-11-23 22:37:57,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:57,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:57,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2203 transitions. [2023-11-23 22:37:57,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:57,080 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2023-11-23 22:37:57,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2203 transitions. [2023-11-23 22:37:57,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:57,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.480510752688172) internal successors, (2203), 1487 states have internal predecessors, (2203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:57,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2203 transitions. [2023-11-23 22:37:57,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2023-11-23 22:37:57,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:37:57,153 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2023-11-23 22:37:57,153 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-23 22:37:57,154 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2203 transitions. [2023-11-23 22:37:57,163 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:57,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:57,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:57,166 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:57,166 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:57,167 INFO L748 eck$LassoCheckResult]: Stem: 9407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 9408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10389#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10390#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9857#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 9858#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9729#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9622#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9351#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8999#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9000#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9044#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9045#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9987#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9988#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10032#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9448#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9449#L1090 assume !(0 == ~M_E~0); 9491#L1090-2 assume !(0 == ~T1_E~0); 9492#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10180#L1100-1 assume !(0 == ~T3_E~0); 10181#L1105-1 assume !(0 == ~T4_E~0); 9272#L1110-1 assume !(0 == ~T5_E~0); 9273#L1115-1 assume !(0 == ~T6_E~0); 9658#L1120-1 assume !(0 == ~T7_E~0); 9966#L1125-1 assume !(0 == ~T8_E~0); 10438#L1130-1 assume !(0 == ~T9_E~0); 10201#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9453#L1140-1 assume !(0 == ~T11_E~0); 9454#L1145-1 assume !(0 == ~E_1~0); 10135#L1150-1 assume !(0 == ~E_2~0); 9635#L1155-1 assume !(0 == ~E_3~0); 9636#L1160-1 assume !(0 == ~E_4~0); 9734#L1165-1 assume !(0 == ~E_5~0); 9735#L1170-1 assume !(0 == ~E_6~0); 10373#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9815#L1180-1 assume !(0 == ~E_8~0); 9816#L1185-1 assume !(0 == ~E_9~0); 9450#L1190-1 assume !(0 == ~E_10~0); 9451#L1195-1 assume !(0 == ~E_11~0); 9831#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9655#L525 assume !(1 == ~m_pc~0); 9089#L525-2 is_master_triggered_~__retres1~0#1 := 0; 9090#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10275#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10250#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9440#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9441#L544 assume 1 == ~t1_pc~0; 9710#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9657#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9068#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9069#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 9295#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9935#L563 assume !(1 == ~t2_pc~0); 10121#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9108#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9109#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9519#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 9520#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10013#L582 assume 1 == ~t3_pc~0; 9241#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9242#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8991#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8992#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 9177#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9178#L601 assume !(1 == ~t4_pc~0); 10147#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9659#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9191#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9192#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 10142#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10414#L620 assume 1 == ~t5_pc~0; 9140#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9141#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10029#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10281#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 10423#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10424#L639 assume !(1 == ~t6_pc~0); 9964#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9559#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9560#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9608#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 9665#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9666#L658 assume 1 == ~t7_pc~0; 9965#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9882#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10429#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10082#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 9443#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9444#L677 assume 1 == ~t8_pc~0; 9673#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9254#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9255#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9515#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 9516#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10242#L696 assume !(1 == ~t9_pc~0); 9949#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9950#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9720#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9721#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9971#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10184#L715 assume 1 == ~t10_pc~0; 10191#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10063#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9869#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9870#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 9809#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9248#L734 assume !(1 == ~t11_pc~0); 9249#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 9736#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9818#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8989#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 8990#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10030#L1213 assume !(1 == ~M_E~0); 9807#L1213-2 assume !(1 == ~T1_E~0); 9808#L1218-1 assume !(1 == ~T2_E~0); 9022#L1223-1 assume !(1 == ~T3_E~0); 9023#L1228-1 assume !(1 == ~T4_E~0); 9782#L1233-1 assume !(1 == ~T5_E~0); 10425#L1238-1 assume !(1 == ~T6_E~0); 10140#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10141#L1248-1 assume !(1 == ~T8_E~0); 10187#L1253-1 assume !(1 == ~T9_E~0); 10188#L1258-1 assume !(1 == ~T10_E~0); 10163#L1263-1 assume !(1 == ~T11_E~0); 10164#L1268-1 assume !(1 == ~E_1~0); 9984#L1273-1 assume !(1 == ~E_2~0); 9985#L1278-1 assume !(1 == ~E_3~0); 9555#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9556#L1288-1 assume !(1 == ~E_5~0); 10286#L1293-1 assume !(1 == ~E_6~0); 10246#L1298-1 assume !(1 == ~E_7~0); 10017#L1303-1 assume !(1 == ~E_8~0); 9565#L1308-1 assume !(1 == ~E_9~0); 9457#L1313-1 assume !(1 == ~E_10~0); 9458#L1318-1 assume !(1 == ~E_11~0); 9468#L1323-1 assume { :end_inline_reset_delta_events } true; 9469#L1644-2 [2023-11-23 22:37:57,167 INFO L750 eck$LassoCheckResult]: Loop: 9469#L1644-2 assume !false; 10079#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9373#L1065-1 assume !false; 9374#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10421#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9104#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9681#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9570#L906 assume !(0 != eval_~tmp~0#1); 9572#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9892#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9893#L1090-3 assume !(0 == ~M_E~0); 10301#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10358#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10323#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10324#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9346#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9347#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9623#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9624#L1125-3 assume !(0 == ~T8_E~0); 10139#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10396#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9547#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9056#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9057#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9180#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9181#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9528#L1165-3 assume !(0 == ~E_5~0); 9529#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9928#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9442#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9204#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9205#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10384#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10385#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9763#L525-36 assume !(1 == ~m_pc~0); 9764#L525-38 is_master_triggered_~__retres1~0#1 := 0; 9309#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9310#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9580#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9581#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9494#L544-36 assume 1 == ~t1_pc~0; 9495#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10051#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10052#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10391#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10372#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10276#L563-36 assume 1 == ~t2_pc~0; 9293#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9049#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9050#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10257#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9779#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9780#L582-36 assume 1 == ~t3_pc~0; 9612#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9613#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9711#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9712#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9817#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9754#L601-36 assume 1 == ~t4_pc~0; 9643#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9644#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9909#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9910#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10362#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10263#L620-36 assume !(1 == ~t5_pc~0); 9696#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9695#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10124#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9670#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 9313#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9100#L639-36 assume 1 == ~t6_pc~0; 9101#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9138#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9139#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9363#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9364#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9969#L658-36 assume !(1 == ~t7_pc~0); 9113#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 9114#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10348#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9091#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9092#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10113#L677-36 assume 1 == ~t8_pc~0; 10290#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9885#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10014#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10015#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9911#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9912#L696-36 assume 1 == ~t9_pc~0; 9803#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9804#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9745#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9746#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9929#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9930#L715-36 assume !(1 == ~t10_pc~0); 9891#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 8987#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8988#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8965#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8966#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9356#L734-36 assume !(1 == ~t11_pc~0); 9066#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 9067#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9372#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8981#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8982#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9993#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9629#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9630#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9404#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9405#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9584#L1233-3 assume !(1 == ~T5_E~0); 9585#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9854#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9855#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10361#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10363#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9386#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9387#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10336#L1273-3 assume !(1 == ~E_2~0); 10351#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10353#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9732#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9733#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9578#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9579#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10075#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9575#L1313-3 assume !(1 == ~E_10~0); 9576#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9388#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9389#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9331#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9557#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9558#L1663 assume !(0 == start_simulation_~tmp~3#1); 9224#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9967#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9175#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9058#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 9059#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9124#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9447#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9913#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 9469#L1644-2 [2023-11-23 22:37:57,168 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:57,168 INFO L85 PathProgramCache]: Analyzing trace with hash 88517158, now seen corresponding path program 1 times [2023-11-23 22:37:57,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:57,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337531944] [2023-11-23 22:37:57,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:57,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:57,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:57,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:57,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:57,233 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [337531944] [2023-11-23 22:37:57,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [337531944] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:57,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:57,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:57,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674756750] [2023-11-23 22:37:57,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:57,235 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:57,236 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:57,236 INFO L85 PathProgramCache]: Analyzing trace with hash -1935633556, now seen corresponding path program 1 times [2023-11-23 22:37:57,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:57,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44153253] [2023-11-23 22:37:57,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:57,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:57,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:57,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:57,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:57,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44153253] [2023-11-23 22:37:57,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [44153253] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:57,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:57,346 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:57,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833708951] [2023-11-23 22:37:57,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:57,347 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:57,347 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:57,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:57,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:57,348 INFO L87 Difference]: Start difference. First operand 1488 states and 2203 transitions. cyclomatic complexity: 716 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:57,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:57,396 INFO L93 Difference]: Finished difference Result 1488 states and 2202 transitions. [2023-11-23 22:37:57,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2202 transitions. [2023-11-23 22:37:57,412 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:57,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2202 transitions. [2023-11-23 22:37:57,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:57,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:57,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2202 transitions. [2023-11-23 22:37:57,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:57,434 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2023-11-23 22:37:57,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2202 transitions. [2023-11-23 22:37:57,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:57,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4798387096774193) internal successors, (2202), 1487 states have internal predecessors, (2202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:57,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2202 transitions. [2023-11-23 22:37:57,483 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2023-11-23 22:37:57,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:37:57,486 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2023-11-23 22:37:57,486 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-23 22:37:57,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2202 transitions. [2023-11-23 22:37:57,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:57,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:57,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:57,503 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:57,503 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:57,504 INFO L748 eck$LassoCheckResult]: Stem: 12390#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 12391#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13372#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13373#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12840#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 12841#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12712#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12605#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12334#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11982#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11983#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12027#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12028#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12970#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12971#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13015#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12431#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12432#L1090 assume !(0 == ~M_E~0); 12474#L1090-2 assume !(0 == ~T1_E~0); 12475#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13162#L1100-1 assume !(0 == ~T3_E~0); 13163#L1105-1 assume !(0 == ~T4_E~0); 12254#L1110-1 assume !(0 == ~T5_E~0); 12255#L1115-1 assume !(0 == ~T6_E~0); 12641#L1120-1 assume !(0 == ~T7_E~0); 12949#L1125-1 assume !(0 == ~T8_E~0); 13421#L1130-1 assume !(0 == ~T9_E~0); 13184#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12436#L1140-1 assume !(0 == ~T11_E~0); 12437#L1145-1 assume !(0 == ~E_1~0); 13118#L1150-1 assume !(0 == ~E_2~0); 12618#L1155-1 assume !(0 == ~E_3~0); 12619#L1160-1 assume !(0 == ~E_4~0); 12717#L1165-1 assume !(0 == ~E_5~0); 12718#L1170-1 assume !(0 == ~E_6~0); 13356#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12798#L1180-1 assume !(0 == ~E_8~0); 12799#L1185-1 assume !(0 == ~E_9~0); 12433#L1190-1 assume !(0 == ~E_10~0); 12434#L1195-1 assume !(0 == ~E_11~0); 12814#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12633#L525 assume !(1 == ~m_pc~0); 12072#L525-2 is_master_triggered_~__retres1~0#1 := 0; 12073#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13258#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13231#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12423#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12424#L544 assume 1 == ~t1_pc~0; 12693#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12640#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12046#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12047#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 12278#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12918#L563 assume !(1 == ~t2_pc~0); 13104#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12091#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12092#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12502#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 12503#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12996#L582 assume 1 == ~t3_pc~0; 12222#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12223#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11974#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11975#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 12160#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12161#L601 assume !(1 == ~t4_pc~0); 13130#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12642#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12170#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12171#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 13125#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13397#L620 assume 1 == ~t5_pc~0; 12119#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12120#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13012#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13263#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 13406#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13407#L639 assume !(1 == ~t6_pc~0); 12947#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12540#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12541#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12591#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 12648#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12649#L658 assume 1 == ~t7_pc~0; 12948#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12864#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13412#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13064#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 12426#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12427#L677 assume 1 == ~t8_pc~0; 12654#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12237#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12238#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12498#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 12499#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13225#L696 assume !(1 == ~t9_pc~0); 12930#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12931#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12703#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12704#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12954#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13167#L715 assume 1 == ~t10_pc~0; 13174#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13046#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12852#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12853#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 12792#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12231#L734 assume !(1 == ~t11_pc~0); 12232#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 12719#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12801#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11970#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 11971#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13013#L1213 assume !(1 == ~M_E~0); 12789#L1213-2 assume !(1 == ~T1_E~0); 12790#L1218-1 assume !(1 == ~T2_E~0); 12005#L1223-1 assume !(1 == ~T3_E~0); 12006#L1228-1 assume !(1 == ~T4_E~0); 12765#L1233-1 assume !(1 == ~T5_E~0); 13408#L1238-1 assume !(1 == ~T6_E~0); 13123#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13124#L1248-1 assume !(1 == ~T8_E~0); 13170#L1253-1 assume !(1 == ~T9_E~0); 13171#L1258-1 assume !(1 == ~T10_E~0); 13146#L1263-1 assume !(1 == ~T11_E~0); 13147#L1268-1 assume !(1 == ~E_1~0); 12967#L1273-1 assume !(1 == ~E_2~0); 12968#L1278-1 assume !(1 == ~E_3~0); 12538#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12539#L1288-1 assume !(1 == ~E_5~0); 13269#L1293-1 assume !(1 == ~E_6~0); 13229#L1298-1 assume !(1 == ~E_7~0); 13000#L1303-1 assume !(1 == ~E_8~0); 12548#L1308-1 assume !(1 == ~E_9~0); 12440#L1313-1 assume !(1 == ~E_10~0); 12441#L1318-1 assume !(1 == ~E_11~0); 12448#L1323-1 assume { :end_inline_reset_delta_events } true; 12449#L1644-2 [2023-11-23 22:37:57,504 INFO L750 eck$LassoCheckResult]: Loop: 12449#L1644-2 assume !false; 13062#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12355#L1065-1 assume !false; 12356#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13404#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12087#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12664#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12553#L906 assume !(0 != eval_~tmp~0#1); 12555#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12874#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12875#L1090-3 assume !(0 == ~M_E~0); 13284#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13341#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13306#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13307#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12329#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12330#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12606#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12607#L1125-3 assume !(0 == ~T8_E~0); 13122#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13379#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12528#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12037#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12038#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12162#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12163#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12511#L1165-3 assume !(0 == ~E_5~0); 12512#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12911#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12425#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12186#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12187#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13367#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13368#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12746#L525-36 assume !(1 == ~m_pc~0); 12747#L525-38 is_master_triggered_~__retres1~0#1 := 0; 12287#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12288#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12563#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12564#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12477#L544-36 assume 1 == ~t1_pc~0; 12478#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13034#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13035#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13374#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13354#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13259#L563-36 assume 1 == ~t2_pc~0; 12276#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12035#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12036#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13240#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12762#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12763#L582-36 assume 1 == ~t3_pc~0; 12595#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12596#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12694#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12695#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12800#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12740#L601-36 assume 1 == ~t4_pc~0; 12626#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12627#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12892#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12893#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13345#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13246#L620-36 assume 1 == ~t5_pc~0; 12679#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12680#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13107#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12653#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 12296#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12083#L639-36 assume 1 == ~t6_pc~0; 12084#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12124#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12125#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12346#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12347#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12952#L658-36 assume !(1 == ~t7_pc~0); 12096#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 12097#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13331#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12074#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12075#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13096#L677-36 assume !(1 == ~t8_pc~0); 12867#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12868#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12997#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12998#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12894#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12895#L696-36 assume 1 == ~t9_pc~0; 12786#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12787#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12728#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12729#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12912#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12913#L715-36 assume 1 == ~t10_pc~0; 13057#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11972#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11973#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11948#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11949#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12339#L734-36 assume !(1 == ~t11_pc~0); 12051#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 12052#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12357#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11964#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11965#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12976#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12614#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12615#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12387#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12388#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12567#L1233-3 assume !(1 == ~T5_E~0); 12568#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12837#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12838#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13344#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13346#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12370#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12371#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13319#L1273-3 assume !(1 == ~E_2~0); 13334#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13336#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12715#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12716#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12561#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12562#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13058#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12558#L1313-3 assume !(1 == ~E_10~0); 12559#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12372#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12373#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12314#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12542#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 12543#L1663 assume !(0 == start_simulation_~tmp~3#1); 12212#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12950#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12158#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12044#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 12045#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12107#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12430#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 12896#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 12449#L1644-2 [2023-11-23 22:37:57,506 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:57,506 INFO L85 PathProgramCache]: Analyzing trace with hash -586642968, now seen corresponding path program 1 times [2023-11-23 22:37:57,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:57,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485756516] [2023-11-23 22:37:57,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:57,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:57,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:57,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:57,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:57,580 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485756516] [2023-11-23 22:37:57,580 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485756516] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:57,581 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:57,581 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:57,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594925637] [2023-11-23 22:37:57,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:57,582 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:57,583 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:57,583 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 2 times [2023-11-23 22:37:57,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:57,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171841302] [2023-11-23 22:37:57,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:57,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:57,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:57,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:57,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:57,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171841302] [2023-11-23 22:37:57,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171841302] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:57,731 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:57,732 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:57,732 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [448080506] [2023-11-23 22:37:57,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:57,733 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:57,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:57,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:57,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:57,734 INFO L87 Difference]: Start difference. First operand 1488 states and 2202 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:57,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:57,795 INFO L93 Difference]: Finished difference Result 1488 states and 2201 transitions. [2023-11-23 22:37:57,795 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2201 transitions. [2023-11-23 22:37:57,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:57,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2201 transitions. [2023-11-23 22:37:57,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:57,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:57,830 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2201 transitions. [2023-11-23 22:37:57,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:57,834 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2023-11-23 22:37:57,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2201 transitions. [2023-11-23 22:37:57,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:57,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4791666666666667) internal successors, (2201), 1487 states have internal predecessors, (2201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:57,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2201 transitions. [2023-11-23 22:37:57,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2023-11-23 22:37:57,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:37:57,885 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2023-11-23 22:37:57,885 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-23 22:37:57,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2201 transitions. [2023-11-23 22:37:57,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:57,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:57,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:57,902 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:57,902 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:57,903 INFO L748 eck$LassoCheckResult]: Stem: 15373#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 15374#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16356#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15823#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 15824#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15695#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15588#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15317#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14965#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14966#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15010#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15011#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15953#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15954#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15998#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15414#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15415#L1090 assume !(0 == ~M_E~0); 15457#L1090-2 assume !(0 == ~T1_E~0); 15458#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16146#L1100-1 assume !(0 == ~T3_E~0); 16147#L1105-1 assume !(0 == ~T4_E~0); 15238#L1110-1 assume !(0 == ~T5_E~0); 15239#L1115-1 assume !(0 == ~T6_E~0); 15624#L1120-1 assume !(0 == ~T7_E~0); 15932#L1125-1 assume !(0 == ~T8_E~0); 16404#L1130-1 assume !(0 == ~T9_E~0); 16167#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15419#L1140-1 assume !(0 == ~T11_E~0); 15420#L1145-1 assume !(0 == ~E_1~0); 16101#L1150-1 assume !(0 == ~E_2~0); 15601#L1155-1 assume !(0 == ~E_3~0); 15602#L1160-1 assume !(0 == ~E_4~0); 15700#L1165-1 assume !(0 == ~E_5~0); 15701#L1170-1 assume !(0 == ~E_6~0); 16339#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15781#L1180-1 assume !(0 == ~E_8~0); 15782#L1185-1 assume !(0 == ~E_9~0); 15416#L1190-1 assume !(0 == ~E_10~0); 15417#L1195-1 assume !(0 == ~E_11~0); 15797#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15621#L525 assume !(1 == ~m_pc~0); 15055#L525-2 is_master_triggered_~__retres1~0#1 := 0; 15056#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16241#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16216#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15406#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15407#L544 assume 1 == ~t1_pc~0; 15676#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15623#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15034#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15035#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 15261#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15901#L563 assume !(1 == ~t2_pc~0); 16087#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15074#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15075#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15485#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 15486#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15979#L582 assume 1 == ~t3_pc~0; 15207#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15208#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14957#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14958#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 15143#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15144#L601 assume !(1 == ~t4_pc~0); 16113#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15625#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15157#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15158#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 16108#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16380#L620 assume 1 == ~t5_pc~0; 15104#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15105#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15995#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16247#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 16389#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16390#L639 assume !(1 == ~t6_pc~0); 15930#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15525#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15526#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15574#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 15631#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15632#L658 assume 1 == ~t7_pc~0; 15931#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15848#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16395#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16047#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 15409#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15410#L677 assume 1 == ~t8_pc~0; 15639#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15220#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15481#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 15482#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16208#L696 assume !(1 == ~t9_pc~0); 15915#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15916#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15686#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15687#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15937#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16150#L715 assume 1 == ~t10_pc~0; 16157#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16029#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15835#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15836#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 15775#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15214#L734 assume !(1 == ~t11_pc~0); 15215#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 15702#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15784#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14955#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 14956#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15996#L1213 assume !(1 == ~M_E~0); 15773#L1213-2 assume !(1 == ~T1_E~0); 15774#L1218-1 assume !(1 == ~T2_E~0); 14988#L1223-1 assume !(1 == ~T3_E~0); 14989#L1228-1 assume !(1 == ~T4_E~0); 15748#L1233-1 assume !(1 == ~T5_E~0); 16391#L1238-1 assume !(1 == ~T6_E~0); 16106#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16107#L1248-1 assume !(1 == ~T8_E~0); 16153#L1253-1 assume !(1 == ~T9_E~0); 16154#L1258-1 assume !(1 == ~T10_E~0); 16129#L1263-1 assume !(1 == ~T11_E~0); 16130#L1268-1 assume !(1 == ~E_1~0); 15950#L1273-1 assume !(1 == ~E_2~0); 15951#L1278-1 assume !(1 == ~E_3~0); 15521#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15522#L1288-1 assume !(1 == ~E_5~0); 16252#L1293-1 assume !(1 == ~E_6~0); 16212#L1298-1 assume !(1 == ~E_7~0); 15983#L1303-1 assume !(1 == ~E_8~0); 15531#L1308-1 assume !(1 == ~E_9~0); 15423#L1313-1 assume !(1 == ~E_10~0); 15424#L1318-1 assume !(1 == ~E_11~0); 15434#L1323-1 assume { :end_inline_reset_delta_events } true; 15435#L1644-2 [2023-11-23 22:37:57,904 INFO L750 eck$LassoCheckResult]: Loop: 15435#L1644-2 assume !false; 16045#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15339#L1065-1 assume !false; 15340#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16387#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15070#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15647#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15536#L906 assume !(0 != eval_~tmp~0#1); 15538#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15858#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15859#L1090-3 assume !(0 == ~M_E~0); 16267#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16324#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16289#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16290#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15312#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15313#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15589#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15590#L1125-3 assume !(0 == ~T8_E~0); 16105#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16362#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15513#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15022#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15023#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15146#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15147#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15494#L1165-3 assume !(0 == ~E_5~0); 15495#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15894#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15408#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15170#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15171#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16350#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16351#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15729#L525-36 assume !(1 == ~m_pc~0); 15730#L525-38 is_master_triggered_~__retres1~0#1 := 0; 15275#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15276#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15546#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15547#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15460#L544-36 assume 1 == ~t1_pc~0; 15461#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16017#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16018#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16357#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16338#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16242#L563-36 assume 1 == ~t2_pc~0; 15259#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15018#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15019#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16223#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15745#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15746#L582-36 assume 1 == ~t3_pc~0; 15578#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15579#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15677#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15678#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15783#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15723#L601-36 assume 1 == ~t4_pc~0; 15609#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15610#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15875#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15876#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16328#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16227#L620-36 assume 1 == ~t5_pc~0; 15660#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15661#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16090#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15636#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 15279#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15063#L639-36 assume 1 == ~t6_pc~0; 15064#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15102#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15103#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15329#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15330#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15935#L658-36 assume !(1 == ~t7_pc~0); 15079#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 15080#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16314#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15057#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15058#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16079#L677-36 assume 1 == ~t8_pc~0; 16256#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15851#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15980#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15981#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15877#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15878#L696-36 assume 1 == ~t9_pc~0; 15769#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15770#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15711#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15712#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15895#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15896#L715-36 assume !(1 == ~t10_pc~0); 15857#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14953#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14954#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14931#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14932#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15322#L734-36 assume !(1 == ~t11_pc~0); 15032#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 15033#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15338#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14947#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14948#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15959#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15595#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15596#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15370#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15371#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15550#L1233-3 assume !(1 == ~T5_E~0); 15551#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15820#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15821#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16327#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16329#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15352#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15353#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16302#L1273-3 assume !(1 == ~E_2~0); 16317#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16319#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15698#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15699#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15544#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15545#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16041#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15541#L1313-3 assume !(1 == ~E_10~0); 15542#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15354#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15355#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15297#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15523#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 15524#L1663 assume !(0 == start_simulation_~tmp~3#1); 15190#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15933#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15141#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15024#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 15025#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15087#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15413#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 15879#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 15435#L1644-2 [2023-11-23 22:37:57,905 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:57,906 INFO L85 PathProgramCache]: Analyzing trace with hash 361408998, now seen corresponding path program 1 times [2023-11-23 22:37:57,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:57,906 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350036174] [2023-11-23 22:37:57,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:57,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:57,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:57,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:57,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:57,981 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350036174] [2023-11-23 22:37:57,982 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350036174] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:57,982 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:57,982 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:57,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1212237907] [2023-11-23 22:37:57,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:57,989 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:57,990 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:57,990 INFO L85 PathProgramCache]: Analyzing trace with hash -658480883, now seen corresponding path program 1 times [2023-11-23 22:37:57,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:57,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715542668] [2023-11-23 22:37:57,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:57,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:58,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:58,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:58,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:58,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715542668] [2023-11-23 22:37:58,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [715542668] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:58,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:58,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:58,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53668814] [2023-11-23 22:37:58,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:58,090 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:58,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:58,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:58,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:58,092 INFO L87 Difference]: Start difference. First operand 1488 states and 2201 transitions. cyclomatic complexity: 714 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:58,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:58,142 INFO L93 Difference]: Finished difference Result 1488 states and 2200 transitions. [2023-11-23 22:37:58,142 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2200 transitions. [2023-11-23 22:37:58,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:58,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2200 transitions. [2023-11-23 22:37:58,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:58,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:58,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2200 transitions. [2023-11-23 22:37:58,175 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:58,176 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2023-11-23 22:37:58,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2200 transitions. [2023-11-23 22:37:58,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:58,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.478494623655914) internal successors, (2200), 1487 states have internal predecessors, (2200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:58,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2200 transitions. [2023-11-23 22:37:58,218 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2023-11-23 22:37:58,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:37:58,219 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2023-11-23 22:37:58,220 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-23 22:37:58,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2200 transitions. [2023-11-23 22:37:58,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:58,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:58,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:58,230 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:58,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:58,231 INFO L748 eck$LassoCheckResult]: Stem: 18356#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 18357#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 19338#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19339#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18806#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 18807#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18678#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18571#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18300#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17948#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17949#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17993#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17994#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18936#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18937#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18981#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18397#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18398#L1090 assume !(0 == ~M_E~0); 18440#L1090-2 assume !(0 == ~T1_E~0); 18441#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19128#L1100-1 assume !(0 == ~T3_E~0); 19129#L1105-1 assume !(0 == ~T4_E~0); 18220#L1110-1 assume !(0 == ~T5_E~0); 18221#L1115-1 assume !(0 == ~T6_E~0); 18607#L1120-1 assume !(0 == ~T7_E~0); 18915#L1125-1 assume !(0 == ~T8_E~0); 19387#L1130-1 assume !(0 == ~T9_E~0); 19150#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18402#L1140-1 assume !(0 == ~T11_E~0); 18403#L1145-1 assume !(0 == ~E_1~0); 19084#L1150-1 assume !(0 == ~E_2~0); 18584#L1155-1 assume !(0 == ~E_3~0); 18585#L1160-1 assume !(0 == ~E_4~0); 18683#L1165-1 assume !(0 == ~E_5~0); 18684#L1170-1 assume !(0 == ~E_6~0); 19322#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 18764#L1180-1 assume !(0 == ~E_8~0); 18765#L1185-1 assume !(0 == ~E_9~0); 18399#L1190-1 assume !(0 == ~E_10~0); 18400#L1195-1 assume !(0 == ~E_11~0); 18780#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18599#L525 assume !(1 == ~m_pc~0); 18038#L525-2 is_master_triggered_~__retres1~0#1 := 0; 18039#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19224#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19197#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18389#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18390#L544 assume 1 == ~t1_pc~0; 18659#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18606#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18012#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18013#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 18244#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18884#L563 assume !(1 == ~t2_pc~0); 19070#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18057#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18058#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18468#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 18469#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18962#L582 assume 1 == ~t3_pc~0; 18188#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18189#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17940#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17941#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 18126#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18127#L601 assume !(1 == ~t4_pc~0); 19096#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18608#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18136#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18137#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 19091#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19363#L620 assume 1 == ~t5_pc~0; 18085#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18086#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18978#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19229#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 19372#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19373#L639 assume !(1 == ~t6_pc~0); 18913#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18506#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18507#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18557#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 18614#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18615#L658 assume 1 == ~t7_pc~0; 18914#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18830#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19378#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19030#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 18392#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18393#L677 assume 1 == ~t8_pc~0; 18620#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18203#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18204#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18464#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 18465#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19191#L696 assume !(1 == ~t9_pc~0); 18896#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18897#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18669#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18670#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18920#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19133#L715 assume 1 == ~t10_pc~0; 19140#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19012#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18818#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18819#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 18758#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18197#L734 assume !(1 == ~t11_pc~0); 18198#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 18685#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18767#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17936#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 17937#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18979#L1213 assume !(1 == ~M_E~0); 18755#L1213-2 assume !(1 == ~T1_E~0); 18756#L1218-1 assume !(1 == ~T2_E~0); 17971#L1223-1 assume !(1 == ~T3_E~0); 17972#L1228-1 assume !(1 == ~T4_E~0); 18731#L1233-1 assume !(1 == ~T5_E~0); 19374#L1238-1 assume !(1 == ~T6_E~0); 19089#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19090#L1248-1 assume !(1 == ~T8_E~0); 19136#L1253-1 assume !(1 == ~T9_E~0); 19137#L1258-1 assume !(1 == ~T10_E~0); 19112#L1263-1 assume !(1 == ~T11_E~0); 19113#L1268-1 assume !(1 == ~E_1~0); 18933#L1273-1 assume !(1 == ~E_2~0); 18934#L1278-1 assume !(1 == ~E_3~0); 18504#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18505#L1288-1 assume !(1 == ~E_5~0); 19235#L1293-1 assume !(1 == ~E_6~0); 19195#L1298-1 assume !(1 == ~E_7~0); 18966#L1303-1 assume !(1 == ~E_8~0); 18514#L1308-1 assume !(1 == ~E_9~0); 18406#L1313-1 assume !(1 == ~E_10~0); 18407#L1318-1 assume !(1 == ~E_11~0); 18414#L1323-1 assume { :end_inline_reset_delta_events } true; 18415#L1644-2 [2023-11-23 22:37:58,232 INFO L750 eck$LassoCheckResult]: Loop: 18415#L1644-2 assume !false; 19028#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18321#L1065-1 assume !false; 18322#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19370#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18053#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18630#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18519#L906 assume !(0 != eval_~tmp~0#1); 18521#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18841#L1090-3 assume !(0 == ~M_E~0); 19250#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19307#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19272#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19273#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18295#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18296#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18572#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18573#L1125-3 assume !(0 == ~T8_E~0); 19088#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19345#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18494#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18003#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18004#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18128#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18129#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18477#L1165-3 assume !(0 == ~E_5~0); 18478#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18877#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18391#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18152#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18153#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19333#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19334#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18712#L525-36 assume !(1 == ~m_pc~0); 18713#L525-38 is_master_triggered_~__retres1~0#1 := 0; 18253#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18254#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18529#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18530#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18443#L544-36 assume 1 == ~t1_pc~0; 18444#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19000#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19001#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19340#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19320#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19225#L563-36 assume 1 == ~t2_pc~0; 18242#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18001#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18002#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19206#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18728#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18729#L582-36 assume 1 == ~t3_pc~0; 18561#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18562#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18660#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18661#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18766#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18706#L601-36 assume 1 == ~t4_pc~0; 18592#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18593#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18858#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18859#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19311#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19212#L620-36 assume 1 == ~t5_pc~0; 18645#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18646#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19073#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18619#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 18262#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18049#L639-36 assume 1 == ~t6_pc~0; 18050#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18090#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18091#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18312#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18313#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18918#L658-36 assume 1 == ~t7_pc~0; 18162#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18063#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19297#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18040#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18041#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19062#L677-36 assume !(1 == ~t8_pc~0); 18833#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 18834#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18963#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18964#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18860#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18861#L696-36 assume 1 == ~t9_pc~0; 18752#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18753#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18694#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18695#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18878#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18879#L715-36 assume !(1 == ~t10_pc~0); 18842#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 17938#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17939#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17914#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17915#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18305#L734-36 assume !(1 == ~t11_pc~0); 18017#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 18018#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18323#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17930#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17931#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18942#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18580#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18581#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18353#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18354#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18533#L1233-3 assume !(1 == ~T5_E~0); 18534#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18803#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18804#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19310#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19312#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18336#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18337#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19285#L1273-3 assume !(1 == ~E_2~0); 19300#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19302#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18681#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18682#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18527#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18528#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19024#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18524#L1313-3 assume !(1 == ~E_10~0); 18525#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18338#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18339#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18280#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18508#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 18509#L1663 assume !(0 == start_simulation_~tmp~3#1); 18178#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18916#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18124#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18010#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 18011#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18073#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18396#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 18862#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 18415#L1644-2 [2023-11-23 22:37:58,233 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:58,233 INFO L85 PathProgramCache]: Analyzing trace with hash 946180648, now seen corresponding path program 1 times [2023-11-23 22:37:58,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:58,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534637553] [2023-11-23 22:37:58,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:58,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:58,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:58,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:58,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:58,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534637553] [2023-11-23 22:37:58,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534637553] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:58,321 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:58,321 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:58,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [331271882] [2023-11-23 22:37:58,322 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:58,322 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:58,323 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:58,323 INFO L85 PathProgramCache]: Analyzing trace with hash -1386990515, now seen corresponding path program 1 times [2023-11-23 22:37:58,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:58,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771109268] [2023-11-23 22:37:58,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:58,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:58,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:58,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:58,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:58,403 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771109268] [2023-11-23 22:37:58,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771109268] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:58,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:58,403 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:58,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2064749921] [2023-11-23 22:37:58,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:58,404 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:58,405 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:58,405 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:58,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:58,406 INFO L87 Difference]: Start difference. First operand 1488 states and 2200 transitions. cyclomatic complexity: 713 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:58,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:58,457 INFO L93 Difference]: Finished difference Result 1488 states and 2199 transitions. [2023-11-23 22:37:58,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2199 transitions. [2023-11-23 22:37:58,469 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:58,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2199 transitions. [2023-11-23 22:37:58,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:58,487 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:58,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2199 transitions. [2023-11-23 22:37:58,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:58,490 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2023-11-23 22:37:58,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2199 transitions. [2023-11-23 22:37:58,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:58,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4778225806451613) internal successors, (2199), 1487 states have internal predecessors, (2199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:58,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2199 transitions. [2023-11-23 22:37:58,533 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2023-11-23 22:37:58,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:37:58,534 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2023-11-23 22:37:58,534 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-23 22:37:58,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2199 transitions. [2023-11-23 22:37:58,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:58,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:58,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:58,545 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:58,545 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:58,546 INFO L748 eck$LassoCheckResult]: Stem: 21339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 21340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 22321#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22322#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21789#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 21790#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21661#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21554#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21283#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20931#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20932#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20976#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20977#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21919#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21920#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21964#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21380#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21381#L1090 assume !(0 == ~M_E~0); 21423#L1090-2 assume !(0 == ~T1_E~0); 21424#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22112#L1100-1 assume !(0 == ~T3_E~0); 22113#L1105-1 assume !(0 == ~T4_E~0); 21203#L1110-1 assume !(0 == ~T5_E~0); 21204#L1115-1 assume !(0 == ~T6_E~0); 21590#L1120-1 assume !(0 == ~T7_E~0); 21898#L1125-1 assume !(0 == ~T8_E~0); 22370#L1130-1 assume !(0 == ~T9_E~0); 22133#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21385#L1140-1 assume !(0 == ~T11_E~0); 21386#L1145-1 assume !(0 == ~E_1~0); 22067#L1150-1 assume !(0 == ~E_2~0); 21567#L1155-1 assume !(0 == ~E_3~0); 21568#L1160-1 assume !(0 == ~E_4~0); 21666#L1165-1 assume !(0 == ~E_5~0); 21667#L1170-1 assume !(0 == ~E_6~0); 22305#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 21747#L1180-1 assume !(0 == ~E_8~0); 21748#L1185-1 assume !(0 == ~E_9~0); 21382#L1190-1 assume !(0 == ~E_10~0); 21383#L1195-1 assume !(0 == ~E_11~0); 21763#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21587#L525 assume !(1 == ~m_pc~0); 21021#L525-2 is_master_triggered_~__retres1~0#1 := 0; 21022#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22207#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22180#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21372#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21373#L544 assume 1 == ~t1_pc~0; 21642#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21589#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21000#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21001#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 21227#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21867#L563 assume !(1 == ~t2_pc~0); 22053#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21040#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21041#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21451#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 21452#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21945#L582 assume 1 == ~t3_pc~0; 21173#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21174#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20923#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20924#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 21109#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21110#L601 assume !(1 == ~t4_pc~0); 22079#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21591#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21123#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21124#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 22074#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22346#L620 assume 1 == ~t5_pc~0; 21068#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21069#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21961#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22212#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 22355#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22356#L639 assume !(1 == ~t6_pc~0); 21896#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21491#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21540#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 21597#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21598#L658 assume 1 == ~t7_pc~0; 21897#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21813#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22361#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22013#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 21375#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21376#L677 assume 1 == ~t8_pc~0; 21603#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21186#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21187#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21447#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 21448#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22174#L696 assume !(1 == ~t9_pc~0); 21881#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21882#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21652#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21653#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21903#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22116#L715 assume 1 == ~t10_pc~0; 22123#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21995#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21801#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21802#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 21741#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21180#L734 assume !(1 == ~t11_pc~0); 21181#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21668#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21750#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20921#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 20922#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21962#L1213 assume !(1 == ~M_E~0); 21739#L1213-2 assume !(1 == ~T1_E~0); 21740#L1218-1 assume !(1 == ~T2_E~0); 20954#L1223-1 assume !(1 == ~T3_E~0); 20955#L1228-1 assume !(1 == ~T4_E~0); 21714#L1233-1 assume !(1 == ~T5_E~0); 22357#L1238-1 assume !(1 == ~T6_E~0); 22072#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22073#L1248-1 assume !(1 == ~T8_E~0); 22119#L1253-1 assume !(1 == ~T9_E~0); 22120#L1258-1 assume !(1 == ~T10_E~0); 22095#L1263-1 assume !(1 == ~T11_E~0); 22096#L1268-1 assume !(1 == ~E_1~0); 21916#L1273-1 assume !(1 == ~E_2~0); 21917#L1278-1 assume !(1 == ~E_3~0); 21487#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21488#L1288-1 assume !(1 == ~E_5~0); 22218#L1293-1 assume !(1 == ~E_6~0); 22178#L1298-1 assume !(1 == ~E_7~0); 21949#L1303-1 assume !(1 == ~E_8~0); 21497#L1308-1 assume !(1 == ~E_9~0); 21389#L1313-1 assume !(1 == ~E_10~0); 21390#L1318-1 assume !(1 == ~E_11~0); 21397#L1323-1 assume { :end_inline_reset_delta_events } true; 21398#L1644-2 [2023-11-23 22:37:58,547 INFO L750 eck$LassoCheckResult]: Loop: 21398#L1644-2 assume !false; 22011#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21305#L1065-1 assume !false; 21306#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22353#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21036#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21613#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21502#L906 assume !(0 != eval_~tmp~0#1); 21504#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21824#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21825#L1090-3 assume !(0 == ~M_E~0); 22233#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22290#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22255#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22256#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21278#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21279#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21555#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21556#L1125-3 assume !(0 == ~T8_E~0); 22071#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22328#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21477#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20988#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20989#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21112#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21113#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21460#L1165-3 assume !(0 == ~E_5~0); 21461#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21860#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21374#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21136#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21137#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22316#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22317#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21695#L525-36 assume !(1 == ~m_pc~0); 21696#L525-38 is_master_triggered_~__retres1~0#1 := 0; 21241#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21242#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21512#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21513#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21426#L544-36 assume 1 == ~t1_pc~0; 21427#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21983#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21984#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22323#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22304#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22208#L563-36 assume 1 == ~t2_pc~0; 21225#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20984#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20985#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22189#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21711#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21712#L582-36 assume 1 == ~t3_pc~0; 21544#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21545#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21643#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21644#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21749#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21689#L601-36 assume 1 == ~t4_pc~0; 21575#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21576#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21841#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21842#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22294#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22195#L620-36 assume !(1 == ~t5_pc~0); 21632#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 21631#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22060#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21602#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 21245#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21032#L639-36 assume 1 == ~t6_pc~0; 21033#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21073#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21074#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21293#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21294#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21901#L658-36 assume !(1 == ~t7_pc~0); 21042#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 21043#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22280#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21023#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21024#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22045#L677-36 assume !(1 == ~t8_pc~0); 21815#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 21816#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21946#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21947#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21843#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21844#L696-36 assume 1 == ~t9_pc~0; 21735#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21736#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21677#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21678#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21861#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21862#L715-36 assume 1 == ~t10_pc~0; 22006#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20919#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20920#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20897#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20898#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21288#L734-36 assume !(1 == ~t11_pc~0); 20998#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 20999#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21304#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20913#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20914#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21925#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21561#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21562#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21336#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21337#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21516#L1233-3 assume !(1 == ~T5_E~0); 21517#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21786#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21787#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22293#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22295#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21318#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21319#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22268#L1273-3 assume !(1 == ~E_2~0); 22283#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22285#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21664#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21665#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21509#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21510#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22007#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21507#L1313-3 assume !(1 == ~E_10~0); 21508#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21320#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21321#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21263#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 21490#L1663 assume !(0 == start_simulation_~tmp~3#1); 21154#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21899#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21107#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20990#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 20991#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21053#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21379#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 21845#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 21398#L1644-2 [2023-11-23 22:37:58,548 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:58,548 INFO L85 PathProgramCache]: Analyzing trace with hash 1380686246, now seen corresponding path program 1 times [2023-11-23 22:37:58,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:58,548 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501748766] [2023-11-23 22:37:58,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:58,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:58,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:58,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:58,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:58,612 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1501748766] [2023-11-23 22:37:58,612 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1501748766] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:58,612 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:58,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:58,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777610693] [2023-11-23 22:37:58,613 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:58,613 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:58,614 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:58,614 INFO L85 PathProgramCache]: Analyzing trace with hash -979985172, now seen corresponding path program 1 times [2023-11-23 22:37:58,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:58,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158410584] [2023-11-23 22:37:58,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:58,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:58,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:58,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:58,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:58,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158410584] [2023-11-23 22:37:58,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158410584] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:58,697 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:58,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:58,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608364434] [2023-11-23 22:37:58,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:58,698 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:58,698 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:58,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:58,699 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:58,699 INFO L87 Difference]: Start difference. First operand 1488 states and 2199 transitions. cyclomatic complexity: 712 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:58,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:58,749 INFO L93 Difference]: Finished difference Result 1488 states and 2198 transitions. [2023-11-23 22:37:58,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2198 transitions. [2023-11-23 22:37:58,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:58,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2198 transitions. [2023-11-23 22:37:58,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:58,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:58,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2198 transitions. [2023-11-23 22:37:58,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:58,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2023-11-23 22:37:58,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2198 transitions. [2023-11-23 22:37:58,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:58,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4771505376344085) internal successors, (2198), 1487 states have internal predecessors, (2198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:58,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2198 transitions. [2023-11-23 22:37:58,823 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2023-11-23 22:37:58,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:37:58,824 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2023-11-23 22:37:58,824 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-23 22:37:58,824 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2198 transitions. [2023-11-23 22:37:58,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:58,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:58,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:58,835 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:58,835 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:58,835 INFO L748 eck$LassoCheckResult]: Stem: 24322#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 24323#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 25305#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25306#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24772#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 24773#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24644#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24537#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24266#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23914#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23915#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23959#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23960#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24906#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24907#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24954#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24363#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24364#L1090 assume !(0 == ~M_E~0); 24410#L1090-2 assume !(0 == ~T1_E~0); 24411#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25095#L1100-1 assume !(0 == ~T3_E~0); 25096#L1105-1 assume !(0 == ~T4_E~0); 24187#L1110-1 assume !(0 == ~T5_E~0); 24188#L1115-1 assume !(0 == ~T6_E~0); 24576#L1120-1 assume !(0 == ~T7_E~0); 24881#L1125-1 assume !(0 == ~T8_E~0); 25353#L1130-1 assume !(0 == ~T9_E~0); 25116#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24368#L1140-1 assume !(0 == ~T11_E~0); 24369#L1145-1 assume !(0 == ~E_1~0); 25050#L1150-1 assume !(0 == ~E_2~0); 24550#L1155-1 assume !(0 == ~E_3~0); 24551#L1160-1 assume !(0 == ~E_4~0); 24649#L1165-1 assume !(0 == ~E_5~0); 24650#L1170-1 assume !(0 == ~E_6~0); 25288#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 24730#L1180-1 assume !(0 == ~E_8~0); 24731#L1185-1 assume !(0 == ~E_9~0); 24365#L1190-1 assume !(0 == ~E_10~0); 24366#L1195-1 assume !(0 == ~E_11~0); 24746#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24570#L525 assume !(1 == ~m_pc~0); 24004#L525-2 is_master_triggered_~__retres1~0#1 := 0; 24005#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25190#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25165#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24355#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24356#L544 assume 1 == ~t1_pc~0; 24625#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24572#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23983#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23984#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 24210#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24850#L563 assume !(1 == ~t2_pc~0); 25038#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24023#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24024#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24437#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 24438#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24928#L582 assume 1 == ~t3_pc~0; 24156#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24157#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23906#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23907#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 24092#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24093#L601 assume !(1 == ~t4_pc~0); 25062#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24577#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24106#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24107#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 25057#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25329#L620 assume 1 == ~t5_pc~0; 24055#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24056#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24944#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25196#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 25338#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25339#L639 assume !(1 == ~t6_pc~0); 24879#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24474#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24475#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24523#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 24582#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24583#L658 assume 1 == ~t7_pc~0; 24880#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24797#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25344#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24997#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 24358#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24359#L677 assume 1 == ~t8_pc~0; 24588#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24175#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24176#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24430#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 24431#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25157#L696 assume !(1 == ~t9_pc~0); 24865#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24866#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24635#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24636#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24888#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25100#L715 assume 1 == ~t10_pc~0; 25106#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24978#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24784#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24785#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 24724#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24163#L734 assume !(1 == ~t11_pc~0); 24164#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24652#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24735#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23904#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 23905#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24945#L1213 assume !(1 == ~M_E~0); 24722#L1213-2 assume !(1 == ~T1_E~0); 24723#L1218-1 assume !(1 == ~T2_E~0); 23937#L1223-1 assume !(1 == ~T3_E~0); 23938#L1228-1 assume !(1 == ~T4_E~0); 24697#L1233-1 assume !(1 == ~T5_E~0); 25340#L1238-1 assume !(1 == ~T6_E~0); 25055#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25056#L1248-1 assume !(1 == ~T8_E~0); 25102#L1253-1 assume !(1 == ~T9_E~0); 25103#L1258-1 assume !(1 == ~T10_E~0); 25078#L1263-1 assume !(1 == ~T11_E~0); 25079#L1268-1 assume !(1 == ~E_1~0); 24899#L1273-1 assume !(1 == ~E_2~0); 24900#L1278-1 assume !(1 == ~E_3~0); 24470#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24471#L1288-1 assume !(1 == ~E_5~0); 25201#L1293-1 assume !(1 == ~E_6~0); 25161#L1298-1 assume !(1 == ~E_7~0); 24932#L1303-1 assume !(1 == ~E_8~0); 24480#L1308-1 assume !(1 == ~E_9~0); 24372#L1313-1 assume !(1 == ~E_10~0); 24373#L1318-1 assume !(1 == ~E_11~0); 24379#L1323-1 assume { :end_inline_reset_delta_events } true; 24380#L1644-2 [2023-11-23 22:37:58,836 INFO L750 eck$LassoCheckResult]: Loop: 24380#L1644-2 assume !false; 24994#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24287#L1065-1 assume !false; 24288#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25336#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24019#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24596#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24485#L906 assume !(0 != eval_~tmp~0#1); 24487#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24806#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24807#L1090-3 assume !(0 == ~M_E~0); 25216#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25273#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25238#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25239#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24261#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24262#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24538#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24539#L1125-3 assume !(0 == ~T8_E~0); 25054#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25311#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24460#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23969#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23970#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24094#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24095#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24443#L1165-3 assume !(0 == ~E_5~0); 24444#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24843#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24357#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24118#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24119#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25299#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25300#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24678#L525-36 assume !(1 == ~m_pc~0); 24679#L525-38 is_master_triggered_~__retres1~0#1 := 0; 24219#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24220#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24495#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24496#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24407#L544-36 assume 1 == ~t1_pc~0; 24408#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24966#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24967#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25304#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25286#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25191#L563-36 assume 1 == ~t2_pc~0; 24208#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23967#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23968#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25172#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24694#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24695#L582-36 assume !(1 == ~t3_pc~0); 24529#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 24528#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24626#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24627#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24732#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24672#L601-36 assume !(1 == ~t4_pc~0); 24560#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 24559#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24824#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24825#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25277#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25178#L620-36 assume 1 == ~t5_pc~0; 24611#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24612#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25039#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24585#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 24228#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24015#L639-36 assume 1 == ~t6_pc~0; 24016#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24053#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24054#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24278#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24279#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24884#L658-36 assume 1 == ~t7_pc~0; 24128#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24029#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25263#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24006#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24007#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25028#L677-36 assume 1 == ~t8_pc~0; 25205#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24800#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24929#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24930#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24826#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24827#L696-36 assume !(1 == ~t9_pc~0); 24720#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24719#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24660#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24661#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24844#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24845#L715-36 assume !(1 == ~t10_pc~0); 24808#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 23902#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23903#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23880#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23881#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24271#L734-36 assume 1 == ~t11_pc~0; 24272#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23982#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24289#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23896#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23897#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24908#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24546#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24547#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24319#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24320#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24499#L1233-3 assume !(1 == ~T5_E~0); 24500#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24769#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24770#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25276#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25278#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24302#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24303#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25251#L1273-3 assume !(1 == ~E_2~0); 25266#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25268#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24647#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24648#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24493#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24494#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24990#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24490#L1313-3 assume !(1 == ~E_10~0); 24491#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24304#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24305#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24246#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24472#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 24473#L1663 assume !(0 == start_simulation_~tmp~3#1); 24144#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24882#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24090#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23976#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 23977#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24039#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24362#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 24828#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 24380#L1644-2 [2023-11-23 22:37:58,837 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:58,837 INFO L85 PathProgramCache]: Analyzing trace with hash 1810344552, now seen corresponding path program 1 times [2023-11-23 22:37:58,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:58,838 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583355199] [2023-11-23 22:37:58,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:58,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:58,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:58,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:58,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:58,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1583355199] [2023-11-23 22:37:58,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1583355199] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:58,916 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:58,916 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:58,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [287680031] [2023-11-23 22:37:58,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:58,917 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:58,918 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:58,918 INFO L85 PathProgramCache]: Analyzing trace with hash -2009510740, now seen corresponding path program 1 times [2023-11-23 22:37:58,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:58,918 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533418131] [2023-11-23 22:37:58,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:58,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:58,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:59,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:59,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:59,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533418131] [2023-11-23 22:37:59,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533418131] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:59,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:59,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:59,010 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1399622056] [2023-11-23 22:37:59,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:59,010 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:59,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:59,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:59,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:59,011 INFO L87 Difference]: Start difference. First operand 1488 states and 2198 transitions. cyclomatic complexity: 711 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:59,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:59,056 INFO L93 Difference]: Finished difference Result 1488 states and 2197 transitions. [2023-11-23 22:37:59,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2197 transitions. [2023-11-23 22:37:59,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:59,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2197 transitions. [2023-11-23 22:37:59,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:59,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:59,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2197 transitions. [2023-11-23 22:37:59,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:59,084 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2023-11-23 22:37:59,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2197 transitions. [2023-11-23 22:37:59,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:59,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.476478494623656) internal successors, (2197), 1487 states have internal predecessors, (2197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:59,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2197 transitions. [2023-11-23 22:37:59,121 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2023-11-23 22:37:59,121 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:37:59,123 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2023-11-23 22:37:59,123 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-23 22:37:59,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2197 transitions. [2023-11-23 22:37:59,129 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:59,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:59,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:59,132 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:59,133 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:59,133 INFO L748 eck$LassoCheckResult]: Stem: 27305#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 27306#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 28287#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28288#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27755#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 27756#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27627#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27520#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27249#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26897#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26898#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26942#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26943#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27885#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27886#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27930#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27346#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27347#L1090 assume !(0 == ~M_E~0); 27389#L1090-2 assume !(0 == ~T1_E~0); 27390#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28077#L1100-1 assume !(0 == ~T3_E~0); 28078#L1105-1 assume !(0 == ~T4_E~0); 27169#L1110-1 assume !(0 == ~T5_E~0); 27170#L1115-1 assume !(0 == ~T6_E~0); 27556#L1120-1 assume !(0 == ~T7_E~0); 27864#L1125-1 assume !(0 == ~T8_E~0); 28336#L1130-1 assume !(0 == ~T9_E~0); 28099#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27351#L1140-1 assume !(0 == ~T11_E~0); 27352#L1145-1 assume !(0 == ~E_1~0); 28033#L1150-1 assume !(0 == ~E_2~0); 27533#L1155-1 assume !(0 == ~E_3~0); 27534#L1160-1 assume !(0 == ~E_4~0); 27632#L1165-1 assume !(0 == ~E_5~0); 27633#L1170-1 assume !(0 == ~E_6~0); 28271#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 27713#L1180-1 assume !(0 == ~E_8~0); 27714#L1185-1 assume !(0 == ~E_9~0); 27348#L1190-1 assume !(0 == ~E_10~0); 27349#L1195-1 assume !(0 == ~E_11~0); 27729#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27548#L525 assume !(1 == ~m_pc~0); 26987#L525-2 is_master_triggered_~__retres1~0#1 := 0; 26988#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28173#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28146#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27338#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27339#L544 assume 1 == ~t1_pc~0; 27608#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27555#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26963#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26964#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 27193#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27833#L563 assume !(1 == ~t2_pc~0); 28019#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27006#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27007#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27417#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 27418#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27911#L582 assume 1 == ~t3_pc~0; 27137#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27138#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26889#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26890#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 27075#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27076#L601 assume !(1 == ~t4_pc~0); 28045#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27557#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27089#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27090#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 28040#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28312#L620 assume 1 == ~t5_pc~0; 27034#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27035#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27927#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28178#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 28321#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28322#L639 assume !(1 == ~t6_pc~0); 27862#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27457#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27458#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27506#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 27563#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27564#L658 assume 1 == ~t7_pc~0; 27863#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27779#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28327#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27979#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 27341#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27342#L677 assume 1 == ~t8_pc~0; 27569#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27152#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27153#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27413#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 27414#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28140#L696 assume !(1 == ~t9_pc~0); 27845#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27846#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27618#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27619#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27869#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28082#L715 assume 1 == ~t10_pc~0; 28089#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27961#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27767#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27768#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 27707#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27146#L734 assume !(1 == ~t11_pc~0); 27147#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27634#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27716#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26887#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 26888#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27928#L1213 assume !(1 == ~M_E~0); 27704#L1213-2 assume !(1 == ~T1_E~0); 27705#L1218-1 assume !(1 == ~T2_E~0); 26920#L1223-1 assume !(1 == ~T3_E~0); 26921#L1228-1 assume !(1 == ~T4_E~0); 27680#L1233-1 assume !(1 == ~T5_E~0); 28323#L1238-1 assume !(1 == ~T6_E~0); 28038#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28039#L1248-1 assume !(1 == ~T8_E~0); 28085#L1253-1 assume !(1 == ~T9_E~0); 28086#L1258-1 assume !(1 == ~T10_E~0); 28061#L1263-1 assume !(1 == ~T11_E~0); 28062#L1268-1 assume !(1 == ~E_1~0); 27882#L1273-1 assume !(1 == ~E_2~0); 27883#L1278-1 assume !(1 == ~E_3~0); 27453#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27454#L1288-1 assume !(1 == ~E_5~0); 28184#L1293-1 assume !(1 == ~E_6~0); 28144#L1298-1 assume !(1 == ~E_7~0); 27915#L1303-1 assume !(1 == ~E_8~0); 27463#L1308-1 assume !(1 == ~E_9~0); 27355#L1313-1 assume !(1 == ~E_10~0); 27356#L1318-1 assume !(1 == ~E_11~0); 27363#L1323-1 assume { :end_inline_reset_delta_events } true; 27364#L1644-2 [2023-11-23 22:37:59,134 INFO L750 eck$LassoCheckResult]: Loop: 27364#L1644-2 assume !false; 27977#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27271#L1065-1 assume !false; 27272#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28319#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27002#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27579#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27468#L906 assume !(0 != eval_~tmp~0#1); 27470#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27790#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27791#L1090-3 assume !(0 == ~M_E~0); 28199#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28256#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28221#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28222#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27244#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27245#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27521#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27522#L1125-3 assume !(0 == ~T8_E~0); 28037#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28294#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27443#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26952#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26953#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27078#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27079#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27426#L1165-3 assume !(0 == ~E_5~0); 27427#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27826#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27340#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27101#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27102#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28282#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28283#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27661#L525-36 assume !(1 == ~m_pc~0); 27662#L525-38 is_master_triggered_~__retres1~0#1 := 0; 27202#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27203#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27478#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27479#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27392#L544-36 assume 1 == ~t1_pc~0; 27393#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27949#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27950#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28289#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28270#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28174#L563-36 assume 1 == ~t2_pc~0; 27191#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26950#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26951#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28155#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27677#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27678#L582-36 assume 1 == ~t3_pc~0; 27510#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27511#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27609#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27610#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27715#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27655#L601-36 assume 1 == ~t4_pc~0; 27541#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27542#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27807#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27808#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28260#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28161#L620-36 assume 1 == ~t5_pc~0; 27596#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27597#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28024#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27568#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 27211#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26998#L639-36 assume 1 == ~t6_pc~0; 26999#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27039#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27040#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27261#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27262#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27867#L658-36 assume !(1 == ~t7_pc~0); 27011#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 27012#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28246#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26989#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26990#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28011#L677-36 assume !(1 == ~t8_pc~0); 27782#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 27783#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27912#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27913#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27809#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27810#L696-36 assume 1 == ~t9_pc~0; 27701#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27702#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27640#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27641#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27827#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27828#L715-36 assume 1 == ~t10_pc~0; 27972#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26885#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26886#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26863#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26864#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27251#L734-36 assume !(1 == ~t11_pc~0); 26961#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 26962#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27270#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26879#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26880#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27891#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27527#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27528#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27302#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27303#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27482#L1233-3 assume !(1 == ~T5_E~0); 27483#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27752#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27753#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28259#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28261#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 27284#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27285#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28234#L1273-3 assume !(1 == ~E_2~0); 28249#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28250#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27630#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27631#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27475#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27476#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27973#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27473#L1313-3 assume !(1 == ~E_10~0); 27474#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 27286#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27287#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27229#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27455#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 27456#L1663 assume !(0 == start_simulation_~tmp~3#1); 27120#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27865#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27073#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26956#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 26957#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27019#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27345#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 27811#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 27364#L1644-2 [2023-11-23 22:37:59,135 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:59,135 INFO L85 PathProgramCache]: Analyzing trace with hash -1778026138, now seen corresponding path program 1 times [2023-11-23 22:37:59,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:59,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959937397] [2023-11-23 22:37:59,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:59,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:59,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:59,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:59,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:59,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959937397] [2023-11-23 22:37:59,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959937397] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:59,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:59,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:59,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094184433] [2023-11-23 22:37:59,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:59,199 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:59,200 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:59,200 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 3 times [2023-11-23 22:37:59,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:59,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59117130] [2023-11-23 22:37:59,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:59,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:59,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:59,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:59,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:59,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [59117130] [2023-11-23 22:37:59,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [59117130] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:59,275 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:59,275 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:59,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [267103948] [2023-11-23 22:37:59,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:59,276 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:59,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:59,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:59,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:59,278 INFO L87 Difference]: Start difference. First operand 1488 states and 2197 transitions. cyclomatic complexity: 710 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:59,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:59,326 INFO L93 Difference]: Finished difference Result 1488 states and 2196 transitions. [2023-11-23 22:37:59,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2196 transitions. [2023-11-23 22:37:59,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:59,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2196 transitions. [2023-11-23 22:37:59,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:59,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:59,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2196 transitions. [2023-11-23 22:37:59,364 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:59,365 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2023-11-23 22:37:59,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2196 transitions. [2023-11-23 22:37:59,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:59,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4758064516129032) internal successors, (2196), 1487 states have internal predecessors, (2196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:59,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2196 transitions. [2023-11-23 22:37:59,403 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2023-11-23 22:37:59,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:37:59,405 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2023-11-23 22:37:59,405 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-23 22:37:59,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2196 transitions. [2023-11-23 22:37:59,412 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:59,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:59,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:59,416 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:59,416 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:59,417 INFO L748 eck$LassoCheckResult]: Stem: 30288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 30289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 31271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30738#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 30739#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30610#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30503#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30232#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29880#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29881#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29925#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29926#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30872#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30873#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30920#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30329#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30330#L1090 assume !(0 == ~M_E~0); 30376#L1090-2 assume !(0 == ~T1_E~0); 30377#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31061#L1100-1 assume !(0 == ~T3_E~0); 31062#L1105-1 assume !(0 == ~T4_E~0); 30153#L1110-1 assume !(0 == ~T5_E~0); 30154#L1115-1 assume !(0 == ~T6_E~0); 30542#L1120-1 assume !(0 == ~T7_E~0); 30847#L1125-1 assume !(0 == ~T8_E~0); 31319#L1130-1 assume !(0 == ~T9_E~0); 31082#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30334#L1140-1 assume !(0 == ~T11_E~0); 30335#L1145-1 assume !(0 == ~E_1~0); 31016#L1150-1 assume !(0 == ~E_2~0); 30516#L1155-1 assume !(0 == ~E_3~0); 30517#L1160-1 assume !(0 == ~E_4~0); 30615#L1165-1 assume !(0 == ~E_5~0); 30616#L1170-1 assume !(0 == ~E_6~0); 31254#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 30696#L1180-1 assume !(0 == ~E_8~0); 30697#L1185-1 assume !(0 == ~E_9~0); 30331#L1190-1 assume !(0 == ~E_10~0); 30332#L1195-1 assume !(0 == ~E_11~0); 30712#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30536#L525 assume !(1 == ~m_pc~0); 29970#L525-2 is_master_triggered_~__retres1~0#1 := 0; 29971#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31156#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31131#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30321#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30322#L544 assume 1 == ~t1_pc~0; 30591#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30538#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29949#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29950#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 30176#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30816#L563 assume !(1 == ~t2_pc~0); 31004#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29989#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29990#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30403#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 30404#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30894#L582 assume 1 == ~t3_pc~0; 30122#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30123#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29872#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29873#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 30058#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30059#L601 assume !(1 == ~t4_pc~0); 31028#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30543#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30072#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30073#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 31023#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31295#L620 assume 1 == ~t5_pc~0; 30021#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30022#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30910#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31162#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 31304#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31305#L639 assume !(1 == ~t6_pc~0); 30845#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30440#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30441#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30489#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 30548#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30549#L658 assume 1 == ~t7_pc~0; 30846#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30763#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31310#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30963#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 30324#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30325#L677 assume 1 == ~t8_pc~0; 30554#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30138#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30139#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30396#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 30397#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31123#L696 assume !(1 == ~t9_pc~0); 30831#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 30832#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30601#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30602#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30854#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31066#L715 assume 1 == ~t10_pc~0; 31072#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30944#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30750#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30751#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 30690#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30129#L734 assume !(1 == ~t11_pc~0); 30130#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 30617#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30701#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29870#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 29871#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30911#L1213 assume !(1 == ~M_E~0); 30688#L1213-2 assume !(1 == ~T1_E~0); 30689#L1218-1 assume !(1 == ~T2_E~0); 29903#L1223-1 assume !(1 == ~T3_E~0); 29904#L1228-1 assume !(1 == ~T4_E~0); 30663#L1233-1 assume !(1 == ~T5_E~0); 31306#L1238-1 assume !(1 == ~T6_E~0); 31021#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31022#L1248-1 assume !(1 == ~T8_E~0); 31068#L1253-1 assume !(1 == ~T9_E~0); 31069#L1258-1 assume !(1 == ~T10_E~0); 31044#L1263-1 assume !(1 == ~T11_E~0); 31045#L1268-1 assume !(1 == ~E_1~0); 30865#L1273-1 assume !(1 == ~E_2~0); 30866#L1278-1 assume !(1 == ~E_3~0); 30436#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30437#L1288-1 assume !(1 == ~E_5~0); 31167#L1293-1 assume !(1 == ~E_6~0); 31127#L1298-1 assume !(1 == ~E_7~0); 30898#L1303-1 assume !(1 == ~E_8~0); 30446#L1308-1 assume !(1 == ~E_9~0); 30338#L1313-1 assume !(1 == ~E_10~0); 30339#L1318-1 assume !(1 == ~E_11~0); 30349#L1323-1 assume { :end_inline_reset_delta_events } true; 30350#L1644-2 [2023-11-23 22:37:59,418 INFO L750 eck$LassoCheckResult]: Loop: 30350#L1644-2 assume !false; 30960#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30254#L1065-1 assume !false; 30255#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31302#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29985#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30562#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30451#L906 assume !(0 != eval_~tmp~0#1); 30453#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30773#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30774#L1090-3 assume !(0 == ~M_E~0); 31182#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31239#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31204#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31205#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30227#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30228#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30504#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30505#L1125-3 assume !(0 == ~T8_E~0); 31020#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31277#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30426#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29935#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29936#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30060#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30061#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30409#L1165-3 assume !(0 == ~E_5~0); 30410#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30809#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30323#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30084#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30085#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31265#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31266#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30641#L525-36 assume !(1 == ~m_pc~0); 30642#L525-38 is_master_triggered_~__retres1~0#1 := 0; 30185#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30186#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30461#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30462#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30373#L544-36 assume 1 == ~t1_pc~0; 30374#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30932#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30933#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31270#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31252#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31157#L563-36 assume 1 == ~t2_pc~0; 30174#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29933#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29934#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31138#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30660#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30661#L582-36 assume 1 == ~t3_pc~0; 30493#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30494#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30592#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30593#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30698#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30638#L601-36 assume 1 == ~t4_pc~0; 30524#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30525#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30790#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30791#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31243#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31144#L620-36 assume 1 == ~t5_pc~0; 30577#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30578#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31005#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30551#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 30194#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29981#L639-36 assume 1 == ~t6_pc~0; 29982#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30019#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30020#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30244#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30245#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30850#L658-36 assume !(1 == ~t7_pc~0); 29994#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 29995#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31229#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29972#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29973#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30994#L677-36 assume 1 == ~t8_pc~0; 31171#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30766#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30895#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30896#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30792#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30793#L696-36 assume 1 == ~t9_pc~0; 30684#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30685#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30626#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30627#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30810#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30811#L715-36 assume !(1 == ~t10_pc~0); 30772#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 29868#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29869#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29846#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29847#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30237#L734-36 assume !(1 == ~t11_pc~0); 29947#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 29948#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30253#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29862#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29863#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30874#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30510#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30511#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30285#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30286#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30465#L1233-3 assume !(1 == ~T5_E~0); 30466#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30735#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30736#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31242#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31244#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30267#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30268#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31217#L1273-3 assume !(1 == ~E_2~0); 31232#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31234#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30613#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30614#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30459#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30460#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30956#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30456#L1313-3 assume !(1 == ~E_10~0); 30457#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30269#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30270#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 30212#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30438#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30439#L1663 assume !(0 == start_simulation_~tmp~3#1); 30110#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30848#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 30056#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29939#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29940#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30005#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30328#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 30794#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 30350#L1644-2 [2023-11-23 22:37:59,418 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:59,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1655107556, now seen corresponding path program 1 times [2023-11-23 22:37:59,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:59,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808526042] [2023-11-23 22:37:59,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:59,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:59,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:59,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:59,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:59,484 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808526042] [2023-11-23 22:37:59,484 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808526042] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:59,484 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:59,485 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:59,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [331683398] [2023-11-23 22:37:59,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:59,486 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:59,486 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:59,486 INFO L85 PathProgramCache]: Analyzing trace with hash -658480883, now seen corresponding path program 2 times [2023-11-23 22:37:59,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:59,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25166890] [2023-11-23 22:37:59,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:59,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:59,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:59,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:59,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:59,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25166890] [2023-11-23 22:37:59,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25166890] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:59,622 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:59,622 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:59,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1225356401] [2023-11-23 22:37:59,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:59,623 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:59,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:59,624 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:59,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:59,625 INFO L87 Difference]: Start difference. First operand 1488 states and 2196 transitions. cyclomatic complexity: 709 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:59,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:37:59,671 INFO L93 Difference]: Finished difference Result 1488 states and 2195 transitions. [2023-11-23 22:37:59,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2195 transitions. [2023-11-23 22:37:59,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:59,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2195 transitions. [2023-11-23 22:37:59,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:37:59,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:37:59,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2195 transitions. [2023-11-23 22:37:59,698 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:37:59,698 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2023-11-23 22:37:59,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2195 transitions. [2023-11-23 22:37:59,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:37:59,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4751344086021505) internal successors, (2195), 1487 states have internal predecessors, (2195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:37:59,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2195 transitions. [2023-11-23 22:37:59,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2023-11-23 22:37:59,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:37:59,737 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2023-11-23 22:37:59,737 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-23 22:37:59,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2195 transitions. [2023-11-23 22:37:59,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:37:59,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:37:59,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:37:59,747 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:59,748 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:37:59,748 INFO L748 eck$LassoCheckResult]: Stem: 33271#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 33272#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 34253#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34254#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33721#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 33722#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33593#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33486#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33215#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32863#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32864#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32908#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32909#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33851#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33852#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33896#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 33312#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33313#L1090 assume !(0 == ~M_E~0); 33355#L1090-2 assume !(0 == ~T1_E~0); 33356#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34043#L1100-1 assume !(0 == ~T3_E~0); 34044#L1105-1 assume !(0 == ~T4_E~0); 33135#L1110-1 assume !(0 == ~T5_E~0); 33136#L1115-1 assume !(0 == ~T6_E~0); 33522#L1120-1 assume !(0 == ~T7_E~0); 33830#L1125-1 assume !(0 == ~T8_E~0); 34302#L1130-1 assume !(0 == ~T9_E~0); 34065#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33317#L1140-1 assume !(0 == ~T11_E~0); 33318#L1145-1 assume !(0 == ~E_1~0); 33999#L1150-1 assume !(0 == ~E_2~0); 33499#L1155-1 assume !(0 == ~E_3~0); 33500#L1160-1 assume !(0 == ~E_4~0); 33598#L1165-1 assume !(0 == ~E_5~0); 33599#L1170-1 assume !(0 == ~E_6~0); 34237#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 33679#L1180-1 assume !(0 == ~E_8~0); 33680#L1185-1 assume !(0 == ~E_9~0); 33314#L1190-1 assume !(0 == ~E_10~0); 33315#L1195-1 assume !(0 == ~E_11~0); 33695#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33514#L525 assume !(1 == ~m_pc~0); 32953#L525-2 is_master_triggered_~__retres1~0#1 := 0; 32954#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34139#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34112#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33304#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33305#L544 assume 1 == ~t1_pc~0; 33574#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33521#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32927#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32928#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 33159#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33799#L563 assume !(1 == ~t2_pc~0); 33985#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32972#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32973#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33383#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 33384#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33877#L582 assume 1 == ~t3_pc~0; 33103#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33104#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32855#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32856#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 33041#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33042#L601 assume !(1 == ~t4_pc~0); 34011#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33523#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33053#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33054#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 34006#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34278#L620 assume 1 == ~t5_pc~0; 33000#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33001#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33893#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34144#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 34287#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34288#L639 assume !(1 == ~t6_pc~0); 33828#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33421#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33422#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33472#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 33529#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33530#L658 assume 1 == ~t7_pc~0; 33829#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33745#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34293#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33945#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 33307#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33308#L677 assume 1 == ~t8_pc~0; 33535#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33118#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33119#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33379#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 33380#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34106#L696 assume !(1 == ~t9_pc~0); 33811#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 33812#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33584#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33585#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33835#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34048#L715 assume 1 == ~t10_pc~0; 34055#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33927#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33733#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33734#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 33673#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33112#L734 assume !(1 == ~t11_pc~0); 33113#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 33600#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33682#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32851#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 32852#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33894#L1213 assume !(1 == ~M_E~0); 33670#L1213-2 assume !(1 == ~T1_E~0); 33671#L1218-1 assume !(1 == ~T2_E~0); 32886#L1223-1 assume !(1 == ~T3_E~0); 32887#L1228-1 assume !(1 == ~T4_E~0); 33646#L1233-1 assume !(1 == ~T5_E~0); 34289#L1238-1 assume !(1 == ~T6_E~0); 34004#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34005#L1248-1 assume !(1 == ~T8_E~0); 34051#L1253-1 assume !(1 == ~T9_E~0); 34052#L1258-1 assume !(1 == ~T10_E~0); 34027#L1263-1 assume !(1 == ~T11_E~0); 34028#L1268-1 assume !(1 == ~E_1~0); 33848#L1273-1 assume !(1 == ~E_2~0); 33849#L1278-1 assume !(1 == ~E_3~0); 33419#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33420#L1288-1 assume !(1 == ~E_5~0); 34150#L1293-1 assume !(1 == ~E_6~0); 34110#L1298-1 assume !(1 == ~E_7~0); 33881#L1303-1 assume !(1 == ~E_8~0); 33429#L1308-1 assume !(1 == ~E_9~0); 33321#L1313-1 assume !(1 == ~E_10~0); 33322#L1318-1 assume !(1 == ~E_11~0); 33329#L1323-1 assume { :end_inline_reset_delta_events } true; 33330#L1644-2 [2023-11-23 22:37:59,749 INFO L750 eck$LassoCheckResult]: Loop: 33330#L1644-2 assume !false; 33943#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33236#L1065-1 assume !false; 33237#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34285#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32968#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33545#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33434#L906 assume !(0 != eval_~tmp~0#1); 33436#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33755#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33756#L1090-3 assume !(0 == ~M_E~0); 34165#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34222#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34187#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34188#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33210#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33211#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33487#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33488#L1125-3 assume !(0 == ~T8_E~0); 34003#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34260#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33409#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32918#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32919#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33043#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33044#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33392#L1165-3 assume !(0 == ~E_5~0); 33393#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33792#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33306#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33067#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33068#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34248#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34249#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33627#L525-36 assume !(1 == ~m_pc~0); 33628#L525-38 is_master_triggered_~__retres1~0#1 := 0; 33168#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33169#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33444#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33445#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33358#L544-36 assume !(1 == ~t1_pc~0); 33360#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 33915#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33916#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34255#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34235#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34140#L563-36 assume 1 == ~t2_pc~0; 33157#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32916#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32917#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34121#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33643#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33644#L582-36 assume 1 == ~t3_pc~0; 33476#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33477#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33575#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33576#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33681#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33621#L601-36 assume 1 == ~t4_pc~0; 33507#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33508#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33773#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33774#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34226#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34127#L620-36 assume 1 == ~t5_pc~0; 33560#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33561#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33988#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33534#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 33177#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32964#L639-36 assume 1 == ~t6_pc~0; 32965#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33005#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33006#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33227#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33228#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33833#L658-36 assume !(1 == ~t7_pc~0); 32977#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 32978#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34212#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32955#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32956#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33977#L677-36 assume !(1 == ~t8_pc~0); 33748#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 33749#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33878#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33879#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33775#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33776#L696-36 assume 1 == ~t9_pc~0; 33667#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33668#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33609#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33610#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33793#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33794#L715-36 assume 1 == ~t10_pc~0; 33938#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32853#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32854#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32829#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32830#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33220#L734-36 assume !(1 == ~t11_pc~0); 32932#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 32933#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33238#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32845#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32846#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33857#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33495#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33496#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33268#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33269#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33448#L1233-3 assume !(1 == ~T5_E~0); 33449#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33718#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33719#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34225#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34227#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33251#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33252#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34200#L1273-3 assume !(1 == ~E_2~0); 34215#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34217#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33596#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33597#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33442#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33443#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33939#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33439#L1313-3 assume !(1 == ~E_10~0); 33440#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33253#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33254#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 33195#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33423#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 33424#L1663 assume !(0 == start_simulation_~tmp~3#1); 33086#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33831#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 33039#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 32926#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32988#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33311#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 33777#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 33330#L1644-2 [2023-11-23 22:37:59,750 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:59,750 INFO L85 PathProgramCache]: Analyzing trace with hash -589450842, now seen corresponding path program 1 times [2023-11-23 22:37:59,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:59,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1133787616] [2023-11-23 22:37:59,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:59,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:59,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:59,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:59,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:59,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1133787616] [2023-11-23 22:37:59,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1133787616] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:59,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:59,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:37:59,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768759267] [2023-11-23 22:37:59,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:59,854 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:37:59,855 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:37:59,855 INFO L85 PathProgramCache]: Analyzing trace with hash -1567805460, now seen corresponding path program 1 times [2023-11-23 22:37:59,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:37:59,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866963210] [2023-11-23 22:37:59,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:37:59,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:37:59,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:37:59,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:37:59,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:37:59,942 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1866963210] [2023-11-23 22:37:59,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1866963210] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:37:59,942 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:37:59,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:37:59,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703526124] [2023-11-23 22:37:59,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:37:59,943 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:37:59,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:37:59,944 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:37:59,944 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:37:59,944 INFO L87 Difference]: Start difference. First operand 1488 states and 2195 transitions. cyclomatic complexity: 708 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:00,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:00,022 INFO L93 Difference]: Finished difference Result 1488 states and 2190 transitions. [2023-11-23 22:38:00,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2190 transitions. [2023-11-23 22:38:00,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:38:00,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2190 transitions. [2023-11-23 22:38:00,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:38:00,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:38:00,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2190 transitions. [2023-11-23 22:38:00,052 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:00,052 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2023-11-23 22:38:00,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2190 transitions. [2023-11-23 22:38:00,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:38:00,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.471774193548387) internal successors, (2190), 1487 states have internal predecessors, (2190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:00,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2190 transitions. [2023-11-23 22:38:00,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2023-11-23 22:38:00,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:00,098 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2023-11-23 22:38:00,099 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-23 22:38:00,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2190 transitions. [2023-11-23 22:38:00,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:38:00,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:00,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:00,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:00,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:00,110 INFO L748 eck$LassoCheckResult]: Stem: 36254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 36255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 37237#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37238#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36704#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 36705#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36576#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36469#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36198#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35846#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35847#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35891#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35892#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36836#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36837#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36882#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36295#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36296#L1090 assume !(0 == ~M_E~0); 36341#L1090-2 assume !(0 == ~T1_E~0); 36342#L1095-1 assume !(0 == ~T2_E~0); 37027#L1100-1 assume !(0 == ~T3_E~0); 37028#L1105-1 assume !(0 == ~T4_E~0); 36119#L1110-1 assume !(0 == ~T5_E~0); 36120#L1115-1 assume !(0 == ~T6_E~0); 36505#L1120-1 assume !(0 == ~T7_E~0); 36813#L1125-1 assume !(0 == ~T8_E~0); 37285#L1130-1 assume !(0 == ~T9_E~0); 37048#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36300#L1140-1 assume !(0 == ~T11_E~0); 36301#L1145-1 assume !(0 == ~E_1~0); 36982#L1150-1 assume !(0 == ~E_2~0); 36482#L1155-1 assume !(0 == ~E_3~0); 36483#L1160-1 assume !(0 == ~E_4~0); 36581#L1165-1 assume !(0 == ~E_5~0); 36582#L1170-1 assume !(0 == ~E_6~0); 37220#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 36662#L1180-1 assume !(0 == ~E_8~0); 36663#L1185-1 assume !(0 == ~E_9~0); 36297#L1190-1 assume !(0 == ~E_10~0); 36298#L1195-1 assume !(0 == ~E_11~0); 36678#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36502#L525 assume !(1 == ~m_pc~0); 35936#L525-2 is_master_triggered_~__retres1~0#1 := 0; 35937#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37122#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37097#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36287#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36288#L544 assume 1 == ~t1_pc~0; 36557#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36504#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35915#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35916#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 36142#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36782#L563 assume !(1 == ~t2_pc~0); 36968#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35955#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36369#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 36370#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36860#L582 assume 1 == ~t3_pc~0; 36088#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36089#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35838#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35839#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 36024#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36025#L601 assume !(1 == ~t4_pc~0); 36994#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36506#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36038#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36039#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 36989#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37261#L620 assume 1 == ~t5_pc~0; 35987#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35988#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36876#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37128#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 37270#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37271#L639 assume !(1 == ~t6_pc~0); 36811#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36406#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36407#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36455#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 36512#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36513#L658 assume 1 == ~t7_pc~0; 36812#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36729#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37276#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36929#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 36290#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36291#L677 assume 1 == ~t8_pc~0; 36520#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36101#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36102#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36362#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 36363#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37089#L696 assume !(1 == ~t9_pc~0); 36796#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 36797#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36567#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36568#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36820#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37031#L715 assume 1 == ~t10_pc~0; 37038#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36910#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36716#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36717#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 36656#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36095#L734 assume !(1 == ~t11_pc~0); 36096#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 36583#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36667#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35836#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 35837#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36877#L1213 assume !(1 == ~M_E~0); 36654#L1213-2 assume !(1 == ~T1_E~0); 36655#L1218-1 assume !(1 == ~T2_E~0); 35869#L1223-1 assume !(1 == ~T3_E~0); 35870#L1228-1 assume !(1 == ~T4_E~0); 36629#L1233-1 assume !(1 == ~T5_E~0); 37272#L1238-1 assume !(1 == ~T6_E~0); 36987#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36988#L1248-1 assume !(1 == ~T8_E~0); 37034#L1253-1 assume !(1 == ~T9_E~0); 37035#L1258-1 assume !(1 == ~T10_E~0); 37010#L1263-1 assume !(1 == ~T11_E~0); 37011#L1268-1 assume !(1 == ~E_1~0); 36831#L1273-1 assume !(1 == ~E_2~0); 36832#L1278-1 assume !(1 == ~E_3~0); 36402#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 36403#L1288-1 assume !(1 == ~E_5~0); 37133#L1293-1 assume !(1 == ~E_6~0); 37093#L1298-1 assume !(1 == ~E_7~0); 36864#L1303-1 assume !(1 == ~E_8~0); 36412#L1308-1 assume !(1 == ~E_9~0); 36304#L1313-1 assume !(1 == ~E_10~0); 36305#L1318-1 assume !(1 == ~E_11~0); 36315#L1323-1 assume { :end_inline_reset_delta_events } true; 36316#L1644-2 [2023-11-23 22:38:00,110 INFO L750 eck$LassoCheckResult]: Loop: 36316#L1644-2 assume !false; 36926#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36220#L1065-1 assume !false; 36221#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 37268#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35951#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36528#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36417#L906 assume !(0 != eval_~tmp~0#1); 36419#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36739#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36740#L1090-3 assume !(0 == ~M_E~0); 37148#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37205#L1095-3 assume !(0 == ~T2_E~0); 37170#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37171#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36193#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36194#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36470#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36471#L1125-3 assume !(0 == ~T8_E~0); 36986#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37243#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36394#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35903#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35904#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36027#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36028#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36375#L1165-3 assume !(0 == ~E_5~0); 36376#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36775#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36289#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36053#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36054#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37231#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 37232#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36605#L525-36 assume !(1 == ~m_pc~0); 36606#L525-38 is_master_triggered_~__retres1~0#1 := 0; 36151#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36152#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36427#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36428#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36338#L544-36 assume 1 == ~t1_pc~0; 36339#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36898#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36899#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37236#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37218#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37123#L563-36 assume 1 == ~t2_pc~0; 36140#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35899#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35900#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37104#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36626#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36627#L582-36 assume 1 == ~t3_pc~0; 36459#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36460#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36558#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36559#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36664#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36604#L601-36 assume 1 == ~t4_pc~0; 36490#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36491#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36756#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36757#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37209#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37110#L620-36 assume 1 == ~t5_pc~0; 36541#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36542#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36971#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36517#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 36160#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35947#L639-36 assume 1 == ~t6_pc~0; 35948#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35985#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35986#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36210#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36211#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36816#L658-36 assume !(1 == ~t7_pc~0); 35960#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 35961#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37195#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35938#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35939#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36960#L677-36 assume 1 == ~t8_pc~0; 37137#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36732#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36861#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36862#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36758#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36759#L696-36 assume 1 == ~t9_pc~0; 36650#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36651#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36592#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36593#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36776#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36777#L715-36 assume !(1 == ~t10_pc~0); 36738#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 35834#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35835#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35812#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35813#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36203#L734-36 assume !(1 == ~t11_pc~0); 35913#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 35914#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36219#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35828#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35829#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36840#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36476#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36477#L1218-3 assume !(1 == ~T2_E~0); 36251#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36252#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36431#L1233-3 assume !(1 == ~T5_E~0); 36432#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36701#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36702#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37208#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37210#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36233#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36234#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37183#L1273-3 assume !(1 == ~E_2~0); 37198#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37200#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36579#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36580#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36425#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36426#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36922#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36422#L1313-3 assume !(1 == ~E_10~0); 36423#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36235#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36236#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 36178#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 36405#L1663 assume !(0 == start_simulation_~tmp~3#1); 36076#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36814#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 36022#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35905#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 35906#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35971#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36294#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 36760#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 36316#L1644-2 [2023-11-23 22:38:00,111 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:00,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1863040740, now seen corresponding path program 1 times [2023-11-23 22:38:00,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:00,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121866260] [2023-11-23 22:38:00,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:00,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:00,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:00,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:00,265 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:00,266 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121866260] [2023-11-23 22:38:00,266 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121866260] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:00,266 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:00,266 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:00,283 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [665074713] [2023-11-23 22:38:00,283 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:00,284 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:00,284 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:00,285 INFO L85 PathProgramCache]: Analyzing trace with hash 2067663241, now seen corresponding path program 1 times [2023-11-23 22:38:00,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:00,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145925755] [2023-11-23 22:38:00,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:00,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:00,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:00,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:00,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:00,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145925755] [2023-11-23 22:38:00,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1145925755] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:00,386 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:00,386 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:00,386 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [909179068] [2023-11-23 22:38:00,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:00,387 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:00,387 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:00,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:38:00,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:38:00,389 INFO L87 Difference]: Start difference. First operand 1488 states and 2190 transitions. cyclomatic complexity: 703 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:00,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:00,612 INFO L93 Difference]: Finished difference Result 2840 states and 4171 transitions. [2023-11-23 22:38:00,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2840 states and 4171 transitions. [2023-11-23 22:38:00,633 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2678 [2023-11-23 22:38:00,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2840 states to 2840 states and 4171 transitions. [2023-11-23 22:38:00,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2840 [2023-11-23 22:38:00,666 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2840 [2023-11-23 22:38:00,666 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2840 states and 4171 transitions. [2023-11-23 22:38:00,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:00,671 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2840 states and 4171 transitions. [2023-11-23 22:38:00,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2840 states and 4171 transitions. [2023-11-23 22:38:00,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2840 to 1488. [2023-11-23 22:38:00,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4704301075268817) internal successors, (2188), 1487 states have internal predecessors, (2188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:00,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2188 transitions. [2023-11-23 22:38:00,725 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2188 transitions. [2023-11-23 22:38:00,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:38:00,726 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2188 transitions. [2023-11-23 22:38:00,726 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-23 22:38:00,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2188 transitions. [2023-11-23 22:38:00,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:38:00,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:00,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:00,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:00,738 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:00,739 INFO L748 eck$LassoCheckResult]: Stem: 40592#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 40593#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 41574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41575#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41042#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 41043#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40914#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40807#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40536#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40184#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40185#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40229#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40230#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41172#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41173#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41217#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40633#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40634#L1090 assume !(0 == ~M_E~0); 40676#L1090-2 assume !(0 == ~T1_E~0); 40677#L1095-1 assume !(0 == ~T2_E~0); 41364#L1100-1 assume !(0 == ~T3_E~0); 41365#L1105-1 assume !(0 == ~T4_E~0); 40456#L1110-1 assume !(0 == ~T5_E~0); 40457#L1115-1 assume !(0 == ~T6_E~0); 40843#L1120-1 assume !(0 == ~T7_E~0); 41151#L1125-1 assume !(0 == ~T8_E~0); 41623#L1130-1 assume !(0 == ~T9_E~0); 41386#L1135-1 assume !(0 == ~T10_E~0); 40638#L1140-1 assume !(0 == ~T11_E~0); 40639#L1145-1 assume !(0 == ~E_1~0); 41320#L1150-1 assume !(0 == ~E_2~0); 40820#L1155-1 assume !(0 == ~E_3~0); 40821#L1160-1 assume !(0 == ~E_4~0); 40919#L1165-1 assume !(0 == ~E_5~0); 40920#L1170-1 assume !(0 == ~E_6~0); 41558#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 41000#L1180-1 assume !(0 == ~E_8~0); 41001#L1185-1 assume !(0 == ~E_9~0); 40635#L1190-1 assume !(0 == ~E_10~0); 40636#L1195-1 assume !(0 == ~E_11~0); 41016#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40835#L525 assume !(1 == ~m_pc~0); 40274#L525-2 is_master_triggered_~__retres1~0#1 := 0; 40275#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41460#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41433#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40625#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40626#L544 assume 1 == ~t1_pc~0; 40895#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40842#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40249#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 40480#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41120#L563 assume !(1 == ~t2_pc~0); 41306#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40293#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40294#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40704#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 40705#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41198#L582 assume 1 == ~t3_pc~0; 40424#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40425#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40176#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40177#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 40362#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40363#L601 assume !(1 == ~t4_pc~0); 41332#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40844#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40372#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40373#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 41327#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41599#L620 assume 1 == ~t5_pc~0; 40321#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40322#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41214#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41465#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 41608#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41609#L639 assume !(1 == ~t6_pc~0); 41149#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40742#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40743#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40793#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 40850#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40851#L658 assume 1 == ~t7_pc~0; 41150#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41066#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41614#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41266#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 40628#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40629#L677 assume 1 == ~t8_pc~0; 40856#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40439#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40440#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40700#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 40701#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41427#L696 assume !(1 == ~t9_pc~0); 41132#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 41133#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40905#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40906#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41156#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41369#L715 assume 1 == ~t10_pc~0; 41376#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41248#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41054#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41055#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 40994#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40433#L734 assume !(1 == ~t11_pc~0); 40434#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 40921#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41003#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40172#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 40173#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41215#L1213 assume !(1 == ~M_E~0); 40991#L1213-2 assume !(1 == ~T1_E~0); 40992#L1218-1 assume !(1 == ~T2_E~0); 40207#L1223-1 assume !(1 == ~T3_E~0); 40208#L1228-1 assume !(1 == ~T4_E~0); 40967#L1233-1 assume !(1 == ~T5_E~0); 41610#L1238-1 assume !(1 == ~T6_E~0); 41325#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41326#L1248-1 assume !(1 == ~T8_E~0); 41372#L1253-1 assume !(1 == ~T9_E~0); 41373#L1258-1 assume !(1 == ~T10_E~0); 41348#L1263-1 assume !(1 == ~T11_E~0); 41349#L1268-1 assume !(1 == ~E_1~0); 41169#L1273-1 assume !(1 == ~E_2~0); 41170#L1278-1 assume !(1 == ~E_3~0); 40740#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 40741#L1288-1 assume !(1 == ~E_5~0); 41471#L1293-1 assume !(1 == ~E_6~0); 41431#L1298-1 assume !(1 == ~E_7~0); 41202#L1303-1 assume !(1 == ~E_8~0); 40750#L1308-1 assume !(1 == ~E_9~0); 40642#L1313-1 assume !(1 == ~E_10~0); 40643#L1318-1 assume !(1 == ~E_11~0); 40650#L1323-1 assume { :end_inline_reset_delta_events } true; 40651#L1644-2 [2023-11-23 22:38:00,740 INFO L750 eck$LassoCheckResult]: Loop: 40651#L1644-2 assume !false; 41264#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40557#L1065-1 assume !false; 40558#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41606#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40289#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40866#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40755#L906 assume !(0 != eval_~tmp~0#1); 40757#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41076#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41077#L1090-3 assume !(0 == ~M_E~0); 41486#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41543#L1095-3 assume !(0 == ~T2_E~0); 41508#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41509#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40531#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40532#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40808#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40809#L1125-3 assume !(0 == ~T8_E~0); 41324#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41581#L1135-3 assume !(0 == ~T10_E~0); 40730#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40239#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40240#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40364#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40365#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40713#L1165-3 assume !(0 == ~E_5~0); 40714#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41113#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40627#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40388#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40389#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41569#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41570#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40948#L525-36 assume !(1 == ~m_pc~0); 40949#L525-38 is_master_triggered_~__retres1~0#1 := 0; 40489#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40490#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40765#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40766#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40679#L544-36 assume 1 == ~t1_pc~0; 40680#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41236#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41237#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41576#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41556#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41461#L563-36 assume 1 == ~t2_pc~0; 40478#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40237#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40238#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41442#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40964#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40965#L582-36 assume 1 == ~t3_pc~0; 40797#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40798#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40896#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40897#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41002#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40942#L601-36 assume 1 == ~t4_pc~0; 40828#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40829#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41094#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41095#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41547#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41448#L620-36 assume 1 == ~t5_pc~0; 40881#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40882#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41309#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40855#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 40498#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40285#L639-36 assume 1 == ~t6_pc~0; 40286#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40326#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40327#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40548#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40549#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41154#L658-36 assume !(1 == ~t7_pc~0); 40298#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 40299#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41533#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40276#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40277#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41298#L677-36 assume 1 == ~t8_pc~0; 41475#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41070#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41199#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41200#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41096#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41097#L696-36 assume 1 == ~t9_pc~0; 40988#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40989#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40930#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40931#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41114#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41115#L715-36 assume !(1 == ~t10_pc~0); 41078#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 40174#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40175#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40150#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40151#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40541#L734-36 assume !(1 == ~t11_pc~0); 40253#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 40254#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40559#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40166#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40167#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41178#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40816#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40817#L1218-3 assume !(1 == ~T2_E~0); 40589#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40590#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40769#L1233-3 assume !(1 == ~T5_E~0); 40770#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41039#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41040#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41546#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41548#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40572#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40573#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41521#L1273-3 assume !(1 == ~E_2~0); 41536#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41538#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40917#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40918#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40763#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40764#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41260#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40760#L1313-3 assume !(1 == ~E_10~0); 40761#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40574#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40575#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40516#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40744#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 40745#L1663 assume !(0 == start_simulation_~tmp~3#1); 40414#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41152#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40360#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40246#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 40247#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40309#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40632#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41098#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 40651#L1644-2 [2023-11-23 22:38:00,741 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:00,741 INFO L85 PathProgramCache]: Analyzing trace with hash -268309982, now seen corresponding path program 1 times [2023-11-23 22:38:00,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:00,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826756055] [2023-11-23 22:38:00,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:00,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:00,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:00,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:00,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:00,831 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826756055] [2023-11-23 22:38:00,831 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826756055] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:00,831 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:00,831 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:38:00,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315922787] [2023-11-23 22:38:00,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:00,832 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:00,833 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:00,833 INFO L85 PathProgramCache]: Analyzing trace with hash 17254343, now seen corresponding path program 1 times [2023-11-23 22:38:00,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:00,834 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745777651] [2023-11-23 22:38:00,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:00,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:00,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:00,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:00,917 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:00,917 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745777651] [2023-11-23 22:38:00,917 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745777651] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:00,917 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:00,918 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:00,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1103484843] [2023-11-23 22:38:00,918 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:00,919 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:00,919 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:00,919 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:00,920 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:00,920 INFO L87 Difference]: Start difference. First operand 1488 states and 2188 transitions. cyclomatic complexity: 701 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:01,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:01,021 INFO L93 Difference]: Finished difference Result 1488 states and 2170 transitions. [2023-11-23 22:38:01,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2170 transitions. [2023-11-23 22:38:01,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:38:01,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2170 transitions. [2023-11-23 22:38:01,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-23 22:38:01,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-23 22:38:01,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2170 transitions. [2023-11-23 22:38:01,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:01,049 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2023-11-23 22:38:01,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2170 transitions. [2023-11-23 22:38:01,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-23 22:38:01,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4583333333333333) internal successors, (2170), 1487 states have internal predecessors, (2170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:01,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2170 transitions. [2023-11-23 22:38:01,091 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2023-11-23 22:38:01,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:01,092 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2023-11-23 22:38:01,093 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-23 22:38:01,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2170 transitions. [2023-11-23 22:38:01,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-23 22:38:01,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:01,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:01,103 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:01,103 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:01,104 INFO L748 eck$LassoCheckResult]: Stem: 43575#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 43576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 44557#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44558#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44024#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 44025#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43897#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43790#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43519#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43167#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43168#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43212#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43213#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44155#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44156#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44200#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43616#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43617#L1090 assume !(0 == ~M_E~0); 43659#L1090-2 assume !(0 == ~T1_E~0); 43660#L1095-1 assume !(0 == ~T2_E~0); 44347#L1100-1 assume !(0 == ~T3_E~0); 44348#L1105-1 assume !(0 == ~T4_E~0); 43439#L1110-1 assume !(0 == ~T5_E~0); 43440#L1115-1 assume !(0 == ~T6_E~0); 43826#L1120-1 assume !(0 == ~T7_E~0); 44133#L1125-1 assume !(0 == ~T8_E~0); 44606#L1130-1 assume !(0 == ~T9_E~0); 44369#L1135-1 assume !(0 == ~T10_E~0); 43621#L1140-1 assume !(0 == ~T11_E~0); 43622#L1145-1 assume !(0 == ~E_1~0); 44303#L1150-1 assume !(0 == ~E_2~0); 43803#L1155-1 assume !(0 == ~E_3~0); 43804#L1160-1 assume !(0 == ~E_4~0); 43902#L1165-1 assume !(0 == ~E_5~0); 43903#L1170-1 assume !(0 == ~E_6~0); 44541#L1175-1 assume !(0 == ~E_7~0); 43982#L1180-1 assume !(0 == ~E_8~0); 43983#L1185-1 assume !(0 == ~E_9~0); 43618#L1190-1 assume !(0 == ~E_10~0); 43619#L1195-1 assume !(0 == ~E_11~0); 43998#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43818#L525 assume !(1 == ~m_pc~0); 43257#L525-2 is_master_triggered_~__retres1~0#1 := 0; 43258#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44443#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44416#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43608#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43609#L544 assume 1 == ~t1_pc~0; 43878#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43825#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43231#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43232#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 43463#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44102#L563 assume !(1 == ~t2_pc~0); 44289#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43276#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43277#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43687#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 43688#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44181#L582 assume 1 == ~t3_pc~0; 43407#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43408#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43159#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43160#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 43345#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43346#L601 assume !(1 == ~t4_pc~0); 44315#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43827#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43357#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43358#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 44310#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44582#L620 assume 1 == ~t5_pc~0; 43304#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43305#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44197#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44448#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 44591#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44592#L639 assume !(1 == ~t6_pc~0); 44131#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 43725#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43726#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43776#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 43833#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43834#L658 assume !(1 == ~t7_pc~0); 44047#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 44048#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44597#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44249#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 43611#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43612#L677 assume 1 == ~t8_pc~0; 43839#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43422#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43423#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43683#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 43684#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44410#L696 assume !(1 == ~t9_pc~0); 44114#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 44115#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43888#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43889#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44138#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44352#L715 assume 1 == ~t10_pc~0; 44359#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44231#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44036#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44037#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 43976#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43416#L734 assume !(1 == ~t11_pc~0); 43417#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 43904#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43985#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43155#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 43156#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44198#L1213 assume !(1 == ~M_E~0); 43973#L1213-2 assume !(1 == ~T1_E~0); 43974#L1218-1 assume !(1 == ~T2_E~0); 43190#L1223-1 assume !(1 == ~T3_E~0); 43191#L1228-1 assume !(1 == ~T4_E~0); 43949#L1233-1 assume !(1 == ~T5_E~0); 44593#L1238-1 assume !(1 == ~T6_E~0); 44308#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44309#L1248-1 assume !(1 == ~T8_E~0); 44355#L1253-1 assume !(1 == ~T9_E~0); 44356#L1258-1 assume !(1 == ~T10_E~0); 44331#L1263-1 assume !(1 == ~T11_E~0); 44332#L1268-1 assume !(1 == ~E_1~0); 44152#L1273-1 assume !(1 == ~E_2~0); 44153#L1278-1 assume !(1 == ~E_3~0); 43723#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43724#L1288-1 assume !(1 == ~E_5~0); 44454#L1293-1 assume !(1 == ~E_6~0); 44414#L1298-1 assume !(1 == ~E_7~0); 44185#L1303-1 assume !(1 == ~E_8~0); 43733#L1308-1 assume !(1 == ~E_9~0); 43625#L1313-1 assume !(1 == ~E_10~0); 43626#L1318-1 assume !(1 == ~E_11~0); 43633#L1323-1 assume { :end_inline_reset_delta_events } true; 43634#L1644-2 [2023-11-23 22:38:01,105 INFO L750 eck$LassoCheckResult]: Loop: 43634#L1644-2 assume !false; 44247#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43540#L1065-1 assume !false; 43541#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 44589#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43272#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43849#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43738#L906 assume !(0 != eval_~tmp~0#1); 43740#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44058#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44059#L1090-3 assume !(0 == ~M_E~0); 44469#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44526#L1095-3 assume !(0 == ~T2_E~0); 44491#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44492#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43514#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43515#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43791#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43792#L1125-3 assume !(0 == ~T8_E~0); 44307#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44564#L1135-3 assume !(0 == ~T10_E~0); 43713#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43222#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43223#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43348#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43349#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43696#L1165-3 assume !(0 == ~E_5~0); 43697#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44095#L1175-3 assume !(0 == ~E_7~0); 43610#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43371#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43372#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44552#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44553#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43930#L525-36 assume !(1 == ~m_pc~0); 43931#L525-38 is_master_triggered_~__retres1~0#1 := 0; 43472#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43473#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43748#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43749#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43662#L544-36 assume !(1 == ~t1_pc~0); 43664#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 44219#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44220#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44559#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44539#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44444#L563-36 assume 1 == ~t2_pc~0; 43461#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43220#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43221#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44425#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43946#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43947#L582-36 assume 1 == ~t3_pc~0; 43780#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43781#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43879#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43880#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43984#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43924#L601-36 assume 1 == ~t4_pc~0; 43811#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43812#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44076#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44077#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44530#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44431#L620-36 assume 1 == ~t5_pc~0; 43864#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43865#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44292#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43838#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 43481#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43268#L639-36 assume 1 == ~t6_pc~0; 43269#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43309#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43310#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43531#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43532#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44136#L658-36 assume !(1 == ~t7_pc~0); 43281#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 43282#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44516#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43259#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43260#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44281#L677-36 assume !(1 == ~t8_pc~0); 44051#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 44052#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44182#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44183#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44078#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44079#L696-36 assume 1 == ~t9_pc~0; 43970#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43971#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43913#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43914#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44096#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44097#L715-36 assume 1 == ~t10_pc~0; 44242#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43157#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43158#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43135#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43136#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43524#L734-36 assume !(1 == ~t11_pc~0); 43236#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 43237#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43542#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43149#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43150#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44161#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43799#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43800#L1218-3 assume !(1 == ~T2_E~0); 43572#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43573#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43752#L1233-3 assume !(1 == ~T5_E~0); 43753#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44021#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44022#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44529#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44531#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43555#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43556#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44504#L1273-3 assume !(1 == ~E_2~0); 44519#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44521#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43900#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43901#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43746#L1298-3 assume !(1 == ~E_7~0); 43747#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44243#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43743#L1313-3 assume !(1 == ~E_10~0); 43744#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43557#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 43558#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43499#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43727#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 43728#L1663 assume !(0 == start_simulation_~tmp~3#1); 43390#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 44134#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43343#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43226#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 43227#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43289#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43615#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 44080#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 43634#L1644-2 [2023-11-23 22:38:01,106 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:01,106 INFO L85 PathProgramCache]: Analyzing trace with hash -2032217409, now seen corresponding path program 1 times [2023-11-23 22:38:01,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:01,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021776129] [2023-11-23 22:38:01,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:01,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:01,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:01,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:01,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:01,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021776129] [2023-11-23 22:38:01,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021776129] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:01,249 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:01,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:38:01,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1403248924] [2023-11-23 22:38:01,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:01,250 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:01,250 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:01,250 INFO L85 PathProgramCache]: Analyzing trace with hash -884328670, now seen corresponding path program 1 times [2023-11-23 22:38:01,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:01,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83752690] [2023-11-23 22:38:01,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:01,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:01,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:01,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:01,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:01,333 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [83752690] [2023-11-23 22:38:01,333 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [83752690] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:01,333 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:01,333 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:01,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1186663882] [2023-11-23 22:38:01,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:01,334 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:01,334 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:01,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 22:38:01,335 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 22:38:01,335 INFO L87 Difference]: Start difference. First operand 1488 states and 2170 transitions. cyclomatic complexity: 683 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:01,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:01,933 INFO L93 Difference]: Finished difference Result 3985 states and 5734 transitions. [2023-11-23 22:38:01,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3985 states and 5734 transitions. [2023-11-23 22:38:01,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3653 [2023-11-23 22:38:01,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3985 states to 3985 states and 5734 transitions. [2023-11-23 22:38:01,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3985 [2023-11-23 22:38:02,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3985 [2023-11-23 22:38:02,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3985 states and 5734 transitions. [2023-11-23 22:38:02,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:02,009 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3985 states and 5734 transitions. [2023-11-23 22:38:02,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3985 states and 5734 transitions. [2023-11-23 22:38:02,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3985 to 1530. [2023-11-23 22:38:02,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1530 states, 1530 states have (on average 1.445751633986928) internal successors, (2212), 1529 states have internal predecessors, (2212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:02,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1530 states to 1530 states and 2212 transitions. [2023-11-23 22:38:02,073 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1530 states and 2212 transitions. [2023-11-23 22:38:02,074 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-23 22:38:02,074 INFO L428 stractBuchiCegarLoop]: Abstraction has 1530 states and 2212 transitions. [2023-11-23 22:38:02,074 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-23 22:38:02,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1530 states and 2212 transitions. [2023-11-23 22:38:02,083 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1378 [2023-11-23 22:38:02,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:02,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:02,087 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:02,087 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:02,088 INFO L748 eck$LassoCheckResult]: Stem: 49062#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 49063#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 50070#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50071#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49517#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 49518#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49389#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49280#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49006#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48653#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48654#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48698#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48699#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49650#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49651#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49695#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49105#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49106#L1090 assume !(0 == ~M_E~0); 49148#L1090-2 assume !(0 == ~T1_E~0); 49149#L1095-1 assume !(0 == ~T2_E~0); 49846#L1100-1 assume !(0 == ~T3_E~0); 49847#L1105-1 assume !(0 == ~T4_E~0); 48925#L1110-1 assume !(0 == ~T5_E~0); 48926#L1115-1 assume !(0 == ~T6_E~0); 49316#L1120-1 assume !(0 == ~T7_E~0); 49628#L1125-1 assume !(0 == ~T8_E~0); 50129#L1130-1 assume !(0 == ~T9_E~0); 49869#L1135-1 assume !(0 == ~T10_E~0); 49110#L1140-1 assume !(0 == ~T11_E~0); 49111#L1145-1 assume !(0 == ~E_1~0); 49801#L1150-1 assume !(0 == ~E_2~0); 49293#L1155-1 assume !(0 == ~E_3~0); 49294#L1160-1 assume !(0 == ~E_4~0); 49394#L1165-1 assume !(0 == ~E_5~0); 49395#L1170-1 assume !(0 == ~E_6~0); 50053#L1175-1 assume !(0 == ~E_7~0); 49475#L1180-1 assume !(0 == ~E_8~0); 49476#L1185-1 assume !(0 == ~E_9~0); 49107#L1190-1 assume !(0 == ~E_10~0); 49108#L1195-1 assume !(0 == ~E_11~0); 49491#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49308#L525 assume !(1 == ~m_pc~0); 48743#L525-2 is_master_triggered_~__retres1~0#1 := 0; 48744#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50025#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49918#L1350 assume !(0 != activate_threads_~tmp~1#1); 49096#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49097#L544 assume 1 == ~t1_pc~0; 49368#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49315#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48717#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48718#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 48949#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49596#L563 assume !(1 == ~t2_pc~0); 49787#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48762#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48763#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49176#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 49177#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49676#L582 assume 1 == ~t3_pc~0; 48893#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48894#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48645#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48646#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 48831#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48832#L601 assume !(1 == ~t4_pc~0); 49813#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49317#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48841#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48842#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 49808#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50101#L620 assume 1 == ~t5_pc~0; 48790#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48791#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49692#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49952#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 50113#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50114#L639 assume !(1 == ~t6_pc~0); 49626#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49215#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49216#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49266#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 49323#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49324#L658 assume !(1 == ~t7_pc~0); 49540#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49541#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50119#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49746#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 49100#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49101#L677 assume 1 == ~t8_pc~0; 49329#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48908#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48909#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49172#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 49173#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49912#L696 assume !(1 == ~t9_pc~0); 49608#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 49609#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49378#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49379#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49633#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49851#L715 assume 1 == ~t10_pc~0; 49859#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49726#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49529#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49530#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 49469#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48902#L734 assume !(1 == ~t11_pc~0); 48903#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 49396#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49478#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48641#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 48642#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49693#L1213 assume !(1 == ~M_E~0); 49466#L1213-2 assume !(1 == ~T1_E~0); 49467#L1218-1 assume !(1 == ~T2_E~0); 48676#L1223-1 assume !(1 == ~T3_E~0); 48677#L1228-1 assume !(1 == ~T4_E~0); 49441#L1233-1 assume !(1 == ~T5_E~0); 50115#L1238-1 assume !(1 == ~T6_E~0); 49806#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49807#L1248-1 assume !(1 == ~T8_E~0); 49855#L1253-1 assume !(1 == ~T9_E~0); 49856#L1258-1 assume !(1 == ~T10_E~0); 49829#L1263-1 assume !(1 == ~T11_E~0); 49830#L1268-1 assume !(1 == ~E_1~0); 49647#L1273-1 assume !(1 == ~E_2~0); 49648#L1278-1 assume !(1 == ~E_3~0); 49213#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49214#L1288-1 assume !(1 == ~E_5~0); 49958#L1293-1 assume !(1 == ~E_6~0); 49916#L1298-1 assume !(1 == ~E_7~0); 49680#L1303-1 assume !(1 == ~E_8~0); 49223#L1308-1 assume !(1 == ~E_9~0); 49114#L1313-1 assume !(1 == ~E_10~0); 49115#L1318-1 assume !(1 == ~E_11~0); 49122#L1323-1 assume { :end_inline_reset_delta_events } true; 49123#L1644-2 [2023-11-23 22:38:02,089 INFO L750 eck$LassoCheckResult]: Loop: 49123#L1644-2 assume !false; 49744#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49027#L1065-1 assume !false; 49028#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 50111#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48758#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49339#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49228#L906 assume !(0 != eval_~tmp~0#1); 49230#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49551#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49552#L1090-3 assume !(0 == ~M_E~0); 49974#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50035#L1095-3 assume !(0 == ~T2_E~0); 49998#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49999#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49001#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49002#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49281#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49282#L1125-3 assume !(0 == ~T8_E~0); 49805#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50079#L1135-3 assume !(0 == ~T10_E~0); 49202#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48708#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48709#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48833#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48834#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49185#L1165-3 assume !(0 == ~E_5~0); 49186#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49589#L1175-3 assume !(0 == ~E_7~0); 49099#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48857#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 48858#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50064#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50065#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49422#L525-36 assume 1 == ~m_pc~0; 49424#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50067#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50074#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50075#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49239#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49151#L544-36 assume 1 == ~t1_pc~0; 49152#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49714#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49715#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50072#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50051#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49948#L563-36 assume 1 == ~t2_pc~0; 48947#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48706#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48707#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49927#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49438#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49439#L582-36 assume 1 == ~t3_pc~0; 49270#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49271#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49369#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49370#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49477#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49416#L601-36 assume 1 == ~t4_pc~0; 49301#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49302#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49569#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49570#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50040#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49934#L620-36 assume 1 == ~t5_pc~0; 49354#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49355#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49790#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49328#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 48968#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48754#L639-36 assume 1 == ~t6_pc~0; 48755#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48795#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48796#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49018#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49019#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49631#L658-36 assume !(1 == ~t7_pc~0); 48767#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 48768#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50024#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48745#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48746#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49779#L677-36 assume !(1 == ~t8_pc~0); 49544#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 49545#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49677#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49678#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49571#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49572#L696-36 assume 1 == ~t9_pc~0; 49463#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49464#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49405#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49406#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49590#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49591#L715-36 assume !(1 == ~t10_pc~0); 49553#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 48643#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48644#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48619#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48620#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49011#L734-36 assume !(1 == ~t11_pc~0); 48722#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 48723#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49029#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48635#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48636#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49656#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49289#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49290#L1218-3 assume !(1 == ~T2_E~0); 49059#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49060#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49242#L1233-3 assume !(1 == ~T5_E~0); 49243#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49514#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49515#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50039#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50041#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49042#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49043#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50011#L1273-3 assume !(1 == ~E_2~0); 50028#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50030#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49392#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49393#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49236#L1298-3 assume !(1 == ~E_7~0); 49237#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49739#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49233#L1313-3 assume !(1 == ~E_10~0); 49234#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49044#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49045#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48986#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49217#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 49218#L1663 assume !(0 == start_simulation_~tmp~3#1); 48883#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49629#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48829#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 48715#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 48716#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48778#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49104#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 49574#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 49123#L1644-2 [2023-11-23 22:38:02,090 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:02,091 INFO L85 PathProgramCache]: Analyzing trace with hash -2060717699, now seen corresponding path program 1 times [2023-11-23 22:38:02,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:02,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645325004] [2023-11-23 22:38:02,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:02,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:02,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:02,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:02,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:02,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1645325004] [2023-11-23 22:38:02,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1645325004] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:02,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:02,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:38:02,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [782225515] [2023-11-23 22:38:02,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:02,185 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:02,185 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:02,186 INFO L85 PathProgramCache]: Analyzing trace with hash -1434729917, now seen corresponding path program 1 times [2023-11-23 22:38:02,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:02,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943660281] [2023-11-23 22:38:02,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:02,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:02,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:02,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:02,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:02,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943660281] [2023-11-23 22:38:02,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [943660281] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:02,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:02,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:02,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1253752466] [2023-11-23 22:38:02,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:02,279 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:02,279 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:02,280 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:02,280 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:02,281 INFO L87 Difference]: Start difference. First operand 1530 states and 2212 transitions. cyclomatic complexity: 683 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:02,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:02,479 INFO L93 Difference]: Finished difference Result 2805 states and 4029 transitions. [2023-11-23 22:38:02,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2805 states and 4029 transitions. [2023-11-23 22:38:02,498 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2652 [2023-11-23 22:38:02,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2805 states to 2805 states and 4029 transitions. [2023-11-23 22:38:02,527 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2805 [2023-11-23 22:38:02,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2805 [2023-11-23 22:38:02,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2805 states and 4029 transitions. [2023-11-23 22:38:02,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:02,537 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2805 states and 4029 transitions. [2023-11-23 22:38:02,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2805 states and 4029 transitions. [2023-11-23 22:38:02,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2805 to 2803. [2023-11-23 22:38:02,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2803 states, 2803 states have (on average 1.4366749910809846) internal successors, (4027), 2802 states have internal predecessors, (4027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:02,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2803 states to 2803 states and 4027 transitions. [2023-11-23 22:38:02,616 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2803 states and 4027 transitions. [2023-11-23 22:38:02,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:02,618 INFO L428 stractBuchiCegarLoop]: Abstraction has 2803 states and 4027 transitions. [2023-11-23 22:38:02,619 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-23 22:38:02,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2803 states and 4027 transitions. [2023-11-23 22:38:02,634 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2650 [2023-11-23 22:38:02,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:02,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:02,638 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:02,638 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:02,639 INFO L748 eck$LassoCheckResult]: Stem: 53408#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 53409#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 54428#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54429#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53865#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 53866#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53736#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53627#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53349#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52995#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52996#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53040#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53041#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53999#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54000#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54044#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53450#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53451#L1090 assume !(0 == ~M_E~0); 53494#L1090-2 assume !(0 == ~T1_E~0); 53495#L1095-1 assume !(0 == ~T2_E~0); 54195#L1100-1 assume !(0 == ~T3_E~0); 54196#L1105-1 assume !(0 == ~T4_E~0); 53267#L1110-1 assume !(0 == ~T5_E~0); 53268#L1115-1 assume !(0 == ~T6_E~0); 53664#L1120-1 assume !(0 == ~T7_E~0); 53977#L1125-1 assume !(0 == ~T8_E~0); 54499#L1130-1 assume !(0 == ~T9_E~0); 54220#L1135-1 assume !(0 == ~T10_E~0); 53455#L1140-1 assume !(0 == ~T11_E~0); 53456#L1145-1 assume !(0 == ~E_1~0); 54149#L1150-1 assume !(0 == ~E_2~0); 53641#L1155-1 assume !(0 == ~E_3~0); 53642#L1160-1 assume !(0 == ~E_4~0); 53741#L1165-1 assume !(0 == ~E_5~0); 53742#L1170-1 assume !(0 == ~E_6~0); 54411#L1175-1 assume !(0 == ~E_7~0); 53823#L1180-1 assume !(0 == ~E_8~0); 53824#L1185-1 assume !(0 == ~E_9~0); 53452#L1190-1 assume !(0 == ~E_10~0); 53453#L1195-1 assume !(0 == ~E_11~0); 53839#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53656#L525 assume !(1 == ~m_pc~0); 53085#L525-2 is_master_triggered_~__retres1~0#1 := 0; 53086#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54301#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54273#L1350 assume !(0 != activate_threads_~tmp~1#1); 53442#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53443#L544 assume !(1 == ~t1_pc~0); 53662#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53663#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53059#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53060#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 53290#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53946#L563 assume !(1 == ~t2_pc~0); 54135#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53104#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53105#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53523#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 53524#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54025#L582 assume 1 == ~t3_pc~0; 53235#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53236#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52987#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52988#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 53173#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53174#L601 assume !(1 == ~t4_pc~0); 54162#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53665#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53183#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53184#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 54157#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54471#L620 assume 1 == ~t5_pc~0; 53132#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53133#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54041#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54307#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 54482#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54483#L639 assume !(1 == ~t6_pc~0); 53975#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53562#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53563#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53613#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 53670#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53671#L658 assume !(1 == ~t7_pc~0); 53889#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53890#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54488#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54093#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 53445#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53446#L677 assume 1 == ~t8_pc~0; 53677#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53250#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53251#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53519#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 53520#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54264#L696 assume !(1 == ~t9_pc~0); 53958#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 53959#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53726#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53727#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53982#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54200#L715 assume 1 == ~t10_pc~0; 54209#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 54075#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53877#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53878#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 53816#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53244#L734 assume !(1 == ~t11_pc~0); 53245#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 53743#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53826#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52983#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 52984#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54042#L1213 assume !(1 == ~M_E~0); 53813#L1213-2 assume !(1 == ~T1_E~0); 53814#L1218-1 assume !(1 == ~T2_E~0); 53018#L1223-1 assume !(1 == ~T3_E~0); 53019#L1228-1 assume !(1 == ~T4_E~0); 53789#L1233-1 assume !(1 == ~T5_E~0); 54484#L1238-1 assume !(1 == ~T6_E~0); 54155#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54156#L1248-1 assume !(1 == ~T8_E~0); 54205#L1253-1 assume !(1 == ~T9_E~0); 54206#L1258-1 assume !(1 == ~T10_E~0); 54178#L1263-1 assume !(1 == ~T11_E~0); 54179#L1268-1 assume !(1 == ~E_1~0); 53996#L1273-1 assume !(1 == ~E_2~0); 53997#L1278-1 assume !(1 == ~E_3~0); 53560#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 53561#L1288-1 assume !(1 == ~E_5~0); 54315#L1293-1 assume !(1 == ~E_6~0); 54268#L1298-1 assume !(1 == ~E_7~0); 54029#L1303-1 assume !(1 == ~E_8~0); 53570#L1308-1 assume !(1 == ~E_9~0); 53459#L1313-1 assume !(1 == ~E_10~0); 53460#L1318-1 assume !(1 == ~E_11~0); 53467#L1323-1 assume { :end_inline_reset_delta_events } true; 53468#L1644-2 [2023-11-23 22:38:02,639 INFO L750 eck$LassoCheckResult]: Loop: 53468#L1644-2 assume !false; 54091#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53386#L1065-1 assume !false; 54975#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54823#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54809#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54806#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54803#L906 assume !(0 != eval_~tmp~0#1); 54804#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55665#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55664#L1090-3 assume !(0 == ~M_E~0); 55663#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55662#L1095-3 assume !(0 == ~T2_E~0); 55661#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55660#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55659#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55658#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55657#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55656#L1125-3 assume !(0 == ~T8_E~0); 55655#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 55654#L1135-3 assume !(0 == ~T10_E~0); 55653#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55652#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55651#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55650#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55557#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55509#L1165-3 assume !(0 == ~E_5~0); 55508#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55507#L1175-3 assume !(0 == ~E_7~0); 55506#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 55505#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 55504#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55503#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55500#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55499#L525-36 assume !(1 == ~m_pc~0); 55497#L525-38 is_master_triggered_~__retres1~0#1 := 0; 55495#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55493#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55492#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 53938#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53499#L544-36 assume !(1 == ~t1_pc~0); 53500#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 55598#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55597#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55596#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55595#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55594#L563-36 assume !(1 == ~t2_pc~0); 55592#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 55591#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55590#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55589#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55588#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55587#L582-36 assume 1 == ~t3_pc~0; 55585#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55584#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55583#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55582#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55581#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55580#L601-36 assume !(1 == ~t4_pc~0); 55578#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 55577#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55576#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55575#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55574#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55573#L620-36 assume 1 == ~t5_pc~0; 55571#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55570#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55569#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55568#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 55567#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53096#L639-36 assume 1 == ~t6_pc~0; 53097#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53137#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53138#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53361#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53362#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53980#L658-36 assume !(1 == ~t7_pc~0); 53109#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 53110#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54379#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53087#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53088#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54127#L677-36 assume !(1 == ~t8_pc~0); 53893#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 53894#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54026#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54027#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53920#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53921#L696-36 assume 1 == ~t9_pc~0; 53810#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53811#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53753#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53754#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53940#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53941#L715-36 assume 1 == ~t10_pc~0; 54086#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52985#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52986#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52961#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52962#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53356#L734-36 assume !(1 == ~t11_pc~0); 53064#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 53065#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53374#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52977#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52978#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54005#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53637#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53638#L1218-3 assume !(1 == ~T2_E~0); 53405#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53406#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53589#L1233-3 assume !(1 == ~T5_E~0); 53590#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53862#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53863#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54396#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54398#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53388#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53389#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54366#L1273-3 assume !(1 == ~E_2~0); 54384#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54386#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53739#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53740#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53583#L1298-3 assume !(1 == ~E_7~0); 53584#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54087#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53580#L1313-3 assume !(1 == ~E_10~0); 53581#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53390#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 53391#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 53328#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 53564#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 53565#L1663 assume !(0 == start_simulation_~tmp~3#1); 54516#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55524#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 55514#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 53057#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 53058#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53120#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53449#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 53923#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 53468#L1644-2 [2023-11-23 22:38:02,640 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:02,640 INFO L85 PathProgramCache]: Analyzing trace with hash -2098164388, now seen corresponding path program 1 times [2023-11-23 22:38:02,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:02,641 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569290823] [2023-11-23 22:38:02,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:02,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:02,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:02,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:02,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:02,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [569290823] [2023-11-23 22:38:02,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [569290823] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:02,747 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:02,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:38:02,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245017333] [2023-11-23 22:38:02,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:02,748 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:02,749 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:02,749 INFO L85 PathProgramCache]: Analyzing trace with hash 405655710, now seen corresponding path program 1 times [2023-11-23 22:38:02,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:02,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199211071] [2023-11-23 22:38:02,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:02,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:02,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:02,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:02,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:02,831 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199211071] [2023-11-23 22:38:02,831 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199211071] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:02,832 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:02,832 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:02,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334626783] [2023-11-23 22:38:02,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:02,833 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:02,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:02,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:02,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:02,834 INFO L87 Difference]: Start difference. First operand 2803 states and 4027 transitions. cyclomatic complexity: 1226 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:03,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:03,007 INFO L93 Difference]: Finished difference Result 5250 states and 7502 transitions. [2023-11-23 22:38:03,007 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5250 states and 7502 transitions. [2023-11-23 22:38:03,048 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5094 [2023-11-23 22:38:03,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5250 states to 5250 states and 7502 transitions. [2023-11-23 22:38:03,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5250 [2023-11-23 22:38:03,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5250 [2023-11-23 22:38:03,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5250 states and 7502 transitions. [2023-11-23 22:38:03,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:03,090 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5250 states and 7502 transitions. [2023-11-23 22:38:03,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5250 states and 7502 transitions. [2023-11-23 22:38:03,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5250 to 5246. [2023-11-23 22:38:03,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5246 states, 5246 states have (on average 1.4292794510102935) internal successors, (7498), 5245 states have internal predecessors, (7498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:03,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5246 states to 5246 states and 7498 transitions. [2023-11-23 22:38:03,306 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5246 states and 7498 transitions. [2023-11-23 22:38:03,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:03,307 INFO L428 stractBuchiCegarLoop]: Abstraction has 5246 states and 7498 transitions. [2023-11-23 22:38:03,307 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-23 22:38:03,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5246 states and 7498 transitions. [2023-11-23 22:38:03,332 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5090 [2023-11-23 22:38:03,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:03,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:03,336 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:03,336 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:03,337 INFO L748 eck$LassoCheckResult]: Stem: 61463#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 61464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 62497#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62498#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61917#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 61918#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61786#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61680#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61406#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61055#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 61056#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 61100#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61101#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62057#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62058#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62106#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 61504#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61505#L1090 assume !(0 == ~M_E~0); 61549#L1090-2 assume !(0 == ~T1_E~0); 61550#L1095-1 assume !(0 == ~T2_E~0); 62257#L1100-1 assume !(0 == ~T3_E~0); 62258#L1105-1 assume !(0 == ~T4_E~0); 61326#L1110-1 assume !(0 == ~T5_E~0); 61327#L1115-1 assume !(0 == ~T6_E~0); 61716#L1120-1 assume !(0 == ~T7_E~0); 62031#L1125-1 assume !(0 == ~T8_E~0); 62577#L1130-1 assume !(0 == ~T9_E~0); 62281#L1135-1 assume !(0 == ~T10_E~0); 61509#L1140-1 assume !(0 == ~T11_E~0); 61510#L1145-1 assume !(0 == ~E_1~0); 62211#L1150-1 assume !(0 == ~E_2~0); 61693#L1155-1 assume !(0 == ~E_3~0); 61694#L1160-1 assume !(0 == ~E_4~0); 61791#L1165-1 assume !(0 == ~E_5~0); 61792#L1170-1 assume !(0 == ~E_6~0); 62478#L1175-1 assume !(0 == ~E_7~0); 61874#L1180-1 assume !(0 == ~E_8~0); 61875#L1185-1 assume !(0 == ~E_9~0); 61506#L1190-1 assume !(0 == ~E_10~0); 61507#L1195-1 assume !(0 == ~E_11~0); 61890#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61713#L525 assume !(1 == ~m_pc~0); 61145#L525-2 is_master_triggered_~__retres1~0#1 := 0; 61146#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62364#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62336#L1350 assume !(0 != activate_threads_~tmp~1#1); 61496#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61497#L544 assume !(1 == ~t1_pc~0); 61714#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61715#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61125#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 61348#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61999#L563 assume !(1 == ~t2_pc~0); 62198#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61164#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61165#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61579#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 61580#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62081#L582 assume !(1 == ~t3_pc~0); 62210#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62544#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61047#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61048#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 61233#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61234#L601 assume !(1 == ~t4_pc~0); 62223#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61717#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61247#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61248#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 62218#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62537#L620 assume 1 == ~t5_pc~0; 61196#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 61197#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62097#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62370#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 62555#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62556#L639 assume !(1 == ~t6_pc~0); 62029#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 61617#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61618#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61666#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 61722#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61723#L658 assume !(1 == ~t7_pc~0); 61941#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 61942#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62561#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62154#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 61499#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61500#L677 assume 1 == ~t8_pc~0; 61730#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61311#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61312#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61571#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 61572#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62327#L696 assume !(1 == ~t9_pc~0); 62013#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 62014#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61776#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 61777#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 62039#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62261#L715 assume 1 == ~t10_pc~0; 62271#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 62131#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61929#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61930#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 61867#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61302#L734 assume !(1 == ~t11_pc~0); 61303#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 61793#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61879#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61045#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 61046#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62098#L1213 assume !(1 == ~M_E~0); 61865#L1213-2 assume !(1 == ~T1_E~0); 61866#L1218-1 assume !(1 == ~T2_E~0); 61078#L1223-1 assume !(1 == ~T3_E~0); 61079#L1228-1 assume !(1 == ~T4_E~0); 61840#L1233-1 assume !(1 == ~T5_E~0); 62557#L1238-1 assume !(1 == ~T6_E~0); 62216#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62217#L1248-1 assume !(1 == ~T8_E~0); 62267#L1253-1 assume !(1 == ~T9_E~0); 62268#L1258-1 assume !(1 == ~T10_E~0); 62240#L1263-1 assume !(1 == ~T11_E~0); 62241#L1268-1 assume !(1 == ~E_1~0); 62052#L1273-1 assume !(1 == ~E_2~0); 62053#L1278-1 assume !(1 == ~E_3~0); 61613#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 61614#L1288-1 assume !(1 == ~E_5~0); 62377#L1293-1 assume !(1 == ~E_6~0); 62332#L1298-1 assume !(1 == ~E_7~0); 62085#L1303-1 assume !(1 == ~E_8~0); 61623#L1308-1 assume !(1 == ~E_9~0); 61513#L1313-1 assume !(1 == ~E_10~0); 61514#L1318-1 assume !(1 == ~E_11~0); 61524#L1323-1 assume { :end_inline_reset_delta_events } true; 61525#L1644-2 [2023-11-23 22:38:03,338 INFO L750 eck$LassoCheckResult]: Loop: 61525#L1644-2 assume !false; 63767#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63762#L1065-1 assume !false; 63760#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 63753#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 63742#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 63740#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 63738#L906 assume !(0 != eval_~tmp~0#1); 62306#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61952#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61953#L1090-3 assume !(0 == ~M_E~0); 62394#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62452#L1095-3 assume !(0 == ~T2_E~0); 62418#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62419#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61400#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61401#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61681#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61682#L1125-3 assume !(0 == ~T8_E~0); 62215#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62505#L1135-3 assume !(0 == ~T10_E~0); 61602#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 61110#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61111#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61235#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61236#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 61585#L1165-3 assume !(0 == ~E_5~0); 61586#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61992#L1175-3 assume !(0 == ~E_7~0); 61498#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61261#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 61262#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62489#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62490#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61818#L525-36 assume !(1 == ~m_pc~0); 61819#L525-38 is_master_triggered_~__retres1~0#1 := 0; 61357#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61358#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 61638#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 61639#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61547#L544-36 assume !(1 == ~t1_pc~0); 61548#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 62119#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62120#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62496#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62475#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62365#L563-36 assume 1 == ~t2_pc~0; 61346#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61108#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61109#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62345#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61837#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61838#L582-36 assume !(1 == ~t3_pc~0); 62383#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 61916#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61767#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61768#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61876#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61813#L601-36 assume 1 == ~t4_pc~0; 61814#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 66155#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66154#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66153#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66152#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66151#L620-36 assume 1 == ~t5_pc~0; 66149#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66148#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66147#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66146#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 66145#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66144#L639-36 assume !(1 == ~t6_pc~0); 66143#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 66141#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66140#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66139#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66138#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66137#L658-36 assume !(1 == ~t7_pc~0); 66135#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 66134#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66133#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66132#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66131#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66130#L677-36 assume !(1 == ~t8_pc~0); 66129#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 66127#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66126#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66125#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66124#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66123#L696-36 assume !(1 == ~t9_pc~0); 66121#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 66120#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66119#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66118#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66117#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66116#L715-36 assume !(1 == ~t10_pc~0); 66115#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 66113#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66112#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66111#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66110#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66109#L734-36 assume !(1 == ~t11_pc~0); 66107#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 66106#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66105#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66104#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66103#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62491#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61687#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61688#L1218-3 assume !(1 == ~T2_E~0); 61460#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61461#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61642#L1233-3 assume !(1 == ~T5_E~0); 61643#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61913#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61914#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62459#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62461#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61441#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61442#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62430#L1273-3 assume !(1 == ~E_2~0); 62445#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62447#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61789#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61790#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61636#L1298-3 assume !(1 == ~E_7~0); 61637#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62145#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 61633#L1313-3 assume !(1 == ~E_10~0); 61634#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 61443#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 61444#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 61384#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 61615#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 61616#L1663 assume !(0 == start_simulation_~tmp~3#1); 61286#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 62574#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 63780#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 63778#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 63776#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63774#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63772#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 63770#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 61525#L1644-2 [2023-11-23 22:38:03,339 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:03,339 INFO L85 PathProgramCache]: Analyzing trace with hash 919650235, now seen corresponding path program 1 times [2023-11-23 22:38:03,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:03,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298941530] [2023-11-23 22:38:03,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:03,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:03,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:03,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:03,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:03,526 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298941530] [2023-11-23 22:38:03,526 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1298941530] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:03,526 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:03,526 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:38:03,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765589573] [2023-11-23 22:38:03,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:03,527 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:03,528 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:03,528 INFO L85 PathProgramCache]: Analyzing trace with hash 1517739100, now seen corresponding path program 1 times [2023-11-23 22:38:03,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:03,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510317923] [2023-11-23 22:38:03,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:03,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:03,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:03,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:03,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:03,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510317923] [2023-11-23 22:38:03,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510317923] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:03,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:03,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:03,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563156940] [2023-11-23 22:38:03,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:03,629 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:03,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:03,630 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:03,630 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:03,631 INFO L87 Difference]: Start difference. First operand 5246 states and 7498 transitions. cyclomatic complexity: 2256 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:03,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:03,859 INFO L93 Difference]: Finished difference Result 9941 states and 14145 transitions. [2023-11-23 22:38:03,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9941 states and 14145 transitions. [2023-11-23 22:38:03,941 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9772 [2023-11-23 22:38:03,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9941 states to 9941 states and 14145 transitions. [2023-11-23 22:38:03,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9941 [2023-11-23 22:38:04,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9941 [2023-11-23 22:38:04,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9941 states and 14145 transitions. [2023-11-23 22:38:04,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:04,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9941 states and 14145 transitions. [2023-11-23 22:38:04,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9941 states and 14145 transitions. [2023-11-23 22:38:04,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9941 to 9933. [2023-11-23 22:38:04,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9933 states, 9933 states have (on average 1.4232356790496326) internal successors, (14137), 9932 states have internal predecessors, (14137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:04,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9933 states to 9933 states and 14137 transitions. [2023-11-23 22:38:04,298 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9933 states and 14137 transitions. [2023-11-23 22:38:04,299 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:04,300 INFO L428 stractBuchiCegarLoop]: Abstraction has 9933 states and 14137 transitions. [2023-11-23 22:38:04,300 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-23 22:38:04,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9933 states and 14137 transitions. [2023-11-23 22:38:04,409 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9764 [2023-11-23 22:38:04,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:04,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:04,413 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:04,413 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:04,413 INFO L748 eck$LassoCheckResult]: Stem: 76655#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 76656#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 77733#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77734#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77122#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 77123#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76990#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76878#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76596#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76249#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76250#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76294#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76295#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77265#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77266#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77315#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76699#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76700#L1090 assume !(0 == ~M_E~0); 76745#L1090-2 assume !(0 == ~T1_E~0); 76746#L1095-1 assume !(0 == ~T2_E~0); 77480#L1100-1 assume !(0 == ~T3_E~0); 77481#L1105-1 assume !(0 == ~T4_E~0); 76515#L1110-1 assume !(0 == ~T5_E~0); 76516#L1115-1 assume !(0 == ~T6_E~0); 76915#L1120-1 assume !(0 == ~T7_E~0); 77238#L1125-1 assume !(0 == ~T8_E~0); 77835#L1130-1 assume !(0 == ~T9_E~0); 77508#L1135-1 assume !(0 == ~T10_E~0); 76706#L1140-1 assume !(0 == ~T11_E~0); 76707#L1145-1 assume !(0 == ~E_1~0); 77431#L1150-1 assume !(0 == ~E_2~0); 76891#L1155-1 assume !(0 == ~E_3~0); 76892#L1160-1 assume !(0 == ~E_4~0); 76995#L1165-1 assume !(0 == ~E_5~0); 76996#L1170-1 assume !(0 == ~E_6~0); 77715#L1175-1 assume !(0 == ~E_7~0); 77078#L1180-1 assume !(0 == ~E_8~0); 77079#L1185-1 assume !(0 == ~E_9~0); 76701#L1190-1 assume !(0 == ~E_10~0); 76702#L1195-1 assume !(0 == ~E_11~0); 77094#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76907#L525 assume !(1 == ~m_pc~0); 76337#L525-2 is_master_triggered_~__retres1~0#1 := 0; 76338#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77598#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 77566#L1350 assume !(0 != activate_threads_~tmp~1#1); 76691#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76692#L544 assume !(1 == ~t1_pc~0); 76913#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76914#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76312#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76313#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 76539#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77205#L563 assume !(1 == ~t2_pc~0); 77415#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76359#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76360#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76772#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 76773#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77295#L582 assume !(1 == ~t3_pc~0); 77430#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77790#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76241#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76242#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 76424#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76425#L601 assume !(1 == ~t4_pc~0); 77445#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76916#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76434#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76435#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 77438#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77785#L620 assume !(1 == ~t5_pc~0); 77254#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 77255#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77312#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77607#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 77800#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77801#L639 assume !(1 == ~t6_pc~0); 77236#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76811#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76812#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76863#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 76922#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76923#L658 assume !(1 == ~t7_pc~0); 77147#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 77148#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77808#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77367#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 76694#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76695#L677 assume 1 == ~t8_pc~0; 76929#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76498#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76499#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76768#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 76769#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77556#L696 assume !(1 == ~t9_pc~0); 77218#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 77219#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76978#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76979#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77243#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77486#L715 assume 1 == ~t10_pc~0; 77496#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 77348#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77136#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77137#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 77071#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76492#L734 assume !(1 == ~t11_pc~0); 76493#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 76997#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77081#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76237#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 76238#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77313#L1213 assume !(1 == ~M_E~0); 77068#L1213-2 assume !(1 == ~T1_E~0); 77069#L1218-1 assume !(1 == ~T2_E~0); 76272#L1223-1 assume !(1 == ~T3_E~0); 76273#L1228-1 assume !(1 == ~T4_E~0); 77045#L1233-1 assume !(1 == ~T5_E~0); 77802#L1238-1 assume !(1 == ~T6_E~0); 77436#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77437#L1248-1 assume !(1 == ~T8_E~0); 77492#L1253-1 assume !(1 == ~T9_E~0); 77493#L1258-1 assume !(1 == ~T10_E~0); 77463#L1263-1 assume !(1 == ~T11_E~0); 77464#L1268-1 assume !(1 == ~E_1~0); 77262#L1273-1 assume !(1 == ~E_2~0); 77263#L1278-1 assume !(1 == ~E_3~0); 76809#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 76810#L1288-1 assume !(1 == ~E_5~0); 77614#L1293-1 assume !(1 == ~E_6~0); 77561#L1298-1 assume !(1 == ~E_7~0); 77299#L1303-1 assume !(1 == ~E_8~0); 76819#L1308-1 assume !(1 == ~E_9~0); 76710#L1313-1 assume !(1 == ~E_10~0); 76711#L1318-1 assume !(1 == ~E_11~0); 76718#L1323-1 assume { :end_inline_reset_delta_events } true; 76719#L1644-2 [2023-11-23 22:38:04,414 INFO L750 eck$LassoCheckResult]: Loop: 76719#L1644-2 assume !false; 77365#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76618#L1065-1 assume !false; 76619#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 77798#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 76352#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 76940#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 76824#L906 assume !(0 != eval_~tmp~0#1); 76826#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77159#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77160#L1090-3 assume !(0 == ~M_E~0); 77638#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77697#L1095-3 assume !(0 == ~T2_E~0); 77661#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77662#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76591#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76592#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76879#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 76880#L1125-3 assume !(0 == ~T8_E~0); 77435#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 77743#L1135-3 assume !(0 == ~T10_E~0); 76798#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 76303#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 76304#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76426#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76427#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76781#L1165-3 assume !(0 == ~E_5~0); 76782#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77198#L1175-3 assume !(0 == ~E_7~0); 76693#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 76450#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 76451#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77727#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77728#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77876#L525-36 assume !(1 == ~m_pc~0); 85962#L525-38 is_master_triggered_~__retres1~0#1 := 0; 76548#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76549#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76834#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 76835#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76750#L544-36 assume !(1 == ~t1_pc~0); 76751#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 77335#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77336#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77735#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77713#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77601#L563-36 assume 1 == ~t2_pc~0; 77603#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86122#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86121#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 86119#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86117#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86115#L582-36 assume !(1 == ~t3_pc~0); 86113#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 86110#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86108#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86106#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86104#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86102#L601-36 assume 1 == ~t4_pc~0; 86099#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 86096#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86094#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86092#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86075#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86074#L620-36 assume !(1 == ~t5_pc~0); 86072#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 86071#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86061#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86059#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 86057#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86054#L639-36 assume 1 == ~t6_pc~0; 86051#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86049#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86047#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86045#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86043#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86040#L658-36 assume !(1 == ~t7_pc~0); 86037#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 86036#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86012#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86011#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86010#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86009#L677-36 assume !(1 == ~t8_pc~0); 85981#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 85978#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85974#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85971#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85968#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85966#L696-36 assume !(1 == ~t9_pc~0); 85963#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 85961#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85960#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85959#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85957#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85954#L715-36 assume !(1 == ~t10_pc~0); 85952#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 85949#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85948#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85947#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85946#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85945#L734-36 assume !(1 == ~t11_pc~0); 76317#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 76318#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76620#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76231#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 76232#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77271#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76887#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76888#L1218-3 assume !(1 == ~T2_E~0); 85858#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85857#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85856#L1233-3 assume !(1 == ~T5_E~0); 85855#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85854#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 85853#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 85852#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 85851#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 85850#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85557#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 85556#L1273-3 assume !(1 == ~E_2~0); 85555#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85554#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85553#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85552#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 85551#L1298-3 assume !(1 == ~E_7~0); 85550#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85549#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 85548#L1313-3 assume !(1 == ~E_10~0); 85547#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85546#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 77868#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 76575#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 76813#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 76814#L1663 assume !(0 == start_simulation_~tmp~3#1); 76476#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 77239#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 76422#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 76310#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 76311#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76374#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76698#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 77182#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 76719#L1644-2 [2023-11-23 22:38:04,415 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:04,415 INFO L85 PathProgramCache]: Analyzing trace with hash -258324326, now seen corresponding path program 1 times [2023-11-23 22:38:04,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:04,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82515843] [2023-11-23 22:38:04,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:04,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:04,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:04,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:04,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:04,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82515843] [2023-11-23 22:38:04,505 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [82515843] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:04,505 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:04,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:38:04,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758809777] [2023-11-23 22:38:04,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:04,507 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:04,507 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:04,508 INFO L85 PathProgramCache]: Analyzing trace with hash 726001948, now seen corresponding path program 1 times [2023-11-23 22:38:04,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:04,508 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140157920] [2023-11-23 22:38:04,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:04,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:04,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:04,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:04,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:04,585 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140157920] [2023-11-23 22:38:04,587 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140157920] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:04,588 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:04,588 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:04,588 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060449654] [2023-11-23 22:38:04,588 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:04,590 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:04,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:04,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:04,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:04,591 INFO L87 Difference]: Start difference. First operand 9933 states and 14137 transitions. cyclomatic complexity: 4212 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:04,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:04,831 INFO L93 Difference]: Finished difference Result 18924 states and 26826 transitions. [2023-11-23 22:38:04,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18924 states and 26826 transitions. [2023-11-23 22:38:04,954 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18720 [2023-11-23 22:38:05,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18924 states to 18924 states and 26826 transitions. [2023-11-23 22:38:05,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18924 [2023-11-23 22:38:05,180 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18924 [2023-11-23 22:38:05,180 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18924 states and 26826 transitions. [2023-11-23 22:38:05,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:05,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18924 states and 26826 transitions. [2023-11-23 22:38:05,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18924 states and 26826 transitions. [2023-11-23 22:38:05,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18924 to 18908. [2023-11-23 22:38:05,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18908 states, 18908 states have (on average 1.4179183414427756) internal successors, (26810), 18907 states have internal predecessors, (26810), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:05,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18908 states to 18908 states and 26810 transitions. [2023-11-23 22:38:05,659 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18908 states and 26810 transitions. [2023-11-23 22:38:05,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:05,661 INFO L428 stractBuchiCegarLoop]: Abstraction has 18908 states and 26810 transitions. [2023-11-23 22:38:05,661 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-23 22:38:05,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18908 states and 26810 transitions. [2023-11-23 22:38:05,748 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18704 [2023-11-23 22:38:05,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:05,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:05,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:05,752 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:05,752 INFO L748 eck$LassoCheckResult]: Stem: 105517#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 105518#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 106576#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 106577#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105971#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 105972#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105843#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105736#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105461#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105113#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105114#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 105158#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 105159#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 106117#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 106118#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 106162#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 105559#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105560#L1090 assume !(0 == ~M_E~0); 105604#L1090-2 assume !(0 == ~T1_E~0); 105605#L1095-1 assume !(0 == ~T2_E~0); 106322#L1100-1 assume !(0 == ~T3_E~0); 106323#L1105-1 assume !(0 == ~T4_E~0); 105381#L1110-1 assume !(0 == ~T5_E~0); 105382#L1115-1 assume !(0 == ~T6_E~0); 105774#L1120-1 assume !(0 == ~T7_E~0); 106091#L1125-1 assume !(0 == ~T8_E~0); 106670#L1130-1 assume !(0 == ~T9_E~0); 106343#L1135-1 assume !(0 == ~T10_E~0); 105565#L1140-1 assume !(0 == ~T11_E~0); 105566#L1145-1 assume !(0 == ~E_1~0); 106274#L1150-1 assume !(0 == ~E_2~0); 105750#L1155-1 assume !(0 == ~E_3~0); 105751#L1160-1 assume !(0 == ~E_4~0); 105848#L1165-1 assume !(0 == ~E_5~0); 105849#L1170-1 assume !(0 == ~E_6~0); 106556#L1175-1 assume !(0 == ~E_7~0); 105930#L1180-1 assume !(0 == ~E_8~0); 105931#L1185-1 assume !(0 == ~E_9~0); 105561#L1190-1 assume !(0 == ~E_10~0); 105562#L1195-1 assume !(0 == ~E_11~0); 105946#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105771#L525 assume !(1 == ~m_pc~0); 105202#L525-2 is_master_triggered_~__retres1~0#1 := 0; 105203#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106433#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 106404#L1350 assume !(0 != activate_threads_~tmp~1#1); 105551#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105552#L544 assume !(1 == ~t1_pc~0); 105772#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105773#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105181#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 105182#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 105404#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106058#L563 assume !(1 == ~t2_pc~0); 106258#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105224#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105225#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 105633#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 105634#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106143#L582 assume !(1 == ~t3_pc~0); 106273#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 106630#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105105#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 105106#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 105289#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105290#L601 assume !(1 == ~t4_pc~0); 106288#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105775#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105303#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 105304#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 106283#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106619#L620 assume !(1 == ~t5_pc~0); 106107#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 106108#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106159#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 106441#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 106639#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 106640#L639 assume !(1 == ~t6_pc~0); 106089#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 105674#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 105675#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 105723#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 105780#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 105781#L658 assume !(1 == ~t7_pc~0); 105997#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 105998#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 106648#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 106217#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 105554#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 105555#L677 assume !(1 == ~t8_pc~0); 105578#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 105363#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 105364#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 105629#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 105630#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 106392#L696 assume !(1 == ~t9_pc~0); 106073#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 106074#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 105833#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 105834#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 106096#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 106326#L715 assume 1 == ~t10_pc~0; 106333#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 106193#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 105985#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 105986#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 105923#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 105357#L734 assume !(1 == ~t11_pc~0); 105358#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 105850#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 105933#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 105103#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 105104#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106160#L1213 assume !(1 == ~M_E~0); 105921#L1213-2 assume !(1 == ~T1_E~0); 105922#L1218-1 assume !(1 == ~T2_E~0); 105136#L1223-1 assume !(1 == ~T3_E~0); 105137#L1228-1 assume !(1 == ~T4_E~0); 105897#L1233-1 assume !(1 == ~T5_E~0); 106641#L1238-1 assume !(1 == ~T6_E~0); 106281#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 106282#L1248-1 assume !(1 == ~T8_E~0); 106329#L1253-1 assume !(1 == ~T9_E~0); 106330#L1258-1 assume !(1 == ~T10_E~0); 106305#L1263-1 assume !(1 == ~T11_E~0); 106306#L1268-1 assume !(1 == ~E_1~0); 106114#L1273-1 assume !(1 == ~E_2~0); 106115#L1278-1 assume !(1 == ~E_3~0); 105670#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 105671#L1288-1 assume !(1 == ~E_5~0); 106448#L1293-1 assume !(1 == ~E_6~0); 106397#L1298-1 assume !(1 == ~E_7~0); 106147#L1303-1 assume !(1 == ~E_8~0); 105680#L1308-1 assume !(1 == ~E_9~0); 105569#L1313-1 assume !(1 == ~E_10~0); 105570#L1318-1 assume !(1 == ~E_11~0); 105579#L1323-1 assume { :end_inline_reset_delta_events } true; 105580#L1644-2 [2023-11-23 22:38:05,753 INFO L750 eck$LassoCheckResult]: Loop: 105580#L1644-2 assume !false; 106213#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105483#L1065-1 assume !false; 105484#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 106637#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 105217#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 105796#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 105685#L906 assume !(0 != eval_~tmp~0#1); 105687#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123146#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 123145#L1090-3 assume !(0 == ~M_E~0); 123144#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 123143#L1095-3 assume !(0 == ~T2_E~0); 123142#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 123141#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 123140#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 123139#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 123138#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 123137#L1125-3 assume !(0 == ~T8_E~0); 123136#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 123135#L1135-3 assume !(0 == ~T10_E~0); 123134#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 123133#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 123132#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 123131#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123130#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 123129#L1165-3 assume !(0 == ~E_5~0); 123128#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 123127#L1175-3 assume !(0 == ~E_7~0); 123126#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 123125#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 123124#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 123123#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 123122#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123121#L525-36 assume 1 == ~m_pc~0; 123120#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 123118#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123116#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 123113#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123112#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123111#L544-36 assume !(1 == ~t1_pc~0); 123110#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 123109#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123108#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123107#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123106#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123105#L563-36 assume 1 == ~t2_pc~0; 123103#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 123101#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123100#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123099#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123095#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123093#L582-36 assume !(1 == ~t3_pc~0); 123091#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 123089#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123086#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123084#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 123082#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123080#L601-36 assume !(1 == ~t4_pc~0); 123077#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 123075#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123073#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123071#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 123069#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123066#L620-36 assume !(1 == ~t5_pc~0); 123064#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 123062#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123060#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 123058#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 123056#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 123054#L639-36 assume 1 == ~t6_pc~0; 123051#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 123049#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123047#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 123045#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 123043#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 123040#L658-36 assume !(1 == ~t7_pc~0); 123037#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 123035#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123033#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 123031#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 123029#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 123027#L677-36 assume !(1 == ~t8_pc~0); 123025#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 123023#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 123021#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 123019#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 123017#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123014#L696-36 assume !(1 == ~t9_pc~0); 123011#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 123009#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 123007#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123005#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 123002#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 123000#L715-36 assume 1 == ~t10_pc~0; 122997#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 122995#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 122993#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 122991#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 122989#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 122987#L734-36 assume 1 == ~t11_pc~0; 122985#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 122982#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 122980#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 122978#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 122976#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122973#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 122971#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 122969#L1218-3 assume !(1 == ~T2_E~0); 122967#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122965#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 122963#L1233-3 assume !(1 == ~T5_E~0); 122960#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 122958#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 122956#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 122954#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 122952#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 122950#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 122949#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 122946#L1273-3 assume !(1 == ~E_2~0); 122944#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 122942#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 122940#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 122938#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 122936#L1298-3 assume !(1 == ~E_7~0); 122934#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 122932#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 122930#L1313-3 assume !(1 == ~E_10~0); 122928#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 122926#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 122905#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 122898#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 122896#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 122892#L1663 assume !(0 == start_simulation_~tmp~3#1); 122511#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 122345#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 122329#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 122323#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 122317#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 122315#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122311#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 122310#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 105580#L1644-2 [2023-11-23 22:38:05,754 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:05,754 INFO L85 PathProgramCache]: Analyzing trace with hash 1174510393, now seen corresponding path program 1 times [2023-11-23 22:38:05,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:05,754 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279254159] [2023-11-23 22:38:05,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:05,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:05,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:05,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:05,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:05,862 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [279254159] [2023-11-23 22:38:05,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [279254159] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:05,862 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:05,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-23 22:38:05,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091591801] [2023-11-23 22:38:05,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:05,863 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:05,864 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:05,864 INFO L85 PathProgramCache]: Analyzing trace with hash 51239904, now seen corresponding path program 1 times [2023-11-23 22:38:05,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:05,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018297625] [2023-11-23 22:38:05,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:05,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:05,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:06,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:06,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:06,081 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018297625] [2023-11-23 22:38:06,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018297625] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:06,081 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:06,082 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:06,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83952318] [2023-11-23 22:38:06,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:06,083 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:06,083 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:06,084 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-23 22:38:06,084 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-23 22:38:06,084 INFO L87 Difference]: Start difference. First operand 18908 states and 26810 transitions. cyclomatic complexity: 7918 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:06,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:06,856 INFO L93 Difference]: Finished difference Result 39837 states and 56132 transitions. [2023-11-23 22:38:06,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39837 states and 56132 transitions. [2023-11-23 22:38:07,222 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 39520 [2023-11-23 22:38:07,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39837 states to 39837 states and 56132 transitions. [2023-11-23 22:38:07,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39837 [2023-11-23 22:38:07,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39837 [2023-11-23 22:38:07,596 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39837 states and 56132 transitions. [2023-11-23 22:38:07,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:07,648 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39837 states and 56132 transitions. [2023-11-23 22:38:07,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39837 states and 56132 transitions. [2023-11-23 22:38:08,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39837 to 19439. [2023-11-23 22:38:08,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19439 states, 19439 states have (on average 1.406502392098359) internal successors, (27341), 19438 states have internal predecessors, (27341), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:08,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19439 states to 19439 states and 27341 transitions. [2023-11-23 22:38:08,276 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19439 states and 27341 transitions. [2023-11-23 22:38:08,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-23 22:38:08,277 INFO L428 stractBuchiCegarLoop]: Abstraction has 19439 states and 27341 transitions. [2023-11-23 22:38:08,277 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-23 22:38:08,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19439 states and 27341 transitions. [2023-11-23 22:38:08,353 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19232 [2023-11-23 22:38:08,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:08,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:08,357 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:08,357 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:08,357 INFO L748 eck$LassoCheckResult]: Stem: 164273#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 164274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 165346#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 165347#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 164739#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 164740#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 164605#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 164497#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164216#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 163871#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 163872#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 163916#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 163917#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 164882#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 164883#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 164934#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 164317#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164318#L1090 assume !(0 == ~M_E~0); 164367#L1090-2 assume !(0 == ~T1_E~0); 164368#L1095-1 assume !(0 == ~T2_E~0); 165088#L1100-1 assume !(0 == ~T3_E~0); 165089#L1105-1 assume !(0 == ~T4_E~0); 164137#L1110-1 assume !(0 == ~T5_E~0); 164138#L1115-1 assume !(0 == ~T6_E~0); 164536#L1120-1 assume !(0 == ~T7_E~0); 164850#L1125-1 assume !(0 == ~T8_E~0); 165439#L1130-1 assume !(0 == ~T9_E~0); 165112#L1135-1 assume !(0 == ~T10_E~0); 164323#L1140-1 assume !(0 == ~T11_E~0); 164324#L1145-1 assume !(0 == ~E_1~0); 165040#L1150-1 assume !(0 == ~E_2~0); 164511#L1155-1 assume !(0 == ~E_3~0); 164512#L1160-1 assume !(0 == ~E_4~0); 164612#L1165-1 assume !(0 == ~E_5~0); 164613#L1170-1 assume !(0 == ~E_6~0); 165320#L1175-1 assume !(0 == ~E_7~0); 164695#L1180-1 assume !(0 == ~E_8~0); 164696#L1185-1 assume !(0 == ~E_9~0); 164319#L1190-1 assume !(0 == ~E_10~0); 164320#L1195-1 assume !(0 == ~E_11~0); 164711#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164530#L525 assume !(1 == ~m_pc~0); 163960#L525-2 is_master_triggered_~__retres1~0#1 := 0; 163961#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165197#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 165168#L1350 assume !(0 != activate_threads_~tmp~1#1); 164309#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164310#L544 assume !(1 == ~t1_pc~0); 164531#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 164532#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163940#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163941#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 164159#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 164818#L563 assume !(1 == ~t2_pc~0); 165026#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 163979#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163980#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 164393#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 164394#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164906#L582 assume !(1 == ~t3_pc~0); 165039#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 165399#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163863#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163864#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 164045#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164046#L601 assume !(1 == ~t4_pc~0); 165054#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 164537#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164059#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 164060#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 165049#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 165392#L620 assume !(1 == ~t5_pc~0); 164869#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 164870#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164924#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 165203#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 165408#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 165409#L639 assume !(1 == ~t6_pc~0); 164848#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 164431#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 164432#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 164481#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 164542#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 164543#L658 assume !(1 == ~t7_pc~0); 164763#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 164764#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 165417#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 164980#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 164312#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 164313#L677 assume !(1 == ~t8_pc~0); 164337#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 164125#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 164126#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 164386#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 164387#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 165159#L696 assume !(1 == ~t9_pc~0); 164833#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 164834#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 164941#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 164858#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 164859#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 165093#L715 assume 1 == ~t10_pc~0; 165101#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 164960#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 164751#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 164752#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 164688#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 164113#L734 assume !(1 == ~t11_pc~0); 164114#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 164614#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 164700#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 163861#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 163862#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164925#L1213 assume !(1 == ~M_E~0); 164686#L1213-2 assume !(1 == ~T1_E~0); 164687#L1218-1 assume !(1 == ~T2_E~0); 163894#L1223-1 assume !(1 == ~T3_E~0); 163895#L1228-1 assume !(1 == ~T4_E~0); 164661#L1233-1 assume !(1 == ~T5_E~0); 165410#L1238-1 assume !(1 == ~T6_E~0); 165047#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 165048#L1248-1 assume !(1 == ~T8_E~0); 165097#L1253-1 assume !(1 == ~T9_E~0); 165098#L1258-1 assume !(1 == ~T10_E~0); 165071#L1263-1 assume !(1 == ~T11_E~0); 165072#L1268-1 assume !(1 == ~E_1~0); 164874#L1273-1 assume !(1 == ~E_2~0); 164875#L1278-1 assume !(1 == ~E_3~0); 164427#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 164428#L1288-1 assume !(1 == ~E_5~0); 165210#L1293-1 assume !(1 == ~E_6~0); 165164#L1298-1 assume !(1 == ~E_7~0); 164910#L1303-1 assume !(1 == ~E_8~0); 164438#L1308-1 assume !(1 == ~E_9~0); 164327#L1313-1 assume !(1 == ~E_10~0); 164328#L1318-1 assume !(1 == ~E_11~0); 164338#L1323-1 assume { :end_inline_reset_delta_events } true; 164339#L1644-2 [2023-11-23 22:38:08,358 INFO L750 eck$LassoCheckResult]: Loop: 164339#L1644-2 assume !false; 169562#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 169557#L1065-1 assume !false; 169554#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 169542#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 169527#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 169522#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 169514#L906 assume !(0 != eval_~tmp~0#1); 169515#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 172326#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 172325#L1090-3 assume !(0 == ~M_E~0); 172324#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 172323#L1095-3 assume !(0 == ~T2_E~0); 172322#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 172321#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 172320#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 172319#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 172318#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 172317#L1125-3 assume !(0 == ~T8_E~0); 172316#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 172315#L1135-3 assume !(0 == ~T10_E~0); 172314#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 172313#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 172312#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 172311#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 172310#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 172309#L1165-3 assume !(0 == ~E_5~0); 172308#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 172307#L1175-3 assume !(0 == ~E_7~0); 172306#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 172305#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 172304#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 172303#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 172302#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 172301#L525-36 assume 1 == ~m_pc~0; 172299#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 172297#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 172295#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 172293#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 172292#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 172291#L544-36 assume !(1 == ~t1_pc~0); 172290#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 172289#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 172288#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 172287#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 172286#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 172285#L563-36 assume !(1 == ~t2_pc~0); 172283#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 172282#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172281#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 172280#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 172279#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 172278#L582-36 assume !(1 == ~t3_pc~0); 172277#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 172276#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172275#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 172274#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 172273#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 172272#L601-36 assume !(1 == ~t4_pc~0); 172270#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 172269#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172268#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 172267#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 172266#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172265#L620-36 assume !(1 == ~t5_pc~0); 172264#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 172263#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 172262#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 172261#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 172260#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 172259#L639-36 assume !(1 == ~t6_pc~0); 172258#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 172256#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 172255#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 172254#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 172253#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 172252#L658-36 assume !(1 == ~t7_pc~0); 172250#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 172249#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 172248#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 172247#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 172246#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 172245#L677-36 assume !(1 == ~t8_pc~0); 172244#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 172243#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 172242#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 172241#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 172240#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 172239#L696-36 assume !(1 == ~t9_pc~0); 172238#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 172236#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 172234#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 172232#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 169789#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 169787#L715-36 assume 1 == ~t10_pc~0; 169784#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 169781#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 169779#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 169777#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 169775#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 169773#L734-36 assume !(1 == ~t11_pc~0); 169770#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 169767#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 169765#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 169763#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 169761#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169760#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 169759#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 169758#L1218-3 assume !(1 == ~T2_E~0); 169757#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 169756#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 169755#L1233-3 assume !(1 == ~T5_E~0); 169754#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 169752#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 169749#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 169746#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 169743#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 169740#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 169738#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 169736#L1273-3 assume !(1 == ~E_2~0); 169734#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 169732#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 169730#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 169727#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 169724#L1298-3 assume !(1 == ~E_7~0); 169721#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 169717#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 169714#L1313-3 assume !(1 == ~E_10~0); 169711#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 169709#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 169678#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 169670#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 169667#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 169655#L1663 assume !(0 == start_simulation_~tmp~3#1); 169653#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 169642#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 169625#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 169617#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 169605#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 169594#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 169586#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 169576#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 164339#L1644-2 [2023-11-23 22:38:08,359 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:08,359 INFO L85 PathProgramCache]: Analyzing trace with hash 145151095, now seen corresponding path program 1 times [2023-11-23 22:38:08,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:08,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226577212] [2023-11-23 22:38:08,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:08,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:08,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:08,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:08,551 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:08,551 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226577212] [2023-11-23 22:38:08,551 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226577212] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:08,551 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:08,552 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:38:08,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1225372040] [2023-11-23 22:38:08,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:08,553 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:08,553 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:08,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1579793467, now seen corresponding path program 1 times [2023-11-23 22:38:08,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:08,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211615582] [2023-11-23 22:38:08,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:08,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:08,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:08,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:08,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:08,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211615582] [2023-11-23 22:38:08,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1211615582] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:08,651 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:08,651 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:08,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1186962297] [2023-11-23 22:38:08,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:08,653 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:08,653 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:08,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:08,654 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:08,654 INFO L87 Difference]: Start difference. First operand 19439 states and 27341 transitions. cyclomatic complexity: 7918 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:09,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:09,083 INFO L93 Difference]: Finished difference Result 37110 states and 52010 transitions. [2023-11-23 22:38:09,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37110 states and 52010 transitions. [2023-11-23 22:38:09,478 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36816 [2023-11-23 22:38:09,611 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37110 states to 37110 states and 52010 transitions. [2023-11-23 22:38:09,611 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37110 [2023-11-23 22:38:09,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37110 [2023-11-23 22:38:09,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37110 states and 52010 transitions. [2023-11-23 22:38:09,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:09,782 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37110 states and 52010 transitions. [2023-11-23 22:38:09,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37110 states and 52010 transitions. [2023-11-23 22:38:10,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37110 to 37078. [2023-11-23 22:38:10,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.4018555477641728) internal successors, (51978), 37077 states have internal predecessors, (51978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:10,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 51978 transitions. [2023-11-23 22:38:10,483 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51978 transitions. [2023-11-23 22:38:10,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:10,484 INFO L428 stractBuchiCegarLoop]: Abstraction has 37078 states and 51978 transitions. [2023-11-23 22:38:10,484 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-23 22:38:10,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 51978 transitions. [2023-11-23 22:38:10,866 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-23 22:38:10,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:10,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:10,871 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:10,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:10,872 INFO L748 eck$LassoCheckResult]: Stem: 220831#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 220832#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 221902#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 221903#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221298#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 221299#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 221163#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 221054#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 220775#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 220427#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 220428#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 220473#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 220474#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 221452#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 221453#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 221501#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 220875#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 220876#L1090 assume !(0 == ~M_E~0); 220923#L1090-2 assume !(0 == ~T1_E~0); 220924#L1095-1 assume !(0 == ~T2_E~0); 221659#L1100-1 assume !(0 == ~T3_E~0); 221660#L1105-1 assume !(0 == ~T4_E~0); 220697#L1110-1 assume !(0 == ~T5_E~0); 220698#L1115-1 assume !(0 == ~T6_E~0); 221094#L1120-1 assume !(0 == ~T7_E~0); 221420#L1125-1 assume !(0 == ~T8_E~0); 221986#L1130-1 assume !(0 == ~T9_E~0); 221678#L1135-1 assume !(0 == ~T10_E~0); 220881#L1140-1 assume !(0 == ~T11_E~0); 220882#L1145-1 assume !(0 == ~E_1~0); 221608#L1150-1 assume !(0 == ~E_2~0); 221069#L1155-1 assume !(0 == ~E_3~0); 221070#L1160-1 assume !(0 == ~E_4~0); 221168#L1165-1 assume !(0 == ~E_5~0); 221169#L1170-1 assume !(0 == ~E_6~0); 221882#L1175-1 assume !(0 == ~E_7~0); 221253#L1180-1 assume !(0 == ~E_8~0); 221254#L1185-1 assume !(0 == ~E_9~0); 220877#L1190-1 assume !(0 == ~E_10~0); 220878#L1195-1 assume !(0 == ~E_11~0); 221269#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221088#L525 assume !(1 == ~m_pc~0); 220517#L525-2 is_master_triggered_~__retres1~0#1 := 0; 220518#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221852#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221739#L1350 assume !(0 != activate_threads_~tmp~1#1); 220867#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220868#L544 assume !(1 == ~t1_pc~0); 221089#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 221090#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220497#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220498#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 220720#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221385#L563 assume !(1 == ~t2_pc~0); 221596#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 220536#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220537#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 220949#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 220950#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221474#L582 assume !(1 == ~t3_pc~0); 221607#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221946#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220419#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 220420#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 220602#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220603#L601 assume !(1 == ~t4_pc~0); 221623#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 221095#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220616#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 220617#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 221617#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221941#L620 assume !(1 == ~t5_pc~0); 221436#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 221437#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221493#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 221773#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 221954#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221955#L639 assume !(1 == ~t6_pc~0); 221418#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 220989#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220990#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 221039#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 221098#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 221099#L658 assume !(1 == ~t7_pc~0); 221324#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 221325#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221963#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 221550#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 220870#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 220871#L677 assume !(1 == ~t8_pc~0); 220894#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 220681#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 220682#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220942#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 220943#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 221730#L696 assume !(1 == ~t9_pc~0); 221403#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 221404#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 221153#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 221154#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 221429#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 221663#L715 assume !(1 == ~t10_pc~0); 221919#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 221528#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 221310#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 221311#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 221247#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 220672#L734 assume !(1 == ~t11_pc~0); 220673#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 221170#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 221258#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 220417#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 220418#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221494#L1213 assume !(1 == ~M_E~0); 221245#L1213-2 assume !(1 == ~T1_E~0); 221246#L1218-1 assume !(1 == ~T2_E~0); 220450#L1223-1 assume !(1 == ~T3_E~0); 220451#L1228-1 assume !(1 == ~T4_E~0); 221217#L1233-1 assume !(1 == ~T5_E~0); 221956#L1238-1 assume !(1 == ~T6_E~0); 221615#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 221616#L1248-1 assume !(1 == ~T8_E~0); 221666#L1253-1 assume !(1 == ~T9_E~0); 221667#L1258-1 assume !(1 == ~T10_E~0); 221642#L1263-1 assume !(1 == ~T11_E~0); 221643#L1268-1 assume !(1 == ~E_1~0); 221444#L1273-1 assume !(1 == ~E_2~0); 221445#L1278-1 assume !(1 == ~E_3~0); 220985#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 220986#L1288-1 assume !(1 == ~E_5~0); 221777#L1293-1 assume !(1 == ~E_6~0); 221735#L1298-1 assume !(1 == ~E_7~0); 221478#L1303-1 assume !(1 == ~E_8~0); 220995#L1308-1 assume !(1 == ~E_9~0); 220885#L1313-1 assume !(1 == ~E_10~0); 220886#L1318-1 assume !(1 == ~E_11~0); 220895#L1323-1 assume { :end_inline_reset_delta_events } true; 220896#L1644-2 [2023-11-23 22:38:10,873 INFO L750 eck$LassoCheckResult]: Loop: 220896#L1644-2 assume !false; 244497#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 244491#L1065-1 assume !false; 244486#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 244237#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 244216#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 244208#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 244197#L906 assume !(0 != eval_~tmp~0#1); 244198#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 247367#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 247365#L1090-3 assume !(0 == ~M_E~0); 247363#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 247361#L1095-3 assume !(0 == ~T2_E~0); 247359#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 247357#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 247355#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 247352#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 247350#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 247348#L1125-3 assume !(0 == ~T8_E~0); 247346#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 247345#L1135-3 assume !(0 == ~T10_E~0); 247341#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 247339#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 247337#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 247334#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 247333#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 247332#L1165-3 assume !(0 == ~E_5~0); 247320#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 247310#L1175-3 assume !(0 == ~E_7~0); 247309#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 247308#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 247295#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 247286#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 247279#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247210#L525-36 assume 1 == ~m_pc~0; 247193#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 247187#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247179#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 247115#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 247113#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247111#L544-36 assume !(1 == ~t1_pc~0); 247109#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 247107#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247105#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 247102#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 247100#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247098#L563-36 assume !(1 == ~t2_pc~0); 247095#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 247093#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247091#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 247088#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 247086#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247084#L582-36 assume !(1 == ~t3_pc~0); 247080#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 247068#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247058#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 247049#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 247042#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247035#L601-36 assume 1 == ~t4_pc~0; 247030#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 247023#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247015#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247009#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 247002#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 246995#L620-36 assume !(1 == ~t5_pc~0); 246988#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 246979#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 245378#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 245365#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 245363#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 245361#L639-36 assume !(1 == ~t6_pc~0); 245359#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 245356#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 245354#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 245352#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 245350#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 245345#L658-36 assume !(1 == ~t7_pc~0); 245342#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 245340#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 245339#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 245338#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 245337#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 245318#L677-36 assume !(1 == ~t8_pc~0); 245311#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 245305#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 245276#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 245270#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 245264#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 244972#L696-36 assume !(1 == ~t9_pc~0); 244970#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 244968#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 244966#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 244964#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 244961#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 244959#L715-36 assume !(1 == ~t10_pc~0); 244957#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 244955#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 244953#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 244951#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 244947#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 244945#L734-36 assume 1 == ~t11_pc~0; 244942#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 244938#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 244936#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 244934#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 244932#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 244930#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 244928#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 244926#L1218-3 assume !(1 == ~T2_E~0); 244924#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 244922#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 244919#L1233-3 assume !(1 == ~T5_E~0); 244917#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 244915#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 244913#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 244911#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 244910#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 244909#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 244894#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 244884#L1273-3 assume !(1 == ~E_2~0); 244883#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 244882#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 244881#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 244879#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 244878#L1298-3 assume !(1 == ~E_7~0); 244845#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 244829#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 244820#L1313-3 assume !(1 == ~E_10~0); 244814#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 244810#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 244669#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 244656#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 244648#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 244638#L1663 assume !(0 == start_simulation_~tmp~3#1); 244633#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 244559#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 244544#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 244539#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 244532#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 244527#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 244521#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 244512#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 220896#L1644-2 [2023-11-23 22:38:10,874 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:10,875 INFO L85 PathProgramCache]: Analyzing trace with hash -1619665514, now seen corresponding path program 1 times [2023-11-23 22:38:10,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:10,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988199613] [2023-11-23 22:38:10,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:10,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:10,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:11,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:11,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:11,020 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988199613] [2023-11-23 22:38:11,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [988199613] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:11,021 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:11,021 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:11,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750802411] [2023-11-23 22:38:11,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:11,023 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:11,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:11,023 INFO L85 PathProgramCache]: Analyzing trace with hash 1328081372, now seen corresponding path program 1 times [2023-11-23 22:38:11,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:11,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303816130] [2023-11-23 22:38:11,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:11,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:11,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:11,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:11,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:11,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303816130] [2023-11-23 22:38:11,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [303816130] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:11,116 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:11,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:11,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [42316809] [2023-11-23 22:38:11,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:11,117 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:11,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:11,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:38:11,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:38:11,119 INFO L87 Difference]: Start difference. First operand 37078 states and 51978 transitions. cyclomatic complexity: 14932 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:12,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:12,045 INFO L93 Difference]: Finished difference Result 77699 states and 108961 transitions. [2023-11-23 22:38:12,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77699 states and 108961 transitions. [2023-11-23 22:38:12,356 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 77136 [2023-11-23 22:38:12,856 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77699 states to 77699 states and 108961 transitions. [2023-11-23 22:38:12,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77699 [2023-11-23 22:38:12,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77699 [2023-11-23 22:38:12,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77699 states and 108961 transitions. [2023-11-23 22:38:12,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:12,989 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77699 states and 108961 transitions. [2023-11-23 22:38:13,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77699 states and 108961 transitions. [2023-11-23 22:38:13,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77699 to 40755. [2023-11-23 22:38:13,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40755 states, 40755 states have (on average 1.404367562262299) internal successors, (57235), 40754 states have internal predecessors, (57235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:14,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40755 states to 40755 states and 57235 transitions. [2023-11-23 22:38:14,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40755 states and 57235 transitions. [2023-11-23 22:38:14,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:38:14,009 INFO L428 stractBuchiCegarLoop]: Abstraction has 40755 states and 57235 transitions. [2023-11-23 22:38:14,009 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-23 22:38:14,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40755 states and 57235 transitions. [2023-11-23 22:38:14,163 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40352 [2023-11-23 22:38:14,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:14,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:14,167 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:14,167 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:14,168 INFO L748 eck$LassoCheckResult]: Stem: 335625#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 335626#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 336724#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 336725#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 336090#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 336091#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 335958#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 335847#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 335567#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 335214#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 335215#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 335259#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 335260#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 336247#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 336248#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 336299#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 335666#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 335667#L1090 assume !(0 == ~M_E~0); 335716#L1090-2 assume !(0 == ~T1_E~0); 335717#L1095-1 assume !(0 == ~T2_E~0); 336466#L1100-1 assume !(0 == ~T3_E~0); 336467#L1105-1 assume !(0 == ~T4_E~0); 335484#L1110-1 assume !(0 == ~T5_E~0); 335485#L1115-1 assume !(0 == ~T6_E~0); 335888#L1120-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 336215#L1125-1 assume !(0 == ~T8_E~0); 336833#L1130-1 assume !(0 == ~T9_E~0); 336489#L1135-1 assume !(0 == ~T10_E~0); 335672#L1140-1 assume !(0 == ~T11_E~0); 335673#L1145-1 assume !(0 == ~E_1~0); 336933#L1150-1 assume !(0 == ~E_2~0); 335864#L1155-1 assume !(0 == ~E_3~0); 335865#L1160-1 assume !(0 == ~E_4~0); 336932#L1165-1 assume !(0 == ~E_5~0); 336701#L1170-1 assume !(0 == ~E_6~0); 336702#L1175-1 assume !(0 == ~E_7~0); 336931#L1180-1 assume !(0 == ~E_8~0); 336930#L1185-1 assume !(0 == ~E_9~0); 336929#L1190-1 assume !(0 == ~E_10~0); 336928#L1195-1 assume !(0 == ~E_11~0); 336670#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 336671#L525 assume !(1 == ~m_pc~0); 336926#L525-2 is_master_triggered_~__retres1~0#1 := 0; 336924#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 336922#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 336920#L1350 assume !(0 != activate_threads_~tmp~1#1); 336919#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 336121#L544 assume !(1 == ~t1_pc~0); 336122#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 336410#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 335282#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 335283#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 336179#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 336180#L563 assume !(1 == ~t2_pc~0); 336397#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 336398#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 335861#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 336269#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 336270#L582 assume !(1 == ~t3_pc~0); 336835#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 336836#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 336914#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 336711#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 335391#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 335392#L601 assume !(1 == ~t4_pc~0); 336911#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 336910#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 336909#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 336908#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 336858#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336859#L620 assume !(1 == ~t5_pc~0); 336235#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 336236#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 336907#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 336876#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 336877#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 336838#L639 assume !(1 == ~t6_pc~0); 336839#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 335780#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 335781#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 336789#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 335894#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 335895#L658 assume !(1 == ~t7_pc~0); 336214#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 336803#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 336804#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 336347#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 335661#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 335662#L677 assume !(1 == ~t8_pc~0); 335900#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 335471#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 335472#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 336508#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 336900#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 336899#L696 assume !(1 == ~t9_pc~0); 336195#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 336196#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 336938#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 336224#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 336225#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 336472#L715 assume !(1 == ~t10_pc~0); 336818#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 336819#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 336106#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 336107#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 336037#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 336038#L734 assume !(1 == ~t11_pc~0); 336888#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 336887#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 336357#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 336358#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 336289#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336290#L1213 assume !(1 == ~M_E~0); 336886#L1213-2 assume !(1 == ~T1_E~0); 336885#L1218-1 assume !(1 == ~T2_E~0); 336884#L1223-1 assume !(1 == ~T3_E~0); 336883#L1228-1 assume !(1 == ~T4_E~0); 336793#L1233-1 assume !(1 == ~T5_E~0); 336794#L1238-1 assume !(1 == ~T6_E~0); 336882#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 336422#L1248-1 assume !(1 == ~T8_E~0); 336477#L1253-1 assume !(1 == ~T9_E~0); 336478#L1258-1 assume !(1 == ~T10_E~0); 336447#L1263-1 assume !(1 == ~T11_E~0); 336448#L1268-1 assume !(1 == ~E_1~0); 336240#L1273-1 assume !(1 == ~E_2~0); 336241#L1278-1 assume !(1 == ~E_3~0); 335776#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 335777#L1288-1 assume !(1 == ~E_5~0); 336588#L1293-1 assume !(1 == ~E_6~0); 336543#L1298-1 assume !(1 == ~E_7~0); 336274#L1303-1 assume !(1 == ~E_8~0); 335787#L1308-1 assume !(1 == ~E_9~0); 335676#L1313-1 assume !(1 == ~E_10~0); 335677#L1318-1 assume !(1 == ~E_11~0); 335688#L1323-1 assume { :end_inline_reset_delta_events } true; 335689#L1644-2 [2023-11-23 22:38:14,168 INFO L750 eck$LassoCheckResult]: Loop: 335689#L1644-2 assume !false; 343116#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 343111#L1065-1 assume !false; 343109#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 343092#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 343081#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 343079#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 343076#L906 assume !(0 != eval_~tmp~0#1); 343077#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 343442#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 343441#L1090-3 assume !(0 == ~M_E~0); 343440#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 343439#L1095-3 assume !(0 == ~T2_E~0); 343438#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 343437#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 343436#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 343435#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 343433#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 343432#L1125-3 assume !(0 == ~T8_E~0); 343431#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 343430#L1135-3 assume !(0 == ~T10_E~0); 343429#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 343428#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 343427#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 343426#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 343425#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 343424#L1165-3 assume !(0 == ~E_5~0); 343423#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 343422#L1175-3 assume !(0 == ~E_7~0); 343421#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 343420#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 343419#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 343418#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 343417#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 343416#L525-36 assume !(1 == ~m_pc~0); 343415#L525-38 is_master_triggered_~__retres1~0#1 := 0; 343413#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 343411#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 343409#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 343407#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343406#L544-36 assume !(1 == ~t1_pc~0); 343405#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 343404#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 343403#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 343402#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 343401#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 343400#L563-36 assume 1 == ~t2_pc~0; 343399#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 343397#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 343396#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 343395#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 343394#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 343393#L582-36 assume !(1 == ~t3_pc~0); 343392#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 343391#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 343390#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 343389#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 343388#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 343387#L601-36 assume !(1 == ~t4_pc~0); 343385#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 343384#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 343383#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 343382#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 343381#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 343380#L620-36 assume !(1 == ~t5_pc~0); 343379#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 343378#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 343377#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 343376#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 343375#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 343374#L639-36 assume !(1 == ~t6_pc~0); 343373#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 343371#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 343370#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 343369#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 343368#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 343367#L658-36 assume !(1 == ~t7_pc~0); 343365#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 343364#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 343363#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 343362#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 343361#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 343360#L677-36 assume !(1 == ~t8_pc~0); 343359#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 343358#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 343357#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 343356#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 343355#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 343354#L696-36 assume !(1 == ~t9_pc~0); 343353#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 343351#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 343349#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 343347#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 343345#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 343344#L715-36 assume !(1 == ~t10_pc~0); 343343#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 343342#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 343341#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 343340#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 343339#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 343338#L734-36 assume 1 == ~t11_pc~0; 343337#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 343335#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 343334#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 343333#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 343332#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 343331#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 343330#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 343329#L1218-3 assume !(1 == ~T2_E~0); 343328#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 343327#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 343326#L1233-3 assume !(1 == ~T5_E~0); 343325#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 343323#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 343321#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 343318#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 343316#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 343314#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 343312#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 343310#L1273-3 assume !(1 == ~E_2~0); 343308#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 343306#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 343304#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 343302#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 343300#L1298-3 assume !(1 == ~E_7~0); 343298#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 343296#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 343293#L1313-3 assume !(1 == ~E_10~0); 343291#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 343289#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 343274#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 343267#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 343264#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 343152#L1663 assume !(0 == start_simulation_~tmp~3#1); 343149#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 343140#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 343129#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 343127#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 343125#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 343123#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 343121#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 343119#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 335689#L1644-2 [2023-11-23 22:38:14,169 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:14,169 INFO L85 PathProgramCache]: Analyzing trace with hash 948156820, now seen corresponding path program 1 times [2023-11-23 22:38:14,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:14,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863390067] [2023-11-23 22:38:14,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:14,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:14,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:14,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:14,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:14,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [863390067] [2023-11-23 22:38:14,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [863390067] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:14,269 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:14,270 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:14,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1222609839] [2023-11-23 22:38:14,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:14,271 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:14,271 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:14,271 INFO L85 PathProgramCache]: Analyzing trace with hash 1460114489, now seen corresponding path program 1 times [2023-11-23 22:38:14,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:14,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359760768] [2023-11-23 22:38:14,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:14,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:14,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:14,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:14,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:14,341 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359760768] [2023-11-23 22:38:14,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359760768] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:14,341 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:14,342 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:14,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1846857109] [2023-11-23 22:38:14,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:14,343 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:14,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:14,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:38:14,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:38:14,344 INFO L87 Difference]: Start difference. First operand 40755 states and 57235 transitions. cyclomatic complexity: 16512 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:14,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:14,925 INFO L93 Difference]: Finished difference Result 37078 states and 51880 transitions. [2023-11-23 22:38:14,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37078 states and 51880 transitions. [2023-11-23 22:38:15,154 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-23 22:38:15,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37078 states to 37078 states and 51880 transitions. [2023-11-23 22:38:15,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37078 [2023-11-23 22:38:15,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37078 [2023-11-23 22:38:15,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37078 states and 51880 transitions. [2023-11-23 22:38:15,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:15,408 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51880 transitions. [2023-11-23 22:38:15,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37078 states and 51880 transitions. [2023-11-23 22:38:16,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37078 to 37078. [2023-11-23 22:38:16,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.3992124710070661) internal successors, (51880), 37077 states have internal predecessors, (51880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:16,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 51880 transitions. [2023-11-23 22:38:16,166 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51880 transitions. [2023-11-23 22:38:16,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:16,168 INFO L428 stractBuchiCegarLoop]: Abstraction has 37078 states and 51880 transitions. [2023-11-23 22:38:16,168 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-23 22:38:16,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 51880 transitions. [2023-11-23 22:38:16,327 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-23 22:38:16,327 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:16,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:16,331 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:16,332 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:16,333 INFO L748 eck$LassoCheckResult]: Stem: 413465#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 413466#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 414562#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 414563#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 413926#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 413927#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 413793#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 413685#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 413408#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 413057#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 413058#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 413102#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 413103#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 414073#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 414074#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 414120#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 413507#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 413508#L1090 assume !(0 == ~M_E~0); 413554#L1090-2 assume !(0 == ~T1_E~0); 413555#L1095-1 assume !(0 == ~T2_E~0); 414293#L1100-1 assume !(0 == ~T3_E~0); 414294#L1105-1 assume !(0 == ~T4_E~0); 413328#L1110-1 assume !(0 == ~T5_E~0); 413329#L1115-1 assume !(0 == ~T6_E~0); 413721#L1120-1 assume !(0 == ~T7_E~0); 414047#L1125-1 assume !(0 == ~T8_E~0); 414693#L1130-1 assume !(0 == ~T9_E~0); 414317#L1135-1 assume !(0 == ~T10_E~0); 413513#L1140-1 assume !(0 == ~T11_E~0); 413514#L1145-1 assume !(0 == ~E_1~0); 414234#L1150-1 assume !(0 == ~E_2~0); 413699#L1155-1 assume !(0 == ~E_3~0); 413700#L1160-1 assume !(0 == ~E_4~0); 413798#L1165-1 assume !(0 == ~E_5~0); 413799#L1170-1 assume !(0 == ~E_6~0); 414533#L1175-1 assume !(0 == ~E_7~0); 413882#L1180-1 assume !(0 == ~E_8~0); 413883#L1185-1 assume !(0 == ~E_9~0); 413509#L1190-1 assume !(0 == ~E_10~0); 413510#L1195-1 assume !(0 == ~E_11~0); 413898#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 413718#L525 assume !(1 == ~m_pc~0); 413147#L525-2 is_master_triggered_~__retres1~0#1 := 0; 413148#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 414500#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 414377#L1350 assume !(0 != activate_threads_~tmp~1#1); 413498#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 413499#L544 assume !(1 == ~t1_pc~0); 413719#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 413720#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 413125#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 413126#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 413352#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 414012#L563 assume !(1 == ~t2_pc~0); 414218#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 413169#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 413170#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 413582#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 413583#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 414100#L582 assume !(1 == ~t3_pc~0); 414233#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 414636#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 413049#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 413050#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 413234#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 413235#L601 assume !(1 == ~t4_pc~0); 414249#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 413722#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 413248#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 413249#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 414244#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 414627#L620 assume !(1 == ~t5_pc~0); 414061#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 414062#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 414117#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 414412#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 414648#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 414649#L639 assume !(1 == ~t6_pc~0); 414045#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 413620#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 413621#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 413670#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 413727#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 413728#L658 assume !(1 == ~t7_pc~0); 413955#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 413956#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 414661#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 414172#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 413502#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 413503#L677 assume !(1 == ~t8_pc~0); 413526#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 413309#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 413310#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 413575#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 413576#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 414365#L696 assume !(1 == ~t9_pc~0); 414028#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 414029#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 413783#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 413784#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 414052#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 414297#L715 assume !(1 == ~t10_pc~0); 414585#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 414152#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 413942#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 413943#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 413875#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 413303#L734 assume !(1 == ~t11_pc~0); 413304#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 413800#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 413887#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 413047#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 413048#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 414118#L1213 assume !(1 == ~M_E~0); 413873#L1213-2 assume !(1 == ~T1_E~0); 413874#L1218-1 assume !(1 == ~T2_E~0); 413080#L1223-1 assume !(1 == ~T3_E~0); 413081#L1228-1 assume !(1 == ~T4_E~0); 413846#L1233-1 assume !(1 == ~T5_E~0); 414650#L1238-1 assume !(1 == ~T6_E~0); 414242#L1243-1 assume !(1 == ~T7_E~0); 414243#L1248-1 assume !(1 == ~T8_E~0); 414302#L1253-1 assume !(1 == ~T9_E~0); 414303#L1258-1 assume !(1 == ~T10_E~0); 414270#L1263-1 assume !(1 == ~T11_E~0); 414271#L1268-1 assume !(1 == ~E_1~0); 414069#L1273-1 assume !(1 == ~E_2~0); 414070#L1278-1 assume !(1 == ~E_3~0); 413616#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 413617#L1288-1 assume !(1 == ~E_5~0); 414419#L1293-1 assume !(1 == ~E_6~0); 414370#L1298-1 assume !(1 == ~E_7~0); 414104#L1303-1 assume !(1 == ~E_8~0); 413626#L1308-1 assume !(1 == ~E_9~0); 413517#L1313-1 assume !(1 == ~E_10~0); 413518#L1318-1 assume !(1 == ~E_11~0); 413527#L1323-1 assume { :end_inline_reset_delta_events } true; 413528#L1644-2 [2023-11-23 22:38:16,334 INFO L750 eck$LassoCheckResult]: Loop: 413528#L1644-2 assume !false; 423154#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 423150#L1065-1 assume !false; 423147#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 423136#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 423125#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 423122#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 423120#L906 assume !(0 != eval_~tmp~0#1); 423121#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 423582#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 423579#L1090-3 assume !(0 == ~M_E~0); 423577#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 423575#L1095-3 assume !(0 == ~T2_E~0); 423573#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 423571#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 423569#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 423567#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 423565#L1120-3 assume !(0 == ~T7_E~0); 423563#L1125-3 assume !(0 == ~T8_E~0); 423561#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 423559#L1135-3 assume !(0 == ~T10_E~0); 423557#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 423554#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 423552#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 423550#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 423548#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 423546#L1165-3 assume !(0 == ~E_5~0); 423544#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 423542#L1175-3 assume !(0 == ~E_7~0); 423540#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 423538#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 423536#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 423534#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 423532#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 423529#L525-36 assume 1 == ~m_pc~0; 423527#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 423528#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 423590#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 423518#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 423516#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 423513#L544-36 assume !(1 == ~t1_pc~0); 423511#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 423509#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 423507#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 423505#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 423503#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 423501#L563-36 assume !(1 == ~t2_pc~0); 423498#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 423496#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 423494#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 423492#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 423488#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 423486#L582-36 assume !(1 == ~t3_pc~0); 423484#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 423482#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 423479#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 423477#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 423475#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 423473#L601-36 assume !(1 == ~t4_pc~0); 423470#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 423468#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 423466#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 423464#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 423462#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 423459#L620-36 assume !(1 == ~t5_pc~0); 423457#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 423455#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 423453#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 423451#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 423450#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 423449#L639-36 assume 1 == ~t6_pc~0; 423447#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 423446#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 423445#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 423444#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 423443#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 423442#L658-36 assume !(1 == ~t7_pc~0); 423440#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 423439#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 423438#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 423437#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 423436#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 423435#L677-36 assume !(1 == ~t8_pc~0); 423434#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 423432#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 423430#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 423428#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 423425#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 423423#L696-36 assume 1 == ~t9_pc~0; 423424#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 423422#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 423420#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 423416#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 423415#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 423414#L715-36 assume !(1 == ~t10_pc~0); 423412#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 423411#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 423410#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 423409#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 423408#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 423407#L734-36 assume 1 == ~t11_pc~0; 423406#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 423404#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 423403#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 423402#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 423401#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 423400#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 423399#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 423398#L1218-3 assume !(1 == ~T2_E~0); 423397#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 423396#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 423395#L1233-3 assume !(1 == ~T5_E~0); 423394#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 423392#L1243-3 assume !(1 == ~T7_E~0); 423391#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 423390#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 423389#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 423385#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 423383#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 423381#L1273-3 assume !(1 == ~E_2~0); 423379#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 423376#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 423374#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 423372#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 423370#L1298-3 assume !(1 == ~E_7~0); 423368#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 423366#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 423364#L1313-3 assume !(1 == ~E_10~0); 423362#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 423360#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 423344#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 423337#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 423335#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 423190#L1663 assume !(0 == start_simulation_~tmp~3#1); 423188#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 423179#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 423167#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 423165#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 423163#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 423161#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 423159#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 423157#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 413528#L1644-2 [2023-11-23 22:38:16,335 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:16,336 INFO L85 PathProgramCache]: Analyzing trace with hash 1086953880, now seen corresponding path program 1 times [2023-11-23 22:38:16,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:16,336 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575234094] [2023-11-23 22:38:16,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:16,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:16,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:16,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:16,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:16,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1575234094] [2023-11-23 22:38:16,475 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1575234094] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:16,475 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:16,475 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:16,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1809680354] [2023-11-23 22:38:16,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:16,476 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:16,477 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:16,477 INFO L85 PathProgramCache]: Analyzing trace with hash -1878490685, now seen corresponding path program 1 times [2023-11-23 22:38:16,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:16,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104109542] [2023-11-23 22:38:16,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:16,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:16,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:16,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:16,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:16,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [104109542] [2023-11-23 22:38:16,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [104109542] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:16,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:16,857 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:16,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280153657] [2023-11-23 22:38:16,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:16,858 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:16,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:16,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:38:16,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:38:16,868 INFO L87 Difference]: Start difference. First operand 37078 states and 51880 transitions. cyclomatic complexity: 14834 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:17,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:17,527 INFO L93 Difference]: Finished difference Result 77241 states and 107480 transitions. [2023-11-23 22:38:17,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77241 states and 107480 transitions. [2023-11-23 22:38:17,894 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 76600 [2023-11-23 22:38:18,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77241 states to 77241 states and 107480 transitions. [2023-11-23 22:38:18,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77241 [2023-11-23 22:38:18,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77241 [2023-11-23 22:38:18,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77241 states and 107480 transitions. [2023-11-23 22:38:18,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:18,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77241 states and 107480 transitions. [2023-11-23 22:38:18,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77241 states and 107480 transitions. [2023-11-23 22:38:19,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77241 to 40755. [2023-11-23 22:38:19,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40755 states, 40755 states have (on average 1.3940866151392468) internal successors, (56816), 40754 states have internal predecessors, (56816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:19,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40755 states to 40755 states and 56816 transitions. [2023-11-23 22:38:19,473 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40755 states and 56816 transitions. [2023-11-23 22:38:19,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:38:19,474 INFO L428 stractBuchiCegarLoop]: Abstraction has 40755 states and 56816 transitions. [2023-11-23 22:38:19,474 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-23 22:38:19,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40755 states and 56816 transitions. [2023-11-23 22:38:19,611 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40352 [2023-11-23 22:38:19,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:19,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:19,614 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:19,615 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:19,616 INFO L748 eck$LassoCheckResult]: Stem: 527791#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 527792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 528852#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 528853#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 528255#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 528256#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 528126#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 528016#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 527735#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 527386#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 527387#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 527430#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 527431#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 528401#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 528402#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 528447#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 527832#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 527833#L1090 assume !(0 == ~M_E~0); 527880#L1090-2 assume !(0 == ~T1_E~0); 527881#L1095-1 assume !(0 == ~T2_E~0); 528611#L1100-1 assume !(0 == ~T3_E~0); 528612#L1105-1 assume !(0 == ~T4_E~0); 527651#L1110-1 assume !(0 == ~T5_E~0); 527652#L1115-1 assume !(0 == ~T6_E~0); 528055#L1120-1 assume !(0 == ~T7_E~0); 528375#L1125-1 assume !(0 == ~T8_E~0); 528954#L1130-1 assume !(0 == ~T9_E~0); 528633#L1135-1 assume !(0 == ~T10_E~0); 527838#L1140-1 assume !(0 == ~T11_E~0); 527839#L1145-1 assume !(0 == ~E_1~0); 528565#L1150-1 assume !(0 == ~E_2~0); 528031#L1155-1 assume !(0 == ~E_3~0); 528032#L1160-1 assume 0 == ~E_4~0;~E_4~0 := 1; 528131#L1165-1 assume !(0 == ~E_5~0); 528132#L1170-1 assume !(0 == ~E_6~0); 528928#L1175-1 assume !(0 == ~E_7~0); 528213#L1180-1 assume !(0 == ~E_8~0); 528214#L1185-1 assume !(0 == ~E_9~0); 527834#L1190-1 assume !(0 == ~E_10~0); 527835#L1195-1 assume !(0 == ~E_11~0); 528229#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 528047#L525 assume !(1 == ~m_pc~0); 527475#L525-2 is_master_triggered_~__retres1~0#1 := 0; 527476#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 528715#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 528685#L1350 assume !(0 != activate_threads_~tmp~1#1); 527824#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 527825#L544 assume !(1 == ~t1_pc~0); 528053#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 528054#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 527449#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 527450#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 528341#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 528342#L563 assume !(1 == ~t2_pc~0); 528547#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 528548#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 528027#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 528028#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 528427#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 528428#L582 assume !(1 == ~t3_pc~0); 528564#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 528909#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 528910#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 528838#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 527559#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 527560#L601 assume !(1 == ~t4_pc~0); 529076#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 529075#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 529074#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 529073#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 529072#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 529071#L620 assume !(1 == ~t5_pc~0); 529070#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 529069#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 529068#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 529067#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 529066#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 529065#L639 assume !(1 == ~t6_pc~0); 529063#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 529062#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 529061#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 529060#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 529059#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 529058#L658 assume !(1 == ~t7_pc~0); 529056#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 529055#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 529054#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 529053#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 529052#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 529051#L677 assume !(1 == ~t8_pc~0); 529050#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 529049#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 529048#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 529047#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 529046#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 529045#L696 assume !(1 == ~t9_pc~0); 529043#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 529041#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 529039#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 529037#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 529036#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 529035#L715 assume !(1 == ~t10_pc~0); 529034#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 529033#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 529032#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 529031#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 529030#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 529029#L734 assume !(1 == ~t11_pc~0); 529027#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 529026#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 529025#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 529024#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 529023#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 529022#L1213 assume !(1 == ~M_E~0); 529021#L1213-2 assume !(1 == ~T1_E~0); 529020#L1218-1 assume !(1 == ~T2_E~0); 529019#L1223-1 assume !(1 == ~T3_E~0); 529018#L1228-1 assume !(1 == ~T4_E~0); 529017#L1233-1 assume !(1 == ~T5_E~0); 529016#L1238-1 assume !(1 == ~T6_E~0); 529015#L1243-1 assume !(1 == ~T7_E~0); 529014#L1248-1 assume !(1 == ~T8_E~0); 529013#L1253-1 assume !(1 == ~T9_E~0); 529012#L1258-1 assume !(1 == ~T10_E~0); 529011#L1263-1 assume !(1 == ~T11_E~0); 529010#L1268-1 assume !(1 == ~E_1~0); 529009#L1273-1 assume !(1 == ~E_2~0); 529008#L1278-1 assume !(1 == ~E_3~0); 529007#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 527947#L1288-1 assume !(1 == ~E_5~0); 528728#L1293-1 assume !(1 == ~E_6~0); 528680#L1298-1 assume !(1 == ~E_7~0); 528432#L1303-1 assume !(1 == ~E_8~0); 527956#L1308-1 assume !(1 == ~E_9~0); 527842#L1313-1 assume !(1 == ~E_10~0); 527843#L1318-1 assume !(1 == ~E_11~0); 527850#L1323-1 assume { :end_inline_reset_delta_events } true; 527851#L1644-2 [2023-11-23 22:38:19,617 INFO L750 eck$LassoCheckResult]: Loop: 527851#L1644-2 assume !false; 541703#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 541698#L1065-1 assume !false; 541695#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 541684#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 541673#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 541670#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 541668#L906 assume !(0 != eval_~tmp~0#1); 541669#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 542069#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 542067#L1090-3 assume !(0 == ~M_E~0); 542064#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 542062#L1095-3 assume !(0 == ~T2_E~0); 542060#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 542058#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 542056#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 542054#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 542051#L1120-3 assume !(0 == ~T7_E~0); 542049#L1125-3 assume !(0 == ~T8_E~0); 542047#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 542045#L1135-3 assume !(0 == ~T10_E~0); 542043#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 542041#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 542039#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 542037#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 542035#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 542034#L1165-3 assume !(0 == ~E_5~0); 542033#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 542032#L1175-3 assume !(0 == ~E_7~0); 542031#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 542030#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 542029#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 542028#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 542027#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 542026#L525-36 assume 1 == ~m_pc~0; 542024#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 542022#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 542020#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 542018#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 542017#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 542016#L544-36 assume !(1 == ~t1_pc~0); 542015#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 542014#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 542013#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 542012#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 542011#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 542010#L563-36 assume !(1 == ~t2_pc~0); 542008#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 542007#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 542006#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 542005#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 542004#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 542003#L582-36 assume !(1 == ~t3_pc~0); 542002#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 542001#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 542000#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 541999#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 541998#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 541997#L601-36 assume !(1 == ~t4_pc~0); 541994#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 541993#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 541992#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 541991#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 541990#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 541989#L620-36 assume !(1 == ~t5_pc~0); 541988#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 541987#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 541986#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 541985#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 541984#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 541983#L639-36 assume 1 == ~t6_pc~0; 541981#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 541980#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 541979#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 541978#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 541977#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 541976#L658-36 assume !(1 == ~t7_pc~0); 541974#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 541973#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 541972#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 541971#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 541970#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 541969#L677-36 assume !(1 == ~t8_pc~0); 541968#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 541967#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 541966#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 541965#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 541964#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 541963#L696-36 assume 1 == ~t9_pc~0; 541961#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 541959#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 541957#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 541955#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 541954#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 541953#L715-36 assume !(1 == ~t10_pc~0); 541952#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 541951#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 541950#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 541949#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 541948#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 541947#L734-36 assume !(1 == ~t11_pc~0); 541945#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 541944#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 541943#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 541942#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 541941#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 541940#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 541939#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 541938#L1218-3 assume !(1 == ~T2_E~0); 541937#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 541936#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 541935#L1233-3 assume !(1 == ~T5_E~0); 541934#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 541933#L1243-3 assume !(1 == ~T7_E~0); 541932#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 541931#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 541930#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 541929#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 541928#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 541927#L1273-3 assume !(1 == ~E_2~0); 541926#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 541924#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 541922#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 541920#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 541918#L1298-3 assume !(1 == ~E_7~0); 541916#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 541914#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 541912#L1313-3 assume !(1 == ~E_10~0); 541910#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 541907#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 541892#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 541885#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 541883#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 541739#L1663 assume !(0 == start_simulation_~tmp~3#1); 541737#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 541728#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 541716#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 541714#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 541712#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 541710#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 541708#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 541706#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 527851#L1644-2 [2023-11-23 22:38:19,617 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:19,618 INFO L85 PathProgramCache]: Analyzing trace with hash 968512406, now seen corresponding path program 1 times [2023-11-23 22:38:19,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:19,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283487672] [2023-11-23 22:38:19,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:19,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:19,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:19,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:19,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:19,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283487672] [2023-11-23 22:38:19,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1283487672] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:19,729 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:19,729 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:19,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258955317] [2023-11-23 22:38:19,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:19,730 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:19,731 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:19,731 INFO L85 PathProgramCache]: Analyzing trace with hash 260962210, now seen corresponding path program 1 times [2023-11-23 22:38:19,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:19,731 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146049449] [2023-11-23 22:38:19,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:19,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:19,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:19,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:19,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:19,801 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2146049449] [2023-11-23 22:38:19,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2146049449] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:19,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:19,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:19,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164136162] [2023-11-23 22:38:19,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:19,802 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:19,802 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:19,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-23 22:38:19,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-23 22:38:19,803 INFO L87 Difference]: Start difference. First operand 40755 states and 56816 transitions. cyclomatic complexity: 16093 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:20,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:20,143 INFO L93 Difference]: Finished difference Result 54950 states and 76421 transitions. [2023-11-23 22:38:20,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54950 states and 76421 transitions. [2023-11-23 22:38:20,858 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 54576 [2023-11-23 22:38:20,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54950 states to 54950 states and 76421 transitions. [2023-11-23 22:38:20,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54950 [2023-11-23 22:38:21,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54950 [2023-11-23 22:38:21,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54950 states and 76421 transitions. [2023-11-23 22:38:21,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:21,101 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54950 states and 76421 transitions. [2023-11-23 22:38:21,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54950 states and 76421 transitions. [2023-11-23 22:38:21,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54950 to 37078. [2023-11-23 22:38:21,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.3879119693618858) internal successors, (51461), 37077 states have internal predecessors, (51461), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:21,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 51461 transitions. [2023-11-23 22:38:21,614 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51461 transitions. [2023-11-23 22:38:21,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-23 22:38:21,615 INFO L428 stractBuchiCegarLoop]: Abstraction has 37078 states and 51461 transitions. [2023-11-23 22:38:21,615 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-23 22:38:21,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 51461 transitions. [2023-11-23 22:38:21,732 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-23 22:38:21,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:21,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:21,736 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:21,736 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:21,737 INFO L748 eck$LassoCheckResult]: Stem: 623508#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 623509#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 624591#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 624592#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 623966#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 623967#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 623837#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 623728#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 623451#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 623101#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 623102#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 623145#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 623146#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 624112#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 624113#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 624164#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 623550#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 623551#L1090 assume !(0 == ~M_E~0); 623594#L1090-2 assume !(0 == ~T1_E~0); 623595#L1095-1 assume !(0 == ~T2_E~0); 624328#L1100-1 assume !(0 == ~T3_E~0); 624329#L1105-1 assume !(0 == ~T4_E~0); 623369#L1110-1 assume !(0 == ~T5_E~0); 623370#L1115-1 assume !(0 == ~T6_E~0); 623766#L1120-1 assume !(0 == ~T7_E~0); 624088#L1125-1 assume !(0 == ~T8_E~0); 624699#L1130-1 assume !(0 == ~T9_E~0); 624353#L1135-1 assume !(0 == ~T10_E~0); 623556#L1140-1 assume !(0 == ~T11_E~0); 623557#L1145-1 assume !(0 == ~E_1~0); 624277#L1150-1 assume !(0 == ~E_2~0); 623742#L1155-1 assume !(0 == ~E_3~0); 623743#L1160-1 assume !(0 == ~E_4~0); 623843#L1165-1 assume !(0 == ~E_5~0); 623844#L1170-1 assume !(0 == ~E_6~0); 624567#L1175-1 assume !(0 == ~E_7~0); 623925#L1180-1 assume !(0 == ~E_8~0); 623926#L1185-1 assume !(0 == ~E_9~0); 623552#L1190-1 assume !(0 == ~E_10~0); 623553#L1195-1 assume !(0 == ~E_11~0); 623941#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 623758#L525 assume !(1 == ~m_pc~0); 623189#L525-2 is_master_triggered_~__retres1~0#1 := 0; 623190#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 624533#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 624416#L1350 assume !(0 != activate_threads_~tmp~1#1); 623542#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 623543#L544 assume !(1 == ~t1_pc~0); 623764#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 623765#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 623163#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 623164#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 623394#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 624054#L563 assume !(1 == ~t2_pc~0); 624261#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 623211#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 623212#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 623622#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 623623#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 624141#L582 assume !(1 == ~t3_pc~0); 624276#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 624651#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 623093#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 623094#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 623276#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 623277#L601 assume !(1 == ~t4_pc~0); 624291#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 623767#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 623286#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 623287#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 624286#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 624643#L620 assume !(1 == ~t5_pc~0); 624102#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 624103#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 624161#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 624452#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 624663#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 624664#L639 assume !(1 == ~t6_pc~0); 624086#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 623663#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 623664#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 623714#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 623772#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 623773#L658 assume !(1 == ~t7_pc~0); 623992#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 623993#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 624676#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 624217#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 623545#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 623546#L677 assume !(1 == ~t8_pc~0); 623567#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 623352#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 623353#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 623618#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 623619#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 624405#L696 assume !(1 == ~t9_pc~0); 624066#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 624067#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 623826#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 623827#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 624093#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 624334#L715 assume !(1 == ~t10_pc~0); 624614#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 624196#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 623980#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 623981#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 623918#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 623346#L734 assume !(1 == ~t11_pc~0); 623347#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 623845#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 623928#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 623089#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 623090#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 624162#L1213 assume !(1 == ~M_E~0); 623915#L1213-2 assume !(1 == ~T1_E~0); 623916#L1218-1 assume !(1 == ~T2_E~0); 623124#L1223-1 assume !(1 == ~T3_E~0); 623125#L1228-1 assume !(1 == ~T4_E~0); 623888#L1233-1 assume !(1 == ~T5_E~0); 624665#L1238-1 assume !(1 == ~T6_E~0); 624284#L1243-1 assume !(1 == ~T7_E~0); 624285#L1248-1 assume !(1 == ~T8_E~0); 624340#L1253-1 assume !(1 == ~T9_E~0); 624341#L1258-1 assume !(1 == ~T10_E~0); 624311#L1263-1 assume !(1 == ~T11_E~0); 624312#L1268-1 assume !(1 == ~E_1~0); 624109#L1273-1 assume !(1 == ~E_2~0); 624110#L1278-1 assume !(1 == ~E_3~0); 623661#L1283-1 assume !(1 == ~E_4~0); 623662#L1288-1 assume !(1 == ~E_5~0); 624460#L1293-1 assume !(1 == ~E_6~0); 624411#L1298-1 assume !(1 == ~E_7~0); 624145#L1303-1 assume !(1 == ~E_8~0); 623671#L1308-1 assume !(1 == ~E_9~0); 623560#L1313-1 assume !(1 == ~E_10~0); 623561#L1318-1 assume !(1 == ~E_11~0); 623568#L1323-1 assume { :end_inline_reset_delta_events } true; 623569#L1644-2 [2023-11-23 22:38:21,737 INFO L750 eck$LassoCheckResult]: Loop: 623569#L1644-2 assume !false; 634022#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 634013#L1065-1 assume !false; 634008#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 633801#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 633783#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 633777#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 633768#L906 assume !(0 != eval_~tmp~0#1); 633769#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 635716#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 635710#L1090-3 assume !(0 == ~M_E~0); 635703#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 635696#L1095-3 assume !(0 == ~T2_E~0); 635688#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 635681#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 635674#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 635666#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 635658#L1120-3 assume !(0 == ~T7_E~0); 635649#L1125-3 assume !(0 == ~T8_E~0); 635643#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 635637#L1135-3 assume !(0 == ~T10_E~0); 635630#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 635624#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 635617#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 635611#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 635605#L1160-3 assume !(0 == ~E_4~0); 635599#L1165-3 assume !(0 == ~E_5~0); 635592#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 634810#L1175-3 assume !(0 == ~E_7~0); 634806#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 634804#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 634802#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 634800#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 634797#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 634795#L525-36 assume !(1 == ~m_pc~0); 634793#L525-38 is_master_triggered_~__retres1~0#1 := 0; 635581#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 635576#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 634784#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 634781#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 634779#L544-36 assume !(1 == ~t1_pc~0); 634776#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 634774#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 634772#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 634770#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 634768#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 634767#L563-36 assume 1 == ~t2_pc~0; 634760#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 634757#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 634755#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 634753#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 634751#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 634749#L582-36 assume !(1 == ~t3_pc~0); 634747#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 634745#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 634743#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 634741#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 634739#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 634737#L601-36 assume !(1 == ~t4_pc~0); 634734#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 634732#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 634730#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 634728#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 634726#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 634724#L620-36 assume !(1 == ~t5_pc~0); 634722#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 634720#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 634718#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 634716#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 634713#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 634711#L639-36 assume !(1 == ~t6_pc~0); 634709#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 634707#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 634704#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 634702#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 634700#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 634698#L658-36 assume !(1 == ~t7_pc~0); 634695#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 634693#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 634691#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 634689#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 634687#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 634684#L677-36 assume !(1 == ~t8_pc~0); 634682#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 634680#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 634678#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 634676#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 634674#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 634672#L696-36 assume 1 == ~t9_pc~0; 634669#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 634667#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 634665#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 634661#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 634659#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 634657#L715-36 assume !(1 == ~t10_pc~0); 634654#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 634652#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 634650#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 634648#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 634646#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 634644#L734-36 assume !(1 == ~t11_pc~0); 634641#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 634639#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 634637#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 634635#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 634633#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 634631#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 634629#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 634626#L1218-3 assume !(1 == ~T2_E~0); 634624#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 634622#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 634608#L1233-3 assume !(1 == ~T5_E~0); 634599#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 634590#L1243-3 assume !(1 == ~T7_E~0); 634580#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 634572#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 634565#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 634558#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 634554#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 634550#L1273-3 assume !(1 == ~E_2~0); 634545#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 634541#L1283-3 assume !(1 == ~E_4~0); 634536#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 634530#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 634523#L1298-3 assume !(1 == ~E_7~0); 634517#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 634510#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 634505#L1313-3 assume !(1 == ~E_10~0); 634501#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 634499#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 634395#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 634384#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 634378#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 634370#L1663 assume !(0 == start_simulation_~tmp~3#1); 634366#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 634111#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 634092#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 634081#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 634070#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 634061#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 634052#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 634043#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 623569#L1644-2 [2023-11-23 22:38:21,738 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:21,738 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 1 times [2023-11-23 22:38:21,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:21,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102606306] [2023-11-23 22:38:21,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:21,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:21,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:38:21,763 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:38:21,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:38:21,911 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:38:21,912 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:21,912 INFO L85 PathProgramCache]: Analyzing trace with hash -936814973, now seen corresponding path program 1 times [2023-11-23 22:38:21,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:21,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514735020] [2023-11-23 22:38:21,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:21,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:22,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:22,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:22,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:22,339 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514735020] [2023-11-23 22:38:22,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514735020] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:22,339 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:22,340 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:22,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1971504678] [2023-11-23 22:38:22,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:22,341 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:22,341 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:22,342 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:22,342 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:22,342 INFO L87 Difference]: Start difference. First operand 37078 states and 51461 transitions. cyclomatic complexity: 14415 Second operand has 3 states, 3 states have (on average 47.333333333333336) internal successors, (142), 3 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:22,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:22,569 INFO L93 Difference]: Finished difference Result 40755 states and 56651 transitions. [2023-11-23 22:38:22,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40755 states and 56651 transitions. [2023-11-23 22:38:22,802 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40352 [2023-11-23 22:38:22,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40755 states to 40755 states and 56651 transitions. [2023-11-23 22:38:22,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40755 [2023-11-23 22:38:22,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40755 [2023-11-23 22:38:22,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40755 states and 56651 transitions. [2023-11-23 22:38:22,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:22,991 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40755 states and 56651 transitions. [2023-11-23 22:38:23,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40755 states and 56651 transitions. [2023-11-23 22:38:23,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40755 to 40755. [2023-11-23 22:38:23,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40755 states, 40755 states have (on average 1.3900380321432952) internal successors, (56651), 40754 states have internal predecessors, (56651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:23,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40755 states to 40755 states and 56651 transitions. [2023-11-23 22:38:23,616 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40755 states and 56651 transitions. [2023-11-23 22:38:23,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:23,617 INFO L428 stractBuchiCegarLoop]: Abstraction has 40755 states and 56651 transitions. [2023-11-23 22:38:23,617 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-23 22:38:23,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40755 states and 56651 transitions. [2023-11-23 22:38:23,743 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40352 [2023-11-23 22:38:23,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:23,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:23,746 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:23,746 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:23,747 INFO L748 eck$LassoCheckResult]: Stem: 701349#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 701350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 702477#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 702478#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 701821#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 701822#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 701690#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 701578#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 701293#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 700940#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 700941#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 700985#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 700986#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 701977#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 701978#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 702027#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 701393#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 701394#L1090 assume !(0 == ~M_E~0); 701440#L1090-2 assume !(0 == ~T1_E~0); 701441#L1095-1 assume !(0 == ~T2_E~0); 702202#L1100-1 assume !(0 == ~T3_E~0); 702203#L1105-1 assume !(0 == ~T4_E~0); 701209#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 701210#L1115-1 assume !(0 == ~T6_E~0); 701620#L1120-1 assume !(0 == ~T7_E~0); 702597#L1125-1 assume !(0 == ~T8_E~0); 702598#L1130-1 assume !(0 == ~T9_E~0); 702709#L1135-1 assume !(0 == ~T10_E~0); 702708#L1140-1 assume !(0 == ~T11_E~0); 702149#L1145-1 assume !(0 == ~E_1~0); 702150#L1150-1 assume !(0 == ~E_2~0); 701596#L1155-1 assume !(0 == ~E_3~0); 701597#L1160-1 assume !(0 == ~E_4~0); 702707#L1165-1 assume !(0 == ~E_5~0); 702454#L1170-1 assume !(0 == ~E_6~0); 702455#L1175-1 assume !(0 == ~E_7~0); 702706#L1180-1 assume !(0 == ~E_8~0); 702704#L1185-1 assume !(0 == ~E_9~0); 702703#L1190-1 assume !(0 == ~E_10~0); 702702#L1195-1 assume !(0 == ~E_11~0); 702421#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 702422#L525 assume !(1 == ~m_pc~0); 702700#L525-2 is_master_triggered_~__retres1~0#1 := 0; 702698#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 702696#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 702694#L1350 assume !(0 != activate_threads_~tmp~1#1); 702693#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 701847#L544 assume !(1 == ~t1_pc~0); 701848#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 702145#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 702146#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 701235#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 701236#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 702692#L563 assume !(1 == ~t2_pc~0); 702691#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 701049#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 701050#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 701469#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 701470#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 702689#L582 assume !(1 == ~t3_pc~0); 702593#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 702594#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 702688#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 702465#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 701115#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 701116#L601 assume !(1 == ~t4_pc~0); 702685#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 702684#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 702683#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 702682#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 702620#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 702621#L620 assume !(1 == ~t5_pc~0); 701966#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 701967#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 702681#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 702680#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 702553#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 702554#L639 assume !(1 == ~t6_pc~0); 701942#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 701943#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 701562#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 701563#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 702679#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 702678#L658 assume !(1 == ~t7_pc~0); 701844#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 701845#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 702611#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 702612#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 702676#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 702675#L677 assume !(1 == ~t8_pc~0); 702674#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 701192#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 701193#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 702246#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 702672#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 702671#L696 assume !(1 == ~t9_pc~0); 701921#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 701922#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 702705#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 701953#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 701954#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 702207#L715 assume !(1 == ~t10_pc~0); 702577#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 702578#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 702663#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 702662#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 702661#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 701186#L734 assume !(1 == ~t11_pc~0); 701187#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 701698#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 701783#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 700928#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 700929#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 702025#L1213 assume !(1 == ~M_E~0); 701769#L1213-2 assume !(1 == ~T1_E~0); 701770#L1218-1 assume !(1 == ~T2_E~0); 700963#L1223-1 assume !(1 == ~T3_E~0); 700964#L1228-1 assume !(1 == ~T4_E~0); 701741#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 702555#L1238-1 assume !(1 == ~T6_E~0); 702158#L1243-1 assume !(1 == ~T7_E~0); 702159#L1248-1 assume !(1 == ~T8_E~0); 702213#L1253-1 assume !(1 == ~T9_E~0); 702214#L1258-1 assume !(1 == ~T10_E~0); 702183#L1263-1 assume !(1 == ~T11_E~0); 702184#L1268-1 assume !(1 == ~E_1~0); 701974#L1273-1 assume !(1 == ~E_2~0); 701975#L1278-1 assume !(1 == ~E_3~0); 701509#L1283-1 assume !(1 == ~E_4~0); 701510#L1288-1 assume !(1 == ~E_5~0); 702332#L1293-1 assume !(1 == ~E_6~0); 702282#L1298-1 assume !(1 == ~E_7~0); 702008#L1303-1 assume !(1 == ~E_8~0); 701519#L1308-1 assume !(1 == ~E_9~0); 701403#L1313-1 assume !(1 == ~E_10~0); 701404#L1318-1 assume !(1 == ~E_11~0); 701412#L1323-1 assume { :end_inline_reset_delta_events } true; 701413#L1644-2 [2023-11-23 22:38:23,748 INFO L750 eck$LassoCheckResult]: Loop: 701413#L1644-2 assume !false; 720448#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 720444#L1065-1 assume !false; 720442#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 720430#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 720419#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 720417#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 720413#L906 assume !(0 != eval_~tmp~0#1); 720414#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 720908#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 720907#L1090-3 assume !(0 == ~M_E~0); 720906#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 720904#L1095-3 assume !(0 == ~T2_E~0); 720903#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 720902#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 720901#L1110-3 assume !(0 == ~T5_E~0); 720899#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 720897#L1120-3 assume !(0 == ~T7_E~0); 720895#L1125-3 assume !(0 == ~T8_E~0); 720893#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 720891#L1135-3 assume !(0 == ~T10_E~0); 720889#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 720887#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 720885#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 720883#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 720881#L1160-3 assume !(0 == ~E_4~0); 720879#L1165-3 assume !(0 == ~E_5~0); 720877#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 720875#L1175-3 assume !(0 == ~E_7~0); 720873#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 720871#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 720869#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 720867#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 720865#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 720861#L525-36 assume 1 == ~m_pc~0; 720859#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 720860#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 720909#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 720849#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 720847#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 720845#L544-36 assume !(1 == ~t1_pc~0); 720843#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 720841#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 720839#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 720837#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 720835#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 720833#L563-36 assume 1 == ~t2_pc~0; 720830#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 720827#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 720825#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 720823#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 720821#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 720819#L582-36 assume !(1 == ~t3_pc~0); 720817#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 720815#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 720813#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 720811#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 720809#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 720806#L601-36 assume !(1 == ~t4_pc~0); 720803#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 720801#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 720799#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 720797#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 720795#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 720793#L620-36 assume !(1 == ~t5_pc~0); 720791#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 720789#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 720787#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 720785#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 720783#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 720781#L639-36 assume !(1 == ~t6_pc~0); 720778#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 720775#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 720773#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 720771#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 720769#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 720766#L658-36 assume !(1 == ~t7_pc~0); 720763#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 720761#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 720759#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 720757#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 720755#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 720753#L677-36 assume !(1 == ~t8_pc~0); 720751#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 720749#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 720747#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 720745#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 720743#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 720740#L696-36 assume !(1 == ~t9_pc~0); 720736#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 720734#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 720732#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 720730#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 720726#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 720724#L715-36 assume !(1 == ~t10_pc~0); 720722#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 720720#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 720718#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 720716#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 720714#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 720712#L734-36 assume 1 == ~t11_pc~0; 720710#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 720706#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 720704#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 720702#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 720700#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 720698#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 720696#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 720694#L1218-3 assume !(1 == ~T2_E~0); 720692#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 720690#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 720687#L1233-3 assume !(1 == ~T5_E~0); 720686#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 720685#L1243-3 assume !(1 == ~T7_E~0); 720681#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 720679#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 720677#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 720675#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 720672#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 720670#L1273-3 assume !(1 == ~E_2~0); 720668#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 720666#L1283-3 assume !(1 == ~E_4~0); 720664#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 720662#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 720660#L1298-3 assume !(1 == ~E_7~0); 720658#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 720656#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 720653#L1313-3 assume !(1 == ~E_10~0); 720651#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 720649#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 720634#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 720626#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 720624#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 720485#L1663 assume !(0 == start_simulation_~tmp~3#1); 720483#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 720473#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 720462#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 720459#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 720457#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 720455#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 720453#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 720451#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 701413#L1644-2 [2023-11-23 22:38:23,748 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:23,749 INFO L85 PathProgramCache]: Analyzing trace with hash 1527023766, now seen corresponding path program 1 times [2023-11-23 22:38:23,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:23,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205079943] [2023-11-23 22:38:23,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:23,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:23,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:23,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:23,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:23,815 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205079943] [2023-11-23 22:38:23,815 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205079943] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:23,815 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:23,815 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:38:23,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834158540] [2023-11-23 22:38:23,816 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:23,816 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:23,817 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:23,817 INFO L85 PathProgramCache]: Analyzing trace with hash -536620826, now seen corresponding path program 1 times [2023-11-23 22:38:23,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:23,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600060208] [2023-11-23 22:38:23,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:23,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:23,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:23,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:23,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:23,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600060208] [2023-11-23 22:38:23,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600060208] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:23,887 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:23,887 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:23,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967325611] [2023-11-23 22:38:23,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:23,888 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:23,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:23,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:23,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:23,889 INFO L87 Difference]: Start difference. First operand 40755 states and 56651 transitions. cyclomatic complexity: 15928 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:24,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:24,087 INFO L93 Difference]: Finished difference Result 37078 states and 51363 transitions. [2023-11-23 22:38:24,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37078 states and 51363 transitions. [2023-11-23 22:38:24,589 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-23 22:38:24,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37078 states to 37078 states and 51363 transitions. [2023-11-23 22:38:24,681 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37078 [2023-11-23 22:38:24,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37078 [2023-11-23 22:38:24,702 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37078 states and 51363 transitions. [2023-11-23 22:38:24,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:24,722 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51363 transitions. [2023-11-23 22:38:24,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37078 states and 51363 transitions. [2023-11-23 22:38:25,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37078 to 37078. [2023-11-23 22:38:25,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.3852688926047791) internal successors, (51363), 37077 states have internal predecessors, (51363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:25,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 51363 transitions. [2023-11-23 22:38:25,144 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51363 transitions. [2023-11-23 22:38:25,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:25,145 INFO L428 stractBuchiCegarLoop]: Abstraction has 37078 states and 51363 transitions. [2023-11-23 22:38:25,145 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-23 22:38:25,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 51363 transitions. [2023-11-23 22:38:25,261 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-23 22:38:25,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:25,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:25,264 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:25,264 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:25,265 INFO L748 eck$LassoCheckResult]: Stem: 779193#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 779194#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 780253#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 780254#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 779649#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 779650#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 779521#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 779417#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 779135#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 778780#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 778781#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 778825#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 778826#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 779793#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 779794#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 779839#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 779236#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 779237#L1090 assume !(0 == ~M_E~0); 779282#L1090-2 assume !(0 == ~T1_E~0); 779283#L1095-1 assume !(0 == ~T2_E~0); 780002#L1100-1 assume !(0 == ~T3_E~0); 780003#L1105-1 assume !(0 == ~T4_E~0); 779049#L1110-1 assume !(0 == ~T5_E~0); 779050#L1115-1 assume !(0 == ~T6_E~0); 779451#L1120-1 assume !(0 == ~T7_E~0); 779769#L1125-1 assume !(0 == ~T8_E~0); 780364#L1130-1 assume !(0 == ~T9_E~0); 780025#L1135-1 assume !(0 == ~T10_E~0); 779242#L1140-1 assume !(0 == ~T11_E~0); 779243#L1145-1 assume !(0 == ~E_1~0); 779953#L1150-1 assume !(0 == ~E_2~0); 779430#L1155-1 assume !(0 == ~E_3~0); 779431#L1160-1 assume !(0 == ~E_4~0); 779526#L1165-1 assume !(0 == ~E_5~0); 779527#L1170-1 assume !(0 == ~E_6~0); 780230#L1175-1 assume !(0 == ~E_7~0); 779608#L1180-1 assume !(0 == ~E_8~0); 779609#L1185-1 assume !(0 == ~E_9~0); 779238#L1190-1 assume !(0 == ~E_10~0); 779239#L1195-1 assume !(0 == ~E_11~0); 779624#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 779443#L525 assume !(1 == ~m_pc~0); 778869#L525-2 is_master_triggered_~__retres1~0#1 := 0; 778870#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 780194#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 780080#L1350 assume !(0 != activate_threads_~tmp~1#1); 779228#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 779229#L544 assume !(1 == ~t1_pc~0); 779449#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 779450#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 778843#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 778844#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 779076#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 779736#L563 assume !(1 == ~t2_pc~0); 779937#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 778891#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 778892#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 779309#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 779310#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 779819#L582 assume !(1 == ~t3_pc~0); 779952#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 780318#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 778772#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 778773#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 778957#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 778958#L601 assume !(1 == ~t4_pc~0); 779967#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 779452#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 778967#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 778968#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 779962#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 780307#L620 assume !(1 == ~t5_pc~0); 779783#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 779784#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 779836#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 780116#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 780327#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 780328#L639 assume !(1 == ~t6_pc~0); 779767#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 779348#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 779349#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 779401#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 779457#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 779458#L658 assume !(1 == ~t7_pc~0); 779675#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 779676#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 780334#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 779889#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 779231#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 779232#L677 assume !(1 == ~t8_pc~0); 779253#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 779032#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 779033#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 779305#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 779306#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 780070#L696 assume !(1 == ~t9_pc~0); 779748#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 779749#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 779511#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 779512#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 779774#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 780007#L715 assume !(1 == ~t10_pc~0); 780276#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 779869#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 779664#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 779665#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 779601#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 779026#L734 assume !(1 == ~t11_pc~0); 779027#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 779528#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 779611#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 778768#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 778769#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 779837#L1213 assume !(1 == ~M_E~0); 779598#L1213-2 assume !(1 == ~T1_E~0); 779599#L1218-1 assume !(1 == ~T2_E~0); 778803#L1223-1 assume !(1 == ~T3_E~0); 778804#L1228-1 assume !(1 == ~T4_E~0); 779573#L1233-1 assume !(1 == ~T5_E~0); 780329#L1238-1 assume !(1 == ~T6_E~0); 779960#L1243-1 assume !(1 == ~T7_E~0); 779961#L1248-1 assume !(1 == ~T8_E~0); 780013#L1253-1 assume !(1 == ~T9_E~0); 780014#L1258-1 assume !(1 == ~T10_E~0); 779984#L1263-1 assume !(1 == ~T11_E~0); 779985#L1268-1 assume !(1 == ~E_1~0); 779790#L1273-1 assume !(1 == ~E_2~0); 779791#L1278-1 assume !(1 == ~E_3~0); 779346#L1283-1 assume !(1 == ~E_4~0); 779347#L1288-1 assume !(1 == ~E_5~0); 780123#L1293-1 assume !(1 == ~E_6~0); 780075#L1298-1 assume !(1 == ~E_7~0); 779823#L1303-1 assume !(1 == ~E_8~0); 779356#L1308-1 assume !(1 == ~E_9~0); 779246#L1313-1 assume !(1 == ~E_10~0); 779247#L1318-1 assume !(1 == ~E_11~0); 779254#L1323-1 assume { :end_inline_reset_delta_events } true; 779255#L1644-2 [2023-11-23 22:38:25,266 INFO L750 eck$LassoCheckResult]: Loop: 779255#L1644-2 assume !false; 793526#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 793520#L1065-1 assume !false; 793518#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 793503#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 793492#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 793490#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 793486#L906 assume !(0 != eval_~tmp~0#1); 793487#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 793976#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 793974#L1090-3 assume !(0 == ~M_E~0); 793972#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 793970#L1095-3 assume !(0 == ~T2_E~0); 793968#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 793966#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 793964#L1110-3 assume !(0 == ~T5_E~0); 793962#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 793960#L1120-3 assume !(0 == ~T7_E~0); 793958#L1125-3 assume !(0 == ~T8_E~0); 793956#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 793954#L1135-3 assume !(0 == ~T10_E~0); 793950#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 793948#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 793946#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 793944#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 793941#L1160-3 assume !(0 == ~E_4~0); 793939#L1165-3 assume !(0 == ~E_5~0); 793937#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 793935#L1175-3 assume !(0 == ~E_7~0); 793933#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 793931#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 793929#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 793927#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 793925#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 793922#L525-36 assume !(1 == ~m_pc~0); 793918#L525-38 is_master_triggered_~__retres1~0#1 := 0; 793916#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 793914#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 793912#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 793910#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 793906#L544-36 assume !(1 == ~t1_pc~0); 793904#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 793902#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 793899#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 793898#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 793897#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 793894#L563-36 assume !(1 == ~t2_pc~0); 793889#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 793888#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 793887#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 793886#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 793885#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 793884#L582-36 assume !(1 == ~t3_pc~0); 793883#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 793882#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 793881#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 793880#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 793879#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 793878#L601-36 assume !(1 == ~t4_pc~0); 793876#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 793875#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 793874#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 793873#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 793872#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 793871#L620-36 assume !(1 == ~t5_pc~0); 793870#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 793869#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 793868#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 793867#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 793866#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 793865#L639-36 assume !(1 == ~t6_pc~0); 793864#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 793862#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 793860#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 793859#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 793858#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 793857#L658-36 assume !(1 == ~t7_pc~0); 793854#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 793853#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 793852#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 793851#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 793849#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 793847#L677-36 assume !(1 == ~t8_pc~0); 793843#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 793841#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 793839#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 793837#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 793834#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 793827#L696-36 assume 1 == ~t9_pc~0; 793828#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 793829#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 793861#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 793818#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 793816#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 793813#L715-36 assume !(1 == ~t10_pc~0); 793811#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 793809#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 793807#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 793805#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 793803#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 793800#L734-36 assume !(1 == ~t11_pc~0); 793797#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 793795#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 793793#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 793791#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 793788#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 793786#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 793784#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 793782#L1218-3 assume !(1 == ~T2_E~0); 793780#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 793778#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 793776#L1233-3 assume !(1 == ~T5_E~0); 793773#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 793771#L1243-3 assume !(1 == ~T7_E~0); 793769#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 793767#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 793765#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 793763#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 793760#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 793758#L1273-3 assume !(1 == ~E_2~0); 793756#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 793754#L1283-3 assume !(1 == ~E_4~0); 793752#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 793749#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 793747#L1298-3 assume !(1 == ~E_7~0); 793745#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 793743#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 793741#L1313-3 assume !(1 == ~E_10~0); 793739#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 793737#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 793712#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 793705#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 793703#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 793561#L1663 assume !(0 == start_simulation_~tmp~3#1); 793559#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 793551#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 793540#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 793537#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 793535#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 793533#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 793531#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 793529#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 779255#L1644-2 [2023-11-23 22:38:25,266 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:25,266 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 2 times [2023-11-23 22:38:25,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:25,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964444677] [2023-11-23 22:38:25,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:25,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:25,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:38:25,284 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:38:25,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:38:25,375 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:38:25,376 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:25,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1015724124, now seen corresponding path program 1 times [2023-11-23 22:38:25,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:25,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046943616] [2023-11-23 22:38:25,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:25,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:25,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:25,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:25,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:25,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046943616] [2023-11-23 22:38:25,432 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046943616] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:25,432 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:25,432 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:25,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108526729] [2023-11-23 22:38:25,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:25,433 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:25,433 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:25,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:25,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:25,434 INFO L87 Difference]: Start difference. First operand 37078 states and 51363 transitions. cyclomatic complexity: 14317 Second operand has 3 states, 3 states have (on average 47.333333333333336) internal successors, (142), 3 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:25,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:25,776 INFO L93 Difference]: Finished difference Result 70243 states and 96408 transitions. [2023-11-23 22:38:25,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70243 states and 96408 transitions. [2023-11-23 22:38:26,522 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 69696 [2023-11-23 22:38:26,658 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70243 states to 70243 states and 96408 transitions. [2023-11-23 22:38:26,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70243 [2023-11-23 22:38:26,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70243 [2023-11-23 22:38:26,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70243 states and 96408 transitions. [2023-11-23 22:38:26,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:26,716 INFO L218 hiAutomatonCegarLoop]: Abstraction has 70243 states and 96408 transitions. [2023-11-23 22:38:26,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70243 states and 96408 transitions. [2023-11-23 22:38:27,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70243 to 70227. [2023-11-23 22:38:27,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70227 states, 70227 states have (on average 1.3725774986828427) internal successors, (96392), 70226 states have internal predecessors, (96392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:27,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70227 states to 70227 states and 96392 transitions. [2023-11-23 22:38:27,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 70227 states and 96392 transitions. [2023-11-23 22:38:27,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:27,359 INFO L428 stractBuchiCegarLoop]: Abstraction has 70227 states and 96392 transitions. [2023-11-23 22:38:27,359 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-23 22:38:27,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70227 states and 96392 transitions. [2023-11-23 22:38:27,915 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 69680 [2023-11-23 22:38:27,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:27,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:27,918 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:27,918 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:27,919 INFO L748 eck$LassoCheckResult]: Stem: 886512#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 886513#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 887591#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 887592#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 886973#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 886974#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 886843#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 886734#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 886456#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 886107#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 886108#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 886151#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 886152#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 887119#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 887120#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 887168#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 886554#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 886555#L1090 assume !(0 == ~M_E~0); 886599#L1090-2 assume !(0 == ~T1_E~0); 886600#L1095-1 assume !(0 == ~T2_E~0); 887333#L1100-1 assume !(0 == ~T3_E~0); 887334#L1105-1 assume !(0 == ~T4_E~0); 886374#L1110-1 assume !(0 == ~T5_E~0); 886375#L1115-1 assume !(0 == ~T6_E~0); 886772#L1120-1 assume !(0 == ~T7_E~0); 887092#L1125-1 assume !(0 == ~T8_E~0); 887705#L1130-1 assume !(0 == ~T9_E~0); 887353#L1135-1 assume !(0 == ~T10_E~0); 886560#L1140-1 assume !(0 == ~T11_E~0); 886561#L1145-1 assume !(0 == ~E_1~0); 887285#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 887327#L1155-1 assume !(0 == ~E_3~0); 887699#L1160-1 assume !(0 == ~E_4~0); 886850#L1165-1 assume !(0 == ~E_5~0); 886851#L1170-1 assume !(0 == ~E_6~0); 887672#L1175-1 assume !(0 == ~E_7~0); 886930#L1180-1 assume !(0 == ~E_8~0); 886931#L1185-1 assume !(0 == ~E_9~0); 886556#L1190-1 assume !(0 == ~E_10~0); 886557#L1195-1 assume !(0 == ~E_11~0); 886946#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 886764#L525 assume !(1 == ~m_pc~0); 886197#L525-2 is_master_triggered_~__retres1~0#1 := 0; 886198#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 887444#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 887412#L1350 assume !(0 != activate_threads_~tmp~1#1); 886546#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 886547#L544 assume !(1 == ~t1_pc~0); 887809#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 887808#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 886170#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 886171#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 887055#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 887056#L563 assume !(1 == ~t2_pc~0); 887268#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 887269#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 887802#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 886628#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 886629#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 887801#L582 assume !(1 == ~t3_pc~0); 887706#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 887707#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 887800#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 887580#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 886282#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 886283#L601 assume !(1 == ~t4_pc~0); 887797#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 887796#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 887795#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 887794#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 887729#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 887730#L620 assume !(1 == ~t5_pc~0); 887108#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 887109#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 887793#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 887792#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 887668#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 887669#L639 assume !(1 == ~t6_pc~0); 887088#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 887089#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 886719#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 886720#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 887791#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 887790#L658 assume !(1 == ~t7_pc~0); 886997#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 886998#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 887720#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 887721#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 887788#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 887787#L677 assume !(1 == ~t8_pc~0); 886571#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 886572#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 887786#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 886623#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 886624#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 887403#L696 assume !(1 == ~t9_pc~0); 887503#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 887782#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 887780#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 887778#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 887777#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 887776#L715 assume !(1 == ~t10_pc~0); 887690#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 887691#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 886985#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 886986#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 886924#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 886352#L734 assume !(1 == ~t11_pc~0); 886353#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 886852#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 886933#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 886095#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 886096#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 887166#L1213 assume !(1 == ~M_E~0); 886921#L1213-2 assume !(1 == ~T1_E~0); 886922#L1218-1 assume !(1 == ~T2_E~0); 886130#L1223-1 assume !(1 == ~T3_E~0); 886131#L1228-1 assume !(1 == ~T4_E~0); 886896#L1233-1 assume !(1 == ~T5_E~0); 887670#L1238-1 assume !(1 == ~T6_E~0); 887291#L1243-1 assume !(1 == ~T7_E~0); 887292#L1248-1 assume !(1 == ~T8_E~0); 887341#L1253-1 assume !(1 == ~T9_E~0); 887342#L1258-1 assume !(1 == ~T10_E~0); 887315#L1263-1 assume !(1 == ~T11_E~0); 887316#L1268-1 assume !(1 == ~E_1~0); 887116#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 887117#L1278-1 assume !(1 == ~E_3~0); 886665#L1283-1 assume !(1 == ~E_4~0); 886666#L1288-1 assume !(1 == ~E_5~0); 887457#L1293-1 assume !(1 == ~E_6~0); 887409#L1298-1 assume !(1 == ~E_7~0); 887150#L1303-1 assume !(1 == ~E_8~0); 886675#L1308-1 assume !(1 == ~E_9~0); 886564#L1313-1 assume !(1 == ~E_10~0); 886565#L1318-1 assume !(1 == ~E_11~0); 886573#L1323-1 assume { :end_inline_reset_delta_events } true; 886574#L1644-2 [2023-11-23 22:38:27,919 INFO L750 eck$LassoCheckResult]: Loop: 886574#L1644-2 assume !false; 906339#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 906334#L1065-1 assume !false; 906331#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 906320#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 906309#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 906306#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 906304#L906 assume !(0 != eval_~tmp~0#1); 906305#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 906889#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 906888#L1090-3 assume !(0 == ~M_E~0); 906886#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 906884#L1095-3 assume !(0 == ~T2_E~0); 906882#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 906880#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 906878#L1110-3 assume !(0 == ~T5_E~0); 906876#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 906874#L1120-3 assume !(0 == ~T7_E~0); 906872#L1125-3 assume !(0 == ~T8_E~0); 906870#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 906868#L1135-3 assume !(0 == ~T10_E~0); 906865#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 906863#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 906856#L1150-3 assume !(0 == ~E_2~0); 906857#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 906887#L1160-3 assume !(0 == ~E_4~0); 906885#L1165-3 assume !(0 == ~E_5~0); 906883#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 906881#L1175-3 assume !(0 == ~E_7~0); 906879#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 906877#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 906875#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 906873#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 906871#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 906869#L525-36 assume !(1 == ~m_pc~0); 906867#L525-38 is_master_triggered_~__retres1~0#1 := 0; 914065#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 911210#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 906860#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 906855#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 906853#L544-36 assume !(1 == ~t1_pc~0); 906851#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 906849#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 906847#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 906845#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 906843#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 906839#L563-36 assume 1 == ~t2_pc~0; 906840#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 906800#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 906798#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 906796#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 906794#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 906792#L582-36 assume !(1 == ~t3_pc~0); 906790#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 906788#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 906786#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 906783#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 906781#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 906779#L601-36 assume !(1 == ~t4_pc~0); 906776#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 906774#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 906771#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 906769#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 906767#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 906765#L620-36 assume !(1 == ~t5_pc~0); 906763#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 906761#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 906759#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 906757#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 906755#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 906753#L639-36 assume !(1 == ~t6_pc~0); 906751#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 906748#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 906747#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 906743#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 906741#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 906739#L658-36 assume !(1 == ~t7_pc~0); 906736#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 906733#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 906731#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 906729#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 906727#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 906725#L677-36 assume !(1 == ~t8_pc~0); 906723#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 906721#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 906719#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 906717#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 906714#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 906709#L696-36 assume 1 == ~t9_pc~0; 906710#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 906711#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 906892#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 906700#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 906698#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 906696#L715-36 assume !(1 == ~t10_pc~0); 906694#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 906692#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 906690#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 906688#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 906686#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 906684#L734-36 assume !(1 == ~t11_pc~0); 906681#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 906679#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 906677#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 906676#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 906675#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 906673#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 906672#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 906671#L1218-3 assume !(1 == ~T2_E~0); 906670#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 906666#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 906664#L1233-3 assume !(1 == ~T5_E~0); 906662#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 906660#L1243-3 assume !(1 == ~T7_E~0); 906657#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 906655#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 906653#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 906651#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 906649#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 906647#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 906644#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 906642#L1283-3 assume !(1 == ~E_4~0); 906640#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 906637#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 906635#L1298-3 assume !(1 == ~E_7~0); 906633#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 906631#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 906629#L1313-3 assume !(1 == ~E_10~0); 906627#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 906625#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 906608#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 906601#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 906599#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 906385#L1663 assume !(0 == start_simulation_~tmp~3#1); 906383#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 906364#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 906352#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 906350#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 906348#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 906346#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 906344#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 906342#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 886574#L1644-2 [2023-11-23 22:38:27,920 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:27,920 INFO L85 PathProgramCache]: Analyzing trace with hash -1087159146, now seen corresponding path program 1 times [2023-11-23 22:38:27,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:27,921 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683177217] [2023-11-23 22:38:27,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:27,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:27,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:27,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:27,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:27,987 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683177217] [2023-11-23 22:38:27,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683177217] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:27,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:27,988 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-23 22:38:27,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816273014] [2023-11-23 22:38:27,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:27,988 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-23 22:38:27,989 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:27,989 INFO L85 PathProgramCache]: Analyzing trace with hash -848054523, now seen corresponding path program 1 times [2023-11-23 22:38:27,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:27,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930105161] [2023-11-23 22:38:27,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:27,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:28,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:28,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:28,058 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:28,058 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930105161] [2023-11-23 22:38:28,059 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930105161] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:28,059 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:28,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:28,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442945420] [2023-11-23 22:38:28,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:28,060 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:28,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:28,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:28,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:28,061 INFO L87 Difference]: Start difference. First operand 70227 states and 96392 transitions. cyclomatic complexity: 26197 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:28,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:28,238 INFO L93 Difference]: Finished difference Result 37078 states and 50928 transitions. [2023-11-23 22:38:28,238 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37078 states and 50928 transitions. [2023-11-23 22:38:28,368 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-23 22:38:28,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37078 states to 37078 states and 50928 transitions. [2023-11-23 22:38:28,451 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37078 [2023-11-23 22:38:28,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37078 [2023-11-23 22:38:28,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37078 states and 50928 transitions. [2023-11-23 22:38:28,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:28,489 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37078 states and 50928 transitions. [2023-11-23 22:38:28,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37078 states and 50928 transitions. [2023-11-23 22:38:28,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37078 to 37078. [2023-11-23 22:38:28,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.3735368682237445) internal successors, (50928), 37077 states have internal predecessors, (50928), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:28,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 50928 transitions. [2023-11-23 22:38:28,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 50928 transitions. [2023-11-23 22:38:28,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-23 22:38:28,842 INFO L428 stractBuchiCegarLoop]: Abstraction has 37078 states and 50928 transitions. [2023-11-23 22:38:28,842 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-23 22:38:28,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 50928 transitions. [2023-11-23 22:38:28,954 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-23 22:38:28,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-23 22:38:28,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-23 22:38:28,956 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:28,956 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-23 22:38:28,957 INFO L748 eck$LassoCheckResult]: Stem: 993825#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 993826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 994888#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 994889#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 994282#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 994283#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 994151#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 994046#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 993768#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 993419#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 993420#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 993463#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 993464#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 994423#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 994424#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 994471#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 993868#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 993869#L1090 assume !(0 == ~M_E~0); 993913#L1090-2 assume !(0 == ~T1_E~0); 993914#L1095-1 assume !(0 == ~T2_E~0); 994631#L1100-1 assume !(0 == ~T3_E~0); 994632#L1105-1 assume !(0 == ~T4_E~0); 993687#L1110-1 assume !(0 == ~T5_E~0); 993688#L1115-1 assume !(0 == ~T6_E~0); 994081#L1120-1 assume !(0 == ~T7_E~0); 994397#L1125-1 assume !(0 == ~T8_E~0); 995010#L1130-1 assume !(0 == ~T9_E~0); 994651#L1135-1 assume !(0 == ~T10_E~0); 993874#L1140-1 assume !(0 == ~T11_E~0); 993875#L1145-1 assume !(0 == ~E_1~0); 994581#L1150-1 assume !(0 == ~E_2~0); 994060#L1155-1 assume !(0 == ~E_3~0); 994061#L1160-1 assume !(0 == ~E_4~0); 994156#L1165-1 assume !(0 == ~E_5~0); 994157#L1170-1 assume !(0 == ~E_6~0); 994868#L1175-1 assume !(0 == ~E_7~0); 994237#L1180-1 assume !(0 == ~E_8~0); 994238#L1185-1 assume !(0 == ~E_9~0); 993870#L1190-1 assume !(0 == ~E_10~0); 993871#L1195-1 assume !(0 == ~E_11~0); 994253#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 994078#L525 assume !(1 == ~m_pc~0); 993506#L525-2 is_master_triggered_~__retres1~0#1 := 0; 993507#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 994832#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 994711#L1350 assume !(0 != activate_threads_~tmp~1#1); 993860#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 993861#L544 assume !(1 == ~t1_pc~0); 994079#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 994080#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 993486#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 993487#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 993710#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 994365#L563 assume !(1 == ~t2_pc~0); 994566#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 993528#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 993529#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 993940#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 993941#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 994449#L582 assume !(1 == ~t3_pc~0); 994580#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 994953#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 993411#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 993412#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 993593#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 993594#L601 assume !(1 == ~t4_pc~0); 994596#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 994082#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 993607#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 993608#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 994590#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 994943#L620 assume !(1 == ~t5_pc~0); 994412#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 994413#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 994468#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 994753#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 994966#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 994967#L639 assume !(1 == ~t6_pc~0); 994396#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 993981#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 993982#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 994031#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 994087#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 994088#L658 assume !(1 == ~t7_pc~0); 994309#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 994310#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 994980#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 994521#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 993863#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 993864#L677 assume !(1 == ~t8_pc~0); 993887#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 993670#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 993671#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 993936#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 993937#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 994702#L696 assume !(1 == ~t9_pc~0); 994379#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 994380#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 994141#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 994142#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 994402#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 994635#L715 assume !(1 == ~t10_pc~0); 994909#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 994502#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 994296#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 994297#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 994230#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 993664#L734 assume !(1 == ~t11_pc~0); 993665#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 994158#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 994240#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 993409#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 993410#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 994469#L1213 assume !(1 == ~M_E~0); 994228#L1213-2 assume !(1 == ~T1_E~0); 994229#L1218-1 assume !(1 == ~T2_E~0); 993442#L1223-1 assume !(1 == ~T3_E~0); 993443#L1228-1 assume !(1 == ~T4_E~0); 994204#L1233-1 assume !(1 == ~T5_E~0); 994968#L1238-1 assume !(1 == ~T6_E~0); 994588#L1243-1 assume !(1 == ~T7_E~0); 994589#L1248-1 assume !(1 == ~T8_E~0); 994638#L1253-1 assume !(1 == ~T9_E~0); 994639#L1258-1 assume !(1 == ~T10_E~0); 994614#L1263-1 assume !(1 == ~T11_E~0); 994615#L1268-1 assume !(1 == ~E_1~0); 994420#L1273-1 assume !(1 == ~E_2~0); 994421#L1278-1 assume !(1 == ~E_3~0); 993977#L1283-1 assume !(1 == ~E_4~0); 993978#L1288-1 assume !(1 == ~E_5~0); 994757#L1293-1 assume !(1 == ~E_6~0); 994706#L1298-1 assume !(1 == ~E_7~0); 994453#L1303-1 assume !(1 == ~E_8~0); 993987#L1308-1 assume !(1 == ~E_9~0); 993878#L1313-1 assume !(1 == ~E_10~0); 993879#L1318-1 assume !(1 == ~E_11~0); 993888#L1323-1 assume { :end_inline_reset_delta_events } true; 993889#L1644-2 [2023-11-23 22:38:28,957 INFO L750 eck$LassoCheckResult]: Loop: 993889#L1644-2 assume !false; 1006555#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1006550#L1065-1 assume !false; 1006548#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1006540#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1006529#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1006520#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1006513#L906 assume !(0 != eval_~tmp~0#1); 1006514#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1006962#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1006960#L1090-3 assume !(0 == ~M_E~0); 1006958#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1006956#L1095-3 assume !(0 == ~T2_E~0); 1006954#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1006951#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1006949#L1110-3 assume !(0 == ~T5_E~0); 1006947#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1006945#L1120-3 assume !(0 == ~T7_E~0); 1006943#L1125-3 assume !(0 == ~T8_E~0); 1006941#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1006939#L1135-3 assume !(0 == ~T10_E~0); 1006937#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1006935#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1006933#L1150-3 assume !(0 == ~E_2~0); 1006931#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1006929#L1160-3 assume !(0 == ~E_4~0); 1006927#L1165-3 assume !(0 == ~E_5~0); 1006924#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1006922#L1175-3 assume !(0 == ~E_7~0); 1006920#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1006918#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1006916#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1006913#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1006911#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1006909#L525-36 assume 1 == ~m_pc~0; 1006907#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1006908#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006970#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1006898#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1006896#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1006894#L544-36 assume !(1 == ~t1_pc~0); 1006892#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1006890#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1006888#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1006884#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1006882#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1006878#L563-36 assume !(1 == ~t2_pc~0); 1006875#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1006873#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1006871#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1006869#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1006867#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1006865#L582-36 assume !(1 == ~t3_pc~0); 1006863#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1006861#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1006859#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1006856#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1006854#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1006852#L601-36 assume !(1 == ~t4_pc~0); 1006849#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1006847#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1006846#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1006842#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1006840#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1006838#L620-36 assume !(1 == ~t5_pc~0); 1006835#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1006834#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1006833#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1006830#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1006826#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1006825#L639-36 assume !(1 == ~t6_pc~0); 1006824#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1006822#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1006821#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1006820#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1006819#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1006818#L658-36 assume !(1 == ~t7_pc~0); 1006816#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1006815#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1006814#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1006813#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1006812#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1006811#L677-36 assume !(1 == ~t8_pc~0); 1006810#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1006809#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1006808#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1006807#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1006806#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1006804#L696-36 assume 1 == ~t9_pc~0; 1006805#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1006803#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1006801#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1006797#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1006795#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1006794#L715-36 assume !(1 == ~t10_pc~0); 1006793#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1006792#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1006788#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1006786#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1006784#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1006782#L734-36 assume 1 == ~t11_pc~0; 1006779#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1006776#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1006774#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1006772#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1006770#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1006768#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1006766#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1006764#L1218-3 assume !(1 == ~T2_E~0); 1006761#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1006759#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1006757#L1233-3 assume !(1 == ~T5_E~0); 1006755#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1006753#L1243-3 assume !(1 == ~T7_E~0); 1006751#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1006749#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1006747#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1006745#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1006743#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1006741#L1273-3 assume !(1 == ~E_2~0); 1006739#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1006736#L1283-3 assume !(1 == ~E_4~0); 1006734#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1006732#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1006730#L1298-3 assume !(1 == ~E_7~0); 1006728#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1006726#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1006724#L1313-3 assume !(1 == ~E_10~0); 1006722#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1006720#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1006701#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1006694#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1006692#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1006591#L1663 assume !(0 == start_simulation_~tmp~3#1); 1006588#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1006579#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1006568#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1006566#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1006564#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1006562#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1006560#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1006558#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 993889#L1644-2 [2023-11-23 22:38:28,958 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:28,958 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 3 times [2023-11-23 22:38:28,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:28,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073789839] [2023-11-23 22:38:28,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:28,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:28,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:38:28,975 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-23 22:38:28,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-23 22:38:29,045 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-23 22:38:29,045 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-23 22:38:29,046 INFO L85 PathProgramCache]: Analyzing trace with hash -1084917654, now seen corresponding path program 1 times [2023-11-23 22:38:29,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-23 22:38:29,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532192233] [2023-11-23 22:38:29,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-23 22:38:29,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-23 22:38:29,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-23 22:38:29,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-23 22:38:29,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-23 22:38:29,325 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532192233] [2023-11-23 22:38:29,325 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1532192233] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-23 22:38:29,325 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-23 22:38:29,326 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-23 22:38:29,326 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407674092] [2023-11-23 22:38:29,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-23 22:38:29,326 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-23 22:38:29,326 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-23 22:38:29,327 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-23 22:38:29,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-23 22:38:29,327 INFO L87 Difference]: Start difference. First operand 37078 states and 50928 transitions. cyclomatic complexity: 13882 Second operand has 3 states, 3 states have (on average 47.333333333333336) internal successors, (142), 3 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-23 22:38:29,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-23 22:38:29,657 INFO L93 Difference]: Finished difference Result 54939 states and 75292 transitions. [2023-11-23 22:38:29,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54939 states and 75292 transitions. [2023-11-23 22:38:29,902 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 54480 [2023-11-23 22:38:30,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54939 states to 54939 states and 75292 transitions. [2023-11-23 22:38:30,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54939 [2023-11-23 22:38:30,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54939 [2023-11-23 22:38:30,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54939 states and 75292 transitions. [2023-11-23 22:38:30,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-23 22:38:30,125 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54939 states and 75292 transitions. [2023-11-23 22:38:30,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54939 states and 75292 transitions.