./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength4.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength4.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash f3d22aeda2fb15b9dd79854281ee0f5e475c0f7ee1551b76594f45703ddc81df --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 10:47:28,438 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 10:47:28,559 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 10:47:28,569 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 10:47:28,570 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 10:47:28,622 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 10:47:28,625 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 10:47:28,625 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 10:47:28,626 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 10:47:28,631 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 10:47:28,633 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 10:47:28,633 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 10:47:28,634 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 10:47:28,636 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 10:47:28,636 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 10:47:28,637 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 10:47:28,637 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 10:47:28,637 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 10:47:28,638 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 10:47:28,638 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 10:47:28,639 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 10:47:28,639 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 10:47:28,640 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 10:47:28,640 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 10:47:28,654 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 10:47:28,654 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 10:47:28,654 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 10:47:28,655 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 10:47:28,655 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 10:47:28,656 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 10:47:28,657 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 10:47:28,657 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 10:47:28,657 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 10:47:28,658 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 10:47:28,658 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 10:47:28,658 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 10:47:28,659 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 10:47:28,659 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 10:47:28,659 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> f3d22aeda2fb15b9dd79854281ee0f5e475c0f7ee1551b76594f45703ddc81df [2023-11-26 10:47:28,954 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 10:47:29,008 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 10:47:29,011 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 10:47:29,012 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 10:47:29,013 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 10:47:29,014 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength4.c [2023-11-26 10:47:32,198 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 10:47:32,469 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 10:47:32,471 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength4.c [2023-11-26 10:47:32,484 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/data/87bd3602e/c82ce5218bb34774a0289b94a6e7fc99/FLAG609d0d8f9 [2023-11-26 10:47:32,522 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/data/87bd3602e/c82ce5218bb34774a0289b94a6e7fc99 [2023-11-26 10:47:32,529 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 10:47:32,530 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 10:47:32,532 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 10:47:32,532 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 10:47:32,543 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 10:47:32,543 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,545 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4e4e4cfe and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32, skipping insertion in model container [2023-11-26 10:47:32,545 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,564 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 10:47:32,725 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:47:32,738 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 10:47:32,756 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:47:32,770 INFO L206 MainTranslator]: Completed translation [2023-11-26 10:47:32,770 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32 WrapperNode [2023-11-26 10:47:32,771 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 10:47:32,772 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 10:47:32,772 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 10:47:32,772 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 10:47:32,781 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,788 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,808 INFO L138 Inliner]: procedures = 8, calls = 14, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 66 [2023-11-26 10:47:32,808 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 10:47:32,809 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 10:47:32,809 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 10:47:32,809 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 10:47:32,819 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,819 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,822 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,836 INFO L175 MemorySlicer]: Split 3 memory accesses to 2 slices as follows [2, 1]. 67 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0, 0]. The 1 writes are split as follows [1, 0]. [2023-11-26 10:47:32,836 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,837 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,843 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,847 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,848 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,849 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,852 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 10:47:32,853 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 10:47:32,853 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 10:47:32,853 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 10:47:32,854 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (1/1) ... [2023-11-26 10:47:32,862 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:47:32,877 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:47:32,894 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:47:32,918 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 10:47:32,938 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2023-11-26 10:47:32,939 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2023-11-26 10:47:32,939 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 10:47:32,939 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 10:47:32,939 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2023-11-26 10:47:32,939 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2023-11-26 10:47:32,940 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2023-11-26 10:47:32,940 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2023-11-26 10:47:33,014 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 10:47:33,016 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 10:47:33,178 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 10:47:33,188 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 10:47:33,188 INFO L309 CfgBuilder]: Removed 3 assume(true) statements. [2023-11-26 10:47:33,190 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:47:33 BoogieIcfgContainer [2023-11-26 10:47:33,190 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 10:47:33,191 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 10:47:33,191 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 10:47:33,195 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 10:47:33,196 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:47:33,196 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 10:47:32" (1/3) ... [2023-11-26 10:47:33,197 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@65b67c04 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:47:33, skipping insertion in model container [2023-11-26 10:47:33,197 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:47:33,197 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:32" (2/3) ... [2023-11-26 10:47:33,198 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@65b67c04 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:47:33, skipping insertion in model container [2023-11-26 10:47:33,198 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:47:33,198 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:47:33" (3/3) ... [2023-11-26 10:47:33,200 INFO L332 chiAutomizerObserver]: Analyzing ICFG ArraysOfVariableLength4.c [2023-11-26 10:47:33,254 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 10:47:33,255 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 10:47:33,255 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 10:47:33,255 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 10:47:33,255 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 10:47:33,255 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 10:47:33,256 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 10:47:33,256 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 10:47:33,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:33,278 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2023-11-26 10:47:33,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:33,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:33,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 10:47:33,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2023-11-26 10:47:33,283 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 10:47:33,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:33,285 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2023-11-26 10:47:33,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:33,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:33,286 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 10:47:33,286 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2023-11-26 10:47:33,293 INFO L748 eck$LassoCheckResult]: Stem: 15#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 6#L25-3true [2023-11-26 10:47:33,294 INFO L750 eck$LassoCheckResult]: Loop: 6#L25-3true assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5#L15-3true assume !(foo_~i~0#1 < foo_~size#1); 11#L15-4true foo_#res#1 := foo_~i~0#1; 3#foo_returnLabel#1true main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset;assume { :end_inline_foo } true;call write~int#0(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 12#L25-2true main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6#L25-3true [2023-11-26 10:47:33,299 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:33,299 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2023-11-26 10:47:33,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:33,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [231954123] [2023-11-26 10:47:33,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:33,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:33,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:33,414 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:47:33,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:33,448 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:47:33,457 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:33,457 INFO L85 PathProgramCache]: Analyzing trace with hash 38364915, now seen corresponding path program 1 times [2023-11-26 10:47:33,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:33,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930092191] [2023-11-26 10:47:33,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:33,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:33,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:33,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:33,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:33,694 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930092191] [2023-11-26 10:47:33,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930092191] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:33,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:33,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:47:33,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86744765] [2023-11-26 10:47:33,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:33,701 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:33,702 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:33,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:47:33,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:47:33,740 INFO L87 Difference]: Start difference. First operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:33,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:33,768 INFO L93 Difference]: Finished difference Result 19 states and 22 transitions. [2023-11-26 10:47:33,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 22 transitions. [2023-11-26 10:47:33,771 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11 [2023-11-26 10:47:33,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 14 states and 16 transitions. [2023-11-26 10:47:33,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2023-11-26 10:47:33,776 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2023-11-26 10:47:33,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 16 transitions. [2023-11-26 10:47:33,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:33,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 16 transitions. [2023-11-26 10:47:33,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 16 transitions. [2023-11-26 10:47:33,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 13. [2023-11-26 10:47:33,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.1538461538461537) internal successors, (15), 12 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:33,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 15 transitions. [2023-11-26 10:47:33,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13 states and 15 transitions. [2023-11-26 10:47:33,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:47:33,812 INFO L428 stractBuchiCegarLoop]: Abstraction has 13 states and 15 transitions. [2023-11-26 10:47:33,812 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 10:47:33,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 15 transitions. [2023-11-26 10:47:33,813 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2023-11-26 10:47:33,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:33,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:33,814 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 10:47:33,814 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:33,814 INFO L748 eck$LassoCheckResult]: Stem: 55#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 56#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 48#L25-3 [2023-11-26 10:47:33,815 INFO L750 eck$LassoCheckResult]: Loop: 48#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 49#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 50#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 57#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 45#L15-4 foo_#res#1 := foo_~i~0#1; 46#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset;assume { :end_inline_foo } true;call write~int#0(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 47#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 48#L25-3 [2023-11-26 10:47:33,815 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:33,816 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2023-11-26 10:47:33,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:33,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401501570] [2023-11-26 10:47:33,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:33,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:33,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:33,829 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:47:33,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:33,839 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:47:33,840 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:33,840 INFO L85 PathProgramCache]: Analyzing trace with hash -1732759051, now seen corresponding path program 1 times [2023-11-26 10:47:33,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:33,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91784792] [2023-11-26 10:47:33,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:33,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:33,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:33,968 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:33,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:33,968 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91784792] [2023-11-26 10:47:33,969 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91784792] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 10:47:33,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1916255820] [2023-11-26 10:47:33,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:33,970 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 10:47:33,970 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:47:33,974 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 10:47:34,020 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2023-11-26 10:47:34,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:34,063 INFO L262 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-26 10:47:34,065 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:47:34,140 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:34,140 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 10:47:34,174 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:34,174 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1916255820] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 10:47:34,175 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 10:47:34,175 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 7 [2023-11-26 10:47:34,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284211014] [2023-11-26 10:47:34,175 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 10:47:34,176 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:34,176 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:34,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2023-11-26 10:47:34,177 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=29, Unknown=0, NotChecked=0, Total=56 [2023-11-26 10:47:34,177 INFO L87 Difference]: Start difference. First operand 13 states and 15 transitions. cyclomatic complexity: 4 Second operand has 8 states, 8 states have (on average 1.875) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:34,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:34,219 INFO L93 Difference]: Finished difference Result 19 states and 21 transitions. [2023-11-26 10:47:34,219 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 21 transitions. [2023-11-26 10:47:34,220 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2023-11-26 10:47:34,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 19 states and 21 transitions. [2023-11-26 10:47:34,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2023-11-26 10:47:34,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2023-11-26 10:47:34,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19 states and 21 transitions. [2023-11-26 10:47:34,222 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:34,222 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19 states and 21 transitions. [2023-11-26 10:47:34,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states and 21 transitions. [2023-11-26 10:47:34,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2023-11-26 10:47:34,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.105263157894737) internal successors, (21), 18 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:34,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2023-11-26 10:47:34,225 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 21 transitions. [2023-11-26 10:47:34,225 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-26 10:47:34,226 INFO L428 stractBuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2023-11-26 10:47:34,226 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 10:47:34,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 21 transitions. [2023-11-26 10:47:34,228 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2023-11-26 10:47:34,228 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:34,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:34,229 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 10:47:34,229 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [4, 4, 1, 1, 1, 1, 1] [2023-11-26 10:47:34,229 INFO L748 eck$LassoCheckResult]: Stem: 132#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 127#L25-3 [2023-11-26 10:47:34,229 INFO L750 eck$LassoCheckResult]: Loop: 127#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 128#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 129#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 136#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 142#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 141#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 140#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 139#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 138#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 137#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 124#L15-4 foo_#res#1 := foo_~i~0#1; 125#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset;assume { :end_inline_foo } true;call write~int#0(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 126#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 127#L25-3 [2023-11-26 10:47:34,230 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:34,230 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 3 times [2023-11-26 10:47:34,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:34,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809764356] [2023-11-26 10:47:34,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:34,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:34,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:34,251 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:47:34,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:34,267 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:47:34,278 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:34,278 INFO L85 PathProgramCache]: Analyzing trace with hash -1316700165, now seen corresponding path program 2 times [2023-11-26 10:47:34,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:34,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514482237] [2023-11-26 10:47:34,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:34,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:34,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:34,595 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:34,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:34,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514482237] [2023-11-26 10:47:34,596 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514482237] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 10:47:34,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [938973846] [2023-11-26 10:47:34,596 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-26 10:47:34,596 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 10:47:34,597 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:47:34,625 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 10:47:34,660 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2023-11-26 10:47:34,734 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-26 10:47:34,734 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 10:47:34,735 INFO L262 TraceCheckSpWp]: Trace formula consists of 74 conjuncts, 8 conjunts are in the unsatisfiable core [2023-11-26 10:47:34,737 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:47:34,875 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:34,875 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 10:47:35,031 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:35,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [938973846] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 10:47:35,031 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 10:47:35,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 16 [2023-11-26 10:47:35,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988763526] [2023-11-26 10:47:35,032 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 10:47:35,033 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:35,033 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:35,034 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2023-11-26 10:47:35,034 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=146, Unknown=0, NotChecked=0, Total=272 [2023-11-26 10:47:35,035 INFO L87 Difference]: Start difference. First operand 19 states and 21 transitions. cyclomatic complexity: 4 Second operand has 17 states, 17 states have (on average 1.9411764705882353) internal successors, (33), 16 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:35,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:35,106 INFO L93 Difference]: Finished difference Result 31 states and 33 transitions. [2023-11-26 10:47:35,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 33 transitions. [2023-11-26 10:47:35,108 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28 [2023-11-26 10:47:35,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 31 states and 33 transitions. [2023-11-26 10:47:35,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2023-11-26 10:47:35,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2023-11-26 10:47:35,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 33 transitions. [2023-11-26 10:47:35,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:35,111 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31 states and 33 transitions. [2023-11-26 10:47:35,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 33 transitions. [2023-11-26 10:47:35,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 31. [2023-11-26 10:47:35,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.064516129032258) internal successors, (33), 30 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:35,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2023-11-26 10:47:35,115 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 33 transitions. [2023-11-26 10:47:35,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-26 10:47:35,116 INFO L428 stractBuchiCegarLoop]: Abstraction has 31 states and 33 transitions. [2023-11-26 10:47:35,116 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 10:47:35,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 33 transitions. [2023-11-26 10:47:35,118 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28 [2023-11-26 10:47:35,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:35,118 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:35,119 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 10:47:35,119 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [10, 10, 1, 1, 1, 1, 1] [2023-11-26 10:47:35,119 INFO L748 eck$LassoCheckResult]: Stem: 275#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 269#L25-3 [2023-11-26 10:47:35,119 INFO L750 eck$LassoCheckResult]: Loop: 269#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 273#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 279#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 270#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 271#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 296#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 295#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 294#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 293#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 292#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 291#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 290#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 289#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 288#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 287#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 286#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 285#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 284#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 283#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 282#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 281#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 280#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 266#L15-4 foo_#res#1 := foo_~i~0#1; 267#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset;assume { :end_inline_foo } true;call write~int#0(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 268#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 269#L25-3 [2023-11-26 10:47:35,120 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:35,120 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 4 times [2023-11-26 10:47:35,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:35,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730302297] [2023-11-26 10:47:35,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:35,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:35,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:35,128 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:47:35,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:35,134 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:47:35,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:35,135 INFO L85 PathProgramCache]: Analyzing trace with hash 2131617415, now seen corresponding path program 3 times [2023-11-26 10:47:35,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:35,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204010670] [2023-11-26 10:47:35,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:35,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:35,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:35,548 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:35,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:35,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1204010670] [2023-11-26 10:47:35,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1204010670] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 10:47:35,554 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [588277750] [2023-11-26 10:47:35,554 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-26 10:47:35,554 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 10:47:35,555 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:47:35,562 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 10:47:35,574 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2023-11-26 10:47:35,678 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2023-11-26 10:47:35,678 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 10:47:35,679 INFO L262 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 14 conjunts are in the unsatisfiable core [2023-11-26 10:47:35,682 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:47:36,092 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:36,092 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 10:47:36,574 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:36,574 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [588277750] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 10:47:36,575 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 10:47:36,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 34 [2023-11-26 10:47:36,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615326053] [2023-11-26 10:47:36,579 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 10:47:36,582 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:36,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:36,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2023-11-26 10:47:36,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=540, Invalid=650, Unknown=0, NotChecked=0, Total=1190 [2023-11-26 10:47:36,587 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. cyclomatic complexity: 4 Second operand has 35 states, 35 states have (on average 1.9714285714285715) internal successors, (69), 34 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:36,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:36,732 INFO L93 Difference]: Finished difference Result 55 states and 57 transitions. [2023-11-26 10:47:36,738 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 57 transitions. [2023-11-26 10:47:36,745 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52 [2023-11-26 10:47:36,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 55 states and 57 transitions. [2023-11-26 10:47:36,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55 [2023-11-26 10:47:36,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55 [2023-11-26 10:47:36,747 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 57 transitions. [2023-11-26 10:47:36,748 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:36,748 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55 states and 57 transitions. [2023-11-26 10:47:36,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 57 transitions. [2023-11-26 10:47:36,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2023-11-26 10:47:36,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.0363636363636364) internal successors, (57), 54 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:36,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 57 transitions. [2023-11-26 10:47:36,754 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 57 transitions. [2023-11-26 10:47:36,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-26 10:47:36,760 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 57 transitions. [2023-11-26 10:47:36,760 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 10:47:36,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 57 transitions. [2023-11-26 10:47:36,766 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52 [2023-11-26 10:47:36,769 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:36,769 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:36,771 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 10:47:36,771 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [22, 22, 1, 1, 1, 1, 1] [2023-11-26 10:47:36,772 INFO L748 eck$LassoCheckResult]: Stem: 543#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 544#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 537#L25-3 [2023-11-26 10:47:36,773 INFO L750 eck$LassoCheckResult]: Loop: 537#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 541#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 547#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 538#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 539#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 588#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 587#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 586#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 585#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 584#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 583#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 582#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 581#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 580#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 579#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 578#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 577#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 576#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 575#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 574#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 573#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 572#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 571#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 570#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 569#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 568#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 567#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 566#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 565#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 564#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 563#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 562#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 561#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 560#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 559#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 558#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 557#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 556#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 555#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 554#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 553#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 552#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 551#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 550#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 549#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 548#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 534#L15-4 foo_#res#1 := foo_~i~0#1; 535#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset;assume { :end_inline_foo } true;call write~int#0(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 536#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 537#L25-3 [2023-11-26 10:47:36,776 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:36,776 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 5 times [2023-11-26 10:47:36,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:36,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804579502] [2023-11-26 10:47:36,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:36,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:36,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:36,787 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:47:36,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:36,799 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:47:36,803 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:36,804 INFO L85 PathProgramCache]: Analyzing trace with hash -1575559777, now seen corresponding path program 4 times [2023-11-26 10:47:36,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:36,804 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142019456] [2023-11-26 10:47:36,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:36,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:36,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:37,897 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:37,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:37,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142019456] [2023-11-26 10:47:37,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142019456] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 10:47:37,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [13973788] [2023-11-26 10:47:37,898 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-26 10:47:37,898 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 10:47:37,898 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:47:37,906 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 10:47:37,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f17d5e-bd74-4292-8c29-f0d8d754da73/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2023-11-26 10:47:38,042 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-26 10:47:38,042 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 10:47:38,045 INFO L262 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjunts are in the unsatisfiable core [2023-11-26 10:47:38,049 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:47:39,163 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:39,163 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 10:47:40,740 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:40,740 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [13973788] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 10:47:40,740 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 10:47:40,741 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 70 [2023-11-26 10:47:40,741 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [999503682] [2023-11-26 10:47:40,741 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 10:47:40,742 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:40,742 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:40,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2023-11-26 10:47:40,746 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2050, Invalid=2920, Unknown=0, NotChecked=0, Total=4970 [2023-11-26 10:47:40,747 INFO L87 Difference]: Start difference. First operand 55 states and 57 transitions. cyclomatic complexity: 4 Second operand has 71 states, 71 states have (on average 1.9859154929577465) internal successors, (141), 70 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:40,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:40,955 INFO L93 Difference]: Finished difference Result 75 states and 77 transitions. [2023-11-26 10:47:40,955 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 77 transitions. [2023-11-26 10:47:40,959 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 72 [2023-11-26 10:47:40,962 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 75 states and 77 transitions. [2023-11-26 10:47:40,962 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2023-11-26 10:47:40,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 [2023-11-26 10:47:40,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 77 transitions. [2023-11-26 10:47:40,964 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:40,965 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75 states and 77 transitions. [2023-11-26 10:47:40,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 77 transitions. [2023-11-26 10:47:40,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2023-11-26 10:47:40,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.0266666666666666) internal successors, (77), 74 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:40,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 77 transitions. [2023-11-26 10:47:40,979 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 77 transitions. [2023-11-26 10:47:40,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2023-11-26 10:47:40,983 INFO L428 stractBuchiCegarLoop]: Abstraction has 75 states and 77 transitions. [2023-11-26 10:47:40,983 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 10:47:40,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 77 transitions. [2023-11-26 10:47:40,987 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 72 [2023-11-26 10:47:40,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:40,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:40,990 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 10:47:40,990 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [32, 32, 1, 1, 1, 1, 1] [2023-11-26 10:47:40,991 INFO L748 eck$LassoCheckResult]: Stem: 1035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1036#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 1028#L25-3 [2023-11-26 10:47:40,991 INFO L750 eck$LassoCheckResult]: Loop: 1028#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1033#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1039#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1030#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1031#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1100#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1099#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1098#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1097#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1096#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1095#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1094#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1093#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1092#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1091#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1090#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1089#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1088#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1087#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1086#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1085#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1084#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1083#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1082#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1081#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1080#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1079#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1078#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1077#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1076#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1075#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1074#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1073#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1072#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1071#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1070#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1069#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1068#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1067#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1066#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1065#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1064#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1063#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1062#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1061#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1060#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1059#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1058#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1057#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1056#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1055#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1054#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1053#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1052#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1051#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1050#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1049#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1048#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1047#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1046#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1045#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1044#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1043#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1042#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int#1(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1041#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1040#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 1029#L15-4 foo_#res#1 := foo_~i~0#1; 1026#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset;assume { :end_inline_foo } true;call write~int#0(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1027#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1028#L25-3 [2023-11-26 10:47:40,991 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:40,991 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 6 times [2023-11-26 10:47:40,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:40,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602685249] [2023-11-26 10:47:40,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:40,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:41,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:41,001 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:47:41,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:41,009 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:47:41,010 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:41,010 INFO L85 PathProgramCache]: Analyzing trace with hash 776556339, now seen corresponding path program 5 times [2023-11-26 10:47:41,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:41,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564338531] [2023-11-26 10:47:41,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:41,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:41,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:41,157 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:47:41,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:41,226 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:47:41,227 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:41,227 INFO L85 PathProgramCache]: Analyzing trace with hash -378248015, now seen corresponding path program 1 times [2023-11-26 10:47:41,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:41,227 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703265650] [2023-11-26 10:47:41,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:41,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:41,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:41,347 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:47:41,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:47:41,444 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace