./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:52:13,947 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:52:14,083 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-64bit-Automizer_Default.epf [2023-11-26 11:52:14,095 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:52:14,096 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:52:14,144 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:52:14,145 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:52:14,146 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:52:14,147 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:52:14,152 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:52:14,154 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:52:14,154 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:52:14,156 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:52:14,158 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:52:14,158 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:52:14,159 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:52:14,159 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:52:14,160 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:52:14,160 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:52:14,161 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:52:14,161 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:52:14,162 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:52:14,162 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:52:14,163 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:52:14,163 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:52:14,164 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:52:14,164 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:52:14,164 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:52:14,165 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:52:14,165 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:52:14,167 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:52:14,167 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:52:14,167 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:52:14,168 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:52:14,168 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:52:14,168 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe [2023-11-26 11:52:14,445 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:52:14,509 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:52:14,512 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:52:14,514 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:52:14,514 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:52:14,516 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2023-11-26 11:52:17,703 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:52:18,002 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:52:18,003 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2023-11-26 11:52:18,019 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/data/84a5e5b4d/1d03dd046b504ea68d69f715a41e574a/FLAG2e138bdf4 [2023-11-26 11:52:18,036 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/data/84a5e5b4d/1d03dd046b504ea68d69f715a41e574a [2023-11-26 11:52:18,039 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:52:18,041 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:52:18,043 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:52:18,043 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:52:18,049 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:52:18,050 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,050 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1c1ecbe2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18, skipping insertion in model container [2023-11-26 11:52:18,051 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,090 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:52:18,357 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:52:18,370 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:52:18,409 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:52:18,441 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:52:18,441 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18 WrapperNode [2023-11-26 11:52:18,442 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:52:18,443 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:52:18,443 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:52:18,444 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:52:18,453 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,466 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,489 INFO L138 Inliner]: procedures = 109, calls = 13, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 33 [2023-11-26 11:52:18,490 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:52:18,491 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:52:18,491 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:52:18,491 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:52:18,505 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,505 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,509 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,524 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [3, 4]. 57 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0, 0]. The 3 writes are split as follows [1, 2]. [2023-11-26 11:52:18,525 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,525 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,529 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,533 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,535 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,536 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,539 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:52:18,540 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:52:18,540 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:52:18,540 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:52:18,541 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (1/1) ... [2023-11-26 11:52:18,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:52:18,565 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:52:18,579 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:52:18,592 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:52:18,620 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2023-11-26 11:52:18,620 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2023-11-26 11:52:18,620 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2023-11-26 11:52:18,621 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2023-11-26 11:52:18,621 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2023-11-26 11:52:18,621 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2023-11-26 11:52:18,621 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:52:18,622 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:52:18,726 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:52:18,729 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:52:18,846 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:52:18,857 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:52:18,860 INFO L309 CfgBuilder]: Removed 2 assume(true) statements. [2023-11-26 11:52:18,862 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:52:18 BoogieIcfgContainer [2023-11-26 11:52:18,863 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:52:18,865 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:52:18,865 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:52:18,869 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:52:18,873 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:52:18,873 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:52:18" (1/3) ... [2023-11-26 11:52:18,892 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@231f34f5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:52:18, skipping insertion in model container [2023-11-26 11:52:18,892 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:52:18,900 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:18" (2/3) ... [2023-11-26 11:52:18,900 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@231f34f5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:52:18, skipping insertion in model container [2023-11-26 11:52:18,900 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:52:18,901 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:52:18" (3/3) ... [2023-11-26 11:52:18,902 INFO L332 chiAutomizerObserver]: Analyzing ICFG Urban-2013WST-Fig2-modified1000-alloca.i [2023-11-26 11:52:19,012 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:52:19,012 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:52:19,012 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:52:19,013 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:52:19,013 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:52:19,013 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:52:19,013 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:52:19,014 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:52:19,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:19,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2023-11-26 11:52:19,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:19,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:19,039 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 11:52:19,039 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2023-11-26 11:52:19,040 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:52:19,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:19,041 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2023-11-26 11:52:19,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:19,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:19,042 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 11:52:19,042 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2023-11-26 11:52:19,049 INFO L748 eck$LassoCheckResult]: Stem: 6#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 5#L549-3true [2023-11-26 11:52:19,049 INFO L750 eck$LassoCheckResult]: Loop: 5#L549-3true call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 2#L549-1true assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 7#L551-3true assume !true; 11#L551-4true call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 5#L549-3true [2023-11-26 11:52:19,053 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:19,054 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2023-11-26 11:52:19,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:19,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769843578] [2023-11-26 11:52:19,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:19,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:19,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:19,171 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:19,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:19,203 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:19,206 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:19,206 INFO L85 PathProgramCache]: Analyzing trace with hash 1144360, now seen corresponding path program 1 times [2023-11-26 11:52:19,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:19,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742505106] [2023-11-26 11:52:19,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:19,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:19,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:19,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:19,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:19,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742505106] [2023-11-26 11:52:19,270 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [742505106] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:19,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:19,271 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:52:19,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18505703] [2023-11-26 11:52:19,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:19,277 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:19,278 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:19,314 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-26 11:52:19,315 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-26 11:52:19,317 INFO L87 Difference]: Start difference. First operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:19,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:19,325 INFO L93 Difference]: Finished difference Result 11 states and 12 transitions. [2023-11-26 11:52:19,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 12 transitions. [2023-11-26 11:52:19,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2023-11-26 11:52:19,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 7 states and 8 transitions. [2023-11-26 11:52:19,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-26 11:52:19,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2023-11-26 11:52:19,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 8 transitions. [2023-11-26 11:52:19,334 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:19,334 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2023-11-26 11:52:19,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 8 transitions. [2023-11-26 11:52:19,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2023-11-26 11:52:19,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:19,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 8 transitions. [2023-11-26 11:52:19,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2023-11-26 11:52:19,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-26 11:52:19,365 INFO L428 stractBuchiCegarLoop]: Abstraction has 7 states and 8 transitions. [2023-11-26 11:52:19,365 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:52:19,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 8 transitions. [2023-11-26 11:52:19,366 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2023-11-26 11:52:19,366 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:19,366 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:19,367 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 11:52:19,367 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2023-11-26 11:52:19,367 INFO L748 eck$LassoCheckResult]: Stem: 33#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 34#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 32#L549-3 [2023-11-26 11:52:19,368 INFO L750 eck$LassoCheckResult]: Loop: 32#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 30#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 31#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 35#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 36#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 32#L549-3 [2023-11-26 11:52:19,368 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:19,369 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2023-11-26 11:52:19,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:19,369 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475885018] [2023-11-26 11:52:19,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:19,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:19,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:19,390 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:19,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:19,403 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:19,404 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:19,404 INFO L85 PathProgramCache]: Analyzing trace with hash 35468273, now seen corresponding path program 1 times [2023-11-26 11:52:19,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:19,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750222861] [2023-11-26 11:52:19,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:19,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:19,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:19,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:19,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:19,606 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1750222861] [2023-11-26 11:52:19,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1750222861] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:19,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:19,607 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 11:52:19,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375785273] [2023-11-26 11:52:19,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:19,607 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:19,608 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:19,608 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:52:19,608 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:52:19,609 INFO L87 Difference]: Start difference. First operand 7 states and 8 transitions. cyclomatic complexity: 2 Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:19,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:19,670 INFO L93 Difference]: Finished difference Result 9 states and 10 transitions. [2023-11-26 11:52:19,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9 states and 10 transitions. [2023-11-26 11:52:19,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2023-11-26 11:52:19,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9 states to 9 states and 10 transitions. [2023-11-26 11:52:19,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-26 11:52:19,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-26 11:52:19,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 10 transitions. [2023-11-26 11:52:19,672 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:19,672 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2023-11-26 11:52:19,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 10 transitions. [2023-11-26 11:52:19,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2023-11-26 11:52:19,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:19,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2023-11-26 11:52:19,674 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2023-11-26 11:52:19,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:52:19,676 INFO L428 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2023-11-26 11:52:19,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:52:19,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2023-11-26 11:52:19,677 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2023-11-26 11:52:19,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:19,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:19,678 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 11:52:19,678 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1] [2023-11-26 11:52:19,678 INFO L748 eck$LassoCheckResult]: Stem: 60#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 61#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 57#L549-3 [2023-11-26 11:52:19,679 INFO L750 eck$LassoCheckResult]: Loop: 57#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 55#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 56#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 58#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 59#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 63#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 62#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 57#L549-3 [2023-11-26 11:52:19,679 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:19,680 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 3 times [2023-11-26 11:52:19,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:19,680 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822589296] [2023-11-26 11:52:19,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:19,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:19,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:19,695 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:19,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:19,704 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:19,705 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:19,706 INFO L85 PathProgramCache]: Analyzing trace with hash -274676436, now seen corresponding path program 1 times [2023-11-26 11:52:19,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:19,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785649083] [2023-11-26 11:52:19,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:19,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:19,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:19,994 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:19,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:19,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785649083] [2023-11-26 11:52:19,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785649083] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:52:19,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1360993634] [2023-11-26 11:52:19,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:19,996 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:52:19,996 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:52:20,000 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:52:20,017 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2023-11-26 11:52:20,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:20,107 INFO L262 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 7 conjunts are in the unsatisfiable core [2023-11-26 11:52:20,112 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:52:20,172 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2023-11-26 11:52:20,243 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2023-11-26 11:52:20,263 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2023-11-26 11:52:20,272 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:20,273 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 11:52:20,335 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:20,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1360993634] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 11:52:20,336 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 11:52:20,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 9 [2023-11-26 11:52:20,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [874376782] [2023-11-26 11:52:20,337 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 11:52:20,337 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:20,338 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:20,338 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2023-11-26 11:52:20,338 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2023-11-26 11:52:20,339 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 2 Second operand has 9 states, 9 states have (on average 1.5555555555555556) internal successors, (14), 9 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:20,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:20,425 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2023-11-26 11:52:20,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2023-11-26 11:52:20,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2023-11-26 11:52:20,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2023-11-26 11:52:20,431 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2023-11-26 11:52:20,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2023-11-26 11:52:20,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2023-11-26 11:52:20,432 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:20,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2023-11-26 11:52:20,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2023-11-26 11:52:20,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2023-11-26 11:52:20,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:20,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2023-11-26 11:52:20,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2023-11-26 11:52:20,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2023-11-26 11:52:20,440 INFO L428 stractBuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2023-11-26 11:52:20,440 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:52:20,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2023-11-26 11:52:20,443 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2023-11-26 11:52:20,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:20,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:20,447 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 11:52:20,447 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [5, 4, 1, 1, 1, 1] [2023-11-26 11:52:20,447 INFO L748 eck$LassoCheckResult]: Stem: 139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 135#L549-3 [2023-11-26 11:52:20,448 INFO L750 eck$LassoCheckResult]: Loop: 135#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 133#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 134#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 136#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 137#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 138#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 147#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 146#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 145#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 144#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 143#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 142#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 141#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 135#L549-3 [2023-11-26 11:52:20,449 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:20,449 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 4 times [2023-11-26 11:52:20,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:20,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [121705619] [2023-11-26 11:52:20,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:20,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:20,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:20,474 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:20,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:20,493 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:20,493 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:20,494 INFO L85 PathProgramCache]: Analyzing trace with hash 351922269, now seen corresponding path program 2 times [2023-11-26 11:52:20,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:20,495 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307801715] [2023-11-26 11:52:20,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:20,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:20,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:21,092 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:21,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:21,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307801715] [2023-11-26 11:52:21,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307801715] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:52:21,098 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [91217277] [2023-11-26 11:52:21,099 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-26 11:52:21,099 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:52:21,099 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:52:21,139 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:52:21,164 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2023-11-26 11:52:21,236 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-26 11:52:21,236 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 11:52:21,237 INFO L262 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 16 conjunts are in the unsatisfiable core [2023-11-26 11:52:21,243 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:52:21,250 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2023-11-26 11:52:21,282 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2023-11-26 11:52:21,301 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:21,320 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:21,346 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:21,363 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2023-11-26 11:52:21,368 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:21,368 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 11:52:21,511 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:21,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [91217277] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 11:52:21,512 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 11:52:21,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 18 [2023-11-26 11:52:21,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2089679018] [2023-11-26 11:52:21,513 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 11:52:21,513 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:21,513 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:21,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2023-11-26 11:52:21,517 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=179, Unknown=0, NotChecked=0, Total=306 [2023-11-26 11:52:21,518 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 2 Second operand has 18 states, 18 states have (on average 1.7777777777777777) internal successors, (32), 18 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:21,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:21,711 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2023-11-26 11:52:21,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2023-11-26 11:52:21,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2023-11-26 11:52:21,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2023-11-26 11:52:21,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2023-11-26 11:52:21,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2023-11-26 11:52:21,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2023-11-26 11:52:21,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:21,720 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2023-11-26 11:52:21,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2023-11-26 11:52:21,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2023-11-26 11:52:21,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:21,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2023-11-26 11:52:21,728 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2023-11-26 11:52:21,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2023-11-26 11:52:21,732 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2023-11-26 11:52:21,732 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:52:21,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2023-11-26 11:52:21,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2023-11-26 11:52:21,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:21,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:21,736 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 11:52:21,736 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [11, 10, 1, 1, 1, 1] [2023-11-26 11:52:21,737 INFO L748 eck$LassoCheckResult]: Stem: 286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 282#L549-3 [2023-11-26 11:52:21,737 INFO L750 eck$LassoCheckResult]: Loop: 282#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 280#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 281#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 283#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 284#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 285#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 306#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 305#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 304#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 303#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 302#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 301#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 300#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 299#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 298#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 297#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 296#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 295#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 294#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 293#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 292#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 291#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 290#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 289#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 288#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 282#L549-3 [2023-11-26 11:52:21,738 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:21,738 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 5 times [2023-11-26 11:52:21,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:21,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106147637] [2023-11-26 11:52:21,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:21,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:21,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:21,748 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:21,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:21,758 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:21,759 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:21,759 INFO L85 PathProgramCache]: Analyzing trace with hash 646907007, now seen corresponding path program 3 times [2023-11-26 11:52:21,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:21,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850851820] [2023-11-26 11:52:21,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:21,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:21,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:23,175 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:23,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:23,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850851820] [2023-11-26 11:52:23,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1850851820] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:52:23,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1184908126] [2023-11-26 11:52:23,176 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-26 11:52:23,176 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:52:23,177 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:52:23,183 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:52:23,192 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2023-11-26 11:52:23,388 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2023-11-26 11:52:23,388 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 11:52:23,390 INFO L262 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 34 conjunts are in the unsatisfiable core [2023-11-26 11:52:23,398 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:52:23,403 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2023-11-26 11:52:23,429 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2023-11-26 11:52:23,442 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:23,455 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:23,469 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:23,483 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:23,496 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:23,510 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:23,524 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:23,537 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:23,550 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:23,557 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2023-11-26 11:52:23,561 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:23,561 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 11:52:23,914 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:23,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1184908126] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 11:52:23,914 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 11:52:23,915 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 14, 14] total 36 [2023-11-26 11:52:23,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1454308670] [2023-11-26 11:52:23,915 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 11:52:23,917 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:23,917 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:23,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2023-11-26 11:52:23,919 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=541, Invalid=719, Unknown=0, NotChecked=0, Total=1260 [2023-11-26 11:52:23,920 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 2 Second operand has 36 states, 36 states have (on average 1.8888888888888888) internal successors, (68), 36 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:24,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:24,349 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions. [2023-11-26 11:52:24,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions. [2023-11-26 11:52:24,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2023-11-26 11:52:24,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions. [2023-11-26 11:52:24,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2023-11-26 11:52:24,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2023-11-26 11:52:24,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions. [2023-11-26 11:52:24,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:24,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2023-11-26 11:52:24,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions. [2023-11-26 11:52:24,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2023-11-26 11:52:24,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:24,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2023-11-26 11:52:24,372 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2023-11-26 11:52:24,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2023-11-26 11:52:24,375 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2023-11-26 11:52:24,375 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:52:24,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2023-11-26 11:52:24,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2023-11-26 11:52:24,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:24,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:24,380 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 11:52:24,380 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [23, 22, 1, 1, 1, 1] [2023-11-26 11:52:24,380 INFO L748 eck$LassoCheckResult]: Stem: 571#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 567#L549-3 [2023-11-26 11:52:24,380 INFO L750 eck$LassoCheckResult]: Loop: 567#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 565#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 566#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 570#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 568#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 569#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 615#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 614#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 613#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 612#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 611#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 610#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 609#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 608#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 607#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 606#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 605#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 604#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 603#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 602#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 601#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 600#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 599#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 598#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 597#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 596#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 595#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 594#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 593#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 592#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 591#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 590#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 589#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 588#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 587#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 586#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 585#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 584#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 583#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 582#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 581#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 580#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 579#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 578#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 577#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 576#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 575#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 574#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 573#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 567#L549-3 [2023-11-26 11:52:24,381 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:24,381 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 6 times [2023-11-26 11:52:24,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:24,381 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273677658] [2023-11-26 11:52:24,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:24,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:24,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:24,389 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:24,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:24,395 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:24,395 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:24,396 INFO L85 PathProgramCache]: Analyzing trace with hash 1009537987, now seen corresponding path program 4 times [2023-11-26 11:52:24,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:24,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080203319] [2023-11-26 11:52:24,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:24,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:24,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:28,068 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:28,068 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:28,068 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080203319] [2023-11-26 11:52:28,069 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1080203319] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:52:28,069 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1856683864] [2023-11-26 11:52:28,069 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-26 11:52:28,069 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:52:28,069 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:52:28,076 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:52:28,088 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2023-11-26 11:52:28,547 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-26 11:52:28,547 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 11:52:28,551 INFO L262 TraceCheckSpWp]: Trace formula consists of 362 conjuncts, 70 conjunts are in the unsatisfiable core [2023-11-26 11:52:28,566 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:52:28,570 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2023-11-26 11:52:28,585 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2023-11-26 11:52:28,596 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,627 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,642 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,657 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,671 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,690 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,703 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,716 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,733 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,747 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,760 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,773 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,791 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,803 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,815 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,826 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,837 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,850 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,861 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,877 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,889 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:52:28,896 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2023-11-26 11:52:28,901 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:28,902 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 11:52:30,112 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:30,112 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1856683864] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 11:52:30,112 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 11:52:30,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 26, 26] total 72 [2023-11-26 11:52:30,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814683349] [2023-11-26 11:52:30,113 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 11:52:30,114 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:30,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:30,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2023-11-26 11:52:30,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2233, Invalid=2879, Unknown=0, NotChecked=0, Total=5112 [2023-11-26 11:52:30,124 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 2 Second operand has 72 states, 72 states have (on average 1.9444444444444444) internal successors, (140), 72 states have internal predecessors, (140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:31,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:31,408 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2023-11-26 11:52:31,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions. [2023-11-26 11:52:31,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2023-11-26 11:52:31,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions. [2023-11-26 11:52:31,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2023-11-26 11:52:31,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2023-11-26 11:52:31,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions. [2023-11-26 11:52:31,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:31,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2023-11-26 11:52:31,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions. [2023-11-26 11:52:31,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2023-11-26 11:52:31,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:31,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2023-11-26 11:52:31,419 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2023-11-26 11:52:31,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2023-11-26 11:52:31,420 INFO L428 stractBuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2023-11-26 11:52:31,420 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:52:31,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2023-11-26 11:52:31,422 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2023-11-26 11:52:31,422 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:31,422 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:31,424 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 11:52:31,424 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [47, 46, 1, 1, 1, 1] [2023-11-26 11:52:31,424 INFO L748 eck$LassoCheckResult]: Stem: 1132#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 1128#L549-3 [2023-11-26 11:52:31,424 INFO L750 eck$LassoCheckResult]: Loop: 1128#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 1126#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1127#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1129#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1130#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1131#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1224#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1223#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1222#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1221#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1220#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1219#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1218#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1217#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1216#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1215#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1214#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1213#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1212#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1211#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1210#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1209#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1208#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1207#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1206#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1205#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1204#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1203#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1202#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1201#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1200#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1199#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1198#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1197#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1196#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1195#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1194#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1193#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1192#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1191#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1190#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1189#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1188#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1187#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1186#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1185#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1184#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1183#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1182#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1181#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1180#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1179#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1178#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1177#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1176#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1175#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1174#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1173#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1172#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1171#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1170#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1169#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1168#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1167#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1166#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1165#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1164#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1163#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1162#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1161#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1160#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1159#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1158#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1157#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1156#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1155#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1154#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1153#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1152#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1151#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1150#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1149#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1148#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1147#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1146#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1145#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1144#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1143#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1142#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1141#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1140#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1139#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1138#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1137#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1136#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1135#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 1134#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 1128#L549-3 [2023-11-26 11:52:31,425 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:31,425 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 7 times [2023-11-26 11:52:31,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:31,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530641431] [2023-11-26 11:52:31,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:31,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:31,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:31,432 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:31,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:31,435 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:31,436 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:31,436 INFO L85 PathProgramCache]: Analyzing trace with hash 1846627915, now seen corresponding path program 5 times [2023-11-26 11:52:31,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:31,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148591146] [2023-11-26 11:52:31,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:31,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:31,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:43,746 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:43,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:43,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148591146] [2023-11-26 11:52:43,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [148591146] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:52:43,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1927685650] [2023-11-26 11:52:43,747 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-26 11:52:43,748 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:52:43,748 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:52:43,753 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:52:43,772 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6cada0b4-8d0d-4940-b6b1-65a225197103/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2023-11-26 11:53:00,781 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2023-11-26 11:53:00,781 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 11:53:00,793 INFO L262 TraceCheckSpWp]: Trace formula consists of 722 conjuncts, 142 conjunts are in the unsatisfiable core [2023-11-26 11:53:00,825 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:53:00,830 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2023-11-26 11:53:00,859 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2023-11-26 11:53:00,867 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,881 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,892 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,906 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,915 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,926 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,936 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,945 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,954 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,964 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,973 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,981 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,990 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:00,999 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,009 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,018 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,029 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,047 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,056 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,069 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,078 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,087 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,095 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,106 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,116 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,126 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,135 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,145 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,157 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,166 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,175 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,184 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,194 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,204 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,212 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,225 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,237 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,245 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,257 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,266 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,274 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,282 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,290 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,297 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,306 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2023-11-26 11:53:01,312 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2023-11-26 11:53:01,316 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:53:01,316 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 11:53:05,104 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:53:05,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1927685650] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 11:53:05,104 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 11:53:05,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 50, 50] total 144 [2023-11-26 11:53:05,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509782781] [2023-11-26 11:53:05,104 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 11:53:05,106 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:53:05,106 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:53:05,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 144 interpolants. [2023-11-26 11:53:05,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9073, Invalid=11519, Unknown=0, NotChecked=0, Total=20592 [2023-11-26 11:53:05,118 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 2 Second operand has 144 states, 144 states have (on average 1.9722222222222223) internal successors, (284), 144 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)