./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu1.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c114a15ea6b1c9b012290758a6a9559b9c02a944706c9768958a3bd9c86822a7 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 12:01:20,163 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 12:01:20,282 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 12:01:20,294 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 12:01:20,295 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 12:01:20,346 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 12:01:20,348 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 12:01:20,349 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 12:01:20,350 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 12:01:20,355 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 12:01:20,356 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 12:01:20,356 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 12:01:20,357 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 12:01:20,359 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 12:01:20,359 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 12:01:20,360 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 12:01:20,360 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 12:01:20,361 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 12:01:20,361 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 12:01:20,362 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 12:01:20,363 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 12:01:20,363 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 12:01:20,364 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 12:01:20,364 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 12:01:20,376 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 12:01:20,376 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 12:01:20,377 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 12:01:20,377 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 12:01:20,378 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 12:01:20,378 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 12:01:20,380 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 12:01:20,380 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 12:01:20,380 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 12:01:20,380 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 12:01:20,381 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 12:01:20,381 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 12:01:20,381 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 12:01:20,382 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 12:01:20,382 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c114a15ea6b1c9b012290758a6a9559b9c02a944706c9768958a3bd9c86822a7 [2023-11-26 12:01:20,728 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 12:01:20,759 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 12:01:20,763 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 12:01:20,765 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 12:01:20,766 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 12:01:20,767 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/kundu1.cil.c [2023-11-26 12:01:23,829 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 12:01:24,091 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 12:01:24,096 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/sv-benchmarks/c/systemc/kundu1.cil.c [2023-11-26 12:01:24,111 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/data/002fca276/c5259444b9b8448e8bc0ad8b727f1371/FLAGae5e9446b [2023-11-26 12:01:24,127 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/data/002fca276/c5259444b9b8448e8bc0ad8b727f1371 [2023-11-26 12:01:24,133 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 12:01:24,135 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 12:01:24,138 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 12:01:24,139 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 12:01:24,144 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 12:01:24,145 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,146 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5f6e251f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24, skipping insertion in model container [2023-11-26 12:01:24,146 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,199 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 12:01:24,395 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:01:24,409 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 12:01:24,447 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:01:24,466 INFO L206 MainTranslator]: Completed translation [2023-11-26 12:01:24,466 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24 WrapperNode [2023-11-26 12:01:24,466 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 12:01:24,467 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 12:01:24,468 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 12:01:24,468 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 12:01:24,475 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,484 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,516 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 37, statements flattened = 375 [2023-11-26 12:01:24,516 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 12:01:24,517 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 12:01:24,517 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 12:01:24,517 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 12:01:24,529 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,529 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,532 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,547 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 12:01:24,547 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,547 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,555 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,562 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,564 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,566 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,570 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 12:01:24,576 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 12:01:24,583 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 12:01:24,583 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 12:01:24,584 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (1/1) ... [2023-11-26 12:01:24,603 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:01:24,618 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:01:24,633 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:01:24,656 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 12:01:24,671 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 12:01:24,671 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 12:01:24,672 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 12:01:24,672 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 12:01:24,800 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 12:01:24,802 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 12:01:25,255 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 12:01:25,268 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 12:01:25,268 INFO L309 CfgBuilder]: Removed 4 assume(true) statements. [2023-11-26 12:01:25,270 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:01:25 BoogieIcfgContainer [2023-11-26 12:01:25,270 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 12:01:25,271 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 12:01:25,272 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 12:01:25,276 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 12:01:25,276 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:01:25,277 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 12:01:24" (1/3) ... [2023-11-26 12:01:25,278 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3c7ce17a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:01:25, skipping insertion in model container [2023-11-26 12:01:25,278 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:01:25,278 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:24" (2/3) ... [2023-11-26 12:01:25,278 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3c7ce17a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:01:25, skipping insertion in model container [2023-11-26 12:01:25,279 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:01:25,279 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:01:25" (3/3) ... [2023-11-26 12:01:25,280 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu1.cil.c [2023-11-26 12:01:25,338 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 12:01:25,338 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 12:01:25,339 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 12:01:25,339 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 12:01:25,339 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 12:01:25,339 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 12:01:25,339 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 12:01:25,339 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 12:01:25,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 128 states, 127 states have (on average 1.4803149606299213) internal successors, (188), 127 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:25,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2023-11-26 12:01:25,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:25,372 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:25,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:25,381 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:25,381 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 12:01:25,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 128 states, 127 states have (on average 1.4803149606299213) internal successors, (188), 127 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:25,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2023-11-26 12:01:25,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:25,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:25,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:25,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:25,406 INFO L748 eck$LassoCheckResult]: Stem: 30#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 43#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 122#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65#L236true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 64#L236-2true assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 124#L241-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6#L117true assume !(1 == ~P_1_pc~0); 21#L117-2true is_P_1_triggered_~__retres1~0#1 := 0; 59#L128true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 51#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 56#L383true assume !(0 != activate_threads_~tmp~1#1); 22#L383-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 55#L199true assume 1 == ~C_1_pc~0; 102#L200true assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 68#L220true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 119#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 79#L391true assume !(0 != activate_threads_~tmp___1~1#1); 3#L391-2true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 80#L445-2true [2023-11-26 12:01:25,407 INFO L750 eck$LassoCheckResult]: Loop: 80#L445-2true assume !false; 105#L446true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 97#L304true assume !true; 82#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4#L117-3true assume 1 == ~P_1_pc~0; 60#L118-1true assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 83#L128-1true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 69#is_P_1_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 34#L383-3true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 15#L383-5true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 118#L199-3true assume 1 == ~C_1_pc~0; 19#L200-1true assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 109#L220-1true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 57#is_C_1_triggered_returnLabel#2true activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 129#L391-3true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 36#L391-5true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11#L254-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 40#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 95#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 106#L464true assume !(0 == start_simulation_~tmp~3#1); 23#L464-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 26#L254-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 84#L267-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 38#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 5#L419true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 111#L426true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 125#stop_simulation_returnLabel#1true start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 27#L477true assume !(0 != start_simulation_~tmp___0~2#1); 80#L445-2true [2023-11-26 12:01:25,416 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:25,416 INFO L85 PathProgramCache]: Analyzing trace with hash -1103808071, now seen corresponding path program 1 times [2023-11-26 12:01:25,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:25,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204397647] [2023-11-26 12:01:25,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:25,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:25,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:25,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:25,707 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:25,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1204397647] [2023-11-26 12:01:25,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1204397647] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:25,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:25,709 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:25,710 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1540083119] [2023-11-26 12:01:25,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:25,716 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:25,717 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:25,717 INFO L85 PathProgramCache]: Analyzing trace with hash -144884610, now seen corresponding path program 1 times [2023-11-26 12:01:25,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:25,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341383527] [2023-11-26 12:01:25,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:25,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:25,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:25,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:25,745 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:25,745 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341383527] [2023-11-26 12:01:25,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341383527] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:25,746 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:25,746 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:01:25,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1347982685] [2023-11-26 12:01:25,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:25,748 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:25,749 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:25,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:25,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:25,786 INFO L87 Difference]: Start difference. First operand has 128 states, 127 states have (on average 1.4803149606299213) internal successors, (188), 127 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 7.0) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:25,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:25,832 INFO L93 Difference]: Finished difference Result 122 states and 172 transitions. [2023-11-26 12:01:25,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 172 transitions. [2023-11-26 12:01:25,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 90 [2023-11-26 12:01:25,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 115 states and 165 transitions. [2023-11-26 12:01:25,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2023-11-26 12:01:25,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2023-11-26 12:01:25,858 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 165 transitions. [2023-11-26 12:01:25,859 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:25,860 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 165 transitions. [2023-11-26 12:01:25,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 165 transitions. [2023-11-26 12:01:25,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2023-11-26 12:01:25,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.434782608695652) internal successors, (165), 114 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:25,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 165 transitions. [2023-11-26 12:01:25,918 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 165 transitions. [2023-11-26 12:01:25,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:25,929 INFO L428 stractBuchiCegarLoop]: Abstraction has 115 states and 165 transitions. [2023-11-26 12:01:25,929 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 12:01:25,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 165 transitions. [2023-11-26 12:01:25,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 90 [2023-11-26 12:01:25,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:25,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:25,941 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:25,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:25,943 INFO L748 eck$LassoCheckResult]: Stem: 313#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 314#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 329#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 327#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 354#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 355#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 365#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 266#L117 assume !(1 == ~P_1_pc~0); 267#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 299#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 341#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 342#L383 assume !(0 != activate_threads_~tmp~1#1); 300#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 301#L199 assume 1 == ~C_1_pc~0; 347#L200 assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 278#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 357#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 361#L391 assume !(0 != activate_threads_~tmp___1~1#1); 259#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 260#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 309#L445-2 [2023-11-26 12:01:25,945 INFO L750 eck$LassoCheckResult]: Loop: 309#L445-2 assume !false; 362#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 283#L304 assume !false; 366#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 351#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 303#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 285#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 286#L284 assume !(0 != eval_~tmp___2~0#1); 356#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 363#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 328#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 261#L117-3 assume !(1 == ~P_1_pc~0); 262#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 352#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 358#is_P_1_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 316#L383-3 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 287#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 288#L199-3 assume 1 == ~C_1_pc~0; 294#L200-1 assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 295#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 349#is_C_1_triggered_returnLabel#2 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 350#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 318#L391-5 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 279#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 280#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 325#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 367#L464 assume !(0 == start_simulation_~tmp~3#1); 273#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 302#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 306#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 323#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 264#L419 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 265#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 373#stop_simulation_returnLabel#1 start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 308#L477 assume !(0 != start_simulation_~tmp___0~2#1); 309#L445-2 [2023-11-26 12:01:25,946 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:25,947 INFO L85 PathProgramCache]: Analyzing trace with hash 484539831, now seen corresponding path program 1 times [2023-11-26 12:01:25,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:25,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1470455049] [2023-11-26 12:01:25,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:25,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:25,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:26,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:26,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:26,080 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1470455049] [2023-11-26 12:01:26,080 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1470455049] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:26,080 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:26,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:01:26,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395073127] [2023-11-26 12:01:26,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:26,081 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:26,082 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:26,082 INFO L85 PathProgramCache]: Analyzing trace with hash 771129349, now seen corresponding path program 1 times [2023-11-26 12:01:26,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:26,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807136997] [2023-11-26 12:01:26,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:26,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:26,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:26,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:26,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:26,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807136997] [2023-11-26 12:01:26,224 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807136997] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:26,224 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:26,225 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:01:26,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264458704] [2023-11-26 12:01:26,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:26,225 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:26,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:26,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:01:26,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:01:26,227 INFO L87 Difference]: Start difference. First operand 115 states and 165 transitions. cyclomatic complexity: 51 Second operand has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:26,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:26,461 INFO L93 Difference]: Finished difference Result 281 states and 389 transitions. [2023-11-26 12:01:26,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281 states and 389 transitions. [2023-11-26 12:01:26,466 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 246 [2023-11-26 12:01:26,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281 states to 281 states and 389 transitions. [2023-11-26 12:01:26,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2023-11-26 12:01:26,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2023-11-26 12:01:26,477 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281 states and 389 transitions. [2023-11-26 12:01:26,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:26,482 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281 states and 389 transitions. [2023-11-26 12:01:26,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states and 389 transitions. [2023-11-26 12:01:26,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 262. [2023-11-26 12:01:26,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 262 states, 262 states have (on average 1.3969465648854962) internal successors, (366), 261 states have internal predecessors, (366), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:26,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 366 transitions. [2023-11-26 12:01:26,513 INFO L240 hiAutomatonCegarLoop]: Abstraction has 262 states and 366 transitions. [2023-11-26 12:01:26,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:01:26,516 INFO L428 stractBuchiCegarLoop]: Abstraction has 262 states and 366 transitions. [2023-11-26 12:01:26,516 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 12:01:26,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 262 states and 366 transitions. [2023-11-26 12:01:26,523 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 239 [2023-11-26 12:01:26,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:26,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:26,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:26,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:26,525 INFO L748 eck$LassoCheckResult]: Stem: 722#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 723#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 737#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 734#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 735#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 767#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 768#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 781#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 674#L117 assume !(1 == ~P_1_pc~0); 675#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 706#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 750#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 751#L383 assume !(0 != activate_threads_~tmp~1#1); 708#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 709#L199 assume !(1 == ~C_1_pc~0); 756#L199-2 assume !(2 == ~C_1_pc~0); 687#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 688#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 770#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 774#L391 assume !(0 != activate_threads_~tmp___1~1#1); 670#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 671#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 716#L445-2 [2023-11-26 12:01:26,526 INFO L750 eck$LassoCheckResult]: Loop: 716#L445-2 assume !false; 775#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 690#L304 assume !false; 782#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 759#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 710#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 692#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 693#L284 assume !(0 != eval_~tmp___2~0#1); 769#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 779#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 736#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 668#L117-3 assume !(1 == ~P_1_pc~0); 669#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 773#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 771#is_P_1_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 725#L383-3 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 694#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 695#L199-3 assume !(1 == ~C_1_pc~0); 790#L199-5 assume !(2 == ~C_1_pc~0); 720#L209-3 is_C_1_triggered_~__retres1~1#1 := 0; 721#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 757#is_C_1_triggered_returnLabel#2 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 758#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 726#L391-5 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 727#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 683#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 684#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 733#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 783#L464 assume !(0 == start_simulation_~tmp~3#1); 680#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 707#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 713#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 731#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 672#L419 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 673#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 791#stop_simulation_returnLabel#1 start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 715#L477 assume !(0 != start_simulation_~tmp___0~2#1); 716#L445-2 [2023-11-26 12:01:26,529 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:26,529 INFO L85 PathProgramCache]: Analyzing trace with hash 1818999495, now seen corresponding path program 1 times [2023-11-26 12:01:26,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:26,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032832048] [2023-11-26 12:01:26,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:26,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:26,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:26,585 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:01:26,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:26,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:01:26,652 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:26,652 INFO L85 PathProgramCache]: Analyzing trace with hash -1040524350, now seen corresponding path program 1 times [2023-11-26 12:01:26,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:26,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288680406] [2023-11-26 12:01:26,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:26,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:26,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:26,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:26,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:26,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288680406] [2023-11-26 12:01:26,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288680406] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:26,754 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:26,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:01:26,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [182689142] [2023-11-26 12:01:26,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:26,755 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:26,755 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:26,756 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 12:01:26,756 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 12:01:26,756 INFO L87 Difference]: Start difference. First operand 262 states and 366 transitions. cyclomatic complexity: 106 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:26,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:26,878 INFO L93 Difference]: Finished difference Result 451 states and 622 transitions. [2023-11-26 12:01:26,878 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451 states and 622 transitions. [2023-11-26 12:01:26,883 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 428 [2023-11-26 12:01:26,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451 states to 451 states and 622 transitions. [2023-11-26 12:01:26,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451 [2023-11-26 12:01:26,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451 [2023-11-26 12:01:26,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451 states and 622 transitions. [2023-11-26 12:01:26,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:26,891 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451 states and 622 transitions. [2023-11-26 12:01:26,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states and 622 transitions. [2023-11-26 12:01:26,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 271. [2023-11-26 12:01:26,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.3837638376383763) internal successors, (375), 270 states have internal predecessors, (375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:26,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 375 transitions. [2023-11-26 12:01:26,907 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 375 transitions. [2023-11-26 12:01:26,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 12:01:26,908 INFO L428 stractBuchiCegarLoop]: Abstraction has 271 states and 375 transitions. [2023-11-26 12:01:26,908 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 12:01:26,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 375 transitions. [2023-11-26 12:01:26,911 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 248 [2023-11-26 12:01:26,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:26,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:26,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:26,912 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:26,912 INFO L748 eck$LassoCheckResult]: Stem: 1453#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1454#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 1470#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1467#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1468#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1500#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1501#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1518#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1404#L117 assume !(1 == ~P_1_pc~0); 1405#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1436#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1483#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1484#L383 assume !(0 != activate_threads_~tmp~1#1); 1438#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 1439#L199 assume !(1 == ~C_1_pc~0); 1489#L199-2 assume !(2 == ~C_1_pc~0); 1417#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 1418#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 1503#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1510#L391 assume !(0 != activate_threads_~tmp___1~1#1); 1400#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1401#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1448#L445-2 [2023-11-26 12:01:26,913 INFO L750 eck$LassoCheckResult]: Loop: 1448#L445-2 assume !false; 1511#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1420#L304 assume !false; 1519#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1492#L254 assume !(0 == ~P_1_st~0); 1455#L258 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 1456#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1599#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1598#L284 assume !(0 != eval_~tmp___2~0#1); 1514#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1515#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1469#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1398#L117-3 assume !(1 == ~P_1_pc~0); 1399#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 1509#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1504#is_P_1_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1505#L383-3 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1424#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 1425#L199-3 assume !(1 == ~C_1_pc~0); 1534#L199-5 assume 2 == ~C_1_pc~0; 1450#L210-1 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1; 1452#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 1490#is_C_1_triggered_returnLabel#2 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1491#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1460#L391-5 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1461#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1520#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1609#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1608#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1606#L464 assume !(0 == start_simulation_~tmp~3#1); 1607#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1444#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1445#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1464#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 1402#L419 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1403#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1535#stop_simulation_returnLabel#1 start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1447#L477 assume !(0 != start_simulation_~tmp___0~2#1); 1448#L445-2 [2023-11-26 12:01:26,913 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:26,913 INFO L85 PathProgramCache]: Analyzing trace with hash 1818999495, now seen corresponding path program 2 times [2023-11-26 12:01:26,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:26,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453419536] [2023-11-26 12:01:26,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:26,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:26,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:26,924 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:01:26,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:26,936 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:01:26,937 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:26,937 INFO L85 PathProgramCache]: Analyzing trace with hash 884081765, now seen corresponding path program 1 times [2023-11-26 12:01:26,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:26,938 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698438619] [2023-11-26 12:01:26,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:26,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:26,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:27,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:27,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:27,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698438619] [2023-11-26 12:01:27,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698438619] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:27,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:27,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:01:27,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814306940] [2023-11-26 12:01:27,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:27,051 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:27,051 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:27,052 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 12:01:27,052 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 12:01:27,052 INFO L87 Difference]: Start difference. First operand 271 states and 375 transitions. cyclomatic complexity: 106 Second operand has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:27,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:27,124 INFO L93 Difference]: Finished difference Result 466 states and 640 transitions. [2023-11-26 12:01:27,124 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 466 states and 640 transitions. [2023-11-26 12:01:27,128 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 443 [2023-11-26 12:01:27,132 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 466 states to 466 states and 640 transitions. [2023-11-26 12:01:27,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 466 [2023-11-26 12:01:27,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 466 [2023-11-26 12:01:27,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 466 states and 640 transitions. [2023-11-26 12:01:27,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:27,134 INFO L218 hiAutomatonCegarLoop]: Abstraction has 466 states and 640 transitions. [2023-11-26 12:01:27,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states and 640 transitions. [2023-11-26 12:01:27,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 283. [2023-11-26 12:01:27,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 283 states, 283 states have (on average 1.3568904593639577) internal successors, (384), 282 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:27,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 283 states to 283 states and 384 transitions. [2023-11-26 12:01:27,143 INFO L240 hiAutomatonCegarLoop]: Abstraction has 283 states and 384 transitions. [2023-11-26 12:01:27,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 12:01:27,145 INFO L428 stractBuchiCegarLoop]: Abstraction has 283 states and 384 transitions. [2023-11-26 12:01:27,145 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 12:01:27,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 283 states and 384 transitions. [2023-11-26 12:01:27,147 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 260 [2023-11-26 12:01:27,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:27,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:27,148 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:27,148 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:27,149 INFO L748 eck$LassoCheckResult]: Stem: 2202#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2203#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 2221#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2217#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2218#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2250#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2251#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2269#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2153#L117 assume !(1 == ~P_1_pc~0); 2154#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 2185#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2234#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2235#L383 assume !(0 != activate_threads_~tmp~1#1); 2186#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 2187#L199 assume !(1 == ~C_1_pc~0); 2240#L199-2 assume !(2 == ~C_1_pc~0); 2163#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 2164#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 2253#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2260#L391 assume !(0 != activate_threads_~tmp___1~1#1); 2147#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2148#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 2281#L445-2 [2023-11-26 12:01:27,149 INFO L750 eck$LassoCheckResult]: Loop: 2281#L445-2 assume !false; 2305#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2301#L304 assume !false; 2300#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2299#L254 assume !(0 == ~P_1_st~0); 2297#L258 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2296#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2295#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2293#L284 assume !(0 != eval_~tmp___2~0#1); 2292#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2291#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2290#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2149#L117-3 assume !(1 == ~P_1_pc~0); 2150#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 2362#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2360#is_P_1_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2358#L383-3 assume !(0 != activate_threads_~tmp~1#1); 2356#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 2354#L199-3 assume !(1 == ~C_1_pc~0); 2352#L199-5 assume !(2 == ~C_1_pc~0); 2349#L209-3 is_C_1_triggered_~__retres1~1#1 := 0; 2347#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 2344#is_C_1_triggered_returnLabel#2 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2342#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2340#L391-5 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2338#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2335#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2333#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2331#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2328#L464 assume !(0 == start_simulation_~tmp~3#1); 2327#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2325#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2324#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2323#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 2322#L419 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2320#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2317#stop_simulation_returnLabel#1 start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2312#L477 assume !(0 != start_simulation_~tmp___0~2#1); 2281#L445-2 [2023-11-26 12:01:27,149 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,150 INFO L85 PathProgramCache]: Analyzing trace with hash 1818999495, now seen corresponding path program 3 times [2023-11-26 12:01:27,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562129234] [2023-11-26 12:01:27,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,159 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:01:27,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,169 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:01:27,170 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,170 INFO L85 PathProgramCache]: Analyzing trace with hash 2094101156, now seen corresponding path program 1 times [2023-11-26 12:01:27,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1502700352] [2023-11-26 12:01:27,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:27,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:27,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:27,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1502700352] [2023-11-26 12:01:27,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1502700352] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:27,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:27,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:27,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388020286] [2023-11-26 12:01:27,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:27,198 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:27,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:27,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:27,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:27,199 INFO L87 Difference]: Start difference. First operand 283 states and 384 transitions. cyclomatic complexity: 103 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:27,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:27,232 INFO L93 Difference]: Finished difference Result 427 states and 570 transitions. [2023-11-26 12:01:27,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 427 states and 570 transitions. [2023-11-26 12:01:27,235 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 397 [2023-11-26 12:01:27,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 427 states to 427 states and 570 transitions. [2023-11-26 12:01:27,239 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 427 [2023-11-26 12:01:27,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 427 [2023-11-26 12:01:27,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 427 states and 570 transitions. [2023-11-26 12:01:27,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:27,241 INFO L218 hiAutomatonCegarLoop]: Abstraction has 427 states and 570 transitions. [2023-11-26 12:01:27,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 427 states and 570 transitions. [2023-11-26 12:01:27,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 427 to 427. [2023-11-26 12:01:27,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 427 states, 427 states have (on average 1.334894613583138) internal successors, (570), 426 states have internal predecessors, (570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:27,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 570 transitions. [2023-11-26 12:01:27,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 427 states and 570 transitions. [2023-11-26 12:01:27,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:27,252 INFO L428 stractBuchiCegarLoop]: Abstraction has 427 states and 570 transitions. [2023-11-26 12:01:27,252 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 12:01:27,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 427 states and 570 transitions. [2023-11-26 12:01:27,255 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 397 [2023-11-26 12:01:27,255 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:27,255 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:27,256 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:27,256 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:27,256 INFO L748 eck$LassoCheckResult]: Stem: 2916#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2917#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 2933#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2929#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2930#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2963#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2964#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2979#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2869#L117 assume !(1 == ~P_1_pc~0); 2870#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 2901#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2946#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2947#L383 assume !(0 != activate_threads_~tmp~1#1); 2902#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 2903#L199 assume !(1 == ~C_1_pc~0); 2952#L199-2 assume !(2 == ~C_1_pc~0); 2879#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 2880#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 2965#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2971#L391 assume !(0 != activate_threads_~tmp___1~1#1); 2863#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2864#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 2991#L445-2 assume !false; 3231#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 3227#L304 [2023-11-26 12:01:27,256 INFO L750 eck$LassoCheckResult]: Loop: 3227#L304 assume !false; 3152#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3153#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3167#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3235#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3234#L284 assume 0 != eval_~tmp___2~0#1; 3233#L284-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2996#L293 assume !(0 != eval_~tmp~0#1); 2997#L289 assume !(0 == ~C_1_st~0); 3227#L304 [2023-11-26 12:01:27,257 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,257 INFO L85 PathProgramCache]: Analyzing trace with hash 6828137, now seen corresponding path program 1 times [2023-11-26 12:01:27,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369074474] [2023-11-26 12:01:27,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,265 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:01:27,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,275 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:01:27,276 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,276 INFO L85 PathProgramCache]: Analyzing trace with hash 602709065, now seen corresponding path program 1 times [2023-11-26 12:01:27,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138084302] [2023-11-26 12:01:27,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,280 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:01:27,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,285 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:01:27,285 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,285 INFO L85 PathProgramCache]: Analyzing trace with hash 462446817, now seen corresponding path program 1 times [2023-11-26 12:01:27,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [366465917] [2023-11-26 12:01:27,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:27,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:27,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:27,318 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [366465917] [2023-11-26 12:01:27,318 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [366465917] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:27,318 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:27,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:01:27,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556086780] [2023-11-26 12:01:27,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:27,382 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:27,382 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:27,383 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:27,383 INFO L87 Difference]: Start difference. First operand 427 states and 570 transitions. cyclomatic complexity: 146 Second operand has 3 states, 2 states have (on average 16.5) internal successors, (33), 3 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:27,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:27,422 INFO L93 Difference]: Finished difference Result 706 states and 924 transitions. [2023-11-26 12:01:27,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 706 states and 924 transitions. [2023-11-26 12:01:27,428 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2023-11-26 12:01:27,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 706 states to 706 states and 924 transitions. [2023-11-26 12:01:27,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 706 [2023-11-26 12:01:27,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 706 [2023-11-26 12:01:27,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 706 states and 924 transitions. [2023-11-26 12:01:27,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:27,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 706 states and 924 transitions. [2023-11-26 12:01:27,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 706 states and 924 transitions. [2023-11-26 12:01:27,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 706 to 706. [2023-11-26 12:01:27,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 706 states, 706 states have (on average 1.3087818696883853) internal successors, (924), 705 states have internal predecessors, (924), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:27,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 706 states to 706 states and 924 transitions. [2023-11-26 12:01:27,457 INFO L240 hiAutomatonCegarLoop]: Abstraction has 706 states and 924 transitions. [2023-11-26 12:01:27,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:27,460 INFO L428 stractBuchiCegarLoop]: Abstraction has 706 states and 924 transitions. [2023-11-26 12:01:27,460 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 12:01:27,460 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 706 states and 924 transitions. [2023-11-26 12:01:27,464 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2023-11-26 12:01:27,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:27,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:27,467 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:27,467 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:27,467 INFO L748 eck$LassoCheckResult]: Stem: 4058#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 4059#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 4078#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4074#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4075#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 4109#L236-2 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 4110#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4455#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4454#L117 assume !(1 == ~P_1_pc~0); 4453#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 4451#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4449#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4447#L383 assume !(0 != activate_threads_~tmp~1#1); 4045#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 4046#L199 assume !(1 == ~C_1_pc~0); 4097#L199-2 assume !(2 == ~C_1_pc~0); 4141#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 4430#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 4429#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4427#L391 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4004#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4005#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 4143#L445-2 assume !false; 4512#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 4488#L304 [2023-11-26 12:01:27,468 INFO L750 eck$LassoCheckResult]: Loop: 4488#L304 assume !false; 4510#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4505#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4503#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4501#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4499#L284 assume 0 != eval_~tmp___2~0#1; 4497#L284-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4494#L293 assume !(0 != eval_~tmp~0#1); 4492#L289 assume 0 == ~C_1_st~0;havoc eval_#t~nondet7#1;eval_~tmp___1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4354#L308 assume !(0 != eval_~tmp___1~0#1); 4488#L304 [2023-11-26 12:01:27,468 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,468 INFO L85 PathProgramCache]: Analyzing trace with hash -1683962647, now seen corresponding path program 1 times [2023-11-26 12:01:27,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007723272] [2023-11-26 12:01:27,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:27,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:27,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:27,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007723272] [2023-11-26 12:01:27,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1007723272] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:27,492 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:27,492 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:27,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101657867] [2023-11-26 12:01:27,492 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:27,492 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:27,493 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,493 INFO L85 PathProgramCache]: Analyzing trace with hash 1504109555, now seen corresponding path program 1 times [2023-11-26 12:01:27,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318903472] [2023-11-26 12:01:27,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,497 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:01:27,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,501 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:01:27,558 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:27,559 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:27,559 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:27,559 INFO L87 Difference]: Start difference. First operand 706 states and 924 transitions. cyclomatic complexity: 221 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:27,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:27,569 INFO L93 Difference]: Finished difference Result 687 states and 901 transitions. [2023-11-26 12:01:27,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 687 states and 901 transitions. [2023-11-26 12:01:27,574 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2023-11-26 12:01:27,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 687 states to 687 states and 901 transitions. [2023-11-26 12:01:27,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 687 [2023-11-26 12:01:27,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 687 [2023-11-26 12:01:27,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 687 states and 901 transitions. [2023-11-26 12:01:27,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:27,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 687 states and 901 transitions. [2023-11-26 12:01:27,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 687 states and 901 transitions. [2023-11-26 12:01:27,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 687 to 687. [2023-11-26 12:01:27,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 687 states, 687 states have (on average 1.3114992721979621) internal successors, (901), 686 states have internal predecessors, (901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:27,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 687 states to 687 states and 901 transitions. [2023-11-26 12:01:27,596 INFO L240 hiAutomatonCegarLoop]: Abstraction has 687 states and 901 transitions. [2023-11-26 12:01:27,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:27,598 INFO L428 stractBuchiCegarLoop]: Abstraction has 687 states and 901 transitions. [2023-11-26 12:01:27,598 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 12:01:27,598 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 687 states and 901 transitions. [2023-11-26 12:01:27,602 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2023-11-26 12:01:27,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:27,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:27,603 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:27,603 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:27,603 INFO L748 eck$LassoCheckResult]: Stem: 5456#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 5457#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 5475#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5471#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5472#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 5503#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 5504#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5524#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 5409#L117 assume !(1 == ~P_1_pc~0); 5410#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 5441#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 5488#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5489#L383 assume !(0 != activate_threads_~tmp~1#1); 5442#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 5443#L199 assume !(1 == ~C_1_pc~0); 5494#L199-2 assume !(2 == ~C_1_pc~0); 5419#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 5420#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 5505#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5515#L391 assume !(0 != activate_threads_~tmp___1~1#1); 5403#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5404#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 5541#L445-2 assume !false; 5751#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 5725#L304 [2023-11-26 12:01:27,603 INFO L750 eck$LassoCheckResult]: Loop: 5725#L304 assume !false; 5746#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5742#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5740#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5738#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5736#L284 assume 0 != eval_~tmp___2~0#1; 5733#L284-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5730#L293 assume !(0 != eval_~tmp~0#1); 5726#L289 assume 0 == ~C_1_st~0;havoc eval_#t~nondet7#1;eval_~tmp___1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5724#L308 assume !(0 != eval_~tmp___1~0#1); 5725#L304 [2023-11-26 12:01:27,604 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,604 INFO L85 PathProgramCache]: Analyzing trace with hash 6828137, now seen corresponding path program 2 times [2023-11-26 12:01:27,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723303040] [2023-11-26 12:01:27,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,611 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:01:27,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,633 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:01:27,633 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,634 INFO L85 PathProgramCache]: Analyzing trace with hash 1504109555, now seen corresponding path program 2 times [2023-11-26 12:01:27,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051140223] [2023-11-26 12:01:27,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,638 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:01:27,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,641 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:01:27,642 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,642 INFO L85 PathProgramCache]: Analyzing trace with hash 1450947163, now seen corresponding path program 1 times [2023-11-26 12:01:27,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246486667] [2023-11-26 12:01:27,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,650 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:01:27,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:27,660 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:01:28,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:28,432 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:01:28,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:01:28,531 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.11 12:01:28 BoogieIcfgContainer [2023-11-26 12:01:28,531 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-26 12:01:28,532 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-26 12:01:28,532 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-26 12:01:28,532 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-26 12:01:28,533 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:01:25" (3/4) ... [2023-11-26 12:01:28,534 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-26 12:01:28,597 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/witness.graphml [2023-11-26 12:01:28,597 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-26 12:01:28,598 INFO L158 Benchmark]: Toolchain (without parser) took 4462.85ms. Allocated memory was 176.2MB in the beginning and 211.8MB in the end (delta: 35.7MB). Free memory was 145.3MB in the beginning and 82.5MB in the end (delta: 62.8MB). Peak memory consumption was 97.5MB. Max. memory is 16.1GB. [2023-11-26 12:01:28,598 INFO L158 Benchmark]: CDTParser took 0.25ms. Allocated memory is still 134.2MB. Free memory is still 106.2MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 12:01:28,599 INFO L158 Benchmark]: CACSL2BoogieTranslator took 328.26ms. Allocated memory is still 176.2MB. Free memory was 145.1MB in the beginning and 134.9MB in the end (delta: 10.2MB). Peak memory consumption was 11.0MB. Max. memory is 16.1GB. [2023-11-26 12:01:28,599 INFO L158 Benchmark]: Boogie Procedure Inliner took 48.89ms. Allocated memory is still 176.2MB. Free memory was 134.9MB in the beginning and 132.3MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-26 12:01:28,599 INFO L158 Benchmark]: Boogie Preprocessor took 57.96ms. Allocated memory is still 176.2MB. Free memory was 132.3MB in the beginning and 129.4MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 12:01:28,600 INFO L158 Benchmark]: RCFGBuilder took 694.80ms. Allocated memory is still 176.2MB. Free memory was 129.4MB in the beginning and 127.6MB in the end (delta: 1.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2023-11-26 12:01:28,600 INFO L158 Benchmark]: BuchiAutomizer took 3260.11ms. Allocated memory was 176.2MB in the beginning and 211.8MB in the end (delta: 35.7MB). Free memory was 127.6MB in the beginning and 86.7MB in the end (delta: 40.9MB). Peak memory consumption was 78.5MB. Max. memory is 16.1GB. [2023-11-26 12:01:28,601 INFO L158 Benchmark]: Witness Printer took 65.29ms. Allocated memory is still 211.8MB. Free memory was 86.7MB in the beginning and 82.5MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 12:01:28,603 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25ms. Allocated memory is still 134.2MB. Free memory is still 106.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 328.26ms. Allocated memory is still 176.2MB. Free memory was 145.1MB in the beginning and 134.9MB in the end (delta: 10.2MB). Peak memory consumption was 11.0MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 48.89ms. Allocated memory is still 176.2MB. Free memory was 134.9MB in the beginning and 132.3MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 57.96ms. Allocated memory is still 176.2MB. Free memory was 132.3MB in the beginning and 129.4MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 694.80ms. Allocated memory is still 176.2MB. Free memory was 129.4MB in the beginning and 127.6MB in the end (delta: 1.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 3260.11ms. Allocated memory was 176.2MB in the beginning and 211.8MB in the end (delta: 35.7MB). Free memory was 127.6MB in the beginning and 86.7MB in the end (delta: 40.9MB). Peak memory consumption was 78.5MB. Max. memory is 16.1GB. * Witness Printer took 65.29ms. Allocated memory is still 211.8MB. Free memory was 86.7MB in the beginning and 82.5MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 7 terminating modules (7 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.7 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 687 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.1s and 8 iterations. TraceHistogramMax:1. Analysis of lassos took 2.1s. Construction of modules took 0.2s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 0. Minimization of det autom 7. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 7 MinimizatonAttempts, 382 StatesRemovedByMinimization, 3 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1224 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1224 mSDsluCounter, 2553 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1428 mSDsCounter, 60 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 184 IncrementalHoareTripleChecker+Invalid, 244 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 60 mSolverCounterUnsat, 1125 mSDtfsCounter, 184 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN1 SILU0 SILI2 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 279]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int C_1_pc ; [L133] int C_1_st ; [L134] int C_1_i ; [L135] int C_1_ev ; [L136] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L500] int count ; [L501] int __retres2 ; [L505] num = 0 [L506] i = 0 [L507] max_loop = 2 [L509] timer = 0 [L510] P_1_pc = 0 [L511] C_1_pc = 0 [L513] count = 0 [L514] CALL init_model() [L493] P_1_i = 1 [L494] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L514] RET init_model() [L515] CALL start_simulation() [L431] int kernel_st ; [L432] int tmp ; [L433] int tmp___0 ; [L437] kernel_st = 0 [L438] FCALL update_channels() [L439] CALL init_threads() [L236] COND TRUE (int )P_1_i == 1 [L237] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L241] COND TRUE (int )C_1_i == 1 [L242] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L439] RET init_threads() [L440] FCALL fire_delta_events() [L441] CALL activate_threads() [L375] int tmp ; [L376] int tmp___0 ; [L377] int tmp___1 ; [L381] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L381] RET, EXPR is_P_1_triggered() [L381] tmp = is_P_1_triggered() [L383] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0, tmp=0] [L389] CALL, EXPR is_C_1_triggered() [L196] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L209] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L219] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L221] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L389] RET, EXPR is_C_1_triggered() [L389] tmp___1 = is_C_1_triggered() [L391] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0, tmp=0, tmp___1=0] [L441] RET activate_threads() [L442] FCALL reset_delta_events() [L445] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, timer=0] [L448] kernel_st = 1 [L449] CALL eval() [L272] int tmp ; [L273] int tmp___0 ; [L274] int tmp___1 ; [L275] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L279] COND TRUE 1 [L282] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE (int )P_1_st == 0 [L255] __retres1 = 1 [L268] return (__retres1); [L282] RET, EXPR exists_runnable_thread() [L282] tmp___2 = exists_runnable_thread() [L284] COND TRUE \read(tmp___2) [L289] COND TRUE (int )P_1_st == 0 [L291] tmp = __VERIFIER_nondet_int() [L293] COND FALSE !(\read(tmp)) [L304] COND TRUE (int )C_1_st == 0 [L306] tmp___1 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 279]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int C_1_pc ; [L133] int C_1_st ; [L134] int C_1_i ; [L135] int C_1_ev ; [L136] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L500] int count ; [L501] int __retres2 ; [L505] num = 0 [L506] i = 0 [L507] max_loop = 2 [L509] timer = 0 [L510] P_1_pc = 0 [L511] C_1_pc = 0 [L513] count = 0 [L514] CALL init_model() [L493] P_1_i = 1 [L494] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L514] RET init_model() [L515] CALL start_simulation() [L431] int kernel_st ; [L432] int tmp ; [L433] int tmp___0 ; [L437] kernel_st = 0 [L438] FCALL update_channels() [L439] CALL init_threads() [L236] COND TRUE (int )P_1_i == 1 [L237] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L241] COND TRUE (int )C_1_i == 1 [L242] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L439] RET init_threads() [L440] FCALL fire_delta_events() [L441] CALL activate_threads() [L375] int tmp ; [L376] int tmp___0 ; [L377] int tmp___1 ; [L381] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L381] RET, EXPR is_P_1_triggered() [L381] tmp = is_P_1_triggered() [L383] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0, tmp=0] [L389] CALL, EXPR is_C_1_triggered() [L196] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L209] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L219] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L221] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L389] RET, EXPR is_C_1_triggered() [L389] tmp___1 = is_C_1_triggered() [L391] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0, tmp=0, tmp___1=0] [L441] RET activate_threads() [L442] FCALL reset_delta_events() [L445] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, timer=0] [L448] kernel_st = 1 [L449] CALL eval() [L272] int tmp ; [L273] int tmp___0 ; [L274] int tmp___1 ; [L275] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L279] COND TRUE 1 [L282] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE (int )P_1_st == 0 [L255] __retres1 = 1 [L268] return (__retres1); [L282] RET, EXPR exists_runnable_thread() [L282] tmp___2 = exists_runnable_thread() [L284] COND TRUE \read(tmp___2) [L289] COND TRUE (int )P_1_st == 0 [L291] tmp = __VERIFIER_nondet_int() [L293] COND FALSE !(\read(tmp)) [L304] COND TRUE (int )C_1_st == 0 [L306] tmp___1 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-26 12:01:28,660 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5316706-a5e3-4690-9ef5-b3ad3d7fa7a4/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)