./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:45:22,696 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:45:22,803 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:45:22,811 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:45:22,811 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:45:22,852 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:45:22,853 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:45:22,853 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:45:22,854 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:45:22,859 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:45:22,861 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:45:22,861 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:45:22,862 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:45:22,864 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:45:22,864 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:45:22,865 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:45:22,865 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:45:22,866 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:45:22,866 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:45:22,867 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:45:22,868 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:45:22,869 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:45:22,869 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:45:22,870 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:45:22,870 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:45:22,871 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:45:22,871 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:45:22,872 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:45:22,872 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:45:22,873 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:45:22,874 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:45:22,874 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:45:22,875 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:45:22,875 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:45:22,875 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:45:22,876 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:45:22,876 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:45:22,877 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:45:22,877 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 [2023-11-26 11:45:23,177 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:45:23,230 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:45:23,233 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:45:23,234 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:45:23,235 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:45:23,237 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2023-11-26 11:45:26,311 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:45:26,697 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:45:26,697 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2023-11-26 11:45:26,718 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/data/57351cf1e/cd347e3a91a749d4943ef12c04c47890/FLAGdbf2fffa5 [2023-11-26 11:45:26,740 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/data/57351cf1e/cd347e3a91a749d4943ef12c04c47890 [2023-11-26 11:45:26,749 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:45:26,754 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:45:26,759 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:45:26,759 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:45:26,765 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:45:26,766 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:45:26" (1/1) ... [2023-11-26 11:45:26,767 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@384df3ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:26, skipping insertion in model container [2023-11-26 11:45:26,767 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:45:26" (1/1) ... [2023-11-26 11:45:26,825 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:45:27,027 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:45:27,042 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:45:27,106 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:45:27,125 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:45:27,125 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27 WrapperNode [2023-11-26 11:45:27,126 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:45:27,127 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:45:27,127 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:45:27,127 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:45:27,135 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,145 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,198 INFO L138 Inliner]: procedures = 34, calls = 42, calls flagged for inlining = 37, calls inlined = 65, statements flattened = 836 [2023-11-26 11:45:27,199 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:45:27,200 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:45:27,200 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:45:27,200 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:45:27,212 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,212 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,219 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,238 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 11:45:27,239 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,239 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,255 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,267 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,270 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,274 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,280 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:45:27,281 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:45:27,281 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:45:27,281 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:45:27,282 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (1/1) ... [2023-11-26 11:45:27,288 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:45:27,302 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:45:27,324 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:45:27,326 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:45:27,360 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:45:27,360 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:45:27,360 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:45:27,360 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:45:27,441 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:45:27,443 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:45:28,349 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:45:28,379 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:45:28,382 INFO L309 CfgBuilder]: Removed 6 assume(true) statements. [2023-11-26 11:45:28,384 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:45:28 BoogieIcfgContainer [2023-11-26 11:45:28,384 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:45:28,386 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:45:28,386 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:45:28,390 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:45:28,391 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:45:28,391 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:45:26" (1/3) ... [2023-11-26 11:45:28,392 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@182f705f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:45:28, skipping insertion in model container [2023-11-26 11:45:28,393 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:45:28,395 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:45:27" (2/3) ... [2023-11-26 11:45:28,397 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@182f705f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:45:28, skipping insertion in model container [2023-11-26 11:45:28,397 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:45:28,398 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:45:28" (3/3) ... [2023-11-26 11:45:28,399 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2023-11-26 11:45:28,462 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:45:28,463 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:45:28,463 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:45:28,463 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:45:28,463 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:45:28,463 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:45:28,464 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:45:28,464 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:45:28,470 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:28,509 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2023-11-26 11:45:28,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:28,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:28,521 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:28,521 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:28,521 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:45:28,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:28,539 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2023-11-26 11:45:28,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:28,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:28,543 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:28,543 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:28,553 INFO L748 eck$LassoCheckResult]: Stem: 211#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 222#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 331#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 219#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 288#L304true assume !(1 == ~m_i~0);~m_st~0 := 2; 124#L304-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 27#L309-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 242#L314-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 139#L319-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L441true assume !(0 == ~M_E~0); 122#L441-2true assume !(0 == ~T1_E~0); 258#L446-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 96#L451-1true assume !(0 == ~T3_E~0); 279#L456-1true assume !(0 == ~E_M~0); 234#L461-1true assume !(0 == ~E_1~0); 254#L466-1true assume !(0 == ~E_2~0); 303#L471-1true assume !(0 == ~E_3~0); 49#L476-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87#L220true assume 1 == ~m_pc~0; 268#L221true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 105#L231true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67#L543true assume !(0 != activate_threads_~tmp~1#1); 329#L543-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 207#L239true assume !(1 == ~t1_pc~0); 230#L239-2true is_transmit1_triggered_~__retres1~1#1 := 0; 275#L250true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 212#L551true assume !(0 != activate_threads_~tmp___0~0#1); 333#L551-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213#L258true assume 1 == ~t2_pc~0; 252#L259true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86#L269true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 228#L559true assume !(0 != activate_threads_~tmp___1~0#1); 131#L559-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173#L277true assume !(1 == ~t3_pc~0); 330#L277-2true is_transmit3_triggered_~__retres1~3#1 := 0; 38#L288true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64#L567true assume !(0 != activate_threads_~tmp___2~0#1); 93#L567-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311#L489true assume !(1 == ~M_E~0); 231#L489-2true assume !(1 == ~T1_E~0); 151#L494-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 59#L499-1true assume !(1 == ~T3_E~0); 125#L504-1true assume !(1 == ~E_M~0); 267#L509-1true assume !(1 == ~E_1~0); 51#L514-1true assume !(1 == ~E_2~0); 181#L519-1true assume !(1 == ~E_3~0); 56#L524-1true assume { :end_inline_reset_delta_events } true; 37#L690-2true [2023-11-26 11:45:28,555 INFO L750 eck$LassoCheckResult]: Loop: 37#L690-2true assume !false; 52#L691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 192#L416-1true assume false; 114#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 154#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199#L441-3true assume 0 == ~M_E~0;~M_E~0 := 1; 9#L441-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 260#L446-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 195#L451-3true assume !(0 == ~T3_E~0); 35#L456-3true assume 0 == ~E_M~0;~E_M~0 := 1; 72#L461-3true assume 0 == ~E_1~0;~E_1~0 := 1; 156#L466-3true assume 0 == ~E_2~0;~E_2~0 := 1; 263#L471-3true assume 0 == ~E_3~0;~E_3~0 := 1; 65#L476-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106#L220-15true assume !(1 == ~m_pc~0); 162#L220-17true is_master_triggered_~__retres1~0#1 := 0; 210#L231-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107#is_master_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 224#L543-15true assume !(0 != activate_threads_~tmp~1#1); 132#L543-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123#L239-15true assume !(1 == ~t1_pc~0); 266#L239-17true is_transmit1_triggered_~__retres1~1#1 := 0; 286#L250-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28#L551-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 321#L551-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 320#L258-15true assume !(1 == ~t2_pc~0); 95#L258-17true is_transmit2_triggered_~__retres1~2#1 := 0; 283#L269-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 284#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 338#L559-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 237#L559-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307#L277-15true assume !(1 == ~t3_pc~0); 14#L277-17true is_transmit3_triggered_~__retres1~3#1 := 0; 332#L288-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 274#L567-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33#L567-17true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29#L489-3true assume 1 == ~M_E~0;~M_E~0 := 2; 176#L489-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 225#L494-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 305#L499-3true assume !(1 == ~T3_E~0); 108#L504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 18#L509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 304#L514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 167#L519-3true assume 1 == ~E_3~0;~E_3~0 := 2; 42#L524-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 53#L332-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 57#L354-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 287#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 152#L709true assume !(0 == start_simulation_~tmp~3#1); 8#L709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 116#L332-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 55#L354-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 47#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 54#L664true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 157#L671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 178#stop_simulation_returnLabel#1true start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 85#L722true assume !(0 != start_simulation_~tmp___0~1#1); 37#L690-2true [2023-11-26 11:45:28,561 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:28,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2023-11-26 11:45:28,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:28,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036103536] [2023-11-26 11:45:28,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:28,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:28,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:28,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:28,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:28,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036103536] [2023-11-26 11:45:28,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036103536] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:28,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:28,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:45:28,881 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135774070] [2023-11-26 11:45:28,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:28,886 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:45:28,888 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:28,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1950122617, now seen corresponding path program 1 times [2023-11-26 11:45:28,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:28,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1886036123] [2023-11-26 11:45:28,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:28,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:28,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:28,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:28,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:28,971 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1886036123] [2023-11-26 11:45:28,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1886036123] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:28,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:28,973 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:45:28,973 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1241171354] [2023-11-26 11:45:28,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:28,975 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:28,976 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:29,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:29,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:29,033 INFO L87 Difference]: Start difference. First operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:29,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:29,123 INFO L93 Difference]: Finished difference Result 333 states and 495 transitions. [2023-11-26 11:45:29,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 333 states and 495 transitions. [2023-11-26 11:45:29,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-26 11:45:29,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 333 states to 327 states and 489 transitions. [2023-11-26 11:45:29,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2023-11-26 11:45:29,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2023-11-26 11:45:29,142 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 489 transitions. [2023-11-26 11:45:29,145 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:29,145 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 489 transitions. [2023-11-26 11:45:29,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 489 transitions. [2023-11-26 11:45:29,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2023-11-26 11:45:29,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.4954128440366972) internal successors, (489), 326 states have internal predecessors, (489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:29,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 489 transitions. [2023-11-26 11:45:29,200 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 489 transitions. [2023-11-26 11:45:29,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:29,205 INFO L428 stractBuchiCegarLoop]: Abstraction has 327 states and 489 transitions. [2023-11-26 11:45:29,205 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:45:29,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 489 transitions. [2023-11-26 11:45:29,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-26 11:45:29,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:29,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:29,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:29,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:29,212 INFO L748 eck$LassoCheckResult]: Stem: 956#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 969#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 967#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 968#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 887#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 737#L309-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 738#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 906#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 745#L441 assume !(0 == ~M_E~0); 746#L441-2 assume !(0 == ~T1_E~0); 883#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 850#L451-1 assume !(0 == ~T3_E~0); 851#L456-1 assume !(0 == ~E_M~0); 973#L461-1 assume !(0 == ~E_1~0); 974#L466-1 assume !(0 == ~E_2~0); 984#L471-1 assume !(0 == ~E_3~0); 780#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 781#L220 assume 1 == ~m_pc~0; 840#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 813#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 864#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 808#L543 assume !(0 != activate_threads_~tmp~1#1); 809#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 955#L239 assume !(1 == ~t1_pc~0); 953#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 954#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 776#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 777#L551 assume !(0 != activate_threads_~tmp___0~0#1); 958#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 959#L258 assume 1 == ~t2_pc~0; 960#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 837#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 838#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 971#L559 assume !(0 != activate_threads_~tmp___1~0#1); 895#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 896#L277 assume !(1 == ~t3_pc~0); 934#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 756#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 712#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 713#L567 assume !(0 != activate_threads_~tmp___2~0#1); 804#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 845#L489 assume !(1 == ~M_E~0); 972#L489-2 assume !(1 == ~T1_E~0); 917#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 795#L499-1 assume !(1 == ~T3_E~0); 796#L504-1 assume !(1 == ~E_M~0); 888#L509-1 assume !(1 == ~E_1~0); 782#L514-1 assume !(1 == ~E_2~0); 783#L519-1 assume !(1 == ~E_3~0); 789#L524-1 assume { :end_inline_reset_delta_events } true; 754#L690-2 [2023-11-26 11:45:29,212 INFO L750 eck$LassoCheckResult]: Loop: 754#L690-2 assume !false; 755#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 784#L416-1 assume !false; 818#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 819#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 763#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 714#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 715#L369 assume !(0 != eval_~tmp~0#1); 874#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 875#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 919#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 695#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 696#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 944#L451-3 assume !(0 == ~T3_E~0); 750#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 751#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 817#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 921#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 806#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 807#L220-15 assume 1 == ~m_pc~0; 701#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 702#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 865#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 866#L543-15 assume !(0 != activate_threads_~tmp~1#1); 894#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 884#L239-15 assume 1 == ~t1_pc~0; 885#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 987#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 735#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 736#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1005#L258-15 assume 1 == ~t2_pc~0; 918#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 847#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 996#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 975#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 976#L277-15 assume 1 == ~t3_pc~0; 816#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 708#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 980#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 981#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 747#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 739#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 740#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 937#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 970#L499-3 assume !(1 == ~T3_E~0); 863#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 716#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 717#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 928#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 764#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 765#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 786#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 790#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 916#L709 assume !(0 == start_simulation_~tmp~3#1); 691#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 692#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 788#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 770#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 787#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 920#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 836#L722 assume !(0 != start_simulation_~tmp___0~1#1); 754#L690-2 [2023-11-26 11:45:29,213 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:29,213 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2023-11-26 11:45:29,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:29,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1890762017] [2023-11-26 11:45:29,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:29,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:29,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:29,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:29,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:29,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1890762017] [2023-11-26 11:45:29,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1890762017] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:29,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:29,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:45:29,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3648944] [2023-11-26 11:45:29,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:29,274 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:45:29,275 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:29,275 INFO L85 PathProgramCache]: Analyzing trace with hash 67370114, now seen corresponding path program 1 times [2023-11-26 11:45:29,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:29,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350297661] [2023-11-26 11:45:29,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:29,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:29,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:29,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:29,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:29,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1350297661] [2023-11-26 11:45:29,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1350297661] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:29,519 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:29,520 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:45:29,520 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120049650] [2023-11-26 11:45:29,520 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:29,521 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:29,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:29,521 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:29,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:29,522 INFO L87 Difference]: Start difference. First operand 327 states and 489 transitions. cyclomatic complexity: 163 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:29,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:29,549 INFO L93 Difference]: Finished difference Result 327 states and 488 transitions. [2023-11-26 11:45:29,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 488 transitions. [2023-11-26 11:45:29,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-26 11:45:29,560 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 327 states and 488 transitions. [2023-11-26 11:45:29,560 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2023-11-26 11:45:29,562 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2023-11-26 11:45:29,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 488 transitions. [2023-11-26 11:45:29,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:29,570 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 488 transitions. [2023-11-26 11:45:29,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 488 transitions. [2023-11-26 11:45:29,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2023-11-26 11:45:29,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.492354740061162) internal successors, (488), 326 states have internal predecessors, (488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:29,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 488 transitions. [2023-11-26 11:45:29,603 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 488 transitions. [2023-11-26 11:45:29,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:29,606 INFO L428 stractBuchiCegarLoop]: Abstraction has 327 states and 488 transitions. [2023-11-26 11:45:29,606 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:45:29,606 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 488 transitions. [2023-11-26 11:45:29,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-26 11:45:29,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:29,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:29,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:29,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:29,613 INFO L748 eck$LassoCheckResult]: Stem: 1619#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1632#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1630#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1631#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 1551#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1400#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1401#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1569#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1408#L441 assume !(0 == ~M_E~0); 1409#L441-2 assume !(0 == ~T1_E~0); 1546#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1511#L451-1 assume !(0 == ~T3_E~0); 1512#L456-1 assume !(0 == ~E_M~0); 1636#L461-1 assume !(0 == ~E_1~0); 1637#L466-1 assume !(0 == ~E_2~0); 1647#L471-1 assume !(0 == ~E_3~0); 1441#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1442#L220 assume 1 == ~m_pc~0; 1502#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1476#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1526#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1471#L543 assume !(0 != activate_threads_~tmp~1#1); 1472#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1618#L239 assume !(1 == ~t1_pc~0); 1616#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1617#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1439#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1440#L551 assume !(0 != activate_threads_~tmp___0~0#1); 1621#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1622#L258 assume 1 == ~t2_pc~0; 1623#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1500#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1634#L559 assume !(0 != activate_threads_~tmp___1~0#1); 1557#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1558#L277 assume !(1 == ~t3_pc~0); 1596#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1419#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1375#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1376#L567 assume !(0 != activate_threads_~tmp___2~0#1); 1467#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1508#L489 assume !(1 == ~M_E~0); 1635#L489-2 assume !(1 == ~T1_E~0); 1579#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L499-1 assume !(1 == ~T3_E~0); 1457#L504-1 assume !(1 == ~E_M~0); 1550#L509-1 assume !(1 == ~E_1~0); 1445#L514-1 assume !(1 == ~E_2~0); 1446#L519-1 assume !(1 == ~E_3~0); 1452#L524-1 assume { :end_inline_reset_delta_events } true; 1417#L690-2 [2023-11-26 11:45:29,613 INFO L750 eck$LassoCheckResult]: Loop: 1417#L690-2 assume !false; 1418#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1447#L416-1 assume !false; 1481#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1482#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1426#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1377#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1378#L369 assume !(0 != eval_~tmp~0#1); 1536#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1537#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1581#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1358#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1359#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1607#L451-3 assume !(0 == ~T3_E~0); 1413#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1414#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1480#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1583#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1469#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1470#L220-15 assume 1 == ~m_pc~0; 1364#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1365#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1527#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1528#L543-15 assume !(0 != activate_threads_~tmp~1#1); 1559#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1547#L239-15 assume 1 == ~t1_pc~0; 1548#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1650#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1506#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1398#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1399#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1668#L258-15 assume !(1 == ~t2_pc~0); 1509#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 1510#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1658#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1659#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1638#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1639#L277-15 assume 1 == ~t3_pc~0; 1479#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1371#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1643#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1644#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1410#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1402#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1403#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1600#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1633#L499-3 assume !(1 == ~T3_E~0); 1529#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1379#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1380#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1591#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1427#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1428#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1449#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1453#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1580#L709 assume !(0 == start_simulation_~tmp~3#1); 1356#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1357#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1451#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1437#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1438#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1450#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1584#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1499#L722 assume !(0 != start_simulation_~tmp___0~1#1); 1417#L690-2 [2023-11-26 11:45:29,614 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:29,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2023-11-26 11:45:29,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:29,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1146655150] [2023-11-26 11:45:29,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:29,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:29,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:29,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:29,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:29,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1146655150] [2023-11-26 11:45:29,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1146655150] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:29,707 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:29,710 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:45:29,710 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568624557] [2023-11-26 11:45:29,710 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:29,711 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:45:29,711 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:29,712 INFO L85 PathProgramCache]: Analyzing trace with hash -1509187645, now seen corresponding path program 1 times [2023-11-26 11:45:29,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:29,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413987836] [2023-11-26 11:45:29,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:29,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:29,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:29,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:29,887 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:29,888 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413987836] [2023-11-26 11:45:29,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413987836] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:29,888 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:29,888 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:45:29,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2033989336] [2023-11-26 11:45:29,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:29,889 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:29,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:29,890 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:29,890 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:29,890 INFO L87 Difference]: Start difference. First operand 327 states and 488 transitions. cyclomatic complexity: 162 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:29,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:29,903 INFO L93 Difference]: Finished difference Result 327 states and 487 transitions. [2023-11-26 11:45:29,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 487 transitions. [2023-11-26 11:45:29,907 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-26 11:45:29,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 327 states and 487 transitions. [2023-11-26 11:45:29,910 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2023-11-26 11:45:29,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2023-11-26 11:45:29,911 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 487 transitions. [2023-11-26 11:45:29,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:29,912 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 487 transitions. [2023-11-26 11:45:29,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 487 transitions. [2023-11-26 11:45:29,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2023-11-26 11:45:29,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.489296636085627) internal successors, (487), 326 states have internal predecessors, (487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:29,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 487 transitions. [2023-11-26 11:45:29,925 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 487 transitions. [2023-11-26 11:45:29,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:29,927 INFO L428 stractBuchiCegarLoop]: Abstraction has 327 states and 487 transitions. [2023-11-26 11:45:29,927 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:45:29,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 487 transitions. [2023-11-26 11:45:29,929 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-26 11:45:29,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:29,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:29,932 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:29,932 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:29,934 INFO L748 eck$LassoCheckResult]: Stem: 2282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2295#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2293#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2294#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 2213#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2061#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2062#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2232#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2071#L441 assume !(0 == ~M_E~0); 2072#L441-2 assume !(0 == ~T1_E~0); 2209#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2174#L451-1 assume !(0 == ~T3_E~0); 2175#L456-1 assume !(0 == ~E_M~0); 2299#L461-1 assume !(0 == ~E_1~0); 2300#L466-1 assume !(0 == ~E_2~0); 2310#L471-1 assume !(0 == ~E_3~0); 2104#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2105#L220 assume 1 == ~m_pc~0; 2165#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2139#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2189#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2134#L543 assume !(0 != activate_threads_~tmp~1#1); 2135#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2281#L239 assume !(1 == ~t1_pc~0); 2279#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2280#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2103#L551 assume !(0 != activate_threads_~tmp___0~0#1); 2284#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2285#L258 assume 1 == ~t2_pc~0; 2286#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2163#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2164#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2297#L559 assume !(0 != activate_threads_~tmp___1~0#1); 2220#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2221#L277 assume !(1 == ~t3_pc~0); 2259#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2082#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2038#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2039#L567 assume !(0 != activate_threads_~tmp___2~0#1); 2130#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2171#L489 assume !(1 == ~M_E~0); 2298#L489-2 assume !(1 == ~T1_E~0); 2242#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2119#L499-1 assume !(1 == ~T3_E~0); 2120#L504-1 assume !(1 == ~E_M~0); 2214#L509-1 assume !(1 == ~E_1~0); 2108#L514-1 assume !(1 == ~E_2~0); 2109#L519-1 assume !(1 == ~E_3~0); 2115#L524-1 assume { :end_inline_reset_delta_events } true; 2080#L690-2 [2023-11-26 11:45:29,935 INFO L750 eck$LassoCheckResult]: Loop: 2080#L690-2 assume !false; 2081#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2110#L416-1 assume !false; 2144#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2145#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2089#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2040#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2041#L369 assume !(0 != eval_~tmp~0#1); 2199#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2200#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2244#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2021#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2022#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2270#L451-3 assume !(0 == ~T3_E~0); 2076#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2077#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2143#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2246#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2132#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2133#L220-15 assume 1 == ~m_pc~0; 2027#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2028#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2190#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2191#L543-15 assume !(0 != activate_threads_~tmp~1#1); 2222#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2210#L239-15 assume 1 == ~t1_pc~0; 2211#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2313#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2169#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2063#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2064#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2331#L258-15 assume 1 == ~t2_pc~0; 2245#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2173#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2321#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2322#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2301#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2302#L277-15 assume !(1 == ~t3_pc~0); 2033#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2034#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2306#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2307#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2073#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2065#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2066#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2263#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2296#L499-3 assume !(1 == ~T3_E~0); 2192#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2042#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2043#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2254#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2090#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2091#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2112#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2116#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2243#L709 assume !(0 == start_simulation_~tmp~3#1); 2019#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2020#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2114#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2100#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2101#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2113#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2247#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2162#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2080#L690-2 [2023-11-26 11:45:29,935 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:29,935 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2023-11-26 11:45:29,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:29,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728927102] [2023-11-26 11:45:29,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:29,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:29,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:30,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:30,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:30,035 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [728927102] [2023-11-26 11:45:30,035 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [728927102] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:30,035 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:30,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:45:30,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426358126] [2023-11-26 11:45:30,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:30,036 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:45:30,036 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:30,036 INFO L85 PathProgramCache]: Analyzing trace with hash -1605147517, now seen corresponding path program 1 times [2023-11-26 11:45:30,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:30,037 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [710797947] [2023-11-26 11:45:30,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:30,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:30,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:30,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:30,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:30,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [710797947] [2023-11-26 11:45:30,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [710797947] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:30,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:30,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:45:30,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044708945] [2023-11-26 11:45:30,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:30,104 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:30,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:30,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:45:30,104 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:45:30,105 INFO L87 Difference]: Start difference. First operand 327 states and 487 transitions. cyclomatic complexity: 161 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:30,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:30,243 INFO L93 Difference]: Finished difference Result 569 states and 842 transitions. [2023-11-26 11:45:30,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 569 states and 842 transitions. [2023-11-26 11:45:30,249 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2023-11-26 11:45:30,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 569 states to 569 states and 842 transitions. [2023-11-26 11:45:30,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 569 [2023-11-26 11:45:30,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 569 [2023-11-26 11:45:30,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 569 states and 842 transitions. [2023-11-26 11:45:30,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:30,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 569 states and 842 transitions. [2023-11-26 11:45:30,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 569 states and 842 transitions. [2023-11-26 11:45:30,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 569 to 569. [2023-11-26 11:45:30,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 569 states, 569 states have (on average 1.4797891036906854) internal successors, (842), 568 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:30,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 842 transitions. [2023-11-26 11:45:30,297 INFO L240 hiAutomatonCegarLoop]: Abstraction has 569 states and 842 transitions. [2023-11-26 11:45:30,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:45:30,301 INFO L428 stractBuchiCegarLoop]: Abstraction has 569 states and 842 transitions. [2023-11-26 11:45:30,302 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:45:30,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 569 states and 842 transitions. [2023-11-26 11:45:30,307 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2023-11-26 11:45:30,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:30,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:30,311 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:30,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:30,318 INFO L748 eck$LassoCheckResult]: Stem: 3218#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3234#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3231#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3232#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 3128#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2969#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2970#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3148#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2980#L441 assume !(0 == ~M_E~0); 2981#L441-2 assume !(0 == ~T1_E~0); 3124#L446-1 assume !(0 == ~T2_E~0); 3086#L451-1 assume !(0 == ~T3_E~0); 3087#L456-1 assume !(0 == ~E_M~0); 3241#L461-1 assume !(0 == ~E_1~0); 3242#L466-1 assume !(0 == ~E_2~0); 3255#L471-1 assume !(0 == ~E_3~0); 3013#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3014#L220 assume 1 == ~m_pc~0; 3076#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3049#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3101#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3044#L543 assume !(0 != activate_threads_~tmp~1#1); 3045#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3216#L239 assume !(1 == ~t1_pc~0); 3214#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3215#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3011#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3012#L551 assume !(0 != activate_threads_~tmp___0~0#1); 3220#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3221#L258 assume 1 == ~t2_pc~0; 3222#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3074#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3075#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3237#L559 assume !(0 != activate_threads_~tmp___1~0#1); 3136#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3137#L277 assume !(1 == ~t3_pc~0); 3180#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2991#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2946#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2947#L567 assume !(0 != activate_threads_~tmp___2~0#1); 3040#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3083#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 3278#L489-2 assume !(1 == ~T1_E~0); 3364#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3160#L499-1 assume !(1 == ~T3_E~0); 3333#L504-1 assume !(1 == ~E_M~0); 3332#L509-1 assume !(1 == ~E_1~0); 3330#L514-1 assume !(1 == ~E_2~0); 3329#L519-1 assume !(1 == ~E_3~0); 3025#L524-1 assume { :end_inline_reset_delta_events } true; 2989#L690-2 [2023-11-26 11:45:30,319 INFO L750 eck$LassoCheckResult]: Loop: 2989#L690-2 assume !false; 2990#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3019#L416-1 assume !false; 3054#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3055#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3249#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3250#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3226#L369 assume !(0 != eval_~tmp~0#1); 3228#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3162#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3163#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3282#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3456#L446-3 assume !(0 == ~T2_E~0); 3455#L451-3 assume !(0 == ~T3_E~0); 3454#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3453#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3452#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3451#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3450#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3449#L220-15 assume 1 == ~m_pc~0; 3447#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3446#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3445#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3444#L543-15 assume !(0 != activate_threads_~tmp~1#1); 3443#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3442#L239-15 assume 1 == ~t1_pc~0; 3440#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3439#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3438#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3437#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3436#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3435#L258-15 assume 1 == ~t2_pc~0; 3433#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3432#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3431#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3430#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3429#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3428#L277-15 assume 1 == ~t3_pc~0; 3426#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3425#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3424#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3423#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3422#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3421#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2974#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3420#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3235#L499-3 assume !(1 == ~T3_E~0); 3419#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3418#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3417#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3416#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2999#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3000#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3411#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3410#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3409#L709 assume !(0 == start_simulation_~tmp~3#1); 3188#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3115#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3024#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3009#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3010#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3023#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3331#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3073#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2989#L690-2 [2023-11-26 11:45:30,319 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:30,320 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2023-11-26 11:45:30,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:30,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53337450] [2023-11-26 11:45:30,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:30,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:30,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:30,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:30,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:30,413 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53337450] [2023-11-26 11:45:30,413 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53337450] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:30,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:30,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:45:30,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719969809] [2023-11-26 11:45:30,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:30,414 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:45:30,415 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:30,415 INFO L85 PathProgramCache]: Analyzing trace with hash 1605710144, now seen corresponding path program 1 times [2023-11-26 11:45:30,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:30,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439713383] [2023-11-26 11:45:30,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:30,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:30,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:30,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:30,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:30,511 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439713383] [2023-11-26 11:45:30,511 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1439713383] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:30,511 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:30,511 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:45:30,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698050857] [2023-11-26 11:45:30,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:30,512 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:30,513 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:30,514 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:30,514 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:30,514 INFO L87 Difference]: Start difference. First operand 569 states and 842 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:30,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:30,586 INFO L93 Difference]: Finished difference Result 1049 states and 1527 transitions. [2023-11-26 11:45:30,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1049 states and 1527 transitions. [2023-11-26 11:45:30,597 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 983 [2023-11-26 11:45:30,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1049 states to 1049 states and 1527 transitions. [2023-11-26 11:45:30,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1049 [2023-11-26 11:45:30,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1049 [2023-11-26 11:45:30,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1049 states and 1527 transitions. [2023-11-26 11:45:30,612 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:30,612 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1049 states and 1527 transitions. [2023-11-26 11:45:30,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1049 states and 1527 transitions. [2023-11-26 11:45:30,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1049 to 995. [2023-11-26 11:45:30,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 995 states, 995 states have (on average 1.4603015075376884) internal successors, (1453), 994 states have internal predecessors, (1453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:30,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 995 states to 995 states and 1453 transitions. [2023-11-26 11:45:30,650 INFO L240 hiAutomatonCegarLoop]: Abstraction has 995 states and 1453 transitions. [2023-11-26 11:45:30,651 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:30,653 INFO L428 stractBuchiCegarLoop]: Abstraction has 995 states and 1453 transitions. [2023-11-26 11:45:30,654 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:45:30,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 995 states and 1453 transitions. [2023-11-26 11:45:30,662 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 929 [2023-11-26 11:45:30,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:30,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:30,664 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:30,665 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:30,665 INFO L748 eck$LassoCheckResult]: Stem: 4866#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4867#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4884#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4879#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4880#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 4766#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4599#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4600#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4785#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4608#L441 assume !(0 == ~M_E~0); 4609#L441-2 assume !(0 == ~T1_E~0); 4762#L446-1 assume !(0 == ~T2_E~0); 4719#L451-1 assume !(0 == ~T3_E~0); 4720#L456-1 assume !(0 == ~E_M~0); 4891#L461-1 assume !(0 == ~E_1~0); 4892#L466-1 assume !(0 == ~E_2~0); 4916#L471-1 assume !(0 == ~E_3~0); 4643#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4644#L220 assume !(1 == ~m_pc~0); 4678#L220-2 is_master_triggered_~__retres1~0#1 := 0; 4679#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4739#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4674#L543 assume !(0 != activate_threads_~tmp~1#1); 4675#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4862#L239 assume !(1 == ~t1_pc~0); 4860#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4861#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4639#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4640#L551 assume !(0 != activate_threads_~tmp___0~0#1); 4868#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4869#L258 assume 1 == ~t2_pc~0; 4870#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4706#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4707#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4888#L559 assume !(0 != activate_threads_~tmp___1~0#1); 4774#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4775#L277 assume !(1 == ~t3_pc~0); 4829#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4619#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4573#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4574#L567 assume !(0 != activate_threads_~tmp___2~0#1); 4669#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4714#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 4889#L489-2 assume !(1 == ~T1_E~0); 4890#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4660#L499-1 assume !(1 == ~T3_E~0); 4661#L504-1 assume !(1 == ~E_M~0); 4767#L509-1 assume !(1 == ~E_1~0); 4647#L514-1 assume !(1 == ~E_2~0); 4648#L519-1 assume !(1 == ~E_3~0); 4653#L524-1 assume { :end_inline_reset_delta_events } true; 4654#L690-2 [2023-11-26 11:45:30,666 INFO L750 eck$LassoCheckResult]: Loop: 4654#L690-2 assume !false; 4645#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4646#L416-1 assume !false; 4684#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4685#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4904#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4575#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4576#L369 assume !(0 != eval_~tmp~0#1); 5403#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5401#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5398#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5399#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5504#L446-3 assume !(0 == ~T2_E~0); 5503#L451-3 assume !(0 == ~T3_E~0); 5502#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5501#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5500#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5499#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5498#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5497#L220-15 assume !(1 == ~m_pc~0); 5496#L220-17 is_master_triggered_~__retres1~0#1 := 0; 5495#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5494#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5493#L543-15 assume !(0 != activate_threads_~tmp~1#1); 5492#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5491#L239-15 assume 1 == ~t1_pc~0; 5489#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5488#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5487#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5486#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5485#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5484#L258-15 assume 1 == ~t2_pc~0; 5482#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5481#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5480#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5479#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5478#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5477#L277-15 assume 1 == ~t3_pc~0; 5475#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5474#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5473#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5472#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5471#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5470#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5222#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5469#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5219#L499-3 assume !(1 == ~T3_E~0); 5468#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5467#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5466#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5465#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5464#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5463#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5459#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5458#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5457#L709 assume !(0 == start_simulation_~tmp~3#1); 4835#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4752#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4754#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5452#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5450#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5448#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5446#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4705#L722 assume !(0 != start_simulation_~tmp___0~1#1); 4654#L690-2 [2023-11-26 11:45:30,667 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:30,667 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2023-11-26 11:45:30,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:30,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266591573] [2023-11-26 11:45:30,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:30,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:30,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:30,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:30,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:30,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266591573] [2023-11-26 11:45:30,732 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266591573] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:30,732 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:30,732 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:45:30,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1963587835] [2023-11-26 11:45:30,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:30,733 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:45:30,733 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:30,734 INFO L85 PathProgramCache]: Analyzing trace with hash 732232449, now seen corresponding path program 1 times [2023-11-26 11:45:30,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:30,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164330893] [2023-11-26 11:45:30,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:30,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:30,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:30,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:30,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:30,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164330893] [2023-11-26 11:45:30,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [164330893] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:30,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:30,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:45:30,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2022167247] [2023-11-26 11:45:30,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:30,838 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:30,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:30,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:30,839 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:30,839 INFO L87 Difference]: Start difference. First operand 995 states and 1453 transitions. cyclomatic complexity: 462 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:30,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:30,896 INFO L93 Difference]: Finished difference Result 1789 states and 2591 transitions. [2023-11-26 11:45:30,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1789 states and 2591 transitions. [2023-11-26 11:45:30,912 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1712 [2023-11-26 11:45:30,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1789 states to 1789 states and 2591 transitions. [2023-11-26 11:45:30,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1789 [2023-11-26 11:45:30,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1789 [2023-11-26 11:45:30,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1789 states and 2591 transitions. [2023-11-26 11:45:30,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:30,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1789 states and 2591 transitions. [2023-11-26 11:45:30,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1789 states and 2591 transitions. [2023-11-26 11:45:31,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1789 to 1781. [2023-11-26 11:45:31,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1781 states, 1781 states have (on average 1.450308815272319) internal successors, (2583), 1780 states have internal predecessors, (2583), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:31,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1781 states to 1781 states and 2583 transitions. [2023-11-26 11:45:31,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1781 states and 2583 transitions. [2023-11-26 11:45:31,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:31,014 INFO L428 stractBuchiCegarLoop]: Abstraction has 1781 states and 2583 transitions. [2023-11-26 11:45:31,014 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:45:31,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1781 states and 2583 transitions. [2023-11-26 11:45:31,025 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1704 [2023-11-26 11:45:31,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:31,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:31,026 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:31,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:31,027 INFO L748 eck$LassoCheckResult]: Stem: 7639#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7640#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7652#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7650#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7651#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 7553#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7388#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7389#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7574#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7398#L441 assume !(0 == ~M_E~0); 7399#L441-2 assume !(0 == ~T1_E~0); 7549#L446-1 assume !(0 == ~T2_E~0); 7507#L451-1 assume !(0 == ~T3_E~0); 7508#L456-1 assume !(0 == ~E_M~0); 7658#L461-1 assume !(0 == ~E_1~0); 7659#L466-1 assume !(0 == ~E_2~0); 7676#L471-1 assume !(0 == ~E_3~0); 7431#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7432#L220 assume !(1 == ~m_pc~0); 7467#L220-2 is_master_triggered_~__retres1~0#1 := 0; 7468#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7523#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7463#L543 assume !(0 != activate_threads_~tmp~1#1); 7464#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7638#L239 assume !(1 == ~t1_pc~0); 7636#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7637#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7429#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7430#L551 assume !(0 != activate_threads_~tmp___0~0#1); 7641#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7642#L258 assume !(1 == ~t2_pc~0); 7643#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7496#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7497#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7655#L559 assume !(0 != activate_threads_~tmp___1~0#1); 7562#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7563#L277 assume !(1 == ~t3_pc~0); 7607#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7409#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7366#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7367#L567 assume !(0 != activate_threads_~tmp___2~0#1); 7459#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7504#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 7656#L489-2 assume !(1 == ~T1_E~0); 7657#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7586#L499-1 assume !(1 == ~T3_E~0); 8539#L504-1 assume !(1 == ~E_M~0); 8537#L509-1 assume !(1 == ~E_1~0); 8536#L514-1 assume !(1 == ~E_2~0); 7617#L519-1 assume !(1 == ~E_3~0); 7442#L524-1 assume { :end_inline_reset_delta_events } true; 7443#L690-2 [2023-11-26 11:45:31,027 INFO L750 eck$LassoCheckResult]: Loop: 7443#L690-2 assume !false; 8077#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8072#L416-1 assume !false; 8070#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8064#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8060#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8058#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8054#L369 assume !(0 != eval_~tmp~0#1); 8052#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8050#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8047#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8043#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8038#L446-3 assume !(0 == ~T2_E~0); 8034#L451-3 assume !(0 == ~T3_E~0); 8029#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8025#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8022#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8018#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8012#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8008#L220-15 assume !(1 == ~m_pc~0); 8005#L220-17 is_master_triggered_~__retres1~0#1 := 0; 8002#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7999#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7996#L543-15 assume !(0 != activate_threads_~tmp~1#1); 7993#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7991#L239-15 assume 1 == ~t1_pc~0; 7918#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7916#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7914#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7911#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7909#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7907#L258-15 assume !(1 == ~t2_pc~0); 7905#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 7903#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7901#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7899#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7896#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7897#L277-15 assume 1 == ~t3_pc~0; 7889#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7887#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7885#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7882#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7880#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7878#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7876#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7874#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7872#L499-3 assume !(1 == ~T3_E~0); 7870#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7868#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7866#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7864#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7862#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7861#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7858#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8328#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 8325#L709 assume !(0 == start_simulation_~tmp~3#1); 8322#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8142#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8137#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8135#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 8134#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8131#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8129#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 8127#L722 assume !(0 != start_simulation_~tmp___0~1#1); 7443#L690-2 [2023-11-26 11:45:31,027 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:31,028 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2023-11-26 11:45:31,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:31,028 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735789477] [2023-11-26 11:45:31,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:31,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:31,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:31,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:31,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:31,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735789477] [2023-11-26 11:45:31,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1735789477] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:31,073 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:31,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:45:31,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777054349] [2023-11-26 11:45:31,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:31,073 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:45:31,074 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:31,074 INFO L85 PathProgramCache]: Analyzing trace with hash -844325310, now seen corresponding path program 1 times [2023-11-26 11:45:31,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:31,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511124383] [2023-11-26 11:45:31,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:31,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:31,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:31,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:31,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:31,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511124383] [2023-11-26 11:45:31,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511124383] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:31,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:31,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:45:31,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [789607279] [2023-11-26 11:45:31,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:31,126 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:31,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:31,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:31,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:31,127 INFO L87 Difference]: Start difference. First operand 1781 states and 2583 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:31,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:31,167 INFO L93 Difference]: Finished difference Result 2597 states and 3764 transitions. [2023-11-26 11:45:31,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2597 states and 3764 transitions. [2023-11-26 11:45:31,190 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2514 [2023-11-26 11:45:31,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2597 states to 2597 states and 3764 transitions. [2023-11-26 11:45:31,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2597 [2023-11-26 11:45:31,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2597 [2023-11-26 11:45:31,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2597 states and 3764 transitions. [2023-11-26 11:45:31,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:31,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2597 states and 3764 transitions. [2023-11-26 11:45:31,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2597 states and 3764 transitions. [2023-11-26 11:45:31,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2597 to 1805. [2023-11-26 11:45:31,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.453185595567867) internal successors, (2623), 1804 states have internal predecessors, (2623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:31,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2623 transitions. [2023-11-26 11:45:31,265 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2623 transitions. [2023-11-26 11:45:31,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:31,267 INFO L428 stractBuchiCegarLoop]: Abstraction has 1805 states and 2623 transitions. [2023-11-26 11:45:31,268 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:45:31,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2623 transitions. [2023-11-26 11:45:31,280 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1736 [2023-11-26 11:45:31,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:31,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:31,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:31,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:31,281 INFO L748 eck$LassoCheckResult]: Stem: 12017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12031#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12029#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12030#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 11934#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11775#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11776#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11954#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11785#L441 assume !(0 == ~M_E~0); 11786#L441-2 assume !(0 == ~T1_E~0); 11930#L446-1 assume !(0 == ~T2_E~0); 11890#L451-1 assume !(0 == ~T3_E~0); 11891#L456-1 assume !(0 == ~E_M~0); 12035#L461-1 assume !(0 == ~E_1~0); 12036#L466-1 assume !(0 == ~E_2~0); 12052#L471-1 assume !(0 == ~E_3~0); 11818#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11819#L220 assume !(1 == ~m_pc~0); 11853#L220-2 is_master_triggered_~__retres1~0#1 := 0; 11854#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11906#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11849#L543 assume !(0 != activate_threads_~tmp~1#1); 11850#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12016#L239 assume !(1 == ~t1_pc~0); 12014#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12015#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11816#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11817#L551 assume !(0 != activate_threads_~tmp___0~0#1); 12019#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12020#L258 assume !(1 == ~t2_pc~0); 12021#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11879#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11880#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12033#L559 assume !(0 != activate_threads_~tmp___1~0#1); 11942#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11943#L277 assume !(1 == ~t3_pc~0); 11991#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11796#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11753#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11754#L567 assume !(0 != activate_threads_~tmp___2~0#1); 11845#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11887#L489 assume !(1 == ~M_E~0); 12034#L489-2 assume !(1 == ~T1_E~0); 11968#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11834#L499-1 assume !(1 == ~T3_E~0); 11835#L504-1 assume !(1 == ~E_M~0); 11935#L509-1 assume !(1 == ~E_1~0); 11822#L514-1 assume !(1 == ~E_2~0); 11823#L519-1 assume !(1 == ~E_3~0); 11829#L524-1 assume { :end_inline_reset_delta_events } true; 11830#L690-2 [2023-11-26 11:45:31,282 INFO L750 eck$LassoCheckResult]: Loop: 11830#L690-2 assume !false; 13411#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13406#L416-1 assume !false; 13392#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13388#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13384#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13382#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13380#L369 assume !(0 != eval_~tmp~0#1); 11919#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11920#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11973#L441-3 assume !(0 == ~M_E~0); 11736#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11737#L446-3 assume !(0 == ~T2_E~0); 12005#L451-3 assume !(0 == ~T3_E~0); 11790#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11791#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11858#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11977#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11847#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11848#L220-15 assume !(1 == ~m_pc~0); 11907#L220-17 is_master_triggered_~__retres1~0#1 := 0; 13524#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13523#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13521#L543-15 assume !(0 != activate_threads_~tmp~1#1); 13520#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13519#L239-15 assume 1 == ~t1_pc~0; 13517#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13516#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13515#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13514#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13513#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13512#L258-15 assume !(1 == ~t2_pc~0); 13490#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 12067#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12068#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12069#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12038#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12039#L277-15 assume 1 == ~t3_pc~0; 11857#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11749#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12048#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12049#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11787#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11779#L489-3 assume !(1 == ~M_E~0); 11780#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11996#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12032#L499-3 assume !(1 == ~T3_E~0); 11910#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11757#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11758#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11986#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11804#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11805#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11826#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11831#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 11969#L709 assume !(0 == start_simulation_~tmp~3#1); 11970#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13431#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13427#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13425#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 13423#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13421#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13419#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 13417#L722 assume !(0 != start_simulation_~tmp___0~1#1); 11830#L690-2 [2023-11-26 11:45:31,282 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:31,282 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2023-11-26 11:45:31,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:31,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833635806] [2023-11-26 11:45:31,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:31,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:31,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:31,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:31,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:31,338 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1833635806] [2023-11-26 11:45:31,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1833635806] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:31,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:31,343 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:45:31,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [221654881] [2023-11-26 11:45:31,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:31,344 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:45:31,344 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:31,344 INFO L85 PathProgramCache]: Analyzing trace with hash 454395522, now seen corresponding path program 1 times [2023-11-26 11:45:31,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:31,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837855255] [2023-11-26 11:45:31,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:31,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:31,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:31,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:31,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:31,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1837855255] [2023-11-26 11:45:31,401 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1837855255] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:31,401 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:31,402 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:45:31,402 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108038736] [2023-11-26 11:45:31,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:31,402 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:31,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:31,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:45:31,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:45:31,403 INFO L87 Difference]: Start difference. First operand 1805 states and 2623 transitions. cyclomatic complexity: 822 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:31,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:31,496 INFO L93 Difference]: Finished difference Result 2591 states and 3732 transitions. [2023-11-26 11:45:31,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2591 states and 3732 transitions. [2023-11-26 11:45:31,518 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2514 [2023-11-26 11:45:31,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2591 states to 2591 states and 3732 transitions. [2023-11-26 11:45:31,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2591 [2023-11-26 11:45:31,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2591 [2023-11-26 11:45:31,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2591 states and 3732 transitions. [2023-11-26 11:45:31,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:31,548 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2591 states and 3732 transitions. [2023-11-26 11:45:31,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2591 states and 3732 transitions. [2023-11-26 11:45:31,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2591 to 1805. [2023-11-26 11:45:31,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.4437673130193907) internal successors, (2606), 1804 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:31,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2606 transitions. [2023-11-26 11:45:31,594 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2606 transitions. [2023-11-26 11:45:31,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:45:31,595 INFO L428 stractBuchiCegarLoop]: Abstraction has 1805 states and 2606 transitions. [2023-11-26 11:45:31,595 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 11:45:31,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2606 transitions. [2023-11-26 11:45:31,606 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1736 [2023-11-26 11:45:31,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:31,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:31,607 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:31,608 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:31,608 INFO L748 eck$LassoCheckResult]: Stem: 16425#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16426#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16438#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16436#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16437#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 16341#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16183#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16184#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16362#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16193#L441 assume !(0 == ~M_E~0); 16194#L441-2 assume !(0 == ~T1_E~0); 16337#L446-1 assume !(0 == ~T2_E~0); 16299#L451-1 assume !(0 == ~T3_E~0); 16300#L456-1 assume !(0 == ~E_M~0); 16443#L461-1 assume !(0 == ~E_1~0); 16444#L466-1 assume !(0 == ~E_2~0); 16458#L471-1 assume !(0 == ~E_3~0); 16226#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16227#L220 assume !(1 == ~m_pc~0); 16260#L220-2 is_master_triggered_~__retres1~0#1 := 0; 16261#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16315#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16256#L543 assume !(0 != activate_threads_~tmp~1#1); 16257#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16424#L239 assume !(1 == ~t1_pc~0); 16422#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16423#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16224#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16225#L551 assume !(0 != activate_threads_~tmp___0~0#1); 16427#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16428#L258 assume !(1 == ~t2_pc~0); 16429#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16288#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16289#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16440#L559 assume !(0 != activate_threads_~tmp___1~0#1); 16349#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16350#L277 assume !(1 == ~t3_pc~0); 16398#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16204#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16161#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16162#L567 assume !(0 != activate_threads_~tmp___2~0#1); 16252#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16296#L489 assume !(1 == ~M_E~0); 16441#L489-2 assume !(1 == ~T1_E~0); 16375#L494-1 assume !(1 == ~T2_E~0); 16241#L499-1 assume !(1 == ~T3_E~0); 16242#L504-1 assume !(1 == ~E_M~0); 16342#L509-1 assume !(1 == ~E_1~0); 16230#L514-1 assume !(1 == ~E_2~0); 16231#L519-1 assume !(1 == ~E_3~0); 16237#L524-1 assume { :end_inline_reset_delta_events } true; 16202#L690-2 [2023-11-26 11:45:31,608 INFO L750 eck$LassoCheckResult]: Loop: 16202#L690-2 assume !false; 16203#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16232#L416-1 assume !false; 16266#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16267#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16211#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16163#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16164#L369 assume !(0 != eval_~tmp~0#1); 16433#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17923#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17921#L441-3 assume !(0 == ~M_E~0); 17920#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17919#L446-3 assume !(0 == ~T2_E~0); 16412#L451-3 assume !(0 == ~T3_E~0); 16198#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16199#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16265#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16383#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16254#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16255#L220-15 assume !(1 == ~m_pc~0); 16316#L220-17 is_master_triggered_~__retres1~0#1 := 0; 16389#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16317#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16318#L543-15 assume !(0 != activate_threads_~tmp~1#1); 16351#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16338#L239-15 assume 1 == ~t1_pc~0; 16339#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16463#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16294#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16185#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16186#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16489#L258-15 assume !(1 == ~t2_pc~0); 16297#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 16298#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16473#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16474#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16445#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16446#L277-15 assume 1 == ~t3_pc~0; 16264#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16157#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16454#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16455#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16195#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16187#L489-3 assume !(1 == ~M_E~0); 16188#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16403#L494-3 assume !(1 == ~T2_E~0); 16439#L499-3 assume !(1 == ~T3_E~0); 16319#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16165#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16166#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16392#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16212#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16213#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16234#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16238#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 16376#L709 assume !(0 == start_simulation_~tmp~3#1); 16142#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16143#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16236#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16222#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 16223#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16235#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16384#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 16287#L722 assume !(0 != start_simulation_~tmp___0~1#1); 16202#L690-2 [2023-11-26 11:45:31,609 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:31,609 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2023-11-26 11:45:31,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:31,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085798988] [2023-11-26 11:45:31,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:31,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:31,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:31,649 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:31,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:31,684 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:31,684 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:31,684 INFO L85 PathProgramCache]: Analyzing trace with hash -1234548220, now seen corresponding path program 1 times [2023-11-26 11:45:31,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:31,685 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870486721] [2023-11-26 11:45:31,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:31,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:31,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:31,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:31,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:31,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870486721] [2023-11-26 11:45:31,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [870486721] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:31,734 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:31,734 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:45:31,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1632202937] [2023-11-26 11:45:31,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:31,735 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:31,735 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:31,735 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:45:31,735 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:45:31,736 INFO L87 Difference]: Start difference. First operand 1805 states and 2606 transitions. cyclomatic complexity: 805 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:31,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:31,862 INFO L93 Difference]: Finished difference Result 3165 states and 4490 transitions. [2023-11-26 11:45:31,862 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3165 states and 4490 transitions. [2023-11-26 11:45:31,885 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3080 [2023-11-26 11:45:31,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3165 states to 3165 states and 4490 transitions. [2023-11-26 11:45:31,912 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3165 [2023-11-26 11:45:31,916 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3165 [2023-11-26 11:45:31,916 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3165 states and 4490 transitions. [2023-11-26 11:45:31,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:31,921 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3165 states and 4490 transitions. [2023-11-26 11:45:31,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3165 states and 4490 transitions. [2023-11-26 11:45:31,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3165 to 1829. [2023-11-26 11:45:31,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1829 states, 1829 states have (on average 1.437944231820667) internal successors, (2630), 1828 states have internal predecessors, (2630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:31,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1829 states to 1829 states and 2630 transitions. [2023-11-26 11:45:31,972 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1829 states and 2630 transitions. [2023-11-26 11:45:31,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 11:45:31,973 INFO L428 stractBuchiCegarLoop]: Abstraction has 1829 states and 2630 transitions. [2023-11-26 11:45:31,973 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 11:45:31,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1829 states and 2630 transitions. [2023-11-26 11:45:31,982 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1760 [2023-11-26 11:45:31,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:31,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:31,983 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:31,983 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:31,984 INFO L748 eck$LassoCheckResult]: Stem: 21424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 21425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21436#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21434#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21435#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 21338#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21171#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21172#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21358#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21181#L441 assume !(0 == ~M_E~0); 21182#L441-2 assume !(0 == ~T1_E~0); 21334#L446-1 assume !(0 == ~T2_E~0); 21292#L451-1 assume !(0 == ~T3_E~0); 21293#L456-1 assume !(0 == ~E_M~0); 21442#L461-1 assume !(0 == ~E_1~0); 21443#L466-1 assume !(0 == ~E_2~0); 21459#L471-1 assume !(0 == ~E_3~0); 21215#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21216#L220 assume !(1 == ~m_pc~0); 21251#L220-2 is_master_triggered_~__retres1~0#1 := 0; 21252#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21308#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21247#L543 assume !(0 != activate_threads_~tmp~1#1); 21248#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21423#L239 assume !(1 == ~t1_pc~0); 21421#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21422#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21213#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21214#L551 assume !(0 != activate_threads_~tmp___0~0#1); 21426#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21427#L258 assume !(1 == ~t2_pc~0); 21428#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21279#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21280#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21440#L559 assume !(0 != activate_threads_~tmp___1~0#1); 21346#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21347#L277 assume !(1 == ~t3_pc~0); 21396#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21192#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21149#L567 assume !(0 != activate_threads_~tmp___2~0#1); 21243#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21289#L489 assume !(1 == ~M_E~0); 21441#L489-2 assume !(1 == ~T1_E~0); 21372#L494-1 assume !(1 == ~T2_E~0); 21232#L499-1 assume !(1 == ~T3_E~0); 21233#L504-1 assume !(1 == ~E_M~0); 21339#L509-1 assume !(1 == ~E_1~0); 21219#L514-1 assume !(1 == ~E_2~0); 21220#L519-1 assume !(1 == ~E_3~0); 21227#L524-1 assume { :end_inline_reset_delta_events } true; 21228#L690-2 [2023-11-26 11:45:31,984 INFO L750 eck$LassoCheckResult]: Loop: 21228#L690-2 assume !false; 22588#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22584#L416-1 assume !false; 22550#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22546#L332 assume !(0 == ~m_st~0); 22547#L336 assume !(0 == ~t1_st~0); 22543#L340 assume !(0 == ~t2_st~0); 22544#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 22545#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21996#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21997#L369 assume !(0 != eval_~tmp~0#1); 22536#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22535#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22534#L441-3 assume !(0 == ~M_E~0); 22533#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22532#L446-3 assume !(0 == ~T2_E~0); 22531#L451-3 assume !(0 == ~T3_E~0); 22530#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22529#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22528#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22527#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22526#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22525#L220-15 assume !(1 == ~m_pc~0); 22524#L220-17 is_master_triggered_~__retres1~0#1 := 0; 22523#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22522#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22521#L543-15 assume !(0 != activate_threads_~tmp~1#1); 21348#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21335#L239-15 assume 1 == ~t1_pc~0; 21336#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21479#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21287#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21173#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21174#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21493#L258-15 assume !(1 == ~t2_pc~0); 21494#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 22752#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22751#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22750#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22749#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22748#L277-15 assume 1 == ~t3_pc~0; 22746#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22744#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21455#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21456#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21183#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21175#L489-3 assume !(1 == ~M_E~0); 21176#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21401#L494-3 assume !(1 == ~T2_E~0); 21439#L499-3 assume !(1 == ~T3_E~0); 21313#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21152#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21153#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22680#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22679#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22678#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22674#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22650#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 21373#L709 assume !(0 == start_simulation_~tmp~3#1); 21374#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22606#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22601#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22600#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 22597#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22596#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22595#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 22592#L722 assume !(0 != start_simulation_~tmp___0~1#1); 21228#L690-2 [2023-11-26 11:45:31,984 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:31,985 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2023-11-26 11:45:31,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:31,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857806165] [2023-11-26 11:45:31,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:31,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:31,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:31,994 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:31,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:32,011 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:32,011 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:32,012 INFO L85 PathProgramCache]: Analyzing trace with hash 435870986, now seen corresponding path program 1 times [2023-11-26 11:45:32,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:32,012 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83957841] [2023-11-26 11:45:32,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:32,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:32,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:32,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:32,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:32,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [83957841] [2023-11-26 11:45:32,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [83957841] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:32,046 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:32,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:45:32,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1650056297] [2023-11-26 11:45:32,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:32,046 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:32,046 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:32,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:32,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:32,047 INFO L87 Difference]: Start difference. First operand 1829 states and 2630 transitions. cyclomatic complexity: 805 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:32,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:32,106 INFO L93 Difference]: Finished difference Result 3277 states and 4630 transitions. [2023-11-26 11:45:32,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3277 states and 4630 transitions. [2023-11-26 11:45:32,128 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3200 [2023-11-26 11:45:32,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3277 states to 3277 states and 4630 transitions. [2023-11-26 11:45:32,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3277 [2023-11-26 11:45:32,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3277 [2023-11-26 11:45:32,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3277 states and 4630 transitions. [2023-11-26 11:45:32,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:32,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3277 states and 4630 transitions. [2023-11-26 11:45:32,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3277 states and 4630 transitions. [2023-11-26 11:45:32,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3277 to 3187. [2023-11-26 11:45:32,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3187 states, 3187 states have (on average 1.4144963915908377) internal successors, (4508), 3186 states have internal predecessors, (4508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:32,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3187 states to 3187 states and 4508 transitions. [2023-11-26 11:45:32,235 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3187 states and 4508 transitions. [2023-11-26 11:45:32,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:32,236 INFO L428 stractBuchiCegarLoop]: Abstraction has 3187 states and 4508 transitions. [2023-11-26 11:45:32,236 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 11:45:32,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3187 states and 4508 transitions. [2023-11-26 11:45:32,251 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3110 [2023-11-26 11:45:32,251 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:32,251 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:32,252 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:32,252 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:32,253 INFO L748 eck$LassoCheckResult]: Stem: 26542#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 26543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26557#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26553#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26554#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 26447#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26285#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26286#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26469#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26293#L441 assume !(0 == ~M_E~0); 26294#L441-2 assume !(0 == ~T1_E~0); 26443#L446-1 assume !(0 == ~T2_E~0); 26405#L451-1 assume !(0 == ~T3_E~0); 26406#L456-1 assume !(0 == ~E_M~0); 26563#L461-1 assume !(0 == ~E_1~0); 26564#L466-1 assume !(0 == ~E_2~0); 26581#L471-1 assume !(0 == ~E_3~0); 26331#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26332#L220 assume !(1 == ~m_pc~0); 26365#L220-2 is_master_triggered_~__retres1~0#1 := 0; 26366#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26423#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26363#L543 assume !(0 != activate_threads_~tmp~1#1); 26364#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26540#L239 assume !(1 == ~t1_pc~0); 26538#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26539#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26327#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26328#L551 assume !(0 != activate_threads_~tmp___0~0#1); 26544#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26545#L258 assume !(1 == ~t2_pc~0); 26546#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26392#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26393#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26560#L559 assume !(0 != activate_threads_~tmp___1~0#1); 26456#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26457#L277 assume !(1 == ~t3_pc~0); 26514#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26305#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26262#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26263#L567 assume !(0 != activate_threads_~tmp___2~0#1); 26357#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26400#L489 assume !(1 == ~M_E~0); 26562#L489-2 assume !(1 == ~T1_E~0); 26486#L494-1 assume !(1 == ~T2_E~0); 26348#L499-1 assume !(1 == ~T3_E~0); 26349#L504-1 assume !(1 == ~E_M~0); 26448#L509-1 assume !(1 == ~E_1~0); 26334#L514-1 assume !(1 == ~E_2~0); 26335#L519-1 assume !(1 == ~E_3~0); 26340#L524-1 assume { :end_inline_reset_delta_events } true; 26341#L690-2 [2023-11-26 11:45:32,253 INFO L750 eck$LassoCheckResult]: Loop: 26341#L690-2 assume !false; 27959#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27893#L416-1 assume !false; 26727#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26697#L332 assume !(0 == ~m_st~0); 26698#L336 assume !(0 == ~t1_st~0); 28554#L340 assume !(0 == ~t2_st~0); 28556#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 28550#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28551#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28937#L369 assume !(0 != eval_~tmp~0#1); 28935#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28933#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28930#L441-3 assume !(0 == ~M_E~0); 28928#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28926#L446-3 assume !(0 == ~T2_E~0); 28924#L451-3 assume !(0 == ~T3_E~0); 28922#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28919#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28917#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28818#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28817#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28816#L220-15 assume !(1 == ~m_pc~0); 28808#L220-17 is_master_triggered_~__retres1~0#1 := 0; 28805#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28802#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28797#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28794#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28791#L239-15 assume 1 == ~t1_pc~0; 28788#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28785#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28779#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28774#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28769#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28764#L258-15 assume !(1 == ~t2_pc~0); 28759#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 28754#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28750#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28744#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28738#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28733#L277-15 assume 1 == ~t3_pc~0; 28728#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28723#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28718#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28714#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28508#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28499#L489-3 assume !(1 == ~M_E~0); 28403#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28489#L494-3 assume !(1 == ~T2_E~0); 28480#L499-3 assume !(1 == ~T3_E~0); 28477#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28473#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28469#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28464#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28459#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28453#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28448#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28443#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 28438#L709 assume !(0 == start_simulation_~tmp~3#1); 28431#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28426#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 27972#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27970#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 27968#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27966#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27964#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 27962#L722 assume !(0 != start_simulation_~tmp___0~1#1); 26341#L690-2 [2023-11-26 11:45:32,254 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:32,254 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2023-11-26 11:45:32,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:32,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322438882] [2023-11-26 11:45:32,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:32,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:32,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:32,263 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:32,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:32,278 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:32,279 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:32,279 INFO L85 PathProgramCache]: Analyzing trace with hash 12224264, now seen corresponding path program 1 times [2023-11-26 11:45:32,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:32,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218543618] [2023-11-26 11:45:32,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:32,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:32,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:32,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:32,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:32,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218543618] [2023-11-26 11:45:32,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218543618] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:32,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:32,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:45:32,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790209554] [2023-11-26 11:45:32,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:32,397 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:45:32,397 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:32,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:45:32,398 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:45:32,398 INFO L87 Difference]: Start difference. First operand 3187 states and 4508 transitions. cyclomatic complexity: 1325 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:32,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:32,582 INFO L93 Difference]: Finished difference Result 4481 states and 6263 transitions. [2023-11-26 11:45:32,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4481 states and 6263 transitions. [2023-11-26 11:45:32,608 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4400 [2023-11-26 11:45:32,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4481 states to 4481 states and 6263 transitions. [2023-11-26 11:45:32,638 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4481 [2023-11-26 11:45:32,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4481 [2023-11-26 11:45:32,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4481 states and 6263 transitions. [2023-11-26 11:45:32,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:32,650 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4481 states and 6263 transitions. [2023-11-26 11:45:32,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4481 states and 6263 transitions. [2023-11-26 11:45:32,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4481 to 2808. [2023-11-26 11:45:32,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2808 states, 2808 states have (on average 1.393162393162393) internal successors, (3912), 2807 states have internal predecessors, (3912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:32,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2808 states to 2808 states and 3912 transitions. [2023-11-26 11:45:32,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2808 states and 3912 transitions. [2023-11-26 11:45:32,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:45:32,723 INFO L428 stractBuchiCegarLoop]: Abstraction has 2808 states and 3912 transitions. [2023-11-26 11:45:32,723 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 11:45:32,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2808 states and 3912 transitions. [2023-11-26 11:45:32,736 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2735 [2023-11-26 11:45:32,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:32,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:32,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:32,738 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:32,738 INFO L748 eck$LassoCheckResult]: Stem: 34217#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 34218#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 34230#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34228#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34229#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 34131#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33964#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33965#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34151#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33972#L441 assume !(0 == ~M_E~0); 33973#L441-2 assume !(0 == ~T1_E~0); 34127#L446-1 assume !(0 == ~T2_E~0); 34085#L451-1 assume !(0 == ~T3_E~0); 34086#L456-1 assume !(0 == ~E_M~0); 34236#L461-1 assume !(0 == ~E_1~0); 34237#L466-1 assume !(0 == ~E_2~0); 34255#L471-1 assume !(0 == ~E_3~0); 34008#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34009#L220 assume !(1 == ~m_pc~0); 34041#L220-2 is_master_triggered_~__retres1~0#1 := 0; 34042#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34106#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34039#L543 assume !(0 != activate_threads_~tmp~1#1); 34040#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34216#L239 assume !(1 == ~t1_pc~0); 34214#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34215#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34004#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34005#L551 assume !(0 != activate_threads_~tmp___0~0#1); 34219#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34220#L258 assume !(1 == ~t2_pc~0); 34221#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34072#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34073#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34233#L559 assume !(0 != activate_threads_~tmp___1~0#1); 34139#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34140#L277 assume !(1 == ~t3_pc~0); 34188#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33983#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33940#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33941#L567 assume !(0 != activate_threads_~tmp___2~0#1); 34033#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34082#L489 assume !(1 == ~M_E~0); 34235#L489-2 assume !(1 == ~T1_E~0); 34163#L494-1 assume !(1 == ~T2_E~0); 34022#L499-1 assume !(1 == ~T3_E~0); 34023#L504-1 assume !(1 == ~E_M~0); 34132#L509-1 assume !(1 == ~E_1~0); 34010#L514-1 assume !(1 == ~E_2~0); 34011#L519-1 assume !(1 == ~E_3~0); 34016#L524-1 assume { :end_inline_reset_delta_events } true; 34017#L690-2 assume !false; 35111#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35107#L416-1 [2023-11-26 11:45:32,739 INFO L750 eck$LassoCheckResult]: Loop: 35107#L416-1 assume !false; 34872#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34873#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34995#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34993#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34990#L369 assume 0 != eval_~tmp~0#1; 34991#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 35139#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 35133#L377-2 havoc eval_~tmp_ndt_1~0#1; 35126#L374-1 assume !(0 == ~t1_st~0); 35007#L388-1 assume !(0 == ~t2_st~0); 35008#L402-1 assume !(0 == ~t3_st~0); 35107#L416-1 [2023-11-26 11:45:32,739 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:32,740 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2023-11-26 11:45:32,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:32,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1730603941] [2023-11-26 11:45:32,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:32,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:32,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:32,751 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:32,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:32,767 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:32,768 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:32,768 INFO L85 PathProgramCache]: Analyzing trace with hash -583220711, now seen corresponding path program 1 times [2023-11-26 11:45:32,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:32,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106450481] [2023-11-26 11:45:32,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:32,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:32,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:32,773 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:32,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:32,777 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:32,778 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:32,778 INFO L85 PathProgramCache]: Analyzing trace with hash 979003743, now seen corresponding path program 1 times [2023-11-26 11:45:32,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:32,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364682004] [2023-11-26 11:45:32,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:32,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:32,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:32,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:32,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:32,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1364682004] [2023-11-26 11:45:32,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1364682004] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:32,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:32,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:45:32,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935371606] [2023-11-26 11:45:32,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:32,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:32,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:32,926 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:32,926 INFO L87 Difference]: Start difference. First operand 2808 states and 3912 transitions. cyclomatic complexity: 1110 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:32,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:32,997 INFO L93 Difference]: Finished difference Result 5040 states and 6945 transitions. [2023-11-26 11:45:32,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5040 states and 6945 transitions. [2023-11-26 11:45:33,024 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4900 [2023-11-26 11:45:33,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5040 states to 5040 states and 6945 transitions. [2023-11-26 11:45:33,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5040 [2023-11-26 11:45:33,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5040 [2023-11-26 11:45:33,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5040 states and 6945 transitions. [2023-11-26 11:45:33,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:33,085 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5040 states and 6945 transitions. [2023-11-26 11:45:33,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5040 states and 6945 transitions. [2023-11-26 11:45:33,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5040 to 4795. [2023-11-26 11:45:33,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4795 states, 4795 states have (on average 1.3826903023983317) internal successors, (6630), 4794 states have internal predecessors, (6630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:33,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4795 states to 4795 states and 6630 transitions. [2023-11-26 11:45:33,228 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4795 states and 6630 transitions. [2023-11-26 11:45:33,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:33,229 INFO L428 stractBuchiCegarLoop]: Abstraction has 4795 states and 6630 transitions. [2023-11-26 11:45:33,230 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 11:45:33,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4795 states and 6630 transitions. [2023-11-26 11:45:33,252 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4655 [2023-11-26 11:45:33,252 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:33,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:33,253 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:33,254 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:33,254 INFO L748 eck$LassoCheckResult]: Stem: 42100#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 42101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 42115#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42112#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42113#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 41994#L304-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 41995#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42131#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42132#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41829#L441 assume !(0 == ~M_E~0); 41830#L441-2 assume !(0 == ~T1_E~0); 42144#L446-1 assume !(0 == ~T2_E~0); 42145#L451-1 assume !(0 == ~T3_E~0); 42164#L456-1 assume !(0 == ~E_M~0); 42165#L461-1 assume !(0 == ~E_1~0); 42140#L466-1 assume !(0 == ~E_2~0); 42141#L471-1 assume !(0 == ~E_3~0); 41866#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41867#L220 assume !(1 == ~m_pc~0); 41902#L220-2 is_master_triggered_~__retres1~0#1 := 0; 41903#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42078#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 42079#L543 assume !(0 != activate_threads_~tmp~1#1); 42201#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42202#L239 assume !(1 == ~t1_pc~0); 42095#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42096#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41862#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 41863#L551 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42103#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42104#L258 assume !(1 == ~t2_pc~0); 42105#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41928#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41929#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 42118#L559 assume !(0 != activate_threads_~tmp___1~0#1); 42119#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42059#L277 assume !(1 == ~t3_pc~0); 42060#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41840#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41841#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41893#L567 assume !(0 != activate_threads_~tmp___2~0#1); 41894#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42190#L489 assume !(1 == ~M_E~0); 42191#L489-2 assume !(1 == ~T1_E~0); 42037#L494-1 assume !(1 == ~T2_E~0); 42038#L499-1 assume !(1 == ~T3_E~0); 41996#L504-1 assume !(1 == ~E_M~0); 41997#L509-1 assume !(1 == ~E_1~0); 41868#L514-1 assume !(1 == ~E_2~0); 41869#L519-1 assume !(1 == ~E_3~0); 41876#L524-1 assume { :end_inline_reset_delta_events } true; 41877#L690-2 assume !false; 43473#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43469#L416-1 [2023-11-26 11:45:33,255 INFO L750 eck$LassoCheckResult]: Loop: 43469#L416-1 assume !false; 43468#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 43466#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 43465#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 43464#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43463#L369 assume 0 != eval_~tmp~0#1; 43461#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 43459#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 43458#L377-2 havoc eval_~tmp_ndt_1~0#1; 43457#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 43183#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 43456#L391-2 havoc eval_~tmp_ndt_2~0#1; 43477#L388-1 assume !(0 == ~t2_st~0); 43471#L402-1 assume !(0 == ~t3_st~0); 43469#L416-1 [2023-11-26 11:45:33,255 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:33,256 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2023-11-26 11:45:33,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:33,256 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067948936] [2023-11-26 11:45:33,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:33,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:33,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:33,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:33,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:33,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2067948936] [2023-11-26 11:45:33,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2067948936] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:33,287 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:33,287 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:45:33,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125149731] [2023-11-26 11:45:33,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:33,288 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:45:33,288 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:33,288 INFO L85 PathProgramCache]: Analyzing trace with hash 2039297175, now seen corresponding path program 1 times [2023-11-26 11:45:33,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:33,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729378018] [2023-11-26 11:45:33,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:33,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:33,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:33,294 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:33,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:33,299 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:33,371 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:33,372 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:33,372 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:33,372 INFO L87 Difference]: Start difference. First operand 4795 states and 6630 transitions. cyclomatic complexity: 1841 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:33,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:33,405 INFO L93 Difference]: Finished difference Result 4746 states and 6561 transitions. [2023-11-26 11:45:33,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4746 states and 6561 transitions. [2023-11-26 11:45:33,433 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4655 [2023-11-26 11:45:33,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4746 states to 4746 states and 6561 transitions. [2023-11-26 11:45:33,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4746 [2023-11-26 11:45:33,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4746 [2023-11-26 11:45:33,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4746 states and 6561 transitions. [2023-11-26 11:45:33,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:33,470 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4746 states and 6561 transitions. [2023-11-26 11:45:33,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4746 states and 6561 transitions. [2023-11-26 11:45:33,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4746 to 4746. [2023-11-26 11:45:33,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4746 states, 4746 states have (on average 1.3824273072060682) internal successors, (6561), 4745 states have internal predecessors, (6561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:33,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4746 states to 4746 states and 6561 transitions. [2023-11-26 11:45:33,593 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4746 states and 6561 transitions. [2023-11-26 11:45:33,593 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:33,594 INFO L428 stractBuchiCegarLoop]: Abstraction has 4746 states and 6561 transitions. [2023-11-26 11:45:33,595 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 11:45:33,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4746 states and 6561 transitions. [2023-11-26 11:45:33,613 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4655 [2023-11-26 11:45:33,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:33,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:33,614 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:33,614 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:33,614 INFO L748 eck$LassoCheckResult]: Stem: 51628#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 51629#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 51642#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51639#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51640#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 51538#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51368#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51369#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51559#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51376#L441 assume !(0 == ~M_E~0); 51377#L441-2 assume !(0 == ~T1_E~0); 51534#L446-1 assume !(0 == ~T2_E~0); 51494#L451-1 assume !(0 == ~T3_E~0); 51495#L456-1 assume !(0 == ~E_M~0); 51646#L461-1 assume !(0 == ~E_1~0); 51647#L466-1 assume !(0 == ~E_2~0); 51664#L471-1 assume !(0 == ~E_3~0); 51413#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51414#L220 assume !(1 == ~m_pc~0); 51448#L220-2 is_master_triggered_~__retres1~0#1 := 0; 51449#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51514#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51446#L543 assume !(0 != activate_threads_~tmp~1#1); 51447#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51627#L239 assume !(1 == ~t1_pc~0); 51625#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 51626#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51409#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51410#L551 assume !(0 != activate_threads_~tmp___0~0#1); 51630#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51631#L258 assume !(1 == ~t2_pc~0); 51632#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51478#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51479#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51644#L559 assume !(0 != activate_threads_~tmp___1~0#1); 51547#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51548#L277 assume !(1 == ~t3_pc~0); 51600#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 51388#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51345#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51346#L567 assume !(0 != activate_threads_~tmp___2~0#1); 51439#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51491#L489 assume !(1 == ~M_E~0); 51645#L489-2 assume !(1 == ~T1_E~0); 51575#L494-1 assume !(1 == ~T2_E~0); 51430#L499-1 assume !(1 == ~T3_E~0); 51431#L504-1 assume !(1 == ~E_M~0); 51539#L509-1 assume !(1 == ~E_1~0); 51416#L514-1 assume !(1 == ~E_2~0); 51417#L519-1 assume !(1 == ~E_3~0); 51422#L524-1 assume { :end_inline_reset_delta_events } true; 51423#L690-2 assume !false; 53284#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53280#L416-1 [2023-11-26 11:45:33,614 INFO L750 eck$LassoCheckResult]: Loop: 53280#L416-1 assume !false; 53278#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 53276#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 53274#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 53273#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53269#L369 assume 0 != eval_~tmp~0#1; 53266#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 53263#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 53262#L377-2 havoc eval_~tmp_ndt_1~0#1; 53259#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 53212#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 53258#L391-2 havoc eval_~tmp_ndt_2~0#1; 53233#L388-1 assume !(0 == ~t2_st~0); 53234#L402-1 assume !(0 == ~t3_st~0); 53280#L416-1 [2023-11-26 11:45:33,615 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:33,615 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2023-11-26 11:45:33,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:33,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707951271] [2023-11-26 11:45:33,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:33,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:33,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:33,630 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:33,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:33,657 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:33,658 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:33,658 INFO L85 PathProgramCache]: Analyzing trace with hash 2039297175, now seen corresponding path program 2 times [2023-11-26 11:45:33,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:33,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13925500] [2023-11-26 11:45:33,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:33,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:33,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:33,663 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:33,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:33,668 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:33,670 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:33,670 INFO L85 PathProgramCache]: Analyzing trace with hash 98443869, now seen corresponding path program 1 times [2023-11-26 11:45:33,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:33,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432080150] [2023-11-26 11:45:33,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:33,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:33,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:33,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:33,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:33,715 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1432080150] [2023-11-26 11:45:33,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1432080150] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:33,716 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:33,716 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:45:33,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045429362] [2023-11-26 11:45:33,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:33,806 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:33,806 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:33,806 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:33,807 INFO L87 Difference]: Start difference. First operand 4746 states and 6561 transitions. cyclomatic complexity: 1821 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:33,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:33,870 INFO L93 Difference]: Finished difference Result 5349 states and 7350 transitions. [2023-11-26 11:45:33,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5349 states and 7350 transitions. [2023-11-26 11:45:33,899 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5266 [2023-11-26 11:45:33,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5349 states to 5349 states and 7350 transitions. [2023-11-26 11:45:33,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5349 [2023-11-26 11:45:33,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5349 [2023-11-26 11:45:33,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5349 states and 7350 transitions. [2023-11-26 11:45:33,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:33,928 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5349 states and 7350 transitions. [2023-11-26 11:45:33,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5349 states and 7350 transitions. [2023-11-26 11:45:34,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5349 to 5195. [2023-11-26 11:45:34,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5195 states, 5195 states have (on average 1.3770933589990375) internal successors, (7154), 5194 states have internal predecessors, (7154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:34,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5195 states to 5195 states and 7154 transitions. [2023-11-26 11:45:34,083 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5195 states and 7154 transitions. [2023-11-26 11:45:34,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:34,084 INFO L428 stractBuchiCegarLoop]: Abstraction has 5195 states and 7154 transitions. [2023-11-26 11:45:34,085 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 11:45:34,085 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5195 states and 7154 transitions. [2023-11-26 11:45:34,101 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5112 [2023-11-26 11:45:34,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:34,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:34,102 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:34,102 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:34,103 INFO L748 eck$LassoCheckResult]: Stem: 61728#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 61729#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 61743#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61740#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61741#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 61635#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61471#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61472#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61656#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61479#L441 assume !(0 == ~M_E~0); 61480#L441-2 assume !(0 == ~T1_E~0); 61631#L446-1 assume !(0 == ~T2_E~0); 61590#L451-1 assume !(0 == ~T3_E~0); 61591#L456-1 assume !(0 == ~E_M~0); 61748#L461-1 assume !(0 == ~E_1~0); 61749#L466-1 assume !(0 == ~E_2~0); 61766#L471-1 assume !(0 == ~E_3~0); 61516#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61517#L220 assume !(1 == ~m_pc~0); 61549#L220-2 is_master_triggered_~__retres1~0#1 := 0; 61550#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61610#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 61547#L543 assume !(0 != activate_threads_~tmp~1#1); 61548#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61727#L239 assume !(1 == ~t1_pc~0); 61725#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61726#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61512#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 61513#L551 assume !(0 != activate_threads_~tmp___0~0#1); 61730#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61731#L258 assume !(1 == ~t2_pc~0); 61732#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61577#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61578#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61745#L559 assume !(0 != activate_threads_~tmp___1~0#1); 61644#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61645#L277 assume !(1 == ~t3_pc~0); 61700#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 61490#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61448#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61449#L567 assume !(0 != activate_threads_~tmp___2~0#1); 61541#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61585#L489 assume !(1 == ~M_E~0); 61747#L489-2 assume !(1 == ~T1_E~0); 61675#L494-1 assume !(1 == ~T2_E~0); 61532#L499-1 assume !(1 == ~T3_E~0); 61533#L504-1 assume !(1 == ~E_M~0); 61636#L509-1 assume !(1 == ~E_1~0); 61519#L514-1 assume !(1 == ~E_2~0); 61520#L519-1 assume !(1 == ~E_3~0); 61524#L524-1 assume { :end_inline_reset_delta_events } true; 61525#L690-2 assume !false; 65920#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65915#L416-1 [2023-11-26 11:45:34,103 INFO L750 eck$LassoCheckResult]: Loop: 65915#L416-1 assume !false; 65913#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 65909#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 65907#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 65905#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65903#L369 assume 0 != eval_~tmp~0#1; 65901#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 65898#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 65896#L377-2 havoc eval_~tmp_ndt_1~0#1; 65894#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 65878#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 65892#L391-2 havoc eval_~tmp_ndt_2~0#1; 65931#L388-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 65928#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 65926#L405-2 havoc eval_~tmp_ndt_3~0#1; 65918#L402-1 assume !(0 == ~t3_st~0); 65915#L416-1 [2023-11-26 11:45:34,104 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:34,104 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2023-11-26 11:45:34,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:34,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974696139] [2023-11-26 11:45:34,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:34,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:34,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:34,119 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:34,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:34,133 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:34,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:34,134 INFO L85 PathProgramCache]: Analyzing trace with hash 1255454681, now seen corresponding path program 1 times [2023-11-26 11:45:34,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:34,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293372695] [2023-11-26 11:45:34,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:34,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:34,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:34,140 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:34,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:34,146 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:34,150 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:34,151 INFO L85 PathProgramCache]: Analyzing trace with hash 111234079, now seen corresponding path program 1 times [2023-11-26 11:45:34,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:34,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969327003] [2023-11-26 11:45:34,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:34,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:34,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:45:34,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:45:34,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:45:34,199 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969327003] [2023-11-26 11:45:34,199 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969327003] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:45:34,199 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:45:34,199 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:45:34,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054581979] [2023-11-26 11:45:34,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:45:34,271 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:45:34,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:45:34,272 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:45:34,272 INFO L87 Difference]: Start difference. First operand 5195 states and 7154 transitions. cyclomatic complexity: 1965 Second operand has 3 states, 2 states have (on average 34.5) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:34,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:45:34,369 INFO L93 Difference]: Finished difference Result 8757 states and 11970 transitions. [2023-11-26 11:45:34,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8757 states and 11970 transitions. [2023-11-26 11:45:34,406 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8646 [2023-11-26 11:45:34,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8757 states to 8757 states and 11970 transitions. [2023-11-26 11:45:34,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8757 [2023-11-26 11:45:34,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8757 [2023-11-26 11:45:34,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8757 states and 11970 transitions. [2023-11-26 11:45:34,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:45:34,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8757 states and 11970 transitions. [2023-11-26 11:45:34,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8757 states and 11970 transitions. [2023-11-26 11:45:34,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8757 to 8613. [2023-11-26 11:45:34,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8613 states, 8613 states have (on average 1.3730407523510972) internal successors, (11826), 8612 states have internal predecessors, (11826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:45:34,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8613 states to 8613 states and 11826 transitions. [2023-11-26 11:45:34,578 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8613 states and 11826 transitions. [2023-11-26 11:45:34,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:45:34,579 INFO L428 stractBuchiCegarLoop]: Abstraction has 8613 states and 11826 transitions. [2023-11-26 11:45:34,579 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 11:45:34,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8613 states and 11826 transitions. [2023-11-26 11:45:34,607 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8502 [2023-11-26 11:45:34,607 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:45:34,607 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:45:34,608 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:34,608 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:45:34,609 INFO L748 eck$LassoCheckResult]: Stem: 75684#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 75685#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 75696#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75694#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75695#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 75597#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75428#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75429#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75618#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75439#L441 assume !(0 == ~M_E~0); 75440#L441-2 assume !(0 == ~T1_E~0); 75593#L446-1 assume !(0 == ~T2_E~0); 75547#L451-1 assume !(0 == ~T3_E~0); 75548#L456-1 assume !(0 == ~E_M~0); 75703#L461-1 assume !(0 == ~E_1~0); 75704#L466-1 assume !(0 == ~E_2~0); 75719#L471-1 assume !(0 == ~E_3~0); 75472#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75473#L220 assume !(1 == ~m_pc~0); 75507#L220-2 is_master_triggered_~__retres1~0#1 := 0; 75508#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75565#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 75503#L543 assume !(0 != activate_threads_~tmp~1#1); 75504#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75682#L239 assume !(1 == ~t1_pc~0); 75680#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75681#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75470#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 75471#L551 assume !(0 != activate_threads_~tmp___0~0#1); 75686#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75687#L258 assume !(1 == ~t2_pc~0); 75688#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75535#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75536#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75701#L559 assume !(0 != activate_threads_~tmp___1~0#1); 75605#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75606#L277 assume !(1 == ~t3_pc~0); 75654#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75450#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75406#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75407#L567 assume !(0 != activate_threads_~tmp___2~0#1); 75499#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75544#L489 assume !(1 == ~M_E~0); 75702#L489-2 assume !(1 == ~T1_E~0); 75632#L494-1 assume !(1 == ~T2_E~0); 75488#L499-1 assume !(1 == ~T3_E~0); 75489#L504-1 assume !(1 == ~E_M~0); 75598#L509-1 assume !(1 == ~E_1~0); 75476#L514-1 assume !(1 == ~E_2~0); 75477#L519-1 assume !(1 == ~E_3~0); 75482#L524-1 assume { :end_inline_reset_delta_events } true; 75483#L690-2 assume !false; 81940#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81936#L416-1 [2023-11-26 11:45:34,609 INFO L750 eck$LassoCheckResult]: Loop: 81936#L416-1 assume !false; 81934#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 81931#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 81927#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 81925#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 81924#L369 assume 0 != eval_~tmp~0#1; 81922#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 81919#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 81917#L377-2 havoc eval_~tmp_ndt_1~0#1; 81915#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 81827#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 81912#L391-2 havoc eval_~tmp_ndt_2~0#1; 82533#L388-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 82516#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 75537#L405-2 havoc eval_~tmp_ndt_3~0#1; 75538#L402-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 81941#L419 assume !(0 != eval_~tmp_ndt_4~0#1); 81939#L419-2 havoc eval_~tmp_ndt_4~0#1; 81936#L416-1 [2023-11-26 11:45:34,609 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:34,609 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2023-11-26 11:45:34,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:34,610 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153331079] [2023-11-26 11:45:34,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:34,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:34,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:34,649 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:34,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:34,665 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:34,665 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:34,665 INFO L85 PathProgramCache]: Analyzing trace with hash -393961001, now seen corresponding path program 1 times [2023-11-26 11:45:34,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:34,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756107128] [2023-11-26 11:45:34,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:34,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:34,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:34,679 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:34,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:34,685 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:34,685 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:45:34,685 INFO L85 PathProgramCache]: Analyzing trace with hash -478331747, now seen corresponding path program 1 times [2023-11-26 11:45:34,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:45:34,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869878072] [2023-11-26 11:45:34,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:45:34,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:45:34,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:34,696 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:34,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:34,713 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:45:35,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:35,942 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:45:35,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:45:36,126 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.11 11:45:36 BoogieIcfgContainer [2023-11-26 11:45:36,126 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-26 11:45:36,127 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-26 11:45:36,127 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-26 11:45:36,127 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-26 11:45:36,127 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:45:28" (3/4) ... [2023-11-26 11:45:36,129 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-26 11:45:36,225 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/witness.graphml [2023-11-26 11:45:36,226 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-26 11:45:36,226 INFO L158 Benchmark]: Toolchain (without parser) took 9472.05ms. Allocated memory was 151.0MB in the beginning and 283.1MB in the end (delta: 132.1MB). Free memory was 119.5MB in the beginning and 185.9MB in the end (delta: -66.4MB). Peak memory consumption was 68.1MB. Max. memory is 16.1GB. [2023-11-26 11:45:36,227 INFO L158 Benchmark]: CDTParser took 0.28ms. Allocated memory is still 151.0MB. Free memory is still 127.0MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 11:45:36,227 INFO L158 Benchmark]: CACSL2BoogieTranslator took 367.43ms. Allocated memory is still 151.0MB. Free memory was 119.1MB in the beginning and 104.2MB in the end (delta: 15.0MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-26 11:45:36,227 INFO L158 Benchmark]: Boogie Procedure Inliner took 72.24ms. Allocated memory is still 151.0MB. Free memory was 104.2MB in the beginning and 100.4MB in the end (delta: 3.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 11:45:36,228 INFO L158 Benchmark]: Boogie Preprocessor took 80.68ms. Allocated memory is still 151.0MB. Free memory was 100.4MB in the beginning and 96.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 11:45:36,228 INFO L158 Benchmark]: RCFGBuilder took 1103.46ms. Allocated memory is still 151.0MB. Free memory was 95.8MB in the beginning and 109.6MB in the end (delta: -13.8MB). Peak memory consumption was 38.5MB. Max. memory is 16.1GB. [2023-11-26 11:45:36,228 INFO L158 Benchmark]: BuchiAutomizer took 7740.06ms. Allocated memory was 151.0MB in the beginning and 283.1MB in the end (delta: 132.1MB). Free memory was 109.6MB in the beginning and 193.2MB in the end (delta: -83.6MB). Peak memory consumption was 48.4MB. Max. memory is 16.1GB. [2023-11-26 11:45:36,229 INFO L158 Benchmark]: Witness Printer took 99.05ms. Allocated memory is still 283.1MB. Free memory was 193.2MB in the beginning and 185.9MB in the end (delta: 7.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2023-11-26 11:45:36,231 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.28ms. Allocated memory is still 151.0MB. Free memory is still 127.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 367.43ms. Allocated memory is still 151.0MB. Free memory was 119.1MB in the beginning and 104.2MB in the end (delta: 15.0MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 72.24ms. Allocated memory is still 151.0MB. Free memory was 104.2MB in the beginning and 100.4MB in the end (delta: 3.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 80.68ms. Allocated memory is still 151.0MB. Free memory was 100.4MB in the beginning and 96.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1103.46ms. Allocated memory is still 151.0MB. Free memory was 95.8MB in the beginning and 109.6MB in the end (delta: -13.8MB). Peak memory consumption was 38.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 7740.06ms. Allocated memory was 151.0MB in the beginning and 283.1MB in the end (delta: 132.1MB). Free memory was 109.6MB in the beginning and 193.2MB in the end (delta: -83.6MB). Peak memory consumption was 48.4MB. Max. memory is 16.1GB. * Witness Printer took 99.05ms. Allocated memory is still 283.1MB. Free memory was 193.2MB in the beginning and 185.9MB in the end (delta: 7.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (15 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 8613 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.5s and 16 iterations. TraceHistogramMax:1. Analysis of lassos took 4.1s. Construction of modules took 0.4s. Büchi inclusion checks took 2.6s. Highest rank in rank-based complementation 0. Minimization of det autom 15. Minimization of nondet autom 0. Automata minimization 1.1s AutomataMinimizationTime, 15 MinimizatonAttempts, 5282 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.5s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 7807 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 7807 mSDsluCounter, 14168 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6376 mSDsCounter, 136 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 333 IncrementalHoareTripleChecker+Invalid, 469 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 136 mSolverCounterUnsat, 7792 mSDtfsCounter, 333 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 364]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L374-L385] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L388-L399] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L402-L413] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L416-L427] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 364]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L374-L385] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L388-L399] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L402-L413] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L416-L427] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-26 11:45:36,319 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1597c292-3d5f-4b4c-ba76-0413fe60bbc1/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)